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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_master_if.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE Connection Matrix Master Interface                ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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39
//  CVS Log
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//
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//  $Id: wb_conmax_master_if.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
42
//
43
//  $Date: 2002-10-03 05:40:07 $
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//  $Revision: 1.2 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.1.1.1  2001/10/19 11:01:41  rudi
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//               WISHBONE CONMAX IP Core
53
//
54
//
55
//
56
//
57
//
58
 
59
//`include "wb_conmax_defines.v"
60
`timescale 1ns / 10ps
61
 
62
module wb_conmax_master_if(
63
 
64
        clk_i, rst_i,
65
 
66
        // Master interface
67
        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
68
        wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
69
    wb_cti_i, wb_bte_i,
70
 
71
        // Slave 0 Interface
72
        s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o,
73
        s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i,
74
    s0_cti_o, s0_bte_o,
75
 
76
        // Slave 1 Interface
77
        s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o,
78
        s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i,
79
    s1_cti_o, s1_bte_o,
80
 
81
        // Slave 2 Interface
82
        s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o,
83
        s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i,
84
    s2_cti_o, s2_bte_o,
85
 
86
        // Slave 3 Interface
87
        s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o,
88
        s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i,
89
    s3_cti_o, s3_bte_o,
90
 
91
        // Slave 4 Interface
92
        s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o,
93
        s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i,
94
    s4_cti_o, s4_bte_o,
95
 
96
        // Slave 5 Interface
97
        s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o,
98
        s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i,
99
    s5_cti_o, s5_bte_o,
100
 
101
        // Slave 6 Interface
102
        s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o,
103
        s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i,
104
    s6_cti_o, s6_bte_o,
105
 
106
        // Slave 7 Interface
107
        s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o,
108
        s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i,
109
    s7_cti_o, s7_bte_o,
110
 
111
        // Slave 8 Interface
112
        s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o,
113
        s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i,
114
    s8_cti_o, s8_bte_o,
115
 
116
        // Slave 9 Interface
117
        s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o,
118
        s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i,
119
    s9_cti_o, s9_bte_o,
120
 
121
        // Slave 10 Interface
122
        s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o,
123
        s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i,
124
    s10_cti_o, s10_bte_o,
125
 
126
        // Slave 11 Interface
127
        s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o,
128
        s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i,
129
    s11_cti_o, s11_bte_o,
130
 
131
        // Slave 12 Interface
132
        s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o,
133
        s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i,
134
    s12_cti_o, s12_bte_o,
135
 
136
        // Slave 13 Interface
137
        s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o,
138
        s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i,
139
    s13_cti_o, s13_bte_o,
140
 
141
        // Slave 14 Interface
142
        s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o,
143
        s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i,
144
    s14_cti_o, s14_bte_o,
145
 
146
        // Slave 15 Interface
147
        s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o,
148
        s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i,
149
    s15_cti_o, s15_bte_o
150
    );
151
 
152
////////////////////////////////////////////////////////////////////
153
//
154
// Module Parameters
155
//
156
 
157
parameter               dw      = 32;           // Data bus Width
158
parameter               aw      = 32;           // Address bus Width
159
parameter               sw      = dw / 8;       // Number of Select Lines
160
 
161
////////////////////////////////////////////////////////////////////
162
//
163
// Module IOs
164
//
165
 
166
input                   clk_i, rst_i;
167
 
168
// Master Interface
169
input   [dw-1:0] wb_data_i;
170
output  [dw-1:0] wb_data_o;
171
input   [aw-1:0] wb_addr_i;
172
input   [sw-1:0] wb_sel_i;
173
input                   wb_we_i;
174
input                   wb_cyc_i;
175
input                   wb_stb_i;
176
output                  wb_ack_o;
177
output                  wb_err_o;
178
output                  wb_rty_o;
179
input   [2:0]   wb_cti_i;
180
input   [1:0]   wb_bte_i;
181
 
182
// Slave 0 Interface
183
input   [dw-1:0] s0_data_i;
184
output  [dw-1:0] s0_data_o;
185
output  [aw-1:0] s0_addr_o;
186
output  [sw-1:0] s0_sel_o;
187
output                  s0_we_o;
188
output                  s0_cyc_o;
189
output                  s0_stb_o;
190
input                   s0_ack_i;
191
input                   s0_err_i;
192
input                   s0_rty_i;
193
output  [2:0]   s0_cti_o;
194
output  [1:0]   s0_bte_o;
195
 
196
// Slave 1 Interface
197
input   [dw-1:0] s1_data_i;
198
output  [dw-1:0] s1_data_o;
199
output  [aw-1:0] s1_addr_o;
200
output  [sw-1:0] s1_sel_o;
201
output                  s1_we_o;
202
output                  s1_cyc_o;
203
output                  s1_stb_o;
204
input                   s1_ack_i;
205
input                   s1_err_i;
206
input                   s1_rty_i;
207
output  [2:0]   s1_cti_o;
208
output  [1:0]   s1_bte_o;
209
 
210
// Slave 2 Interface
211
input   [dw-1:0] s2_data_i;
212
output  [dw-1:0] s2_data_o;
213
output  [aw-1:0] s2_addr_o;
214
output  [sw-1:0] s2_sel_o;
215
output                  s2_we_o;
216
output                  s2_cyc_o;
217
output                  s2_stb_o;
218
input                   s2_ack_i;
219
input                   s2_err_i;
220
input                   s2_rty_i;
221
output  [2:0]   s2_cti_o;
222
output  [1:0]   s2_bte_o;
223
 
224
// Slave 3 Interface
225
input   [dw-1:0] s3_data_i;
226
output  [dw-1:0] s3_data_o;
227
output  [aw-1:0] s3_addr_o;
228
output  [sw-1:0] s3_sel_o;
229
output                  s3_we_o;
230
output                  s3_cyc_o;
231
output                  s3_stb_o;
232
input                   s3_ack_i;
233
input                   s3_err_i;
234
input                   s3_rty_i;
235
output  [2:0]   s3_cti_o;
236
output  [1:0]   s3_bte_o;
237
 
238
// Slave 4 Interface
239
input   [dw-1:0] s4_data_i;
240
output  [dw-1:0] s4_data_o;
241
output  [aw-1:0] s4_addr_o;
242
output  [sw-1:0] s4_sel_o;
243
output                  s4_we_o;
244
output                  s4_cyc_o;
245
output                  s4_stb_o;
246
input                   s4_ack_i;
247
input                   s4_err_i;
248
input                   s4_rty_i;
249
output  [2:0]   s4_cti_o;
250
output  [1:0]   s4_bte_o;
251
 
252
// Slave 5 Interface
253
input   [dw-1:0] s5_data_i;
254
output  [dw-1:0] s5_data_o;
255
output  [aw-1:0] s5_addr_o;
256
output  [sw-1:0] s5_sel_o;
257
output                  s5_we_o;
258
output                  s5_cyc_o;
259
output                  s5_stb_o;
260
input                   s5_ack_i;
261
input                   s5_err_i;
262
input                   s5_rty_i;
263
output  [2:0]   s5_cti_o;
264
output  [1:0]   s5_bte_o;
265
 
266
// Slave 6 Interface
267
input   [dw-1:0] s6_data_i;
268
output  [dw-1:0] s6_data_o;
269
output  [aw-1:0] s6_addr_o;
270
output  [sw-1:0] s6_sel_o;
271
output                  s6_we_o;
272
output                  s6_cyc_o;
273
output                  s6_stb_o;
274
input                   s6_ack_i;
275
input                   s6_err_i;
276
input                   s6_rty_i;
277
output  [2:0]   s6_cti_o;
278
output  [1:0]   s6_bte_o;
279
 
280
// Slave 7 Interface
281
input   [dw-1:0] s7_data_i;
282
output  [dw-1:0] s7_data_o;
283
output  [aw-1:0] s7_addr_o;
284
output  [sw-1:0] s7_sel_o;
285
output                  s7_we_o;
286
output                  s7_cyc_o;
287
output                  s7_stb_o;
288
input                   s7_ack_i;
289
input                   s7_err_i;
290
input                   s7_rty_i;
291
output  [2:0]   s7_cti_o;
292
output  [1:0]   s7_bte_o;
293
 
294
// Slave 8 Interface
295
input   [dw-1:0] s8_data_i;
296
output  [dw-1:0] s8_data_o;
297
output  [aw-1:0] s8_addr_o;
298
output  [sw-1:0] s8_sel_o;
299
output                  s8_we_o;
300
output                  s8_cyc_o;
301
output                  s8_stb_o;
302
input                   s8_ack_i;
303
input                   s8_err_i;
304
input                   s8_rty_i;
305
output  [2:0]   s8_cti_o;
306
output  [1:0]   s8_bte_o;
307
 
308
// Slave 9 Interface
309
input   [dw-1:0] s9_data_i;
310
output  [dw-1:0] s9_data_o;
311
output  [aw-1:0] s9_addr_o;
312
output  [sw-1:0] s9_sel_o;
313
output                  s9_we_o;
314
output                  s9_cyc_o;
315
output                  s9_stb_o;
316
input                   s9_ack_i;
317
input                   s9_err_i;
318
input                   s9_rty_i;
319
output  [2:0]   s9_cti_o;
320
output  [1:0]   s9_bte_o;
321
 
322
// Slave 10 Interface
323
input   [dw-1:0] s10_data_i;
324
output  [dw-1:0] s10_data_o;
325
output  [aw-1:0] s10_addr_o;
326
output  [sw-1:0] s10_sel_o;
327
output                  s10_we_o;
328
output                  s10_cyc_o;
329
output                  s10_stb_o;
330
input                   s10_ack_i;
331
input                   s10_err_i;
332
input                   s10_rty_i;
333
output  [2:0]   s10_cti_o;
334
output  [1:0]   s10_bte_o;
335
 
336
// Slave 11 Interface
337
input   [dw-1:0] s11_data_i;
338
output  [dw-1:0] s11_data_o;
339
output  [aw-1:0] s11_addr_o;
340
output  [sw-1:0] s11_sel_o;
341
output                  s11_we_o;
342
output                  s11_cyc_o;
343
output                  s11_stb_o;
344
input                   s11_ack_i;
345
input                   s11_err_i;
346
input                   s11_rty_i;
347
output  [2:0]   s11_cti_o;
348
output  [1:0]   s11_bte_o;
349
 
350
// Slave 12 Interface
351
input   [dw-1:0] s12_data_i;
352
output  [dw-1:0] s12_data_o;
353
output  [aw-1:0] s12_addr_o;
354
output  [sw-1:0] s12_sel_o;
355
output                  s12_we_o;
356
output                  s12_cyc_o;
357
output                  s12_stb_o;
358
input                   s12_ack_i;
359
input                   s12_err_i;
360
input                   s12_rty_i;
361
output  [2:0]   s12_cti_o;
362
output  [1:0]   s12_bte_o;
363
 
364
// Slave 13 Interface
365
input   [dw-1:0] s13_data_i;
366
output  [dw-1:0] s13_data_o;
367
output  [aw-1:0] s13_addr_o;
368
output  [sw-1:0] s13_sel_o;
369
output                  s13_we_o;
370
output                  s13_cyc_o;
371
output                  s13_stb_o;
372
input                   s13_ack_i;
373
input                   s13_err_i;
374
input                   s13_rty_i;
375
output  [2:0]   s13_cti_o;
376
output  [1:0]   s13_bte_o;
377
 
378
// Slave 14 Interface
379
input   [dw-1:0] s14_data_i;
380
output  [dw-1:0] s14_data_o;
381
output  [aw-1:0] s14_addr_o;
382
output  [sw-1:0] s14_sel_o;
383
output                  s14_we_o;
384
output                  s14_cyc_o;
385
output                  s14_stb_o;
386
input                   s14_ack_i;
387
input                   s14_err_i;
388
input                   s14_rty_i;
389
output  [2:0]   s14_cti_o;
390
output  [1:0]   s14_bte_o;
391
 
392
// Slave 15 Interface
393
input   [dw-1:0] s15_data_i;
394
output  [dw-1:0] s15_data_o;
395
output  [aw-1:0] s15_addr_o;
396
output  [sw-1:0] s15_sel_o;
397
output                  s15_we_o;
398
output                  s15_cyc_o;
399
output                  s15_stb_o;
400
input                   s15_ack_i;
401
input                   s15_err_i;
402
input                   s15_rty_i;
403
output  [2:0]   s15_cti_o;
404
output  [1:0]   s15_bte_o;
405
 
406
////////////////////////////////////////////////////////////////////
407
//
408
// Local Wires
409
//
410
 
411
reg     [dw-1:0] wb_data_o;
412
reg                     wb_ack_o;
413
reg                     wb_err_o;
414
reg                     wb_rty_o;
415
wire    [3:0]            slv_sel;
416
 
417
wire            s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next;
418
wire            s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next;
419
wire            s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next;
420
wire            s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next;
421
 
422
reg             s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o;
423
reg             s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o;
424
reg             s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o;
425
reg             s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o;
426
 
427
////////////////////////////////////////////////////////////////////
428
//
429
// Select logic
430
//
431
 
432
assign slv_sel = wb_addr_i[aw-1:12];// ==> 4KB addr space cells in current LOGIC !!!
433
 
434
////////////////////////////////////////////////////////////////////
435
//
436
// Address & Data Pass
437
//
438
 
439
assign s0_addr_o = wb_addr_i;
440
assign s1_addr_o = wb_addr_i;
441
assign s2_addr_o = wb_addr_i;
442
assign s3_addr_o = wb_addr_i;
443
assign s4_addr_o = wb_addr_i;
444
assign s5_addr_o = wb_addr_i;
445
assign s6_addr_o = wb_addr_i;
446
assign s7_addr_o = wb_addr_i;
447
assign s8_addr_o = wb_addr_i;
448
assign s9_addr_o = wb_addr_i;
449
assign s10_addr_o = wb_addr_i;
450
assign s11_addr_o = wb_addr_i;
451
assign s12_addr_o = wb_addr_i;
452
assign s13_addr_o = wb_addr_i;
453
assign s14_addr_o = wb_addr_i;
454
assign s15_addr_o = wb_addr_i;
455
 
456
assign s0_sel_o = wb_sel_i;
457
assign s1_sel_o = wb_sel_i;
458
assign s2_sel_o = wb_sel_i;
459
assign s3_sel_o = wb_sel_i;
460
assign s4_sel_o = wb_sel_i;
461
assign s5_sel_o = wb_sel_i;
462
assign s6_sel_o = wb_sel_i;
463
assign s7_sel_o = wb_sel_i;
464
assign s8_sel_o = wb_sel_i;
465
assign s9_sel_o = wb_sel_i;
466
assign s10_sel_o = wb_sel_i;
467
assign s11_sel_o = wb_sel_i;
468
assign s12_sel_o = wb_sel_i;
469
assign s13_sel_o = wb_sel_i;
470
assign s14_sel_o = wb_sel_i;
471
assign s15_sel_o = wb_sel_i;
472
 
473
assign s0_data_o = wb_data_i;
474
assign s1_data_o = wb_data_i;
475
assign s2_data_o = wb_data_i;
476
assign s3_data_o = wb_data_i;
477
assign s4_data_o = wb_data_i;
478
assign s5_data_o = wb_data_i;
479
assign s6_data_o = wb_data_i;
480
assign s7_data_o = wb_data_i;
481
assign s8_data_o = wb_data_i;
482
assign s9_data_o = wb_data_i;
483
assign s10_data_o = wb_data_i;
484
assign s11_data_o = wb_data_i;
485
assign s12_data_o = wb_data_i;
486
assign s13_data_o = wb_data_i;
487
assign s14_data_o = wb_data_i;
488
assign s15_data_o = wb_data_i;
489
 
490
always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or
491
        s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or
492
        s9_data_i or s10_data_i or s11_data_i or s12_data_i or
493
        s13_data_i or s14_data_i or s15_data_i)
494
        case(slv_sel)   // synopsys parallel_case
495
           4'd0:        wb_data_o = s0_data_i;
496
           4'd1:        wb_data_o = s1_data_i;
497
           4'd2:        wb_data_o = s2_data_i;
498
           4'd3:        wb_data_o = s3_data_i;
499
           4'd4:        wb_data_o = s4_data_i;
500
           4'd5:        wb_data_o = s5_data_i;
501
           4'd6:        wb_data_o = s6_data_i;
502
           4'd7:        wb_data_o = s7_data_i;
503
           4'd8:        wb_data_o = s8_data_i;
504
           4'd9:        wb_data_o = s9_data_i;
505
           4'd10:       wb_data_o = s10_data_i;
506
           4'd11:       wb_data_o = s11_data_i;
507
           4'd12:       wb_data_o = s12_data_i;
508
           4'd13:       wb_data_o = s13_data_i;
509
           4'd14:       wb_data_o = s14_data_i;
510
           4'd15:       wb_data_o = s15_data_i;
511
           default:     wb_data_o = {dw{1'bx}};
512
        endcase
513
 
514
////////////////////////////////////////////////////////////////////
515
//
516
// Control Signal Pass
517
//
518
 
519
assign s0_we_o = wb_we_i;
520
assign s1_we_o = wb_we_i;
521
assign s2_we_o = wb_we_i;
522
assign s3_we_o = wb_we_i;
523
assign s4_we_o = wb_we_i;
524
assign s5_we_o = wb_we_i;
525
assign s6_we_o = wb_we_i;
526
assign s7_we_o = wb_we_i;
527
assign s8_we_o = wb_we_i;
528
assign s9_we_o = wb_we_i;
529
assign s10_we_o = wb_we_i;
530
assign s11_we_o = wb_we_i;
531
assign s12_we_o = wb_we_i;
532
assign s13_we_o = wb_we_i;
533
assign s14_we_o = wb_we_i;
534
assign s15_we_o = wb_we_i;
535
 
536
assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0);
537
assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0);
538
assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0);
539
assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0);
540
assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0);
541
assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0);
542
assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0);
543
assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0);
544
assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0);
545
assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0);
546
assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0);
547
assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0);
548
assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0);
549
assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0);
550
assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0);
551
assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0);
552
 
553
always @(posedge clk_i or posedge rst_i)
554
        if(rst_i)       s0_cyc_o <= #1 1'b0;
555
        else            s0_cyc_o <= #1 s0_cyc_o_next;
556
 
557
always @(posedge clk_i or posedge rst_i)
558
        if(rst_i)       s1_cyc_o <= #1 1'b0;
559
        else            s1_cyc_o <= #1 s1_cyc_o_next;
560
 
561
always @(posedge clk_i or posedge rst_i)
562
        if(rst_i)       s2_cyc_o <= #1 1'b0;
563
        else            s2_cyc_o <= #1 s2_cyc_o_next;
564
 
565
always @(posedge clk_i or posedge rst_i)
566
        if(rst_i)       s3_cyc_o <= #1 1'b0;
567
        else            s3_cyc_o <= #1 s3_cyc_o_next;
568
 
569
always @(posedge clk_i or posedge rst_i)
570
        if(rst_i)       s4_cyc_o <= #1 1'b0;
571
        else            s4_cyc_o <= #1 s4_cyc_o_next;
572
 
573
always @(posedge clk_i or posedge rst_i)
574
        if(rst_i)       s5_cyc_o <= #1 1'b0;
575
        else            s5_cyc_o <= #1 s5_cyc_o_next;
576
 
577
always @(posedge clk_i or posedge rst_i)
578
        if(rst_i)       s6_cyc_o <= #1 1'b0;
579
        else            s6_cyc_o <= #1 s6_cyc_o_next;
580
 
581
always @(posedge clk_i or posedge rst_i)
582
        if(rst_i)       s7_cyc_o <= #1 1'b0;
583
        else            s7_cyc_o <= #1 s7_cyc_o_next;
584
 
585
always @(posedge clk_i or posedge rst_i)
586
        if(rst_i)       s8_cyc_o <= #1 1'b0;
587
        else            s8_cyc_o <= #1 s8_cyc_o_next;
588
 
589
always @(posedge clk_i or posedge rst_i)
590
        if(rst_i)       s9_cyc_o <= #1 1'b0;
591
        else            s9_cyc_o <= #1 s9_cyc_o_next;
592
 
593
always @(posedge clk_i or posedge rst_i)
594
        if(rst_i)       s10_cyc_o <= #1 1'b0;
595
        else            s10_cyc_o <= #1 s10_cyc_o_next;
596
 
597
always @(posedge clk_i or posedge rst_i)
598
        if(rst_i)       s11_cyc_o <= #1 1'b0;
599
        else            s11_cyc_o <= #1 s11_cyc_o_next;
600
 
601
always @(posedge clk_i or posedge rst_i)
602
        if(rst_i)       s12_cyc_o <= #1 1'b0;
603
        else            s12_cyc_o <= #1 s12_cyc_o_next;
604
 
605
always @(posedge clk_i or posedge rst_i)
606
        if(rst_i)       s13_cyc_o <= #1 1'b0;
607
        else            s13_cyc_o <= #1 s13_cyc_o_next;
608
 
609
always @(posedge clk_i or posedge rst_i)
610
        if(rst_i)       s14_cyc_o <= #1 1'b0;
611
        else            s14_cyc_o <= #1 s14_cyc_o_next;
612
 
613
always @(posedge clk_i or posedge rst_i)
614
        if(rst_i)       s15_cyc_o <= #1 1'b0;
615
        else            s15_cyc_o <= #1 s15_cyc_o_next;
616
 
617
assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0;
618
assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0;
619
assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0;
620
assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0;
621
assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0;
622
assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0;
623
assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0;
624
assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0;
625
assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0;
626
assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0;
627
assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0;
628
assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0;
629
assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0;
630
assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0;
631
assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0;
632
assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0;
633
 
634
always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or
635
        s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or
636
        s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or
637
        s13_ack_i or s14_ack_i or s15_ack_i)
638
        case(slv_sel)   // synopsys parallel_case
639
           4'd0:        wb_ack_o = s0_ack_i;
640
           4'd1:        wb_ack_o = s1_ack_i;
641
           4'd2:        wb_ack_o = s2_ack_i;
642
           4'd3:        wb_ack_o = s3_ack_i;
643
           4'd4:        wb_ack_o = s4_ack_i;
644
           4'd5:        wb_ack_o = s5_ack_i;
645
           4'd6:        wb_ack_o = s6_ack_i;
646
           4'd7:        wb_ack_o = s7_ack_i;
647
           4'd8:        wb_ack_o = s8_ack_i;
648
           4'd9:        wb_ack_o = s9_ack_i;
649
           4'd10:       wb_ack_o = s10_ack_i;
650
           4'd11:       wb_ack_o = s11_ack_i;
651
           4'd12:       wb_ack_o = s12_ack_i;
652
           4'd13:       wb_ack_o = s13_ack_i;
653
           4'd14:       wb_ack_o = s14_ack_i;
654
           4'd15:       wb_ack_o = s15_ack_i;
655
           default:     wb_ack_o = 1'b0;
656
        endcase
657
 
658
always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or
659
        s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or
660
        s9_err_i or s10_err_i or s11_err_i or s12_err_i or
661
        s13_err_i or s14_err_i or s15_err_i)
662
        case(slv_sel)   // synopsys parallel_case
663
           4'd0:        wb_err_o = s0_err_i;
664
           4'd1:        wb_err_o = s1_err_i;
665
           4'd2:        wb_err_o = s2_err_i;
666
           4'd3:        wb_err_o = s3_err_i;
667
           4'd4:        wb_err_o = s4_err_i;
668
           4'd5:        wb_err_o = s5_err_i;
669
           4'd6:        wb_err_o = s6_err_i;
670
           4'd7:        wb_err_o = s7_err_i;
671
           4'd8:        wb_err_o = s8_err_i;
672
           4'd9:        wb_err_o = s9_err_i;
673
           4'd10:       wb_err_o = s10_err_i;
674
           4'd11:       wb_err_o = s11_err_i;
675
           4'd12:       wb_err_o = s12_err_i;
676
           4'd13:       wb_err_o = s13_err_i;
677
           4'd14:       wb_err_o = s14_err_i;
678
           4'd15:       wb_err_o = s15_err_i;
679
           default:     wb_err_o = 1'b0;
680
        endcase
681
 
682
always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or
683
        s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or
684
        s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or
685
        s13_rty_i or s14_rty_i or s15_rty_i)
686
        case(slv_sel)   // synopsys parallel_case
687
           4'd0:        wb_rty_o = s0_rty_i;
688
           4'd1:        wb_rty_o = s1_rty_i;
689
           4'd2:        wb_rty_o = s2_rty_i;
690
           4'd3:        wb_rty_o = s3_rty_i;
691
           4'd4:        wb_rty_o = s4_rty_i;
692
           4'd5:        wb_rty_o = s5_rty_i;
693
           4'd6:        wb_rty_o = s6_rty_i;
694
           4'd7:        wb_rty_o = s7_rty_i;
695
           4'd8:        wb_rty_o = s8_rty_i;
696
           4'd9:        wb_rty_o = s9_rty_i;
697
           4'd10:       wb_rty_o = s10_rty_i;
698
           4'd11:       wb_rty_o = s11_rty_i;
699
           4'd12:       wb_rty_o = s12_rty_i;
700
           4'd13:       wb_rty_o = s13_rty_i;
701
           4'd14:       wb_rty_o = s14_rty_i;
702
           4'd15:       wb_rty_o = s15_rty_i;
703
           default:     wb_rty_o = 1'b0;
704
        endcase
705
//////////////////////////////////////////////////////////////////////////////////
706
//
707
// WB_CTI/WB_BTE addon
708
//  ==> based on WB_STB logic
709
//
710
 
711
assign s0_cti_o     = (slv_sel==4'd0)  ? wb_cti_i : 3'b0;
712
assign s1_cti_o     = (slv_sel==4'd1)  ? wb_cti_i : 3'b0;
713
assign s2_cti_o     = (slv_sel==4'd2)  ? wb_cti_i : 3'b0;
714
assign s3_cti_o     = (slv_sel==4'd3)  ? wb_cti_i : 3'b0;
715
assign s4_cti_o     = (slv_sel==4'd4)  ? wb_cti_i : 3'b0;
716
assign s5_cti_o     = (slv_sel==4'd5)  ? wb_cti_i : 3'b0;
717
assign s6_cti_o     = (slv_sel==4'd6)  ? wb_cti_i : 3'b0;
718
assign s7_cti_o     = (slv_sel==4'd7)  ? wb_cti_i : 3'b0;
719
assign s8_cti_o     = (slv_sel==4'd8)  ? wb_cti_i : 3'b0;
720
assign s9_cti_o     = (slv_sel==4'd9)  ? wb_cti_i : 3'b0;
721
assign s10_cti_o    = (slv_sel==4'd10) ? wb_cti_i : 3'b0;
722
assign s11_cti_o    = (slv_sel==4'd11) ? wb_cti_i : 3'b0;
723
assign s12_cti_o    = (slv_sel==4'd12) ? wb_cti_i : 3'b0;
724
assign s13_cti_o    = (slv_sel==4'd13) ? wb_cti_i : 3'b0;
725
assign s14_cti_o    = (slv_sel==4'd14) ? wb_cti_i : 3'b0;
726
assign s15_cti_o    = (slv_sel==4'd15) ? wb_cti_i : 3'b0;
727
 
728
assign s0_bte_o     = (slv_sel==4'd0)  ? wb_bte_i : 2'b0;
729
assign s1_bte_o     = (slv_sel==4'd1)  ? wb_bte_i : 2'b0;
730
assign s2_bte_o     = (slv_sel==4'd2)  ? wb_bte_i : 2'b0;
731
assign s3_bte_o     = (slv_sel==4'd3)  ? wb_bte_i : 2'b0;
732
assign s4_bte_o     = (slv_sel==4'd4)  ? wb_bte_i : 2'b0;
733
assign s5_bte_o     = (slv_sel==4'd5)  ? wb_bte_i : 2'b0;
734
assign s6_bte_o     = (slv_sel==4'd6)  ? wb_bte_i : 2'b0;
735
assign s7_bte_o     = (slv_sel==4'd7)  ? wb_bte_i : 2'b0;
736
assign s8_bte_o     = (slv_sel==4'd8)  ? wb_bte_i : 2'b0;
737
assign s9_bte_o     = (slv_sel==4'd9)  ? wb_bte_i : 2'b0;
738
assign s10_bte_o    = (slv_sel==4'd10) ? wb_bte_i : 2'b0;
739
assign s11_bte_o    = (slv_sel==4'd11) ? wb_bte_i : 2'b0;
740
assign s12_bte_o    = (slv_sel==4'd12) ? wb_bte_i : 2'b0;
741
assign s13_bte_o    = (slv_sel==4'd13) ? wb_bte_i : 2'b0;
742
assign s14_bte_o    = (slv_sel==4'd14) ? wb_bte_i : 2'b0;
743
assign s15_bte_o    = (slv_sel==4'd15) ? wb_bte_i : 2'b0;
744
 
745
//////////////////////////////////////////////////////////////////////////////////
746
endmodule
747
 
748
 

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