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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_msel.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE Connection Matrix Master Select                   ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: wb_conmax_msel.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
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//
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//  $Date: 2002-10-03 05:40:07 $
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//  $Revision: 1.2 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.1.1.1  2001/10/19 11:01:38  rudi
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//               WISHBONE CONMAX IP Core
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//
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//
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//
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//
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//
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//`include "wb_conmax_defines.v"
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`timescale 1ns / 10ps
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module wb_conmax_msel(
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                clk_i, rst_i,
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                conf, req, sel, next
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        );
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////////////////////////////////////////////////////////////////////
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//
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// Module Parameters
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//
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parameter       [1:0]    pri_sel = 2'd0;
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////////////////////////////////////////////////////////////////////
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//
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// Module IOs
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//
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input           clk_i, rst_i;
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input   [15:0]   conf;
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input   [7:0]    req;
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output  [2:0]    sel;
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input           next;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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wire    [1:0]    pri0, pri1, pri2, pri3;
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wire    [1:0]    pri4, pri5, pri6, pri7;
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wire    [1:0]    pri_out_d;
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reg     [1:0]    pri_out;
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wire    [7:0]    req_p0, req_p1, req_p2, req_p3;
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wire    [2:0]    gnt_p0, gnt_p1, gnt_p2, gnt_p3;
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reg     [2:0]    sel1, sel2;
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wire    [2:0]    sel;
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////////////////////////////////////////////////////////////////////
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//
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// Priority Select logic
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//
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assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];
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assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;
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assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];
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assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;
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assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];
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assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;
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assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];
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assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;
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assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];
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assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;
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assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];
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assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;
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assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];
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assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;
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assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];
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assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;
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// Priority Encoder
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wb_conmax_pri_enc #(pri_sel) pri_enc(
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        .valid(         req             ),
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        .pri0(          pri0            ),
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        .pri1(          pri1            ),
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        .pri2(          pri2            ),
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        .pri3(          pri3            ),
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        .pri4(          pri4            ),
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        .pri5(          pri5            ),
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        .pri6(          pri6            ),
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        .pri7(          pri7            ),
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        .pri_out(       pri_out_d       )
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        );
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always @(posedge clk_i)
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        if(rst_i)       pri_out <= #1 2'h0;
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        else
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        if(next)        pri_out <= #1 pri_out_d;
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////////////////////////////////////////////////////////////////////
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//
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// Arbiters
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//
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assign req_p0[0] = req[0] & (pri0 == 2'd0);
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assign req_p0[1] = req[1] & (pri1 == 2'd0);
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assign req_p0[2] = req[2] & (pri2 == 2'd0);
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assign req_p0[3] = req[3] & (pri3 == 2'd0);
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assign req_p0[4] = req[4] & (pri4 == 2'd0);
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assign req_p0[5] = req[5] & (pri5 == 2'd0);
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assign req_p0[6] = req[6] & (pri6 == 2'd0);
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assign req_p0[7] = req[7] & (pri7 == 2'd0);
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assign req_p1[0] = req[0] & (pri0 == 2'd1);
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assign req_p1[1] = req[1] & (pri1 == 2'd1);
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assign req_p1[2] = req[2] & (pri2 == 2'd1);
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assign req_p1[3] = req[3] & (pri3 == 2'd1);
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assign req_p1[4] = req[4] & (pri4 == 2'd1);
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assign req_p1[5] = req[5] & (pri5 == 2'd1);
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assign req_p1[6] = req[6] & (pri6 == 2'd1);
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assign req_p1[7] = req[7] & (pri7 == 2'd1);
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assign req_p2[0] = req[0] & (pri0 == 2'd2);
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assign req_p2[1] = req[1] & (pri1 == 2'd2);
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assign req_p2[2] = req[2] & (pri2 == 2'd2);
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assign req_p2[3] = req[3] & (pri3 == 2'd2);
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assign req_p2[4] = req[4] & (pri4 == 2'd2);
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assign req_p2[5] = req[5] & (pri5 == 2'd2);
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assign req_p2[6] = req[6] & (pri6 == 2'd2);
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assign req_p2[7] = req[7] & (pri7 == 2'd2);
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assign req_p3[0] = req[0] & (pri0 == 2'd3);
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assign req_p3[1] = req[1] & (pri1 == 2'd3);
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assign req_p3[2] = req[2] & (pri2 == 2'd3);
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assign req_p3[3] = req[3] & (pri3 == 2'd3);
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assign req_p3[4] = req[4] & (pri4 == 2'd3);
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assign req_p3[5] = req[5] & (pri5 == 2'd3);
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assign req_p3[6] = req[6] & (pri6 == 2'd3);
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assign req_p3[7] = req[7] & (pri7 == 2'd3);
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wb_conmax_arb arb0(
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        .clk(           clk_i           ),
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        .rst(           rst_i           ),
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        .req(           req_p0          ),
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        .gnt(           gnt_p0          ),
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        .next(          1'b0            )
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        );
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wb_conmax_arb arb1(
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        .clk(           clk_i           ),
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        .rst(           rst_i           ),
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        .req(           req_p1          ),
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        .gnt(           gnt_p1          ),
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        .next(          1'b0            )
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        );
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wb_conmax_arb arb2(
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        .clk(           clk_i           ),
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        .rst(           rst_i           ),
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        .req(           req_p2          ),
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        .gnt(           gnt_p2          ),
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        .next(          1'b0            )
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        );
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wb_conmax_arb arb3(
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        .clk(           clk_i           ),
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        .rst(           rst_i           ),
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        .req(           req_p3          ),
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        .gnt(           gnt_p3          ),
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        .next(          1'b0            )
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        );
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////////////////////////////////////////////////////////////////////
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//
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// Final Master Select
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//
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always @(pri_out or gnt_p0 or gnt_p1)
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        if(pri_out[0])   sel1 = gnt_p1;
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        else            sel1 = gnt_p0;
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always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)
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        case(pri_out)
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           2'd0: sel2 = gnt_p0;
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           2'd1: sel2 = gnt_p1;
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           2'd2: sel2 = gnt_p2;
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           2'd3: sel2 = gnt_p3;
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        endcase
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assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );
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endmodule
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