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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_rf.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE Connection Matrix Register File                   ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
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//
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//  $Date: 2002-10-03 05:40:07 $
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//  $Revision: 1.2 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.1.1.1  2001/10/19 11:01:42  rudi
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//               WISHBONE CONMAX IP Core
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//
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//
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//
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//
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//
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//`include "wb_conmax_defines.v"
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`timescale 1ns / 10ps
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module wb_conmax_rf(
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                clk_i, rst_i,
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                // Internal Wishbone Interface
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                i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
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                i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
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        i_wb_cti_o, i_wb_bte_o,
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                // External Wishbone Interface
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                e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
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                e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
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        e_wb_cti_o, e_wb_bte_o,
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                // Configuration Registers
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                conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
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                conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
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                );
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////////////////////////////////////////////////////////////////////
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//
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// Module Parameters
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//
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parameter       [3:0]    rf_addr = 4'hf;
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parameter               dw      = 32;           // Data bus Width
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parameter               aw      = 32;           // Address bus Width
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parameter               sw      = dw / 8;       // Number of Select Lines
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////////////////////////////////////////////////////////////////////
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//
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// Module IOs
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//
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input           clk_i, rst_i;
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// Internal Wishbone Interface
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input   [dw-1:0] i_wb_data_i;
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output  [dw-1:0] i_wb_data_o;
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input   [aw-1:0] i_wb_addr_i;
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input   [sw-1:0] i_wb_sel_i;
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input                   i_wb_we_i;
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input                   i_wb_cyc_i;
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input                   i_wb_stb_i;
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output                  i_wb_ack_o;
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output                  i_wb_err_o;
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output                  i_wb_rty_o;
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input   [2:0]   i_wb_cti_o;
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input   [1:0]   i_wb_bte_o;
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// External Wishbone Interface
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input   [dw-1:0] e_wb_data_i;
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output  [dw-1:0] e_wb_data_o;
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output  [aw-1:0] e_wb_addr_o;
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output  [sw-1:0] e_wb_sel_o;
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output                  e_wb_we_o;
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output                  e_wb_cyc_o;
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output                  e_wb_stb_o;
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input                   e_wb_ack_i;
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input                   e_wb_err_i;
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input                   e_wb_rty_i;
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output  [2:0]   e_wb_cti_o;
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output  [1:0]   e_wb_bte_o;
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// Configuration Registers
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output  [15:0]           conf0;
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output  [15:0]           conf1;
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output  [15:0]           conf2;
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output  [15:0]           conf3;
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output  [15:0]           conf4;
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output  [15:0]           conf5;
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output  [15:0]           conf6;
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output  [15:0]           conf7;
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output  [15:0]           conf8;
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output  [15:0]           conf9;
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output  [15:0]           conf10;
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output  [15:0]           conf11;
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output  [15:0]           conf12;
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output  [15:0]           conf13;
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output  [15:0]           conf14;
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output  [15:0]           conf15;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg     [15:0]   conf0, conf1, conf2, conf3, conf4, conf5;
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reg     [15:0]   conf6, conf7, conf8, conf9, conf10, conf11;
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reg     [15:0]   conf12, conf13, conf14, conf15;
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//synopsys infer_multibit "conf0"
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//synopsys infer_multibit "conf1"
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//synopsys infer_multibit "conf2"
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//synopsys infer_multibit "conf3"
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//synopsys infer_multibit "conf4"
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//synopsys infer_multibit "conf5"
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//synopsys infer_multibit "conf6"
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//synopsys infer_multibit "conf7"
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//synopsys infer_multibit "conf8"
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//synopsys infer_multibit "conf9"
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//synopsys infer_multibit "conf10"
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//synopsys infer_multibit "conf11"
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//synopsys infer_multibit "conf12"
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//synopsys infer_multibit "conf13"
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//synopsys infer_multibit "conf14"
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//synopsys infer_multibit "conf15"
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wire            rf_sel;
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reg     [15:0]   rf_dout;
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reg             rf_ack;
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reg             rf_we;
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////////////////////////////////////////////////////////////////////
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//
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// Register File Select Logic
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//
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assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
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////////////////////////////////////////////////////////////////////
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//
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// Register File Logic
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//
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always @(posedge clk_i)
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        rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
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always @(posedge clk_i)
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        rf_ack <= #1 rf_sel & !rf_ack;
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// Writre Logic
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf0 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd0) )         conf0 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf1 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd1) )         conf1 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf2 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd2) )         conf2 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf3 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd3) )         conf3 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf4 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd4) )         conf4 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf5 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd5) )         conf5 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf6 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd6) )         conf6 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf7 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd7) )         conf7 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf8 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd8) )         conf8 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf9 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd9) )         conf9 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf10 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd10) )        conf10 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf11 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd11) )        conf11 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf12 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd12) )        conf12 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf13 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd13) )        conf13 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf14 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd14) )        conf14 <= #1 i_wb_data_i[15:0];
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always @(posedge clk_i or posedge rst_i)
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        if(rst_i)                                       conf15 <= #1 16'h0;
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        else
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        if(rf_we & (i_wb_addr_i[5:2] == 4'd15) )        conf15 <= #1 i_wb_data_i[15:0];
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// Read Logic
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always @(posedge clk_i)
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        if(!rf_sel)     rf_dout <= #1 16'h0;
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        else
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        case(i_wb_addr_i[5:2])
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           4'd0:        rf_dout <= #1 conf0;
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           4'd1:        rf_dout <= #1 conf1;
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           4'd2:        rf_dout <= #1 conf2;
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           4'd3:        rf_dout <= #1 conf3;
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           4'd4:        rf_dout <= #1 conf4;
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           4'd5:        rf_dout <= #1 conf5;
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           4'd6:        rf_dout <= #1 conf6;
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           4'd7:        rf_dout <= #1 conf7;
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           4'd8:        rf_dout <= #1 conf8;
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           4'd9:        rf_dout <= #1 conf9;
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           4'd10:       rf_dout <= #1 conf10;
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           4'd11:       rf_dout <= #1 conf11;
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           4'd12:       rf_dout <= #1 conf12;
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           4'd13:       rf_dout <= #1 conf13;
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           4'd14:       rf_dout <= #1 conf14;
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           4'd15:       rf_dout <= #1 conf15;
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        endcase
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////////////////////////////////////////////////////////////////////
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//
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// Register File By-Pass Logic
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//
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assign e_wb_addr_o = i_wb_addr_i;
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assign e_wb_sel_o  = i_wb_sel_i;
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assign e_wb_data_o = i_wb_data_i;
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assign e_wb_cyc_o  = rf_sel ? 1'b0 : i_wb_cyc_i;
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assign e_wb_stb_o  = i_wb_stb_i;
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assign e_wb_we_o   = i_wb_we_i;
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assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
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assign i_wb_ack_o  = rf_sel ? rf_ack  : e_wb_ack_i;
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assign i_wb_err_o  = rf_sel ? 1'b0    : e_wb_err_i;
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assign i_wb_rty_o  = rf_sel ? 1'b0    : e_wb_rty_i;
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////////////////////////////////////////////////////////////////////
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//
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// WB "B4" direct route signals
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//  ==> possible because of "e_wb_cyc_o" logic
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//
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assign e_wb_cti_o  = i_wb_cti_o;
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assign e_wb_bte_o  = i_wb_bte_o;
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////////////////////////////////////////////////////////////////////
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endmodule

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