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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_rf.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Connection Matrix Register File                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
//
//  $Date: 2002-10-03 05:40:07 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/10/19 11:01:42  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//
 
//`include "wb_conmax_defines.v"
`timescale 1ns / 10ps
 
module wb_conmax_rf(
                clk_i, rst_i,
 
                // Internal Wishbone Interface
                i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
                i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
        i_wb_cti_o, i_wb_bte_o,
 
                // External Wishbone Interface
                e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
                e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
        e_wb_cti_o, e_wb_bte_o,
 
 
                // Configuration Registers
                conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
                conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
 
                );
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
parameter       [3:0]    rf_addr = 4'hf;
parameter               dw      = 32;           // Data bus Width
parameter               aw      = 32;           // Address bus Width
parameter               sw      = dw / 8;       // Number of Select Lines
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk_i, rst_i;
 
// Internal Wishbone Interface
input   [dw-1:0] i_wb_data_i;
output  [dw-1:0] i_wb_data_o;
input   [aw-1:0] i_wb_addr_i;
input   [sw-1:0] i_wb_sel_i;
input                   i_wb_we_i;
input                   i_wb_cyc_i;
input                   i_wb_stb_i;
output                  i_wb_ack_o;
output                  i_wb_err_o;
output                  i_wb_rty_o;
input   [2:0]   i_wb_cti_o;
input   [1:0]   i_wb_bte_o;
 
// External Wishbone Interface
input   [dw-1:0] e_wb_data_i;
output  [dw-1:0] e_wb_data_o;
output  [aw-1:0] e_wb_addr_o;
output  [sw-1:0] e_wb_sel_o;
output                  e_wb_we_o;
output                  e_wb_cyc_o;
output                  e_wb_stb_o;
input                   e_wb_ack_i;
input                   e_wb_err_i;
input                   e_wb_rty_i;
output  [2:0]   e_wb_cti_o;
output  [1:0]   e_wb_bte_o;
 
// Configuration Registers
output  [15:0]           conf0;
output  [15:0]           conf1;
output  [15:0]           conf2;
output  [15:0]           conf3;
output  [15:0]           conf4;
output  [15:0]           conf5;
output  [15:0]           conf6;
output  [15:0]           conf7;
output  [15:0]           conf8;
output  [15:0]           conf9;
output  [15:0]           conf10;
output  [15:0]           conf11;
output  [15:0]           conf12;
output  [15:0]           conf13;
output  [15:0]           conf14;
output  [15:0]           conf15;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [15:0]   conf0, conf1, conf2, conf3, conf4, conf5;
reg     [15:0]   conf6, conf7, conf8, conf9, conf10, conf11;
reg     [15:0]   conf12, conf13, conf14, conf15;
 
//synopsys infer_multibit "conf0"
//synopsys infer_multibit "conf1"
//synopsys infer_multibit "conf2"
//synopsys infer_multibit "conf3"
//synopsys infer_multibit "conf4"
//synopsys infer_multibit "conf5"
//synopsys infer_multibit "conf6"
//synopsys infer_multibit "conf7"
//synopsys infer_multibit "conf8"
//synopsys infer_multibit "conf9"
//synopsys infer_multibit "conf10"
//synopsys infer_multibit "conf11"
//synopsys infer_multibit "conf12"
//synopsys infer_multibit "conf13"
//synopsys infer_multibit "conf14"
//synopsys infer_multibit "conf15"
 
wire            rf_sel;
reg     [15:0]   rf_dout;
reg             rf_ack;
reg             rf_we;
 
////////////////////////////////////////////////////////////////////
//
// Register File Select Logic
//
 
assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
 
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
 
always @(posedge clk_i)
        rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
 
always @(posedge clk_i)
        rf_ack <= #1 rf_sel & !rf_ack;
 
// Writre Logic
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf0 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd0) )         conf0 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf1 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd1) )         conf1 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf2 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd2) )         conf2 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf3 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd3) )         conf3 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf4 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd4) )         conf4 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf5 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd5) )         conf5 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf6 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd6) )         conf6 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf7 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd7) )         conf7 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf8 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd8) )         conf8 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf9 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd9) )         conf9 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf10 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd10) )        conf10 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf11 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd11) )        conf11 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf12 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd12) )        conf12 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf13 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd13) )        conf13 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf14 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd14) )        conf14 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf15 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd15) )        conf15 <= #1 i_wb_data_i[15:0];
 
// Read Logic
always @(posedge clk_i)
        if(!rf_sel)     rf_dout <= #1 16'h0;
        else
        case(i_wb_addr_i[5:2])
           4'd0:        rf_dout <= #1 conf0;
           4'd1:        rf_dout <= #1 conf1;
           4'd2:        rf_dout <= #1 conf2;
           4'd3:        rf_dout <= #1 conf3;
           4'd4:        rf_dout <= #1 conf4;
           4'd5:        rf_dout <= #1 conf5;
           4'd6:        rf_dout <= #1 conf6;
           4'd7:        rf_dout <= #1 conf7;
           4'd8:        rf_dout <= #1 conf8;
           4'd9:        rf_dout <= #1 conf9;
           4'd10:       rf_dout <= #1 conf10;
           4'd11:       rf_dout <= #1 conf11;
           4'd12:       rf_dout <= #1 conf12;
           4'd13:       rf_dout <= #1 conf13;
           4'd14:       rf_dout <= #1 conf14;
           4'd15:       rf_dout <= #1 conf15;
        endcase
 
////////////////////////////////////////////////////////////////////
//
// Register File By-Pass Logic
//
 
assign e_wb_addr_o = i_wb_addr_i;
assign e_wb_sel_o  = i_wb_sel_i;
assign e_wb_data_o = i_wb_data_i;
 
assign e_wb_cyc_o  = rf_sel ? 1'b0 : i_wb_cyc_i;
assign e_wb_stb_o  = i_wb_stb_i;
assign e_wb_we_o   = i_wb_we_i;
 
assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
assign i_wb_ack_o  = rf_sel ? rf_ack  : e_wb_ack_i;
assign i_wb_err_o  = rf_sel ? 1'b0    : e_wb_err_i;
assign i_wb_rty_o  = rf_sel ? 1'b0    : e_wb_rty_i;
 
////////////////////////////////////////////////////////////////////
//
// WB "B4" direct route signals
//  ==> possible because of "e_wb_cyc_o" logic
//
assign e_wb_cti_o  = i_wb_cti_o;
assign e_wb_bte_o  = i_wb_bte_o;
 
////////////////////////////////////////////////////////////////////
endmodule

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_rf.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Connection Matrix Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $`
42			`//`
43			`// $Date: 2002-10-03 05:40:07 $`
44			`// $Revision: 1.2 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/10/19 11:01:42 rudi`
52			`// WISHBONE CONMAX IP Core`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			//`include "wb_conmax_defines.v"
60			`timescale 1ns / 10ps
61
62			`module wb_conmax_rf(`
63			`clk_i, rst_i,`
64
65			`// Internal Wishbone Interface`
66			`i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,`
67			`i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,`
68			`i_wb_cti_o, i_wb_bte_o,`
69
70			`// External Wishbone Interface`
71			`e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,`
72			`e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,`
73			`e_wb_cti_o, e_wb_bte_o,`
74
75
76			`// Configuration Registers`
77			`conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,`
78			`conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15`
79
80			`);`
81
82			`////////////////////////////////////////////////////////////////////`
83			`//`
84			`// Module Parameters`
85			`//`
86
87			`parameter [3:0] rf_addr = 4'hf;`
88			`parameter dw = 32; // Data bus Width`
89			`parameter aw = 32; // Address bus Width`
90			`parameter sw = dw / 8; // Number of Select Lines`
91
92			`////////////////////////////////////////////////////////////////////`
93			`//`
94			`// Module IOs`
95			`//`
96
97			`input clk_i, rst_i;`
98
99			`// Internal Wishbone Interface`
100			`input [dw-1:0] i_wb_data_i;`
101			`output [dw-1:0] i_wb_data_o;`
102			`input [aw-1:0] i_wb_addr_i;`
103			`input [sw-1:0] i_wb_sel_i;`
104			`input i_wb_we_i;`
105			`input i_wb_cyc_i;`
106			`input i_wb_stb_i;`
107			`output i_wb_ack_o;`
108			`output i_wb_err_o;`
109			`output i_wb_rty_o;`
110			`input [2:0] i_wb_cti_o;`
111			`input [1:0] i_wb_bte_o;`
112
113			`// External Wishbone Interface`
114			`input [dw-1:0] e_wb_data_i;`
115			`output [dw-1:0] e_wb_data_o;`
116			`output [aw-1:0] e_wb_addr_o;`
117			`output [sw-1:0] e_wb_sel_o;`
118			`output e_wb_we_o;`
119			`output e_wb_cyc_o;`
120			`output e_wb_stb_o;`
121			`input e_wb_ack_i;`
122			`input e_wb_err_i;`
123			`input e_wb_rty_i;`
124			`output [2:0] e_wb_cti_o;`
125			`output [1:0] e_wb_bte_o;`
126
127			`// Configuration Registers`
128			`output [15:0] conf0;`
129			`output [15:0] conf1;`
130			`output [15:0] conf2;`
131			`output [15:0] conf3;`
132			`output [15:0] conf4;`
133			`output [15:0] conf5;`
134			`output [15:0] conf6;`
135			`output [15:0] conf7;`
136			`output [15:0] conf8;`
137			`output [15:0] conf9;`
138			`output [15:0] conf10;`
139			`output [15:0] conf11;`
140			`output [15:0] conf12;`
141			`output [15:0] conf13;`
142			`output [15:0] conf14;`
143			`output [15:0] conf15;`
144
145			`////////////////////////////////////////////////////////////////////`
146			`//`
147			`// Local Wires`
148			`//`
149
150			`reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5;`
151			`reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11;`
152			`reg [15:0] conf12, conf13, conf14, conf15;`
153
154			`//synopsys infer_multibit "conf0"`
155			`//synopsys infer_multibit "conf1"`
156			`//synopsys infer_multibit "conf2"`
157			`//synopsys infer_multibit "conf3"`
158			`//synopsys infer_multibit "conf4"`
159			`//synopsys infer_multibit "conf5"`
160			`//synopsys infer_multibit "conf6"`
161			`//synopsys infer_multibit "conf7"`
162			`//synopsys infer_multibit "conf8"`
163			`//synopsys infer_multibit "conf9"`
164			`//synopsys infer_multibit "conf10"`
165			`//synopsys infer_multibit "conf11"`
166			`//synopsys infer_multibit "conf12"`
167			`//synopsys infer_multibit "conf13"`
168			`//synopsys infer_multibit "conf14"`
169			`//synopsys infer_multibit "conf15"`
170
171			`wire rf_sel;`
172			`reg [15:0] rf_dout;`
173			`reg rf_ack;`
174			`reg rf_we;`
175
176			`////////////////////////////////////////////////////////////////////`
177			`//`
178			`// Register File Select Logic`
179			`//`
180
181			`assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);`
182
183			`////////////////////////////////////////////////////////////////////`
184			`//`
185			`// Register File Logic`
186			`//`
187
188			`always @(posedge clk_i)`
189			`rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;`
190
191			`always @(posedge clk_i)`
192			`rf_ack <= #1 rf_sel & !rf_ack;`
193
194			`// Writre Logic`
195			`always @(posedge clk_i or posedge rst_i)`
196			`if(rst_i) conf0 <= #1 16'h0;`
197			`else`
198			`if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0];`
199
200			`always @(posedge clk_i or posedge rst_i)`
201			`if(rst_i) conf1 <= #1 16'h0;`
202			`else`
203			`if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0];`
204
205			`always @(posedge clk_i or posedge rst_i)`
206			`if(rst_i) conf2 <= #1 16'h0;`
207			`else`
208			`if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0];`
209
210			`always @(posedge clk_i or posedge rst_i)`
211			`if(rst_i) conf3 <= #1 16'h0;`
212			`else`
213			`if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0];`
214
215			`always @(posedge clk_i or posedge rst_i)`
216			`if(rst_i) conf4 <= #1 16'h0;`
217			`else`
218			`if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0];`
219
220			`always @(posedge clk_i or posedge rst_i)`
221			`if(rst_i) conf5 <= #1 16'h0;`
222			`else`
223			`if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0];`
224
225			`always @(posedge clk_i or posedge rst_i)`
226			`if(rst_i) conf6 <= #1 16'h0;`
227			`else`
228			`if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0];`
229
230			`always @(posedge clk_i or posedge rst_i)`
231			`if(rst_i) conf7 <= #1 16'h0;`
232			`else`
233			`if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0];`
234
235			`always @(posedge clk_i or posedge rst_i)`
236			`if(rst_i) conf8 <= #1 16'h0;`
237			`else`
238			`if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0];`
239
240			`always @(posedge clk_i or posedge rst_i)`
241			`if(rst_i) conf9 <= #1 16'h0;`
242			`else`
243			`if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0];`
244
245			`always @(posedge clk_i or posedge rst_i)`
246			`if(rst_i) conf10 <= #1 16'h0;`
247			`else`
248			`if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0];`
249
250			`always @(posedge clk_i or posedge rst_i)`
251			`if(rst_i) conf11 <= #1 16'h0;`
252			`else`
253			`if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0];`
254
255			`always @(posedge clk_i or posedge rst_i)`
256			`if(rst_i) conf12 <= #1 16'h0;`
257			`else`
258			`if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0];`
259
260			`always @(posedge clk_i or posedge rst_i)`
261			`if(rst_i) conf13 <= #1 16'h0;`
262			`else`
263			`if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0];`
264
265			`always @(posedge clk_i or posedge rst_i)`
266			`if(rst_i) conf14 <= #1 16'h0;`
267			`else`
268			`if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0];`
269
270			`always @(posedge clk_i or posedge rst_i)`
271			`if(rst_i) conf15 <= #1 16'h0;`
272			`else`
273			`if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0];`
274
275			`// Read Logic`
276			`always @(posedge clk_i)`
277			`if(!rf_sel) rf_dout <= #1 16'h0;`
278			`else`
279			`case(i_wb_addr_i[5:2])`
280			`4'd0: rf_dout <= #1 conf0;`
281			`4'd1: rf_dout <= #1 conf1;`
282			`4'd2: rf_dout <= #1 conf2;`
283			`4'd3: rf_dout <= #1 conf3;`
284			`4'd4: rf_dout <= #1 conf4;`
285			`4'd5: rf_dout <= #1 conf5;`
286			`4'd6: rf_dout <= #1 conf6;`
287			`4'd7: rf_dout <= #1 conf7;`
288			`4'd8: rf_dout <= #1 conf8;`
289			`4'd9: rf_dout <= #1 conf9;`
290			`4'd10: rf_dout <= #1 conf10;`
291			`4'd11: rf_dout <= #1 conf11;`
292			`4'd12: rf_dout <= #1 conf12;`
293			`4'd13: rf_dout <= #1 conf13;`
294			`4'd14: rf_dout <= #1 conf14;`
295			`4'd15: rf_dout <= #1 conf15;`
296			`endcase`
297
298			`////////////////////////////////////////////////////////////////////`
299			`//`
300			`// Register File By-Pass Logic`
301			`//`
302
303			`assign e_wb_addr_o = i_wb_addr_i;`
304			`assign e_wb_sel_o = i_wb_sel_i;`
305			`assign e_wb_data_o = i_wb_data_i;`
306
307			`assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i;`
308			`assign e_wb_stb_o = i_wb_stb_i;`
309			`assign e_wb_we_o = i_wb_we_i;`
310
311			`assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;`
312			`assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i;`
313			`assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i;`
314			`assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i;`
315
316			`////////////////////////////////////////////////////////////////////`
317			`//`
318			`// WB "B4" direct route signals`
319			`// ==> possible because of "e_wb_cyc_o" logic`
320			`//`
321			`assign e_wb_cti_o = i_wb_cti_o;`
322			`assign e_wb_bte_o = i_wb_bte_o;`
323
324			`////////////////////////////////////////////////////////////////////`
325			`endmodule`