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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [cross/] [wb_conmax_slave_if.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE Connection Matrix Slave Interface                 ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
38
 
39
//  CVS Log
40
//
41
//  $Id: wb_conmax_slave_if.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
42
//
43
//  $Date: 2002-10-03 05:40:07 $
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//  $Revision: 1.2 $
45
//  $Author: rudi $
46
//  $Locker:  $
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//  $State: Exp $
48
//
49
// Change History:
50
//               $Log: not supported by cvs2svn $
51
//               Revision 1.1.1.1  2001/10/19 11:01:39  rudi
52
//               WISHBONE CONMAX IP Core
53
//
54
//
55
//
56
//
57
//
58
 
59
//`include "wb_conmax_defines.v"
60
`timescale 1ns / 10ps
61
 
62
module wb_conmax_slave_if(
63
 
64
        clk_i, rst_i, conf,
65
 
66
        // Slave interface
67
        wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
68
        wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
69
    wb_cti_o, wb_bte_o,
70
 
71
        // Master 0 Interface
72
        m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i,
73
        m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o,
74
    m0_cti_i, m0_bte_i,
75
 
76
        // Master 1 Interface
77
        m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i,
78
        m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o,
79
    m1_cti_i, m1_bte_i,
80
 
81
        // Master 2 Interface
82
        m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i,
83
        m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o,
84
    m2_cti_i, m2_bte_i,
85
 
86
        // Master 3 Interface
87
        m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i,
88
        m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o,
89
    m3_cti_i, m3_bte_i,
90
 
91
        // Master 4 Interface
92
        m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i,
93
        m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o,
94
    m4_cti_i, m4_bte_i,
95
 
96
        // Master 5 Interface
97
        m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i,
98
        m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o,
99
    m5_cti_i, m5_bte_i,
100
 
101
        // Master 6 Interface
102
        m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i,
103
        m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o,
104
    m6_cti_i, m6_bte_i,
105
 
106
        // Master 7 Interface
107
        m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i,
108
        m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o,
109
    m7_cti_i, m7_bte_i
110
    );
111
 
112
////////////////////////////////////////////////////////////////////
113
//
114
// Module Parameters
115
//
116
 
117
parameter [1:0]          pri_sel = 2'd2;
118
parameter               aw      = 32;           // Address bus Width
119
parameter               dw      = 32;           // Data bus Width
120
parameter               sw      = dw / 8;       // Number of Select Lines
121
 
122
////////////////////////////////////////////////////////////////////
123
//
124
// Module IOs
125
//
126
 
127
input                   clk_i, rst_i;
128
input   [15:0]           conf;
129
 
130
// Slave Interface
131
input   [dw-1:0] wb_data_i;
132
output  [dw-1:0] wb_data_o;
133
output  [aw-1:0] wb_addr_o;
134
output  [sw-1:0] wb_sel_o;
135
output                  wb_we_o;
136
output                  wb_cyc_o;
137
output                  wb_stb_o;
138
input                   wb_ack_i;
139
input                   wb_err_i;
140
input                   wb_rty_i;
141
output  [2:0]   wb_cti_o;
142
output  [1:0]   wb_bte_o;
143
 
144
// Master 0 Interface
145
input   [dw-1:0] m0_data_i;
146
output  [dw-1:0] m0_data_o;
147
input   [aw-1:0] m0_addr_i;
148
input   [sw-1:0] m0_sel_i;
149
input                   m0_we_i;
150
input                   m0_cyc_i;
151
input                   m0_stb_i;
152
output                  m0_ack_o;
153
output                  m0_err_o;
154
output                  m0_rty_o;
155
input   [2:0]   m0_cti_i;
156
input   [1:0]   m0_bte_i;
157
 
158
// Master 1 Interface
159
input   [dw-1:0] m1_data_i;
160
output  [dw-1:0] m1_data_o;
161
input   [aw-1:0] m1_addr_i;
162
input   [sw-1:0] m1_sel_i;
163
input                   m1_we_i;
164
input                   m1_cyc_i;
165
input                   m1_stb_i;
166
output                  m1_ack_o;
167
output                  m1_err_o;
168
output                  m1_rty_o;
169
input   [2:0]   m1_cti_i;
170
input   [1:0]   m1_bte_i;
171
 
172
// Master 2 Interface
173
input   [dw-1:0] m2_data_i;
174
output  [dw-1:0] m2_data_o;
175
input   [aw-1:0] m2_addr_i;
176
input   [sw-1:0] m2_sel_i;
177
input                   m2_we_i;
178
input                   m2_cyc_i;
179
input                   m2_stb_i;
180
output                  m2_ack_o;
181
output                  m2_err_o;
182
output                  m2_rty_o;
183
input   [2:0]   m2_cti_i;
184
input   [1:0]   m2_bte_i;
185
 
186
// Master 3 Interface
187
input   [dw-1:0] m3_data_i;
188
output  [dw-1:0] m3_data_o;
189
input   [aw-1:0] m3_addr_i;
190
input   [sw-1:0] m3_sel_i;
191
input                   m3_we_i;
192
input                   m3_cyc_i;
193
input                   m3_stb_i;
194
output                  m3_ack_o;
195
output                  m3_err_o;
196
output                  m3_rty_o;
197
input   [2:0]   m3_cti_i;
198
input   [1:0]   m3_bte_i;
199
 
200
// Master 4 Interface
201
input   [dw-1:0] m4_data_i;
202
output  [dw-1:0] m4_data_o;
203
input   [aw-1:0] m4_addr_i;
204
input   [sw-1:0] m4_sel_i;
205
input                   m4_we_i;
206
input                   m4_cyc_i;
207
input                   m4_stb_i;
208
output                  m4_ack_o;
209
output                  m4_err_o;
210
output                  m4_rty_o;
211
input   [2:0]   m4_cti_i;
212
input   [1:0]   m4_bte_i;
213
 
214
// Master 5 Interface
215
input   [dw-1:0] m5_data_i;
216
output  [dw-1:0] m5_data_o;
217
input   [aw-1:0] m5_addr_i;
218
input   [sw-1:0] m5_sel_i;
219
input                   m5_we_i;
220
input                   m5_cyc_i;
221
input                   m5_stb_i;
222
output                  m5_ack_o;
223
output                  m5_err_o;
224
output                  m5_rty_o;
225
input   [2:0]   m5_cti_i;
226
input   [1:0]   m5_bte_i;
227
 
228
// Master 6 Interface
229
input   [dw-1:0] m6_data_i;
230
output  [dw-1:0] m6_data_o;
231
input   [aw-1:0] m6_addr_i;
232
input   [sw-1:0] m6_sel_i;
233
input                   m6_we_i;
234
input                   m6_cyc_i;
235
input                   m6_stb_i;
236
output                  m6_ack_o;
237
output                  m6_err_o;
238
output                  m6_rty_o;
239
input   [2:0]   m6_cti_i;
240
input   [1:0]   m6_bte_i;
241
 
242
// Master 7 Interface
243
input   [dw-1:0] m7_data_i;
244
output  [dw-1:0] m7_data_o;
245
input   [aw-1:0] m7_addr_i;
246
input   [sw-1:0] m7_sel_i;
247
input                   m7_we_i;
248
input                   m7_cyc_i;
249
input                   m7_stb_i;
250
output                  m7_ack_o;
251
output                  m7_err_o;
252
output                  m7_rty_o;
253
input   [2:0]   m7_cti_i;
254
input   [1:0]   m7_bte_i;
255
 
256
////////////////////////////////////////////////////////////////////
257
//
258
// Local Wires
259
//
260
 
261
reg     [aw-1:0] wb_addr_o;
262
reg     [dw-1:0] wb_data_o;
263
reg     [sw-1:0] wb_sel_o;
264
reg                     wb_we_o;
265
reg                     wb_cyc_o;
266
reg                     wb_stb_o;
267
reg [2:0]   wb_cti_o;
268
reg [1:0]   wb_bte_o;
269
 
270
wire    [2:0]            mast_sel_simple;
271
wire    [2:0]            mast_sel_pe;
272
wire    [2:0]            mast_sel;
273
 
274
reg                     next;
275
reg                     m0_cyc_r, m1_cyc_r, m2_cyc_r, m3_cyc_r;
276
reg                     m4_cyc_r, m5_cyc_r, m6_cyc_r, m7_cyc_r;
277
 
278
////////////////////////////////////////////////////////////////////
279
//
280
// Select logic
281
//
282
 
283
always @(posedge clk_i)
284
        next <= #1 ~wb_cyc_o;
285
 
286
 
287
wb_conmax_arb arb(
288
        .clk(           clk_i           ),
289
        .rst(           rst_i           ),
290
        .req(   {       m7_cyc_i,
291
                        m6_cyc_i,
292
                        m5_cyc_i,
293
                        m4_cyc_i,
294
                        m3_cyc_i,
295
                        m2_cyc_i,
296
                        m1_cyc_i,
297
                        m0_cyc_i }      ),
298
        .gnt(           mast_sel_simple ),
299
        .next(          1'b0            )
300
        );
301
 
302
wb_conmax_msel #(pri_sel) msel(
303
        .clk_i(         clk_i           ),
304
        .rst_i(         rst_i           ),
305
        .conf(          conf            ),
306
        .req(   {       m7_cyc_i,
307
                        m6_cyc_i,
308
                        m5_cyc_i,
309
                        m4_cyc_i,
310
                        m3_cyc_i,
311
                        m2_cyc_i,
312
                        m1_cyc_i,
313
                        m0_cyc_i}       ),
314
        .sel(           mast_sel_pe     ),
315
        .next(          next            )
316
        );
317
 
318
assign mast_sel = (pri_sel == 2'd0) ? mast_sel_simple : mast_sel_pe;
319
 
320
////////////////////////////////////////////////////////////////////
321
//
322
// Address & Data Pass
323
//
324
 
325
always @(mast_sel or m0_addr_i or m1_addr_i or m2_addr_i or m3_addr_i
326
        or m4_addr_i or m5_addr_i or m6_addr_i or m7_addr_i)
327
        case(mast_sel)  // synopsys parallel_case
328
           3'd0: wb_addr_o = m0_addr_i;
329
           3'd1: wb_addr_o = m1_addr_i;
330
           3'd2: wb_addr_o = m2_addr_i;
331
           3'd3: wb_addr_o = m3_addr_i;
332
           3'd4: wb_addr_o = m4_addr_i;
333
           3'd5: wb_addr_o = m5_addr_i;
334
           3'd6: wb_addr_o = m6_addr_i;
335
           3'd7: wb_addr_o = m7_addr_i;
336
           default: wb_addr_o = {aw{1'bx}};
337
        endcase
338
 
339
always @(mast_sel or m0_sel_i or m1_sel_i or m2_sel_i or m3_sel_i
340
        or m4_sel_i or m5_sel_i or m6_sel_i or m7_sel_i)
341
        case(mast_sel)  // synopsys parallel_case
342
           3'd0: wb_sel_o = m0_sel_i;
343
           3'd1: wb_sel_o = m1_sel_i;
344
           3'd2: wb_sel_o = m2_sel_i;
345
           3'd3: wb_sel_o = m3_sel_i;
346
           3'd4: wb_sel_o = m4_sel_i;
347
           3'd5: wb_sel_o = m5_sel_i;
348
           3'd6: wb_sel_o = m6_sel_i;
349
           3'd7: wb_sel_o = m7_sel_i;
350
           default: wb_sel_o = {sw{1'bx}};
351
        endcase
352
 
353
always @(mast_sel or m0_data_i or m1_data_i or m2_data_i or m3_data_i
354
        or m4_data_i or m5_data_i or m6_data_i or m7_data_i)
355
        case(mast_sel)  // synopsys parallel_case
356
           3'd0: wb_data_o = m0_data_i;
357
           3'd1: wb_data_o = m1_data_i;
358
           3'd2: wb_data_o = m2_data_i;
359
           3'd3: wb_data_o = m3_data_i;
360
           3'd4: wb_data_o = m4_data_i;
361
           3'd5: wb_data_o = m5_data_i;
362
           3'd6: wb_data_o = m6_data_i;
363
           3'd7: wb_data_o = m7_data_i;
364
           default: wb_data_o = {dw{1'bx}};
365
        endcase
366
 
367
assign m0_data_o = wb_data_i;
368
assign m1_data_o = wb_data_i;
369
assign m2_data_o = wb_data_i;
370
assign m3_data_o = wb_data_i;
371
assign m4_data_o = wb_data_i;
372
assign m5_data_o = wb_data_i;
373
assign m6_data_o = wb_data_i;
374
assign m7_data_o = wb_data_i;
375
 
376
////////////////////////////////////////////////////////////////////
377
//
378
// Control Signal Pass
379
//
380
 
381
always @(mast_sel or m0_we_i or m1_we_i or m2_we_i or m3_we_i
382
        or m4_we_i or m5_we_i or m6_we_i or m7_we_i)
383
        case(mast_sel)  // synopsys parallel_case
384
           3'd0: wb_we_o = m0_we_i;
385
           3'd1: wb_we_o = m1_we_i;
386
           3'd2: wb_we_o = m2_we_i;
387
           3'd3: wb_we_o = m3_we_i;
388
           3'd4: wb_we_o = m4_we_i;
389
           3'd5: wb_we_o = m5_we_i;
390
           3'd6: wb_we_o = m6_we_i;
391
           3'd7: wb_we_o = m7_we_i;
392
           default: wb_we_o = 1'bx;
393
        endcase
394
 
395
always @(posedge clk_i)
396
        m0_cyc_r <= #1 m0_cyc_i;
397
 
398
always @(posedge clk_i)
399
        m1_cyc_r <= #1 m1_cyc_i;
400
 
401
always @(posedge clk_i)
402
        m2_cyc_r <= #1 m2_cyc_i;
403
 
404
always @(posedge clk_i)
405
        m3_cyc_r <= #1 m3_cyc_i;
406
 
407
always @(posedge clk_i)
408
        m4_cyc_r <= #1 m4_cyc_i;
409
 
410
always @(posedge clk_i)
411
        m5_cyc_r <= #1 m5_cyc_i;
412
 
413
always @(posedge clk_i)
414
        m6_cyc_r <= #1 m6_cyc_i;
415
 
416
always @(posedge clk_i)
417
        m7_cyc_r <= #1 m7_cyc_i;
418
 
419
always @(mast_sel or m0_cyc_i or m1_cyc_i or m2_cyc_i or m3_cyc_i
420
        or m4_cyc_i or m5_cyc_i or m6_cyc_i or m7_cyc_i
421
        or m0_cyc_r or m1_cyc_r or m2_cyc_r or m3_cyc_r
422
        or m4_cyc_r or m5_cyc_r or m6_cyc_r or m7_cyc_r)
423
        case(mast_sel)  // synopsys parallel_case
424
           3'd0: wb_cyc_o = m0_cyc_i & m0_cyc_r;
425
           3'd1: wb_cyc_o = m1_cyc_i & m1_cyc_r;
426
           3'd2: wb_cyc_o = m2_cyc_i & m2_cyc_r;
427
           3'd3: wb_cyc_o = m3_cyc_i & m3_cyc_r;
428
           3'd4: wb_cyc_o = m4_cyc_i & m4_cyc_r;
429
           3'd5: wb_cyc_o = m5_cyc_i & m5_cyc_r;
430
           3'd6: wb_cyc_o = m6_cyc_i & m6_cyc_r;
431
           3'd7: wb_cyc_o = m7_cyc_i & m7_cyc_r;
432
           default: wb_cyc_o = 1'b0;
433
        endcase
434
 
435
always @(mast_sel or m0_stb_i or m1_stb_i or m2_stb_i or m3_stb_i
436
        or m4_stb_i or m5_stb_i or m6_stb_i or m7_stb_i)
437
        case(mast_sel)  // synopsys parallel_case
438
           3'd0: wb_stb_o = m0_stb_i;
439
           3'd1: wb_stb_o = m1_stb_i;
440
           3'd2: wb_stb_o = m2_stb_i;
441
           3'd3: wb_stb_o = m3_stb_i;
442
           3'd4: wb_stb_o = m4_stb_i;
443
           3'd5: wb_stb_o = m5_stb_i;
444
           3'd6: wb_stb_o = m6_stb_i;
445
           3'd7: wb_stb_o = m7_stb_i;
446
           default: wb_stb_o = 1'b0;
447
        endcase
448
 
449
assign m0_ack_o = (mast_sel==3'd0) & wb_ack_i;
450
assign m1_ack_o = (mast_sel==3'd1) & wb_ack_i;
451
assign m2_ack_o = (mast_sel==3'd2) & wb_ack_i;
452
assign m3_ack_o = (mast_sel==3'd3) & wb_ack_i;
453
assign m4_ack_o = (mast_sel==3'd4) & wb_ack_i;
454
assign m5_ack_o = (mast_sel==3'd5) & wb_ack_i;
455
assign m6_ack_o = (mast_sel==3'd6) & wb_ack_i;
456
assign m7_ack_o = (mast_sel==3'd7) & wb_ack_i;
457
 
458
assign m0_err_o = (mast_sel==3'd0) & wb_err_i;
459
assign m1_err_o = (mast_sel==3'd1) & wb_err_i;
460
assign m2_err_o = (mast_sel==3'd2) & wb_err_i;
461
assign m3_err_o = (mast_sel==3'd3) & wb_err_i;
462
assign m4_err_o = (mast_sel==3'd4) & wb_err_i;
463
assign m5_err_o = (mast_sel==3'd5) & wb_err_i;
464
assign m6_err_o = (mast_sel==3'd6) & wb_err_i;
465
assign m7_err_o = (mast_sel==3'd7) & wb_err_i;
466
 
467
assign m0_rty_o = (mast_sel==3'd0) & wb_rty_i;
468
assign m1_rty_o = (mast_sel==3'd1) & wb_rty_i;
469
assign m2_rty_o = (mast_sel==3'd2) & wb_rty_i;
470
assign m3_rty_o = (mast_sel==3'd3) & wb_rty_i;
471
assign m4_rty_o = (mast_sel==3'd4) & wb_rty_i;
472
assign m5_rty_o = (mast_sel==3'd5) & wb_rty_i;
473
assign m6_rty_o = (mast_sel==3'd6) & wb_rty_i;
474
assign m7_rty_o = (mast_sel==3'd7) & wb_rty_i;
475
//////////////////////////////////////////////////////////////////////////////////
476
//
477
// WB_CTI/WB_BTE addon
478
//  ==> based on WB_SEL logic
479
//
480
 
481
always @(*)
482
    case(mast_sel)  // synopsys parallel_case
483
        3'd0: wb_cti_o = m0_cti_i;
484
        3'd1: wb_cti_o = m1_cti_i;
485
        3'd2: wb_cti_o = m2_cti_i;
486
        3'd3: wb_cti_o = m3_cti_i;
487
        3'd4: wb_cti_o = m4_cti_i;
488
        3'd5: wb_cti_o = m5_cti_i;
489
        3'd6: wb_cti_o = m6_cti_i;
490
        3'd7: wb_cti_o = m7_cti_i;
491
        default: wb_cti_o = 3'b0;
492
    endcase
493
 
494
always @(*)
495
    case(mast_sel)  // synopsys parallel_case
496
        3'd0: wb_bte_o = m0_bte_i;
497
        3'd1: wb_bte_o = m1_bte_i;
498
        3'd2: wb_bte_o = m2_bte_i;
499
        3'd3: wb_bte_o = m3_bte_i;
500
        3'd4: wb_bte_o = m4_bte_i;
501
        3'd5: wb_bte_o = m5_bte_i;
502
        3'd6: wb_bte_o = m6_bte_i;
503
        3'd7: wb_bte_o = m7_bte_i;
504
        default: wb_bte_o = 2'b0;
505
    endcase
506
//////////////////////////////////////////////////////////////////////////////////
507
endmodule
508
 

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