Subversion Repositories pcie_ds_dma

/////////////////////////////////////////////////////////////////////

////                                                             ////

////  WISHBONE Connection Matrix Top Level                       ////

////                                                             ////

////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

////                                                             ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

////                         www.asics.ws                        ////

////                         rudi@asics.ws                       ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//

//  $Id: wb_conmax_top.v,v 1.2 2002-10-03 05:40:07 rudi Exp $

//

//  $Date: 2002-10-03 05:40:07 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Locker:  $

//  $State: Exp $

//

// Change History:

//               $Log: not supported by cvs2svn $

//               Revision 1.1.1.1  2001/10/19 11:01:38  rudi

//               WISHBONE CONMAX IP Core

//

//

/////////////////////////////////////////////////////////////////////

//

//  WB_CONMAX v1.1 (14.10.2011)

//  ==> Kuzmi4 addons:

//      1) add WB_BTE/WB_CTI cross-logic for "B4"  (WB_SEL cross-logic like reference, was MEGA-JOB)

//      2) Memory MAP ==> 4KB granularity (wb_conmax_master_if.v, Select Logic part)

//  

//  

//

//`include "wb_conmax_defines.v"

`timescale 1ns / 10ps

module wb_conmax_top(

        clk_i, rst_i,

        // Master 0 Interface

        m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i,

        m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o,

    m0_cti_i, m0_bte_i,

        // Master 1 Interface

        m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i,

        m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o,

    m1_cti_i, m1_bte_i,

        // Master 2 Interface

        m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i,

        m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o,

    m2_cti_i, m2_bte_i,

        // Master 3 Interface

        m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i,

        m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o,

    m3_cti_i, m3_bte_i,

        // Master 4 Interface

        m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i,

        m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o,

    m4_cti_i, m4_bte_i,

        // Master 5 Interface

        m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i,

        m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o,

    m5_cti_i, m5_bte_i,

        // Master 6 Interface

        m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i,

        m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o,

    m6_cti_i, m6_bte_i,

        // Master 7 Interface

        m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i,

        m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o,

    m7_cti_i, m7_bte_i,

        // Slave 0 Interface

        s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o,

        s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i,

    s0_cti_o, s0_bte_o,

        // Slave 1 Interface

        s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o,

        s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i,

    s1_cti_o, s1_bte_o,

        // Slave 2 Interface

        s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o,

        s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i,

    s2_cti_o, s2_bte_o,

        // Slave 3 Interface

        s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o,

        s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i,

    s3_cti_o, s3_bte_o,

        // Slave 4 Interface

        s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o,

        s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i,

    s4_cti_o, s4_bte_o,

        // Slave 5 Interface

        s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o,

        s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i,

    s5_cti_o, s5_bte_o,

        // Slave 6 Interface

        s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o,

        s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i,

    s6_cti_o, s6_bte_o,

        // Slave 7 Interface

        s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o,

        s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i,

    s7_cti_o, s7_bte_o,

        // Slave 8 Interface

        s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o,

        s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i,

    s8_cti_o, s8_bte_o,

        // Slave 9 Interface

        s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o,

        s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i,

    s9_cti_o, s9_bte_o,

        // Slave 10 Interface

        s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o,

        s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i,

    s10_cti_o, s10_bte_o,

        // Slave 11 Interface

        s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o,

        s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i,

    s11_cti_o, s11_bte_o,

        // Slave 12 Interface

        s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o,

        s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i,

    s12_cti_o, s12_bte_o,

        // Slave 13 Interface

        s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o,

        s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i,

    s13_cti_o, s13_bte_o,

        // Slave 14 Interface

        s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o,

        s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i,

    s14_cti_o, s14_bte_o,

        // Slave 15 Interface

        s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o,

        s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i,

    s15_cti_o, s15_bte_o

        );

////////////////////////////////////////////////////////////////////

//

// Module Parameters

//

parameter               dw       = 0;            // Data bus Width

parameter               aw       = 0;            // Address bus Width

parameter       [3:0]    rf_addr  = 4'hf;

parameter       [1:0]    pri_sel0 = 2'd2;

parameter       [1:0]    pri_sel1 = 2'd2;

parameter       [1:0]    pri_sel2 = 2'd2;

parameter       [1:0]    pri_sel3 = 2'd2;

parameter       [1:0]    pri_sel4 = 2'd2;

parameter       [1:0]    pri_sel5 = 2'd2;

parameter       [1:0]    pri_sel6 = 2'd2;

parameter       [1:0]    pri_sel7 = 2'd2;

parameter       [1:0]    pri_sel8 = 2'd2;

parameter       [1:0]    pri_sel9 = 2'd2;

parameter       [1:0]    pri_sel10 = 2'd2;

parameter       [1:0]    pri_sel11 = 2'd2;

parameter       [1:0]    pri_sel12 = 2'd2;

parameter       [1:0]    pri_sel13 = 2'd2;

parameter       [1:0]    pri_sel14 = 2'd2;

parameter       [1:0]    pri_sel15 = 2'd2;

parameter               sw = dw / 8;    // Number of Select Lines

////////////////////////////////////////////////////////////////////

//

// Module IOs

//

input           clk_i, rst_i;

// Master 0 Interface

input   [dw-1:0] m0_data_i;

output  [dw-1:0] m0_data_o;

input   [aw-1:0] m0_addr_i;

input   [sw-1:0] m0_sel_i;

input                   m0_we_i;

input                   m0_cyc_i;

input                   m0_stb_i;

output                  m0_ack_o;

output                  m0_err_o;

output                  m0_rty_o;

input   [2:0]   m0_cti_i;

input   [1:0]   m0_bte_i;

// Master 1 Interface

input   [dw-1:0] m1_data_i;

output  [dw-1:0] m1_data_o;

input   [aw-1:0] m1_addr_i;

input   [sw-1:0] m1_sel_i;

input                   m1_we_i;

input                   m1_cyc_i;

input                   m1_stb_i;

output                  m1_ack_o;

output                  m1_err_o;

output                  m1_rty_o;

input   [2:0]   m1_cti_i;

input   [1:0]   m1_bte_i;

// Master 2 Interface

input   [dw-1:0] m2_data_i;

output  [dw-1:0] m2_data_o;

input   [aw-1:0] m2_addr_i;

input   [sw-1:0] m2_sel_i;

input                   m2_we_i;

input                   m2_cyc_i;

input                   m2_stb_i;

output                  m2_ack_o;

output                  m2_err_o;

output                  m2_rty_o;

input   [2:0]   m2_cti_i;

input   [1:0]   m2_bte_i;

// Master 3 Interface

input   [dw-1:0] m3_data_i;

output  [dw-1:0] m3_data_o;

input   [aw-1:0] m3_addr_i;

input   [sw-1:0] m3_sel_i;

input                   m3_we_i;

input                   m3_cyc_i;

input                   m3_stb_i;

output                  m3_ack_o;

output                  m3_err_o;

output                  m3_rty_o;

input   [2:0]   m3_cti_i;

input   [1:0]   m3_bte_i;

// Master 4 Interface

input   [dw-1:0] m4_data_i;

output  [dw-1:0] m4_data_o;

input   [aw-1:0] m4_addr_i;

input   [sw-1:0] m4_sel_i;

input                   m4_we_i;

input                   m4_cyc_i;

input                   m4_stb_i;

output                  m4_ack_o;

output                  m4_err_o;

output                  m4_rty_o;

input   [2:0]   m4_cti_i;

input   [1:0]   m4_bte_i;

// Master 5 Interface

input   [dw-1:0] m5_data_i;

output  [dw-1:0] m5_data_o;

input   [aw-1:0] m5_addr_i;

input   [sw-1:0] m5_sel_i;

input                   m5_we_i;

input                   m5_cyc_i;

input                   m5_stb_i;

output                  m5_ack_o;

output                  m5_err_o;

output                  m5_rty_o;

input   [2:0]   m5_cti_i;

input   [1:0]   m5_bte_i;

// Master 6 Interface

input   [dw-1:0] m6_data_i;

output  [dw-1:0] m6_data_o;

input   [aw-1:0] m6_addr_i;

input   [sw-1:0] m6_sel_i;

input                   m6_we_i;

input                   m6_cyc_i;

input                   m6_stb_i;

output                  m6_ack_o;

output                  m6_err_o;

output                  m6_rty_o;

input   [2:0]   m6_cti_i;

input   [1:0]   m6_bte_i;

// Master 7 Interface

input   [dw-1:0] m7_data_i;

output  [dw-1:0] m7_data_o;

input   [aw-1:0] m7_addr_i;

input   [sw-1:0] m7_sel_i;

input                   m7_we_i;

input                   m7_cyc_i;

input                   m7_stb_i;

output                  m7_ack_o;

output                  m7_err_o;

output                  m7_rty_o;

input   [2:0]   m7_cti_i;

input   [1:0]   m7_bte_i;

// Slave 0 Interface

input   [dw-1:0] s0_data_i;

output  [dw-1:0] s0_data_o;

output  [aw-1:0] s0_addr_o;

output  [sw-1:0] s0_sel_o;

output                  s0_we_o;

output                  s0_cyc_o;

output                  s0_stb_o;

input                   s0_ack_i;

input                   s0_err_i;

input                   s0_rty_i;

output  [2:0]   s0_cti_o;

output  [1:0]   s0_bte_o;

// Slave 1 Interface

input   [dw-1:0] s1_data_i;

output  [dw-1:0] s1_data_o;

output  [aw-1:0] s1_addr_o;

output  [sw-1:0] s1_sel_o;

output                  s1_we_o;

output                  s1_cyc_o;

output                  s1_stb_o;

input                   s1_ack_i;

input                   s1_err_i;

input                   s1_rty_i;

output  [2:0]   s1_cti_o;

output  [1:0]   s1_bte_o;

// Slave 2 Interface

input   [dw-1:0] s2_data_i;

output  [dw-1:0] s2_data_o;

output  [aw-1:0] s2_addr_o;

output  [sw-1:0] s2_sel_o;

output                  s2_we_o;

output                  s2_cyc_o;

output                  s2_stb_o;

input                   s2_ack_i;

input                   s2_err_i;

input                   s2_rty_i;

output  [2:0]   s2_cti_o;

output  [1:0]   s2_bte_o;

// Slave 3 Interface

input   [dw-1:0] s3_data_i;

output  [dw-1:0] s3_data_o;

output  [aw-1:0] s3_addr_o;

output  [sw-1:0] s3_sel_o;

output                  s3_we_o;

output                  s3_cyc_o;

output                  s3_stb_o;

input                   s3_ack_i;

input                   s3_err_i;

input                   s3_rty_i;

output  [2:0]   s3_cti_o;

output  [1:0]   s3_bte_o;

// Slave 4 Interface

input   [dw-1:0] s4_data_i;

output  [dw-1:0] s4_data_o;

output  [aw-1:0] s4_addr_o;

output  [sw-1:0] s4_sel_o;

output                  s4_we_o;

output                  s4_cyc_o;

output                  s4_stb_o;

input                   s4_ack_i;

input                   s4_err_i;

input                   s4_rty_i;

output  [2:0]   s4_cti_o;

output  [1:0]   s4_bte_o;

// Slave 5 Interface

input   [dw-1:0] s5_data_i;

output  [dw-1:0] s5_data_o;

output  [aw-1:0] s5_addr_o;

output  [sw-1:0] s5_sel_o;

output                  s5_we_o;

output                  s5_cyc_o;

output                  s5_stb_o;

input                   s5_ack_i;

input                   s5_err_i;

input                   s5_rty_i;

output  [2:0]   s5_cti_o;

output  [1:0]   s5_bte_o;

// Slave 6 Interface

input   [dw-1:0] s6_data_i;

output  [dw-1:0] s6_data_o;

output  [aw-1:0] s6_addr_o;

output  [sw-1:0] s6_sel_o;

output                  s6_we_o;

output                  s6_cyc_o;

output                  s6_stb_o;

input                   s6_ack_i;

input                   s6_err_i;

input                   s6_rty_i;

output  [2:0]   s6_cti_o;

output  [1:0]   s6_bte_o;

// Slave 7 Interface

input   [dw-1:0] s7_data_i;

output  [dw-1:0] s7_data_o;

output  [aw-1:0] s7_addr_o;

output  [sw-1:0] s7_sel_o;

output                  s7_we_o;

output                  s7_cyc_o;

output                  s7_stb_o;

input                   s7_ack_i;

input                   s7_err_i;

input                   s7_rty_i;

output  [2:0]   s7_cti_o;

output  [1:0]   s7_bte_o;

// Slave 8 Interface

input   [dw-1:0] s8_data_i;

output  [dw-1:0] s8_data_o;

output  [aw-1:0] s8_addr_o;

output  [sw-1:0] s8_sel_o;

output                  s8_we_o;

output                  s8_cyc_o;

output                  s8_stb_o;

input                   s8_ack_i;

input                   s8_err_i;

input                   s8_rty_i;

output  [2:0]   s8_cti_o;

output  [1:0]   s8_bte_o;

// Slave 9 Interface

input   [dw-1:0] s9_data_i;

output  [dw-1:0] s9_data_o;

output  [aw-1:0] s9_addr_o;

output  [sw-1:0] s9_sel_o;

output                  s9_we_o;

output                  s9_cyc_o;

output                  s9_stb_o;

input                   s9_ack_i;

input                   s9_err_i;

input                   s9_rty_i;

output  [2:0]   s9_cti_o;

output  [1:0]   s9_bte_o;

// Slave 10 Interface

input   [dw-1:0] s10_data_i;

output  [dw-1:0] s10_data_o;

output  [aw-1:0] s10_addr_o;

output  [sw-1:0] s10_sel_o;

output                  s10_we_o;

output                  s10_cyc_o;

output                  s10_stb_o;

input                   s10_ack_i;

input                   s10_err_i;

input                   s10_rty_i;

output  [2:0]   s10_cti_o;

output  [1:0]   s10_bte_o;

// Slave 11 Interface

input   [dw-1:0] s11_data_i;

output  [dw-1:0] s11_data_o;

output  [aw-1:0] s11_addr_o;

output  [sw-1:0] s11_sel_o;

output                  s11_we_o;

output                  s11_cyc_o;

output                  s11_stb_o;

input                   s11_ack_i;

input                   s11_err_i;

input                   s11_rty_i;

output  [2:0]   s11_cti_o;

output  [1:0]   s11_bte_o;

// Slave 12 Interface

input   [dw-1:0] s12_data_i;

output  [dw-1:0] s12_data_o;

output  [aw-1:0] s12_addr_o;

output  [sw-1:0] s12_sel_o;

output                  s12_we_o;

output                  s12_cyc_o;

output                  s12_stb_o;

input                   s12_ack_i;

input                   s12_err_i;

input                   s12_rty_i;

output  [2:0]   s12_cti_o;

output  [1:0]   s12_bte_o;

// Slave 13 Interface

input   [dw-1:0] s13_data_i;

output  [dw-1:0] s13_data_o;

output  [aw-1:0] s13_addr_o;

output  [sw-1:0] s13_sel_o;

output                  s13_we_o;

output                  s13_cyc_o;

output                  s13_stb_o;

input                   s13_ack_i;

input                   s13_err_i;

input                   s13_rty_i;

output  [2:0]   s13_cti_o;

output  [1:0]   s13_bte_o;

// Slave 14 Interface

input   [dw-1:0] s14_data_i;

output  [dw-1:0] s14_data_o;

output  [aw-1:0] s14_addr_o;

output  [sw-1:0] s14_sel_o;

output                  s14_we_o;

output                  s14_cyc_o;

output                  s14_stb_o;

input                   s14_ack_i;

input                   s14_err_i;

input                   s14_rty_i;

output  [2:0]   s14_cti_o;

output  [1:0]   s14_bte_o;

// Slave 15 Interface

input   [dw-1:0] s15_data_i;

output  [dw-1:0] s15_data_o;

output  [aw-1:0] s15_addr_o;

output  [sw-1:0] s15_sel_o;

output                  s15_we_o;

output                  s15_cyc_o;

output                  s15_stb_o;

input                   s15_ack_i;

input                   s15_err_i;

input                   s15_rty_i;

output  [2:0]   s15_cti_o;

output  [1:0]   s15_bte_o;

////////////////////////////////////////////////////////////////////

//

// Local wires

//

wire    [dw-1:0] i_s15_data_i;

wire    [dw-1:0] i_s15_data_o;

wire    [aw-1:0] i_s15_addr_o;

wire    [sw-1:0] i_s15_sel_o;

wire                    i_s15_we_o;

wire                    i_s15_cyc_o;

wire                    i_s15_stb_o;

wire                    i_s15_ack_i;

wire                    i_s15_err_i;

wire                    i_s15_rty_i;

wire    [2:0]   i_s15_cti_o;

wire    [1:0]   i_s15_bte_o;

wire    [dw-1:0] m0s0_data_i;

wire    [dw-1:0] m0s0_data_o;

wire    [aw-1:0] m0s0_addr;

wire    [sw-1:0] m0s0_sel;

wire                    m0s0_we;

wire                    m0s0_cyc;

wire                    m0s0_stb;

wire                    m0s0_ack;

wire                    m0s0_err;

wire                    m0s0_rty;

wire    [2:0]   m0s0_cti;

wire    [1:0]   m0s0_bte;

wire    [dw-1:0] m0s1_data_i;

wire    [dw-1:0] m0s1_data_o;

wire    [aw-1:0] m0s1_addr;

wire    [sw-1:0] m0s1_sel;

wire                    m0s1_we;

wire                    m0s1_cyc;

wire                    m0s1_stb;

wire                    m0s1_ack;

wire                    m0s1_err;

wire                    m0s1_rty;

wire    [2:0]   m0s1_cti;

wire    [1:0]   m0s1_bte;

wire    [dw-1:0] m0s2_data_i;

wire    [dw-1:0] m0s2_data_o;

wire    [aw-1:0] m0s2_addr;

wire    [sw-1:0] m0s2_sel;

wire                    m0s2_we;

wire                    m0s2_cyc;

wire                    m0s2_stb;

wire                    m0s2_ack;

wire                    m0s2_err;

wire                    m0s2_rty;

wire    [2:0]   m0s2_cti;

wire    [1:0]   m0s2_bte;

wire    [dw-1:0] m0s3_data_i;

wire    [dw-1:0] m0s3_data_o;