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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_pb_wishbone_ctrl/] [sim/] [ds_dma_pb_if.v] - Blame information for rev 2

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1 2 dsmv 
//////////////////////////////////////////////////////////////////////////////////
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// Company:         ;)
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// Engineer:        Kuzmi4
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//
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// Create Date:     14:39:52 05/19/2010
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// Design Name:
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// Module Name:     ds_dma_pb_if
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// Project Name:    DS_DMA
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// Target Devices:  no
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// Tool versions:   any with SV support
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// Description:
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//
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//
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// Revision:
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// Revision 0.01 - File Created
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//
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//////////////////////////////////////////////////////////////////////////////////
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interface ds_dma_pb_if # ( parameter time pt_Tclk = 10ns, parameter time pt_Tdly = 1ns )
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(
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    input   i_clk
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);
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//////////////////////////////////////////////////////////////////////////////////
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    //
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    // B_MASTER (OUT dir) IF
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    logic               o_pb_master_stb0;   // CMD STB
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    logic               o_pb_master_stb1;   // DATA STB
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    logic       [ 2:0]  ov_pb_master_cmd;   // CMD
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    logic       [31:0]  ov_pb_master_addr;  // ADDR
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    logic       [63:0]  ov_pb_master_data;  // DATA
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    //
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    // PB_SLAVE (IN dir) IF:
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    logic               i_pb_slave_ready;
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    logic               i_pb_slave_complete;
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    logic               i_pb_slave_stb0;    // WR CMD ACK STB
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    logic               i_pb_slave_stb1;    // DATA ACK STB
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    logic       [63:0]  iv_pb_slave_data;   // DATA
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    logic       [ 1:0]  iv_pb_slave_dmar;   // ...
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    logic               i_pb_slave_irq;     // ...
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Define Clocking block:
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//
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default clocking cb @(posedge i_clk);
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    default input #(pt_Tdly) output #(pt_Tdly);
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    output o_pb_master_stb0, o_pb_master_stb1, ov_pb_master_cmd, ov_pb_master_addr, ov_pb_master_data;
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    input i_pb_slave_ready, i_pb_slave_complete, i_pb_slave_stb0, i_pb_slave_stb1, iv_pb_slave_data, iv_pb_slave_dmar, i_pb_slave_irq;
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endclocking
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Tasks:
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//
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// Init DATA_OUT
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task    init;
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    //
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    o_pb_master_stb0    <= 0;
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    o_pb_master_stb1    <= 0;
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    ov_pb_master_cmd    <= 0;
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    ov_pb_master_addr   <= 0;
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    ov_pb_master_data   <= 0;
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    //
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endtask
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//
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task write_1_word (input [31:0] iv_addr=0, input [63:0] iv_data=0);
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    //
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    @cb;
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    cb.o_pb_master_stb0     <= 1;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_addr    <= iv_addr;
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    cb.ov_pb_master_cmd     <= 3'b0_0_1;
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    @cb;
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 1;
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    cb.ov_pb_master_data    <= iv_data;
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    cb.ov_pb_master_cmd     <= 3'b0_0_1;
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    do
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        begin   :   PB_SLAVE_STB_0
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            ##1;
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            cb.o_pb_master_stb0     <= 0;
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            cb.o_pb_master_stb1     <= 0;
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            cb.ov_pb_master_data    <= 0;
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            cb.ov_pb_master_cmd     <= 3'b0;
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        end
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    while (cb.i_pb_slave_complete==0);
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    //
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endtask
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//
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task write_512_word (input [31:0] iv_addr=0, input [63:0] iv_start_data=0, input i_rnd=0);
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    //
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    int i=0, rdy_counter=0;
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    //
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    @cb;
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    cb.o_pb_master_stb0     <= 1;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_addr    <= iv_addr;
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    cb.ov_pb_master_cmd     <= 3'b1_0_1;
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    @cb;
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_cmd     <= 3'b1_0_1;
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    @cb;
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    //
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    do
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        begin   :   DATA
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            @cb;
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            if (cb.i_pb_slave_ready==0)
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                rdy_counter++;
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            else
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                rdy_counter=0;
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            if (rdy_counter < 4)
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                begin   :   DATA_OUT
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                    cb.o_pb_master_stb1     <= 1;
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                    cb.ov_pb_master_data    <= (i_rnd)? $urandom()/*$urandom_range()*/ : (iv_start_data+i);
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                    i++;
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                end
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            else
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                begin   :   DATA_HALT
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                    cb.o_pb_master_stb1     <= 0;
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                    cb.ov_pb_master_data    <= 0;
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                end
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        end
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    while (i<512+1);
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 0;
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    //
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endtask
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//
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task read_1_word(input [31:0] iv_addr, output logic [63:0] ov_data);
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    //
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    //
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    @cb;
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    cb.o_pb_master_stb0     <= 1;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_addr    <= iv_addr;
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    cb.ov_pb_master_cmd     <= 3'b0_1_0;
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    @cb;
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 1;
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    cb.ov_pb_master_cmd     <= 3'b0_1_0;
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    //
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    do
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        begin   :   PB_SLAVE_STB_0
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            @cb;
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            cb.o_pb_master_stb0     <= 0;
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            cb.o_pb_master_stb1     <= 0;
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            cb.ov_pb_master_cmd     <= 0;
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        end
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    while (cb.i_pb_slave_stb0==0);
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    //
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    do
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        begin   :   PB_SLAVE_STB_1
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            @cb;
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            if (cb.i_pb_slave_stb1)
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                ov_data = cb.iv_pb_slave_data;
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        end
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    while (cb.i_pb_slave_complete==0);
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    //
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endtask
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//
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task read_512_word (input [31:0] iv_addr, output [63:0] ov_data [512]);
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    //
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    int i=0;
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    //
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    @cb;
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    cb.o_pb_master_stb0     <= 1;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_addr    <= iv_addr;
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    cb.ov_pb_master_cmd     <= 3'b1_1_0;
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    @cb;
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_cmd     <= 3'b1_1_0;
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    //
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    do
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        begin   :   GET_DATA
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            @cb;
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            if (cb.i_pb_slave_stb1)
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                begin
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                    ov_data[i] <= cb.iv_pb_slave_data;
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                    i++;
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                end
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        end
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    while (cb.i_pb_slave_complete==0);
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    // CLR on EXIT
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    cb.o_pb_master_stb0     <= 0;
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    cb.o_pb_master_stb1     <= 0;
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    cb.ov_pb_master_cmd     <= 0;
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    //
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endtask
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Functions:
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//
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// for polling "iv_pb_slave_dmar"
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function automatic bit [1:0] get_pb_slave_dmar;
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    return cb.iv_pb_slave_dmar;
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endfunction
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// for polling "i_pb_slave_irq"
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function automatic bit get_pb_slave_irq;
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    return cb.i_pb_slave_irq;
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endfunction
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//////////////////////////////////////////////////////////////////////////////////
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endinterface

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