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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_pb_wishbone_ctrl/] [sim/] [wb_simple_ram_slave_if.v] - Blame information for rev 2

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1 2 dsmv 
/*
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  parameter int  pA_W  = 32 ;
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  parameter int  pD_W  = 32 ;
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  parameter int pSEL_W = 4 ;
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  logic                wb_tb_simple_ram_slave__clk    ;
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  logic                wb_tb_simple_ram_slave__rst    ;
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  logic                wb_tb_simple_ram_slave__cyc_i  ;
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  logic                wb_tb_simple_ram_slave__stb_i  ;
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  logic                wb_tb_simple_ram_slave__we_i   ;
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  logic   [pA_W-1 : 0] wb_tb_simple_ram_slave__adr_i  ;
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  logic   [pD_W-1 : 0] wb_tb_simple_ram_slave__dat_i  ;
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  logic [pSEL_W-1 : 0] wb_tb_simple_ram_slave__sel_i  ;
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  logic                wb_tb_simple_ram_slave__ack_o  ;
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  logic                wb_tb_simple_ram_slave__err_o  ;
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  logic                wb_tb_simple_ram_slave__rty_o  ;
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  logic   [pD_W-1 : 0] wb_tb_simple_ram_slave__dat_o  ;
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  wb_simple_ram_slave_if
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  #(
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    .pA_W   ( pA_W   ) ,
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    .pD_W   ( pD_W   ) ,
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    .pSEL_W ( pSEL_W )
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  )
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  wb_tb_simple_ram_slave
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  (
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    .clk   ( wb_tb_simple_ram_slave__clk   ) ,
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    .rst   ( wb_tb_simple_ram_slave__rst   ) ,
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    .cyc_i ( wb_tb_simple_ram_slave__cyc_i ) ,
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    .stb_i ( wb_tb_simple_ram_slave__stb_i ) ,
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    .we_i  ( wb_tb_simple_ram_slave__we_i  ) ,
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    .adr_i ( wb_tb_simple_ram_slave__adr_i ) ,
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    .dat_i ( wb_tb_simple_ram_slave__dat_i ) ,
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    .sel_i ( wb_tb_simple_ram_slave__sel_i ) ,
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    .ack_o ( wb_tb_simple_ram_slave__ack_o ) ,
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    .err_o ( wb_tb_simple_ram_slave__err_o ) ,
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    .rty_o ( wb_tb_simple_ram_slave__rty_o ) ,
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    .dat_o ( wb_tb_simple_ram_slave__dat_o )
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  );
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  assign wb_tb_simple_ram_slave__clk   = '0 ;
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  assign wb_tb_simple_ram_slave__rst   = '0 ;
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  assign wb_tb_simple_ram_slave__cyc_i = '0 ;
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  assign wb_tb_simple_ram_slave__stb_i = '0 ;
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  assign wb_tb_simple_ram_slave__we_i  = '0 ;
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  assign wb_tb_simple_ram_slave__adr_i = '0 ;
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  assign wb_tb_simple_ram_slave__dat_i = '0 ;
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  assign wb_tb_simple_ram_slave__sel_i = '0 ;
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*/
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//
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// this interface is for write/read debug only
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//
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interface wb_simple_ram_slave_if
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#(
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  parameter int pA_W   = 32 ,
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  parameter int pD_W   = 32 ,
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  parameter int pSEL_W = 4
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)
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(
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  input clk,
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  input rst
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);
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  //------------------------------------------------------------------------------------------------------
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  //
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  //------------------------------------------------------------------------------------------------------
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    logic                cyc_i ;
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    logic                stb_i ;
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    logic                we_i  ;
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    logic   [pA_W-1 : 0] adr_i ;
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    logic   [pD_W-1 : 0] dat_i ;
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    logic [pSEL_W-1 : 0] sel_i ;
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    logic                ack_o ;
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    logic                err_o ;
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    logic                rty_o ;
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    logic   [pD_W-1 : 0] dat_o ;
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  //------------------------------------------------------------------------------------------------------
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  //
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  //------------------------------------------------------------------------------------------------------
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  default clocking cb @(posedge clk);
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    default input #1ns output #1ns;
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    output ack_o, err_o, rty_o, dat_o;
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    input  cyc_i, stb_i, we_i, adr_i, dat_i, sel_i;
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  endclocking
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  //------------------------------------------------------------------------------------------------------
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  //
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  //------------------------------------------------------------------------------------------------------
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  bit [pD_W-1 : 0] ram [2**pA_W-1:0];
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  bit rnd = 0;  // use random wait states
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  int ws  = 1;  // wait states
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  int counter=0;
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  //------------------------------------------------------------------------------------------------------
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  //
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  //------------------------------------------------------------------------------------------------------
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  initial begin : ini
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    cb.ack_o <= 1'b0;
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    cb.err_o <= 1'b0;
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    cb.rty_o <= 1'b0;
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    cb.dat_o <= 1'b0;
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    run ();
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  end
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  bit tack;
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  assign #1ns tack = (cyc_i & stb_i);
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  task run ();
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    fork
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      forever begin
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        if (ws == 0) begin // ws == 0
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          force ack_o = tack;
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          wait (cyc_i);
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          //
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          if (rnd)
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            ws = $urandom_range(0, 5);
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          //
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          if (cyc_i & stb_i) begin
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            if (we_i)
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              ram[adr_i] = dat_i;
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            else
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              dat_o <= #1ns ++counter;// $urandom_range(0, 255);// ram[adr_i];
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          end
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          //
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          ##1;
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          release ack_o;
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        end // ws == 0
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        else begin // ws > 0
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          ##1;
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          if (cb.cyc_i & cb.stb_i) begin
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            ##(ws-1);
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            if (rnd)
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              ws = $urandom_range(0, 5);
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            if (cb.we_i)
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              ram[cb.adr_i] = cb.dat_i;
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            else
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              cb.dat_o <= ++counter;// ram[cb.adr_i];
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            cb.ack_o <= 1'b1;
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            ##1;
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            cb.ack_o <= 1'b0;
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          end // access
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        end // ws
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      end // forever
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    join_none
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  endtask
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  task stop ();
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    disable run ;
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  endtask
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endinterface

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