URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_pb_wishbone_ctrl/] [sim/] [zz_do/] [setup_sim.do] - Blame information for rev 2

Details | Compare with Previous | View Log


#
#
quit -sim
#
#
echo Cre WORK lib
if {[file exists "work"]} { vdel -all}
vlib work
 
#
#
echo Compile SRC:
vlog     -quiet ../../../../../src/pcie_src/components/rtl/core64_pb_wishbone_ctrl.v
vcom     -quiet ../../../../../src/pcie_src/components/coregen/ctrl_fifo512x64st_v0.vhd
 
#
#
vlog -sv -quiet tb.v
 
#
#
vsim -t ps -novopt -L unisims_ver work.tb
 
#
#
log -r /*
 
#
#
do wave.do
 
#
#
run -all

Line No.	Rev	Author	Line
1	2	dsmv	`#`
2			`#`
3			`quit -sim`
4			`#`
5			`#`
6			`echo Cre WORK lib`
7			`if {[file exists "work"]} { vdel -all}`
8			`vlib work`
9
10			`#`
11			`#`
12			`echo Compile SRC:`
13			`vlog -quiet ../../../../../src/pcie_src/components/rtl/core64_pb_wishbone_ctrl.v`
14			`vcom -quiet ../../../../../src/pcie_src/components/coregen/ctrl_fifo512x64st_v0.vhd`
15
16			`#`
17			`#`
18			`vlog -sv -quiet tb.v`
19
20			`#`
21			`#`
22			`vsim -t ps -novopt -L unisims_ver work.tb`
23
24			`#`
25			`#`
26			`log -r /*`
27
28			`#`
29			`#`
30			`do wave.do`
31
32			`#`
33			`#`
34			`run -all`

Browse

Tools

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_pb_wishbone_ctrl/] [sim/] [zz_do/] [setup_sim.do] - Blame information for rev 2