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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_test_gen/] [sim/] [zz_do/] [setup_sim.do] - Blame information for rev 2

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1 2 dsmv 
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quit -sim
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echo Cre WORK lib
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if {[file exists "work"]} { vdel -all}
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vlib work
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echo Compile SRC:
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vcom     -quiet ../../../../../src/pcie_src/components/rtl/host_pkg.vhd
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vcom     -quiet ../../../../../src/pcie_src/components/rtl/ctrl_ram16_v1.vhd
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vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd
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vlog     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_burst_slave.v
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vcom     -quiet ../../../../../src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd
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vcom     -quiet ../../../../../src/wishbone/block_test_generate/cl_test_generate.vhd
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vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_pkg.vhd
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vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_test_generate_wb.vhd
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vlog -sv -quiet tb.v
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vsim -t ps -novopt work.tb
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log -r /*
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do wave.do
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run -all

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