OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_test_gen/] [sim/] [zz_do/] [setup_sim.do] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dsmv
#
2
#
3
quit -sim
4
#
5
#
6
echo Cre WORK lib
7
if {[file exists "work"]} { vdel -all}
8
vlib work
9
 
10
#
11
#
12
echo Compile SRC:
13
vcom     -quiet ../../../../../src/pcie_src/components/rtl/host_pkg.vhd
14
vcom     -quiet ../../../../../src/pcie_src/components/rtl/ctrl_ram16_v1.vhd
15
vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd
16
 
17
vlog     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_burst_slave.v
18
vcom     -quiet ../../../../../src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd
19
 
20
vcom     -quiet ../../../../../src/wishbone/block_test_generate/cl_test_generate.vhd
21
 
22
vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_generate_wb_pkg.vhd
23
vcom     -quiet ../../../../../src/wishbone/block_test_generate/block_test_generate_wb.vhd
24
 
25
#
26
#
27
vlog -sv -quiet tb.v
28
 
29
#
30
#
31
vsim -t ps -novopt work.tb
32
 
33
#
34
#
35
log -r /*
36
 
37
#
38
#
39
do wave.do
40
 
41
#
42
#
43
run -all

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.