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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_wb_cross/] [sim/] [wb_intf.sv] - Blame information for rev 2

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1 2 dsmv
 
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interface wb_m_if
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#(
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  parameter int   pA_W = 32 ,
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  parameter int   pD_W = 32 ,
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  parameter int pSEL_W =  4
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)
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(
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  input wb_clk, wb_rst
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);
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  logic                cyc_o ;
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  logic                stb_o ;
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  logic                we_o  ;
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  logic   [pA_W-1 : 0] adr_o ;
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  logic   [pD_W-1 : 0] dat_o ;
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  logic [pSEL_W-1 : 0] sel_o ;
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  logic                ack_i ;
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  logic                err_i ;
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  logic                rty_i ;
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  logic   [pD_W-1 : 0] dat_i ;
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  default clocking cb @(posedge wb_clk);
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    default input #1ns output #1ns;
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    output cyc_o, stb_o, we_o, adr_o, dat_o, sel_o;
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    input ack_i, err_i, rty_i, dat_i;
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  endclocking
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  //------------------------------------------------------------------------------------------------------
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  // base drivers
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  //------------------------------------------------------------------------------------------------------
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  // init
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  task init ();
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    cyc_o <= '0;
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    stb_o <= '0;
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    we_o  <= '0;
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    adr_o <= '0;
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    dat_o <= '0;
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    sel_o <= '1;
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  endtask
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  //
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  // write
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  task write (output int err, input bit [pA_W-1 : 0] addr, input bit [pD_W-1 : 0] data, input int delay = 0, hold = 0);
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    cb.cyc_o <= 1'b1;
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    cb.stb_o <= 1'b1;
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    cb.we_o  <= 1'b1;
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    cb.adr_o <= addr;
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    cb.dat_o <= data; //$display("[%t]: %m, ps, adr_o==%h, dat_o==%h", $time, addr, data);
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    do
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      ##1;
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    while ((cb.ack_i | cb.err_i | cb.rty_i) != 1'b1);
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    err = {cb.err_i , cb.rty_i};
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    cb.cyc_o <= hold;
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    cb.stb_o <= 1'b0;
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    cb.we_o  <= 1'b0;
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    ##(delay); //$display("[%t]: %m, pe", $time);
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  endtask
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  task write_begin (output int err, input bit [pA_W-1 : 0] addr, input bit [pD_W-1 : 0] data, input int delay = 0);
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    write (err, addr, data, delay, 1); // hold bus
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  endtask
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  task write_end (output int err, input bit [pA_W-1 : 0] addr, input bit [pD_W-1 : 0] data, input int delay = 0);
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    write(err, addr, data, delay, 0); // free bus
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  endtask
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  //
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  // read
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  task read (output int err, output bit [pD_W-1 : 0] data, input bit [pA_W-1 : 0] addr, input int delay = 0, hold = 0);
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    cb.cyc_o <= 1'b1;
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    cb.stb_o <= 1'b1;
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    cb.we_o  <= 1'b0;
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    cb.adr_o <= addr;
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    do
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      ##1;
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    while ((cb.ack_i | cb.err_i | cb.rty_i) != 1'b1);
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    err     = {cb.err_i , cb.rty_i};
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    data    = cb.dat_i;
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    cb.cyc_o <= hold;
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    cb.stb_o <= 1'b0;
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    cb.we_o  <= 1'b0;
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    ##(delay);
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  endtask
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  task read_begin (output int err, output bit [pD_W-1 : 0] data, input bit [pA_W-1 : 0] addr, input int delay = 0);
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    read (err, data, addr, delay, 1);
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  endtask
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  task read_end (output int err, output bit [pD_W-1 : 0] data, input bit [pA_W-1 : 0] addr, input int delay = 0);
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    read (err, data, addr, delay, 0);
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  endtask
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endinterface
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