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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [testbecnh/] [dev_wb_cross/] [sim/] [wb_tb_simple_master.sv] - Blame information for rev 2

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1 2 dsmv
 
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typedef virtual interface wb_m_if#(lp_ADDR_W, lp_DATA_W, lp_SEL_W)  virt_wb_m_if_t;
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class wb_tb_simple_master;
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  static int id = 0;
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  static function int next_id();
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    next_id = ++id;
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  endfunction
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  string          name;
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  virt_wb_m_if_t  m_if;
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  function new (string name = "master", virt_wb_m_if_t  m_if );
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    string str;
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  begin
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    str.itoa(next_id());
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    this.name = {name, " " ,str};
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    this.m_if = m_if;
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  end
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  endfunction : new
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  //------------------------------------------------------------------------------------------------------
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  // task to generate data packet for ram
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  //------------------------------------------------------------------------------------------------------
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  bit [lp_DATA_W-1 : 0] data [];
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  task generate_data_packet (int length = 10);
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    data = new[length];
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    for (int i = 0; i < length; i++)
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      data[i] = i+$urandom_range(1,512);//$urandom;
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    //$display("[%t]: %m, length==%h", $time, length); //for (int i=0;i<5;i++) $display("[%t]: %m, data[i]==%h", $time, data[i]);
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  endtask
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  //------------------------------------------------------------------------------------------------------
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  //
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  //------------------------------------------------------------------------------------------------------
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  int max_ws  = 0;
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  int err_cnt = 0;
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  //
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  task init ();
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    m_if.init();
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    $display("%s ready", name);
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  endtask
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  //
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  function void log ();
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    $display("%s have %0d errors", name, err_cnt);
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  endfunction
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  //
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  task write_data_packet (input bit [lp_ADDR_W-1:0] start_addr, input int hold = 0, rnd = 0);
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    int addr;
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    int err;
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    int delay;
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  begin
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    //$display("[%t]: %m ps 1, data.size()==%h, hold==%b", $time, data.size(), hold);
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    for (int i = 0; i < data.size(); i++) begin
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      addr  = start_addr + i;
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      delay = rnd ? $urandom_range(0, max_ws) : max_ws;
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      if (hold) begin
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        if (i == (data.size()-1)) begin //$display("[%t]: %m 1", $time);
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            m_if.write_end(err, addr, data[i], delay); //$display("[%t]: %m 2", $time);
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          end
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        else begin //$display("[%t]: %m 3", $time);
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            m_if.write_begin(err, addr, data[i], delay); //$display("[%t]: %m 4", $time);
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          end
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      end
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      else begin //$display("[%t]: %m 5", $time);
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        m_if.write(err, addr, data[i], delay); //$display("[%t]: %m 6", $time);
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      end
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      assert (err == 0) else begin
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        $warning("%s bus error occured", name);
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        $stop;
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      end
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    end
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    //$display("[%t]: %m pe 1", $time);
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  end
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  endtask
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  task write_data_packet_nlocked (input bit [lp_ADDR_W-1:0] start_addr, input int rnd = 0);
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    write_data_packet (start_addr, 0, rnd);
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  endtask
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  task write_data_packet_locked (input bit [lp_ADDR_W-1:0] start_addr, input int rnd = 0);
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    write_data_packet (start_addr, 1, rnd);
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  endtask
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  //
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  task read_data_packet (input bit [lp_ADDR_W-1:0] start_addr, hold = 0, input int rnd = 0);
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    int addr;
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    int err;
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    int delay;
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    bit [lp_DATA_W-1 : 0] rd_data;
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  begin
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    for (int i = 0; i < data.size(); i++) begin
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      addr  = start_addr + i;
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      delay = rnd ? $urandom_range(0, max_ws) : max_ws;
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      if (hold) begin
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        if (i == (data.size()-1))
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          m_if.read_end(err, rd_data, addr, delay);
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        else
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          m_if.read_begin(err, rd_data, addr, delay);
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      end
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      else begin
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        m_if.read(err, rd_data, addr, delay);
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      end
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      assert (rd_data == data[i]) else begin
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        $error("%s slave reading bus error occured, rd_data != data[i] : i=%h, rd_data==%h, data[i]==%h", name, i, rd_data, data[i]); //#10ns; $stop;
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        err_cnt++;
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      end
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      assert (err == 0) else begin
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        $warning("%s bus error occured", name);
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        $stop;
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      end
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    end
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  end
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  endtask
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  task read_data_packet_nlocked (input bit [lp_ADDR_W-1:0] start_addr, input int rnd = 0);
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    read_data_packet (start_addr, 0, rnd);
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  endtask
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  task read_data_packet_locked (input bit [lp_ADDR_W-1:0] start_addr, input int rnd = 0);
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    read_data_packet (start_addr, 1, rnd);
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  endtask
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endclass

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