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---------------------------------------------------------------------------------------------------
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--
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-- Title : test_pkg.vhd
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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--
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-- Version : 1.0
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Ïàêåò äëÿ òåñòèðîâàíèÿ ambpex5.
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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library work;
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use work.cmd_sim_pkg.all;
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use work.block_pkg.all;
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use work.wb_block_pkg.all;
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package test_pkg is
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--! Initialising
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procedure test_init(
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fname: in string --! file name for report
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);
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--! Finished
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procedure test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Read block_test_check 8 kB
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procedure test_adm_read_8kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
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--procedure test_block_main (
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! answer
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-- );
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--
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----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
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--procedure test_adm_read_16kb (
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! answer
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-- );
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--
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--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
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procedure test_adm_write_16kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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---------------------------------------------------------------------------------------------------
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--
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--
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--
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procedure test_num_1(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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procedure test_num_2(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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-- ==> TEST_CHECK.WB_CFG_SLAVE
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procedure test_wb_1(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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-- ==> TEST_GEN.WB_CFG_SLAVE
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procedure test_wb_2(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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end package test_pkg;
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---------------------------------------------------------------------------------------------------
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package body test_pkg is
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FILE log: text;
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shared variable cnt_ok, cnt_error: integer;
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-- Initialising
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procedure test_init(
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fname: in string
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) is
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begin
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file_open( log, fname, WRITE_MODE );
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cnt_ok:=0;
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cnt_error:=0;
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end test_init;
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--! Finished
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procedure test_close is
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variable str : LINE; -- pointer to string
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begin
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std.textio.write( str, string'(" " ));
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writeline( log, str );
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writeline( log, str );
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write( str, string'("check completed" ));
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writeline( log, str );
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write( str, string'("the number of successful tests: " ));
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write( str, cnt_ok );
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writeline( log, str );
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write( str, string'("the number of false test: " ));
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write( str, cnt_error );
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writeline( log, str );
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file_close( log );
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if( cnt_ok>0 and cnt_error=0 ) then
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write( str, string'("TEST finished successfully") );
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writeline( output, str );
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else
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write( str, string'("TEST finished with ERR") );
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writeline( output, str );
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end if;
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end test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data1 : std_logic_vector( 31 downto 0 );
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variable data2 : std_logic_vector( 31 downto 0 );
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variable str : line;
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begin
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write( str, string'("TEST_READ_REG" ));
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
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wait for 100 ns;
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--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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wb_read( cmd, ret, 16#1000#, data1 );
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wb_read( cmd, ret, 16#3000#, data1 );
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write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE
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wait for 100 ns;
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
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wait for 100 ns;
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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end test_read_reg;
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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dsmv |
)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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begin
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write( str, string'("TEST_DSC_INCORRECT" ));
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
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wait for 100 ns;
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---- Init block of descriptor ---
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"03020100" );
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int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" );
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---- DMA program ----
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block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 15 downto 0 )=x"A021" ) then
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write( str, string'(" - Ok" ));
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cnt_ok := cnt_ok + 1;
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else
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write( str, string'(" - Error" ));
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cnt_error := cnt_error + 1;
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end if;
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writeline( log, str );
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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end test_dsc_incorrect;
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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16 |
dsmv |
)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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variable error : integer:=0;
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variable dma_complete : integer;
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begin
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write( str, string'("TEST_READ_4KB" ));
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
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wait for 100 ns;
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---- Init block of descriptor ---
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"00008000" );
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int_mem_write( cmd, ret, x"00100004", x"00000100" );
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int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001FC", x"762C4953" );
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--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
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write( str, string'("BLOCK TEST_GEN ID: " ));
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hwrite( str, data );
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writeline( log, str );
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
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---- DMA program ----
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block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - without request
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
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wait for 1 us;
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 8 )='1' ) then
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write( str, string'(" - descriptor is correct" ));
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else
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write( str, string'(" - descriptor is incorrect" ));
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error := error + 1;
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end if;
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writeline( log, str );
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|
355 |
|
|
if( error=0 ) then
|
356 |
|
|
|
357 |
|
|
---- Wait for DMA finished ----
|
358 |
|
|
dma_complete := 0;
|
359 |
|
|
for ii in 0 to 100 loop
|
360 |
|
|
|
361 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
362 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
363 |
|
|
if( data(5)='1' ) then
|
364 |
|
|
write( str, string'(" - DMA finished " ));
|
365 |
|
|
dma_complete := 1;
|
366 |
|
|
end if;
|
367 |
|
|
writeline( log, str );
|
368 |
|
|
|
369 |
|
|
if( dma_complete=1 ) then
|
370 |
|
|
exit;
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
wait for 1 us;
|
374 |
|
|
|
375 |
|
|
end loop;
|
376 |
|
|
|
377 |
|
|
writeline( log, str );
|
378 |
|
|
|
379 |
|
|
if( dma_complete=0 ) then
|
380 |
|
|
write( str, string'("Error - DMA not finished" ));
|
381 |
|
|
writeline( log, str );
|
382 |
|
|
error:=error+1;
|
383 |
|
|
end if;
|
384 |
|
|
|
385 |
|
|
end if;
|
386 |
|
|
|
387 |
|
|
for ii in 0 to 3 loop
|
388 |
|
|
|
389 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
390 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
391 |
|
|
writeline( log, str );
|
392 |
|
|
wait for 500 ns;
|
393 |
|
|
|
394 |
|
|
end loop;
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
398 |
|
|
|
399 |
|
|
write( str, string'(" Read: " ));
|
400 |
|
|
writeline( log, str );
|
401 |
|
|
|
402 |
|
|
for ii in 0 to 15 loop
|
403 |
|
|
|
404 |
|
|
adr:= x"00800000";
|
405 |
|
|
adr:=adr + ii*4;
|
406 |
|
|
int_mem_read( cmd, ret, adr, data );
|
407 |
|
|
|
408 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
409 |
|
|
writeline( log, str );
|
410 |
|
|
|
411 |
|
|
end loop;
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
415 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
416 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
writeline( log, str );
|
420 |
|
|
if( error=0 ) then
|
421 |
|
|
write( str, string'("Test is correct" ));
|
422 |
|
|
cnt_ok := cnt_ok + 1;
|
423 |
|
|
else
|
424 |
|
|
write( str, string'("Test have ERRORS" ));
|
425 |
|
|
cnt_error := cnt_error + 1;
|
426 |
|
|
end if;
|
427 |
|
|
writeline( log, str );
|
428 |
|
|
writeline( log, str );
|
429 |
|
|
|
430 |
|
|
end test_read_4kb;
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
--! Read block_test_check 8 kB
|
434 |
|
|
procedure test_adm_read_8kb (
|
435 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
436 |
|
|
signal ret: in bh_ret --! answer
|
437 |
16 |
dsmv |
)
|
438 |
|
|
is
|
439 |
|
|
|
440 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
441 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
442 |
|
|
variable str : line;
|
443 |
|
|
|
444 |
|
|
variable error : integer:=0;
|
445 |
29 |
dsmv |
variable dma_complete : integer;
|
446 |
16 |
dsmv |
|
447 |
29 |
dsmv |
variable status : std_logic_vector( 31 downto 0 );
|
448 |
|
|
variable reg_block_wr : std_logic_vector( 31 downto 0 );
|
449 |
|
|
|
450 |
16 |
dsmv |
begin
|
451 |
|
|
|
452 |
|
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
453 |
|
|
writeline( log, str );
|
454 |
|
|
|
455 |
21 |
dsmv |
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
456 |
|
|
wait for 100 ns;
|
457 |
|
|
|
458 |
16 |
dsmv |
---- Init block of descriptor ---
|
459 |
|
|
for ii in 0 to 127 loop
|
460 |
|
|
adr:= x"00100000";
|
461 |
|
|
adr:=adr + ii*4;
|
462 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
463 |
|
|
end loop;
|
464 |
|
|
|
465 |
|
|
--- Desctriptor 0 ---
|
466 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
467 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- jump to next descriptor
|
468 |
|
|
|
469 |
|
|
--- Desctriptor 1 ---
|
470 |
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
471 |
|
|
int_mem_write( cmd, ret, x"0010000C", x"00000110" ); -- stop
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
475 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
476 |
|
|
|
477 |
|
|
|
478 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
479 |
29 |
dsmv |
block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
|
480 |
|
|
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
481 |
16 |
dsmv |
|
482 |
29 |
dsmv |
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
|
483 |
|
|
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
|
484 |
|
|
block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
|
485 |
16 |
dsmv |
|
486 |
|
|
|
487 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
|
488 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
|
489 |
|
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
|
490 |
|
|
write( str, string'("BLOCK TEST_GEN ID: " ));
|
491 |
|
|
hwrite( str, data );
|
492 |
|
|
writeline( log, str );
|
493 |
|
|
|
494 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
|
495 |
|
|
|
496 |
29 |
dsmv |
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
|
497 |
16 |
dsmv |
|
498 |
29 |
dsmv |
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
|
499 |
|
|
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
|
500 |
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
|
501 |
|
|
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
|
502 |
|
|
|
503 |
|
|
|
504 |
16 |
dsmv |
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
|
505 |
|
|
|
506 |
|
|
wait for 20 us;
|
507 |
|
|
|
508 |
29 |
dsmv |
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
509 |
16 |
dsmv |
|
510 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
511 |
|
|
if( data( 8 )='1' ) then
|
512 |
|
|
write( str, string'(" - descriptor is correct" ));
|
513 |
|
|
else
|
514 |
|
|
write( str, string'(" - descriptor is incorrect" ));
|
515 |
|
|
error := error + 1;
|
516 |
|
|
end if;
|
517 |
|
|
|
518 |
|
|
writeline( log, str );
|
519 |
|
|
|
520 |
|
|
if( error=0 ) then
|
521 |
|
|
|
522 |
|
|
---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
523 |
|
|
dma_complete := 0;
|
524 |
|
|
for ii in 0 to 100 loop
|
525 |
|
|
|
526 |
29 |
dsmv |
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
527 |
16 |
dsmv |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
528 |
|
|
if( data(5)='1' ) then
|
529 |
|
|
write( str, string'(" - DMA finished " ));
|
530 |
|
|
dma_complete := 1;
|
531 |
|
|
|
532 |
29 |
dsmv |
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
|
533 |
16 |
dsmv |
|
534 |
|
|
end if;
|
535 |
|
|
writeline( log, str );
|
536 |
|
|
|
537 |
|
|
if( dma_complete=1 ) then
|
538 |
|
|
exit;
|
539 |
|
|
end if;
|
540 |
|
|
|
541 |
|
|
wait for 1 us;
|
542 |
|
|
|
543 |
|
|
end loop;
|
544 |
|
|
|
545 |
|
|
writeline( log, str );
|
546 |
|
|
|
547 |
|
|
if( dma_complete=0 ) then
|
548 |
|
|
write( str, string'("Error - DMA not finished " ));
|
549 |
|
|
writeline( log, str );
|
550 |
|
|
error:=error+1;
|
551 |
|
|
end if;
|
552 |
|
|
|
553 |
29 |
dsmv |
end if;
|
554 |
16 |
dsmv |
|
555 |
29 |
dsmv |
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
|
556 |
|
|
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
|
557 |
|
|
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
|
558 |
|
|
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
|
559 |
|
|
|
560 |
|
|
|
561 |
16 |
dsmv |
for ii in 0 to 3 loop
|
562 |
|
|
|
563 |
29 |
dsmv |
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
564 |
16 |
dsmv |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
565 |
|
|
writeline( log, str );
|
566 |
|
|
wait for 500 ns;
|
567 |
|
|
|
568 |
|
|
end loop;
|
569 |
|
|
|
570 |
|
|
|
571 |
29 |
dsmv |
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
|
572 |
16 |
dsmv |
|
573 |
|
|
write( str, string'(" Block 0 - read: " ));
|
574 |
|
|
writeline( log, str );
|
575 |
|
|
|
576 |
|
|
for ii in 0 to 15 loop
|
577 |
|
|
|
578 |
|
|
adr:= x"00800000";
|
579 |
|
|
adr:=adr + ii*4;
|
580 |
|
|
int_mem_read( cmd, ret, adr, data );
|
581 |
|
|
|
582 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
583 |
|
|
writeline( log, str );
|
584 |
|
|
|
585 |
|
|
end loop;
|
586 |
|
|
|
587 |
|
|
writeline( log, str );
|
588 |
|
|
|
589 |
|
|
write( str, string'(" Block 1 - read: " ));
|
590 |
|
|
writeline( log, str );
|
591 |
|
|
|
592 |
|
|
for ii in 0 to 15 loop
|
593 |
|
|
|
594 |
|
|
adr:= x"00801000";
|
595 |
|
|
adr:=adr + ii*4;
|
596 |
|
|
int_mem_read( cmd, ret, adr, data );
|
597 |
|
|
|
598 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
599 |
|
|
writeline( log, str );
|
600 |
|
|
|
601 |
|
|
end loop;
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
605 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
606 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
607 |
|
|
|
608 |
|
|
|
609 |
|
|
writeline( log, str );
|
610 |
|
|
if( error=0 ) then
|
611 |
|
|
write( str, string'(" Test is correct " ));
|
612 |
|
|
cnt_ok := cnt_ok + 1;
|
613 |
|
|
else
|
614 |
|
|
write( str, string'(" Test have ERRORS " ));
|
615 |
|
|
cnt_error := cnt_error + 1;
|
616 |
|
|
end if;
|
617 |
|
|
writeline( log, str );
|
618 |
|
|
writeline( log, str );
|
619 |
|
|
|
620 |
|
|
end test_adm_read_8kb;
|
621 |
|
|
--
|
622 |
|
|
--
|
623 |
|
|
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
|
624 |
|
|
--procedure test_block_main (
|
625 |
18 |
dsmv |
-- signal cmd: out bh_cmd; --! command
|
626 |
|
|
-- signal ret: in bh_ret --! answer
|
627 |
16 |
dsmv |
-- )
|
628 |
|
|
--is
|
629 |
|
|
--
|
630 |
|
|
--variable adr : std_logic_vector( 31 downto 0 );
|
631 |
|
|
--variable data : std_logic_vector( 31 downto 0 );
|
632 |
|
|
--variable str : line;
|
633 |
|
|
--
|
634 |
|
|
--variable error : integer:=0;
|
635 |
|
|
--variable dma_complete : integer;
|
636 |
|
|
--
|
637 |
|
|
--begin
|
638 |
|
|
--
|
639 |
|
|
-- write( str, string'("TEST_BLOCK_MAIN" ));
|
640 |
|
|
-- writeline( log, str );
|
641 |
|
|
--
|
642 |
|
|
-- block_read( cmd, ret, 4, 16#00#, data );
|
643 |
|
|
-- write( str, string'("ÁËÎÊ 4: " )); hwrite( str, data ); writeline( log, str );
|
644 |
|
|
--
|
645 |
|
|
-- wait for 10 us;
|
646 |
|
|
--
|
647 |
|
|
---- write( str, "Êîíñòàíòû:" );
|
648 |
|
|
---- writeline( log, str );
|
649 |
|
|
---- for ii in 0 to 5 loop
|
650 |
|
|
---- write( str, "Áëîê " );
|
651 |
|
|
---- write( str, ii );
|
652 |
|
|
---- for jj in 0 to 7 loop
|
653 |
|
|
---- block_read( cmd, ret, ii, jj, data );
|
654 |
|
|
---- write( str, " " );
|
655 |
|
|
---- hwrite( str, data );
|
656 |
|
|
---- end loop;
|
657 |
|
|
---- writeline( log, str );
|
658 |
|
|
---- end loop;
|
659 |
|
|
----
|
660 |
|
|
----
|
661 |
|
|
---- writeline( log, str );
|
662 |
|
|
----
|
663 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
664 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
665 |
|
|
----
|
666 |
|
|
---- block_write( cmd, ret, 80, 16#08#, x"00000100" );
|
667 |
|
|
----
|
668 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
669 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
670 |
|
|
----
|
671 |
|
|
---- block_write( cmd, ret, 80, 16#08#, x"00000200" );
|
672 |
|
|
----
|
673 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
674 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
675 |
|
|
----
|
676 |
|
|
----
|
677 |
|
|
---- writeline( log, str );
|
678 |
|
|
---- if( error=0 ) then
|
679 |
|
|
---- write( str, " Òåñò çàâåðø¸í óñïåøíî " );
|
680 |
|
|
---- cnt_ok := cnt_ok + 1;
|
681 |
|
|
---- else
|
682 |
|
|
---- write( str, " Òåñò íå âûïîëíåí " );
|
683 |
|
|
---- cnt_error := cnt_error + 1;
|
684 |
|
|
---- end if;
|
685 |
|
|
--
|
686 |
|
|
-- for ii in 0 to 127 loop
|
687 |
|
|
--
|
688 |
|
|
-- block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
689 |
|
|
-- block_read( cmd, ret, 4, 8, data );
|
690 |
|
|
-- write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
|
691 |
|
|
-- if( data/=x"0000AA55" ) then
|
692 |
|
|
-- error:=error+1;
|
693 |
|
|
-- end if;
|
694 |
|
|
--
|
695 |
|
|
-- end loop;
|
696 |
|
|
--
|
697 |
|
|
--
|
698 |
|
|
--
|
699 |
|
|
--
|
700 |
|
|
-- writeline( log, str );
|
701 |
|
|
-- writeline( log, str );
|
702 |
|
|
--
|
703 |
|
|
--end test_block_main;
|
704 |
|
|
--
|
705 |
|
|
--
|
706 |
|
|
--
|
707 |
|
|
--
|
708 |
|
|
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
|
709 |
|
|
--procedure test_adm_read_16kb (
|
710 |
18 |
dsmv |
-- signal cmd: out bh_cmd; --! command
|
711 |
|
|
-- signal ret: in bh_ret --! answer
|
712 |
16 |
dsmv |
-- )
|
713 |
|
|
--is
|
714 |
|
|
--
|
715 |
|
|
--variable adr : std_logic_vector( 31 downto 0 );
|
716 |
|
|
--variable data : std_logic_vector( 31 downto 0 );
|
717 |
|
|
--variable str : line;
|
718 |
|
|
--
|
719 |
|
|
--variable error : integer:=0;
|
720 |
|
|
--variable dma_complete : integer;
|
721 |
|
|
--variable kk : integer;
|
722 |
|
|
--variable status : std_logic_vector( 15 downto 0 );
|
723 |
|
|
--
|
724 |
|
|
--begin
|
725 |
|
|
--
|
726 |
|
|
-- write( str, string'("TEST_ADM_READ_16KB" ));
|
727 |
|
|
-- writeline( log, str );
|
728 |
|
|
--
|
729 |
|
|
-- ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
730 |
|
|
-- for ii in 0 to 256 loop
|
731 |
|
|
-- adr:= x"00100000";
|
732 |
|
|
-- adr:=adr + ii*4;
|
733 |
|
|
-- int_mem_write( cmd, ret, adr, x"00000000" );
|
734 |
|
|
-- end loop;
|
735 |
|
|
--
|
736 |
|
|
-- --- Áëîê 0 ---
|
737 |
|
|
--
|
738 |
|
|
-- --- Äåñêðèïòîð 0 ---
|
739 |
|
|
-- int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
740 |
|
|
-- int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
741 |
|
|
--
|
742 |
|
|
-- --- Äåñêðèïòîð 1 ---
|
743 |
|
|
-- int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
744 |
|
|
-- int_mem_write( cmd, ret, x"0010000C", x"00000112" ); -- ïåðåõîä ê ñëåäóþùåìó áëîêó
|
745 |
|
|
--
|
746 |
|
|
-- --- Äåñêðèïòîð 2 ---
|
747 |
|
|
-- int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
|
748 |
|
|
-- int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
749 |
|
|
--
|
750 |
|
|
--
|
751 |
|
|
-- int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
752 |
|
|
-- int_mem_write( cmd, ret, x"001001FC", x"14644953" );
|
753 |
|
|
--
|
754 |
|
|
--
|
755 |
|
|
-- --- Áëîê 1 ---
|
756 |
|
|
--
|
757 |
|
|
-- --- Äåñêðèïòîð 0 ---
|
758 |
|
|
-- int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
759 |
|
|
-- int_mem_write( cmd, ret, x"00100204", x"00000111" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
760 |
|
|
--
|
761 |
|
|
-- --- Äåñêðèïòîð 1 ---
|
762 |
|
|
-- int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
763 |
|
|
-- int_mem_write( cmd, ret, x"0010020C", x"00000110" ); -- îñòàíîâêà
|
764 |
|
|
--
|
765 |
|
|
--
|
766 |
|
|
-- int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
767 |
|
|
-- int_mem_write( cmd, ret, x"001003FC", x"D67C4953" );
|
768 |
|
|
--
|
769 |
|
|
--
|
770 |
|
|
--
|
771 |
|
|
-- ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
772 |
|
|
-- block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
773 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
774 |
|
|
--
|
775 |
|
|
-- block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
776 |
|
|
-- block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
777 |
|
|
-- block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
778 |
|
|
--
|
779 |
|
|
--
|
780 |
|
|
-- ---- Ïîäãîòîâêà òåòðàäû ----
|
781 |
|
|
-- trd_test_mode( cmd, ret, 0 ); -- ïåðåõîä â ðàáî÷èé ðåæèì --
|
782 |
|
|
-- trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - îò òåòðàäû 6 --
|
783 |
|
|
--
|
784 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Ðàçìåð áëîêà = 4 êÁ --
|
785 |
|
|
--
|
786 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
787 |
|
|
--
|
788 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
|
789 |
|
|
--
|
790 |
|
|
-- trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- çàïóñê òåòðàäû DIO_IN
|
791 |
|
|
--
|
792 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" ); -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
|
793 |
|
|
--
|
794 |
|
|
-- wait for 20 us;
|
795 |
|
|
--
|
796 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
797 |
|
|
--
|
798 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
799 |
|
|
-- if( data( 8 )='1' ) then
|
800 |
|
|
-- write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
|
801 |
|
|
-- else
|
802 |
|
|
-- write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
|
803 |
|
|
-- error := error + 1;
|
804 |
|
|
-- end if;
|
805 |
|
|
--
|
806 |
|
|
-- writeline( log, str );
|
807 |
|
|
--
|
808 |
|
|
-- if( error=0 ) then
|
809 |
|
|
--
|
810 |
|
|
-- kk:=0;
|
811 |
|
|
-- loop
|
812 |
|
|
--
|
813 |
|
|
-- trd_status( cmd, ret, 6, status );
|
814 |
|
|
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
815 |
|
|
--
|
816 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
817 |
|
|
-- write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
818 |
|
|
--
|
819 |
|
|
-- if( data(4)='1' ) then
|
820 |
|
|
-- write( str, string'(" - çàâåðøåíî ÷òåíèå áëîêà " ));
|
821 |
|
|
-- block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
822 |
|
|
-- kk:=kk+1;
|
823 |
|
|
-- if( kk=4 ) then
|
824 |
|
|
-- exit;
|
825 |
|
|
-- end if;
|
826 |
|
|
-- end if;
|
827 |
|
|
-- writeline( log, str );
|
828 |
|
|
--
|
829 |
|
|
-- wait for 500 ns;
|
830 |
|
|
--
|
831 |
|
|
--
|
832 |
|
|
-- end loop;
|
833 |
|
|
--
|
834 |
|
|
-- ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
835 |
|
|
-- dma_complete := 0;
|
836 |
|
|
-- for ii in 0 to 100 loop
|
837 |
|
|
--
|
838 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
839 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
840 |
|
|
-- if( data(5)='1' ) then
|
841 |
|
|
-- write( str, string'(" - DMA çàâåðø¸í " ));
|
842 |
|
|
-- dma_complete := 1;
|
843 |
|
|
--
|
844 |
|
|
-- block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
845 |
|
|
--
|
846 |
|
|
-- end if;
|
847 |
|
|
-- writeline( log, str );
|
848 |
|
|
--
|
849 |
|
|
-- if( dma_complete=1 ) then
|
850 |
|
|
-- exit;
|
851 |
|
|
-- end if;
|
852 |
|
|
--
|
853 |
|
|
-- wait for 1 us;
|
854 |
|
|
--
|
855 |
|
|
-- end loop;
|
856 |
|
|
--
|
857 |
|
|
-- writeline( log, str );
|
858 |
|
|
--
|
859 |
|
|
-- if( dma_complete=0 ) then
|
860 |
|
|
-- write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
|
861 |
|
|
-- writeline( log, str );
|
862 |
|
|
-- error:=error+1;
|
863 |
|
|
-- end if;
|
864 |
|
|
--
|
865 |
|
|
-- end if;
|
866 |
|
|
--
|
867 |
|
|
-- for ii in 0 to 3 loop
|
868 |
|
|
--
|
869 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
870 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
871 |
|
|
-- writeline( log, str );
|
872 |
|
|
-- wait for 500 ns;
|
873 |
|
|
--
|
874 |
|
|
-- end loop;
|
875 |
|
|
--
|
876 |
|
|
--
|
877 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
878 |
|
|
--
|
879 |
|
|
-- write( str, string'(" Áëîê 0 - ïðî÷èòàíî: " ));
|
880 |
|
|
-- writeline( log, str );
|
881 |
|
|
--
|
882 |
|
|
-- for ii in 0 to 15 loop
|
883 |
|
|
--
|
884 |
|
|
-- adr:= x"00800000";
|
885 |
|
|
-- adr:=adr + ii*4;
|
886 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
887 |
|
|
--
|
888 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
889 |
|
|
-- writeline( log, str );
|
890 |
|
|
--
|
891 |
|
|
-- end loop;
|
892 |
|
|
--
|
893 |
|
|
-- writeline( log, str );
|
894 |
|
|
--
|
895 |
|
|
-- write( str, string'(" Áëîê 1 - ïðî÷èòàíî: " ));
|
896 |
|
|
-- writeline( log, str );
|
897 |
|
|
--
|
898 |
|
|
-- for ii in 0 to 15 loop
|
899 |
|
|
--
|
900 |
|
|
-- adr:= x"00801000";
|
901 |
|
|
-- adr:=adr + ii*4;
|
902 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
903 |
|
|
--
|
904 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
905 |
|
|
-- writeline( log, str );
|
906 |
|
|
--
|
907 |
|
|
-- end loop;
|
908 |
|
|
--
|
909 |
|
|
-- write( str, string'(" Áëîê 2 - ïðî÷èòàíî: " ));
|
910 |
|
|
-- writeline( log, str );
|
911 |
|
|
--
|
912 |
|
|
-- for ii in 0 to 15 loop
|
913 |
|
|
--
|
914 |
|
|
-- adr:= x"00802000";
|
915 |
|
|
-- adr:=adr + ii*4;
|
916 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
917 |
|
|
--
|
918 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
919 |
|
|
-- writeline( log, str );
|
920 |
|
|
--
|
921 |
|
|
-- end loop;
|
922 |
|
|
--
|
923 |
|
|
--
|
924 |
|
|
-- write( str, string'(" Áëîê 3 - ïðî÷èòàíî: " ));
|
925 |
|
|
-- writeline( log, str );
|
926 |
|
|
--
|
927 |
|
|
-- for ii in 0 to 15 loop
|
928 |
|
|
--
|
929 |
|
|
-- adr:= x"00803000";
|
930 |
|
|
-- adr:=adr + ii*4;
|
931 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
932 |
|
|
--
|
933 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
934 |
|
|
-- writeline( log, str );
|
935 |
|
|
--
|
936 |
|
|
-- end loop;
|
937 |
|
|
--
|
938 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
939 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
940 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
941 |
|
|
--
|
942 |
|
|
--
|
943 |
|
|
-- writeline( log, str );
|
944 |
|
|
-- if( error=0 ) then
|
945 |
|
|
-- write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
|
946 |
|
|
-- cnt_ok := cnt_ok + 1;
|
947 |
|
|
-- else
|
948 |
|
|
-- write( str, string'(" Òåñò íå âûïîëíåí " ));
|
949 |
|
|
-- cnt_error := cnt_error + 1;
|
950 |
|
|
-- end if;
|
951 |
|
|
-- writeline( log, str );
|
952 |
|
|
-- writeline( log, str );
|
953 |
|
|
--
|
954 |
|
|
--end test_adm_read_16kb;
|
955 |
|
|
--
|
956 |
|
|
--
|
957 |
|
|
--
|
958 |
|
|
--
|
959 |
|
|
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
|
960 |
|
|
procedure test_adm_write_16kb (
|
961 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
962 |
|
|
signal ret: in bh_ret --! answer
|
963 |
16 |
dsmv |
)
|
964 |
|
|
is
|
965 |
|
|
|
966 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
967 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
968 |
|
|
variable str : line;
|
969 |
|
|
|
970 |
|
|
variable error : integer:=0;
|
971 |
|
|
variable dma_complete : integer;
|
972 |
|
|
variable kk : integer;
|
973 |
|
|
variable status : std_logic_vector( 15 downto 0 );
|
974 |
|
|
|
975 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
976 |
|
|
variable data64n : std_logic_vector( 63 downto 0 );
|
977 |
|
|
|
978 |
|
|
begin
|
979 |
|
|
|
980 |
|
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
981 |
|
|
writeline( log, str );
|
982 |
|
|
|
983 |
21 |
dsmv |
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
|
984 |
|
|
wait for 100 ns;
|
985 |
|
|
|
986 |
16 |
dsmv |
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
987 |
|
|
for ii in 0 to 256 loop
|
988 |
|
|
adr:= x"00100000";
|
989 |
|
|
adr:=adr + ii*4;
|
990 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
991 |
|
|
end loop;
|
992 |
|
|
|
993 |
|
|
|
994 |
|
|
data64 :=x"0000000000000000";
|
995 |
|
|
data64n := not data64;
|
996 |
|
|
|
997 |
|
|
---- Çàïîëíåíèå áëîêà 0 ----
|
998 |
|
|
adr:= x"00800000";
|
999 |
|
|
data:=x"A5A50123";
|
1000 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1001 |
|
|
adr:=adr + 4;
|
1002 |
|
|
|
1003 |
|
|
data:=x"00000000";
|
1004 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1005 |
|
|
adr:=adr + 4;
|
1006 |
|
|
|
1007 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1008 |
|
|
adr:=adr + 4;
|
1009 |
|
|
|
1010 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1011 |
|
|
adr:=adr + 4;
|
1012 |
|
|
|
1013 |
|
|
data64:=data64 + 1;
|
1014 |
|
|
data64n := not data64;
|
1015 |
|
|
|
1016 |
|
|
for ii in 0 to 254 loop
|
1017 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
1018 |
|
|
adr:=adr + 4;
|
1019 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
1020 |
|
|
adr:=adr + 4;
|
1021 |
|
|
|
1022 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1023 |
|
|
adr:=adr + 4;
|
1024 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1025 |
|
|
adr:=adr + 4;
|
1026 |
|
|
|
1027 |
|
|
data64:=data64 + 1;
|
1028 |
|
|
data64n := not data64;
|
1029 |
|
|
|
1030 |
|
|
end loop;
|
1031 |
|
|
|
1032 |
|
|
---- Çàïîëíåíèå áëîêà 1 ----
|
1033 |
|
|
adr:= x"00801000";
|
1034 |
|
|
data:=x"A5A50123";
|
1035 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1036 |
|
|
adr:=adr + 4;
|
1037 |
|
|
|
1038 |
|
|
data:=x"00000001";
|
1039 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1040 |
|
|
adr:=adr + 4;
|
1041 |
|
|
|
1042 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1043 |
|
|
adr:=adr + 4;
|
1044 |
|
|
|
1045 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1046 |
|
|
adr:=adr + 4;
|
1047 |
|
|
|
1048 |
|
|
data64:=data64 + 1;
|
1049 |
|
|
data64n := not data64;
|
1050 |
|
|
|
1051 |
|
|
for ii in 0 to 254 loop
|
1052 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
1053 |
|
|
adr:=adr + 4;
|
1054 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
1055 |
|
|
adr:=adr + 4;
|
1056 |
|
|
|
1057 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1058 |
|
|
adr:=adr + 4;
|
1059 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1060 |
|
|
adr:=adr + 4;
|
1061 |
|
|
|
1062 |
|
|
data64:=data64 + 1;
|
1063 |
|
|
data64n := not data64;
|
1064 |
|
|
|
1065 |
|
|
end loop;
|
1066 |
|
|
|
1067 |
|
|
---- Çàïîëíåíèå áëîêà 2 ----
|
1068 |
|
|
adr:= x"00802000";
|
1069 |
|
|
data:=x"A5A50123";
|
1070 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1071 |
|
|
adr:=adr + 4;
|
1072 |
|
|
|
1073 |
|
|
data:=x"00000002";
|
1074 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1075 |
|
|
adr:=adr + 4;
|
1076 |
|
|
|
1077 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1078 |
|
|
adr:=adr + 4;
|
1079 |
|
|
|
1080 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1081 |
|
|
adr:=adr + 4;
|
1082 |
|
|
|
1083 |
|
|
data64:=data64 + 1;
|
1084 |
|
|
data64n := not data64;
|
1085 |
|
|
|
1086 |
|
|
for ii in 0 to 254 loop
|
1087 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
1088 |
|
|
adr:=adr + 4;
|
1089 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
1090 |
|
|
adr:=adr + 4;
|
1091 |
|
|
|
1092 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1093 |
|
|
adr:=adr + 4;
|
1094 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1095 |
|
|
adr:=adr + 4;
|
1096 |
|
|
|
1097 |
|
|
data64:=data64 + 1;
|
1098 |
|
|
data64n := not data64;
|
1099 |
|
|
|
1100 |
|
|
end loop;
|
1101 |
|
|
|
1102 |
|
|
---- Çàïîëíåíèå áëîêà 3 ----
|
1103 |
|
|
adr:= x"00803000";
|
1104 |
|
|
data:=x"A5A50123";
|
1105 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1106 |
|
|
adr:=adr + 4;
|
1107 |
|
|
|
1108 |
|
|
data:=x"00000003";
|
1109 |
|
|
int_mem_write( cmd, ret, adr, data );
|
1110 |
|
|
adr:=adr + 4;
|
1111 |
|
|
|
1112 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1113 |
|
|
adr:=adr + 4;
|
1114 |
|
|
|
1115 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1116 |
|
|
adr:=adr + 4;
|
1117 |
|
|
|
1118 |
|
|
data64:=data64 + 1;
|
1119 |
|
|
data64n := not data64;
|
1120 |
|
|
|
1121 |
|
|
for ii in 0 to 254 loop
|
1122 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
1123 |
|
|
adr:=adr + 4;
|
1124 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
1125 |
|
|
adr:=adr + 4;
|
1126 |
|
|
|
1127 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
1128 |
|
|
adr:=adr + 4;
|
1129 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
1130 |
|
|
adr:=adr + 4;
|
1131 |
|
|
|
1132 |
|
|
data64:=data64 + 1;
|
1133 |
|
|
data64n := not data64;
|
1134 |
|
|
|
1135 |
|
|
end loop;
|
1136 |
|
|
-- for ii in 0 to 256 loop
|
1137 |
|
|
-- adr:= x"00802000";
|
1138 |
|
|
-- adr:=adr + ii*4;
|
1139 |
|
|
-- data:=x"00A20000";
|
1140 |
|
|
-- data:=data + ii;
|
1141 |
|
|
-- int_mem_write( cmd, ret, adr, data );
|
1142 |
|
|
-- end loop;
|
1143 |
|
|
--
|
1144 |
|
|
-- for ii in 0 to 256 loop
|
1145 |
|
|
-- adr:= x"00803000";
|
1146 |
|
|
-- adr:=adr + ii*4;
|
1147 |
|
|
-- data:=x"00A30000";
|
1148 |
|
|
-- data:=data + ii;
|
1149 |
|
|
-- int_mem_write( cmd, ret, adr, data );
|
1150 |
|
|
-- end loop;
|
1151 |
|
|
|
1152 |
|
|
--- Áëîê 0 ---
|
1153 |
|
|
|
1154 |
|
|
--- Äåñêðèïòîð 0 ---
|
1155 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
1156 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000011" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
1157 |
|
|
|
1158 |
|
|
--- Äåñêðèïòîð 1 ---
|
1159 |
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
1160 |
|
|
int_mem_write( cmd, ret, x"0010000C", x"00000012" ); -- ïåðåõîä ê ñëåäóþùåìó áëîêó
|
1161 |
|
|
|
1162 |
|
|
--- Äåñêðèïòîð 2 ---
|
1163 |
|
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
|
1164 |
|
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
1165 |
|
|
|
1166 |
|
|
|
1167 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
1168 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"14A44953" );
|
1169 |
|
|
|
1170 |
|
|
|
1171 |
|
|
--- Áëîê 1 ---
|
1172 |
|
|
|
1173 |
|
|
--- Äåñêðèïòîð 0 ---
|
1174 |
|
|
int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
1175 |
|
|
int_mem_write( cmd, ret, x"00100204", x"00000011" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
1176 |
|
|
|
1177 |
|
|
--- Äåñêðèïòîð 1 ---
|
1178 |
|
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
1179 |
|
|
int_mem_write( cmd, ret, x"0010020C", x"00000010" ); -- îñòàíîâêà
|
1180 |
|
|
|
1181 |
|
|
|
1182 |
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
1183 |
|
|
int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" );
|
1184 |
|
|
|
1185 |
|
|
|
1186 |
|
|
|
1187 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
1188 |
|
|
block_write( cmd, ret, 5, 8, x"00000023" ); -- DMA_MODE - ñ çàïðîñàìè
|
1189 |
|
|
--block_write( cmd, ret, 5, 8, x"00000021" ); -- DMA_MODE - áåç çàïðîñîâ
|
1190 |
|
|
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
1191 |
|
|
|
1192 |
|
|
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
|
1193 |
|
|
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
|
1194 |
|
|
block_write( cmd, ret, 5, 23, x"00001000" ); -- LOCAL_ADR
|
1195 |
|
|
|
1196 |
|
|
|
1197 |
|
|
---- Ïîäãîòîâêà òåòðàäû ----
|
1198 |
|
|
-- trd_test_mode( cmd, ret, 0 ); -- ïåðåõîä â ðàáî÷èé ðåæèì --
|
1199 |
|
|
-- trd_wait_cmd( cmd, ret, 0, 16, x"1700" ); -- DMAR0 - îò òåòðàäû 7 --
|
1200 |
|
|
--
|
1201 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" ); -- Ðàçìåð áëîêà = 4 êÁ --
|
1202 |
|
|
|
1203 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000001" ); -- ñáðîñ
|
1204 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
|
1205 |
|
|
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data ); -- ÷òåíèå èäåíòèôèêàòîðà áëîêà
|
1206 |
|
|
write( str, string'("BLOCK TEST_CHECK ID: " ));
|
1207 |
|
|
hwrite( str, data );
|
1208 |
|
|
writeline( log, str );
|
1209 |
|
|
|
1210 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_SIZE, x"00000001" ); -- ðàçìåð áëîêà - 1 êèëîáàéò
|
1211 |
|
|
|
1212 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"000006A0" ); -- çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè
|
1213 |
|
|
--
|
1214 |
|
|
--
|
1215 |
|
|
--
|
1216 |
|
|
data:=wb_block_check_burst_ctrl_build('1', 40, 473);
|
1217 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
|
1218 |
|
|
--
|
1219 |
|
|
--
|
1220 |
|
|
--
|
1221 |
|
|
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
|
1222 |
|
|
|
1223 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
|
1224 |
|
|
--
|
1225 |
|
|
-- trd_wait_cmd( cmd, ret, 7, 0, x"2038" ); -- çàïóñê òåòðàäû DIO_OUT
|
1226 |
|
|
--
|
1227 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" ); -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
|
1228 |
|
|
|
1229 |
|
|
wait for 20 us;
|
1230 |
|
|
|
1231 |
|
|
|
1232 |
|
|
for ii in 0 to 20 loop
|
1233 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
1234 |
|
|
|
1235 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1236 |
|
|
if( data( 8 )='1' ) then
|
1237 |
|
|
write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
|
1238 |
|
|
error := 0;
|
1239 |
|
|
exit;
|
1240 |
|
|
else
|
1241 |
|
|
write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
|
1242 |
|
|
error := error + 1;
|
1243 |
|
|
wait for 10 us;
|
1244 |
|
|
end if;
|
1245 |
|
|
|
1246 |
|
|
writeline( log, str );
|
1247 |
|
|
end loop;
|
1248 |
|
|
|
1249 |
|
|
|
1250 |
|
|
if( error=0 ) then
|
1251 |
|
|
|
1252 |
|
|
kk:=0;
|
1253 |
|
|
loop
|
1254 |
|
|
|
1255 |
|
|
-- trd_status( cmd, ret, 6, status );
|
1256 |
|
|
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
1257 |
|
|
|
1258 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
1259 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1260 |
|
|
|
1261 |
|
|
if( data(4)='1' ) then
|
1262 |
|
|
write( str, string'(" - çàâåðøåíà ïåðåäà÷à áëîêà " ));
|
1263 |
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
1264 |
|
|
kk:=kk+1;
|
1265 |
|
|
if( kk=4 ) then
|
1266 |
|
|
exit;
|
1267 |
|
|
end if;
|
1268 |
|
|
end if;
|
1269 |
|
|
writeline( log, str );
|
1270 |
|
|
|
1271 |
|
|
wait for 500 ns;
|
1272 |
|
|
|
1273 |
|
|
|
1274 |
|
|
end loop;
|
1275 |
|
|
|
1276 |
|
|
---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
1277 |
|
|
dma_complete := 0;
|
1278 |
|
|
for ii in 0 to 100 loop
|
1279 |
|
|
|
1280 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
1281 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1282 |
|
|
|
1283 |
|
|
if( data(4)='1' ) then
|
1284 |
|
|
write( str, string'(" - çàâåðø¸íà ïåðåäà÷à áëîêà " ));
|
1285 |
|
|
|
1286 |
|
|
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
1287 |
|
|
|
1288 |
|
|
end if;
|
1289 |
|
|
writeline( log, str );
|
1290 |
|
|
|
1291 |
|
|
|
1292 |
|
|
if( data(5)='1' ) then
|
1293 |
|
|
write( str, string'(" - DMA çàâåðø¸í " ));
|
1294 |
|
|
dma_complete := 1;
|
1295 |
|
|
|
1296 |
|
|
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
1297 |
|
|
|
1298 |
|
|
end if;
|
1299 |
|
|
writeline( log, str );
|
1300 |
|
|
|
1301 |
|
|
if( dma_complete=1 ) then
|
1302 |
|
|
exit;
|
1303 |
|
|
end if;
|
1304 |
|
|
|
1305 |
|
|
wait for 1 us;
|
1306 |
|
|
|
1307 |
|
|
end loop;
|
1308 |
|
|
|
1309 |
|
|
writeline( log, str );
|
1310 |
|
|
|
1311 |
|
|
if( dma_complete=0 ) then
|
1312 |
|
|
write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
|
1313 |
|
|
writeline( log, str );
|
1314 |
|
|
error:=error+1;
|
1315 |
|
|
end if;
|
1316 |
|
|
|
1317 |
|
|
end if;
|
1318 |
|
|
|
1319 |
|
|
for ii in 0 to 3 loop
|
1320 |
|
|
|
1321 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
1322 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1323 |
|
|
writeline( log, str );
|
1324 |
|
|
wait for 500 ns;
|
1325 |
|
|
|
1326 |
|
|
end loop;
|
1327 |
|
|
|
1328 |
|
|
wait for 10 us;
|
1329 |
|
|
|
1330 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
|
1331 |
|
|
write( str, string'( "Ïðèíÿòî áëîêîâ: " ) );
|
1332 |
|
|
hwrite( str, data );
|
1333 |
|
|
kk := conv_integer( data );
|
1334 |
|
|
if( 4/=kk ) then
|
1335 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
1336 |
|
|
error := error + 1;
|
1337 |
|
|
else
|
1338 |
|
|
write( str, string'( " - Ok" ) );
|
1339 |
|
|
end if;
|
1340 |
|
|
writeline( log, str );
|
1341 |
|
|
|
1342 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
|
1343 |
|
|
write( str, string'( "TEST_CHECK_BL_OK: " ) );
|
1344 |
|
|
hwrite( str, data );
|
1345 |
|
|
kk := conv_integer( data );
|
1346 |
|
|
if( 3/=kk ) then
|
1347 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
1348 |
|
|
error := error + 1;
|
1349 |
|
|
else
|
1350 |
|
|
write( str, string'( " - Ok" ) );
|
1351 |
|
|
end if;
|
1352 |
|
|
writeline( log, str );
|
1353 |
|
|
|
1354 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
|
1355 |
|
|
write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
|
1356 |
|
|
hwrite( str, data );
|
1357 |
|
|
kk := conv_integer( data );
|
1358 |
|
|
if( 0/=kk ) then
|
1359 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
1360 |
|
|
error := error + 1;
|
1361 |
|
|
else
|
1362 |
|
|
write( str, string'( " - Ok" ) );
|
1363 |
|
|
end if;
|
1364 |
|
|
writeline( log, str );
|
1365 |
|
|
|
1366 |
|
|
|
1367 |
|
|
|
1368 |
|
|
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
|
1369 |
|
|
|
1370 |
|
|
|
1371 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
1372 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
1373 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
1374 |
|
|
|
1375 |
|
|
|
1376 |
|
|
writeline( log, str );
|
1377 |
|
|
if( error=0 ) then
|
1378 |
|
|
write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
|
1379 |
|
|
cnt_ok := cnt_ok + 1;
|
1380 |
|
|
else
|
1381 |
|
|
write( str, string'(" Òåñò íå âûïîëíåí " ));
|
1382 |
|
|
cnt_error := cnt_error + 1;
|
1383 |
|
|
end if;
|
1384 |
|
|
writeline( log, str );
|
1385 |
|
|
writeline( log, str );
|
1386 |
|
|
|
1387 |
|
|
end test_adm_write_16kb;
|
1388 |
|
|
---------------------------------------------------------------------------------------------------
|
1389 |
|
|
--
|
1390 |
|
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
1391 |
|
|
--
|
1392 |
|
|
procedure test_num_1 (
|
1393 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
1394 |
|
|
signal ret: in bh_ret --! answer
|
1395 |
16 |
dsmv |
) is
|
1396 |
|
|
|
1397 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
1398 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
1399 |
|
|
variable str : line;
|
1400 |
|
|
|
1401 |
|
|
variable error : integer:=0;
|
1402 |
|
|
variable dma_complete : integer:=0;
|
1403 |
|
|
|
1404 |
|
|
begin
|
1405 |
|
|
-- Init Header
|
1406 |
|
|
write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
|
1407 |
|
|
writeline( log, str );
|
1408 |
|
|
--
|
1409 |
|
|
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
1410 |
|
|
for ii in 0 to 127 loop
|
1411 |
|
|
adr:= x"00100000";
|
1412 |
|
|
adr:=adr + ii*4;
|
1413 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
1414 |
|
|
end loop;
|
1415 |
|
|
-- HOST MEM Writes:
|
1416 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
|
1417 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
|
1418 |
|
|
|
1419 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
|
1420 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
|
1421 |
|
|
--
|
1422 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ---- PE_EXT_FIFO module: have bug in PE_EXT_FIFO, for check WB we will make a trick:
|
1423 |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
|
1424 |
|
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
1425 |
|
|
|
1426 |
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
1427 |
|
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
1428 |
|
|
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
|
1429 |
|
|
|
1430 |
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
1431 |
|
|
--
|
1432 |
|
|
-- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
|
1433 |
|
|
wait for 1 us;
|
1434 |
|
|
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
|
1435 |
|
|
--
|
1436 |
|
|
-- Delay for design
|
1437 |
|
|
wait for 20 us;
|
1438 |
|
|
--
|
1439 |
|
|
-- Read STATUS
|
1440 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1441 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
|
1442 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1443 |
|
|
if( data( 8 )='1' ) then
|
1444 |
|
|
write( str, string'(" - Descriptor==OK" ));
|
1445 |
|
|
else
|
1446 |
|
|
write( str, string'(" - Descriptor RD ERR" ));
|
1447 |
|
|
error := error + 1;
|
1448 |
|
|
end if;
|
1449 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1450 |
|
|
--
|
1451 |
|
|
-- Deal with STATUS Results:
|
1452 |
|
|
if( error=0 ) then -- w8ing for DMA final
|
1453 |
|
|
dma_complete := 0;
|
1454 |
|
|
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
|
1455 |
|
|
-- Read STATUS
|
1456 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1457 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
|
1458 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1459 |
|
|
if( data(5)='1' ) then
|
1460 |
|
|
write( str, string'(" - DMA finished" ));
|
1461 |
|
|
dma_complete := 1;
|
1462 |
|
|
end if;
|
1463 |
|
|
writeline( log, str );
|
1464 |
|
|
-- Check "dma_complete"
|
1465 |
|
|
if( dma_complete=1 ) then
|
1466 |
|
|
exit; -- EXIT Loop on FINAL
|
1467 |
|
|
else
|
1468 |
|
|
wait for 1 us; -- DELAY in other case
|
1469 |
|
|
end if;
|
1470 |
|
|
end loop;
|
1471 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1472 |
|
|
|
1473 |
|
|
if( dma_complete=0 ) then -- check "dma_complete" after all
|
1474 |
|
|
write( str, string'("ERR - DMA not finished " ));
|
1475 |
|
|
writeline( log, str );
|
1476 |
|
|
error:=error+1;
|
1477 |
|
|
end if;
|
1478 |
|
|
|
1479 |
|
|
end if;
|
1480 |
|
|
--
|
1481 |
|
|
-- Print STATUS now
|
1482 |
|
|
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
|
1483 |
|
|
-- Read STATUS
|
1484 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1485 |
|
|
-- Construct LOG MSG in accordance to STATUS value
|
1486 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1487 |
|
|
-- upd LOGFILE
|
1488 |
|
|
writeline( log, str );
|
1489 |
|
|
wait for 500 ns;
|
1490 |
|
|
end loop;
|
1491 |
|
|
--
|
1492 |
|
|
-- Now STOP Design
|
1493 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
1494 |
|
|
--
|
1495 |
|
|
-- Now print RX values:
|
1496 |
|
|
--
|
1497 |
|
|
-- Construct Header:
|
1498 |
|
|
writeline( log, str );
|
1499 |
|
|
write( str, string'("PRINT 1st 15 RX values: " ));
|
1500 |
|
|
writeline( log, str );
|
1501 |
|
|
-- Get first 15 DATA values and print it:
|
1502 |
|
|
for ii in 0 to 15 loop
|
1503 |
|
|
adr:= x"00800000"; -- init ADDR value
|
1504 |
|
|
adr:=adr + ii*4; -- upd addr to curr idx
|
1505 |
|
|
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
|
1506 |
|
|
-- Construct LOG MSG in accordance to HOST MEM Read value
|
1507 |
|
|
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
1508 |
|
|
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
|
1509 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1510 |
|
|
end loop;
|
1511 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1512 |
|
|
--
|
1513 |
|
|
-- Final CHECK errors:
|
1514 |
|
|
if( error=0 ) then
|
1515 |
|
|
write( str, string'("SUCCSESSFULL FINAL " ));
|
1516 |
|
|
cnt_ok := cnt_ok + 1;
|
1517 |
|
|
else
|
1518 |
|
|
write( str, string'("FAILED FINAL " ));
|
1519 |
|
|
cnt_error := cnt_error + 1;
|
1520 |
|
|
end if;
|
1521 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1522 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1523 |
|
|
--
|
1524 |
|
|
-- END
|
1525 |
|
|
end test_num_1;
|
1526 |
|
|
--
|
1527 |
|
|
--
|
1528 |
|
|
--
|
1529 |
|
|
procedure test_num_2 (
|
1530 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
1531 |
|
|
signal ret: in bh_ret --! answer
|
1532 |
16 |
dsmv |
) is
|
1533 |
|
|
|
1534 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
1535 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
1536 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
1537 |
|
|
variable str : line;
|
1538 |
|
|
|
1539 |
|
|
variable error : integer:=0;
|
1540 |
|
|
variable dma_complete : integer:=0;
|
1541 |
|
|
|
1542 |
|
|
begin
|
1543 |
|
|
-- Init Header
|
1544 |
|
|
write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
|
1545 |
|
|
writeline( log, str );
|
1546 |
|
|
--
|
1547 |
|
|
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
1548 |
|
|
for ii in 0 to 127 loop
|
1549 |
|
|
adr:= x"00100000";
|
1550 |
|
|
adr:=adr + ii*4;
|
1551 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
1552 |
|
|
end loop;
|
1553 |
|
|
-- HOST MEM Writes:
|
1554 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
|
1555 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
|
1556 |
|
|
|
1557 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
|
1558 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
|
1559 |
|
|
--
|
1560 |
|
|
-- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
|
1561 |
|
|
adr :=x"20002048"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
|
1562 |
|
|
data64 :=x"0000000000000001"; -- TEST_GEN_SIZE=x01
|
1563 |
|
|
data_write64(cmd, ret, adr, data64);-- PCIE WR
|
1564 |
|
|
|
1565 |
|
|
adr :=x"20002040"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
|
1566 |
|
|
data64 :=x"0000000000000022"; -- TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
|
1567 |
|
|
data_write64(cmd, ret, adr, data64);-- PCIE WR
|
1568 |
|
|
|
1569 |
|
|
-- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
|
1570 |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
|
1571 |
|
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
1572 |
|
|
|
1573 |
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
1574 |
|
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
1575 |
|
|
block_write( cmd, ret, 4, 23, x"00003000" ); -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
|
1576 |
|
|
|
1577 |
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
1578 |
|
|
--
|
1579 |
|
|
-- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
|
1580 |
|
|
wait for 1 us;
|
1581 |
|
|
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
|
1582 |
|
|
--
|
1583 |
|
|
-- Delay for design
|
1584 |
|
|
wait for 20 us;
|
1585 |
|
|
--
|
1586 |
|
|
-- Read STATUS (check RD DESCR status):
|
1587 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1588 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
|
1589 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1590 |
|
|
if( data( 8 )='1' ) then
|
1591 |
|
|
write( str, string'(" - Descriptor==OK" ));
|
1592 |
|
|
else
|
1593 |
|
|
write( str, string'(" - Descriptor RD ERR" ));
|
1594 |
|
|
error := error + 1;
|
1595 |
|
|
end if;
|
1596 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1597 |
|
|
--
|
1598 |
|
|
-- W8ing for DMA finish:
|
1599 |
|
|
if( error=0 ) then -- w8ing for DMA final
|
1600 |
|
|
dma_complete := 0;
|
1601 |
|
|
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
|
1602 |
|
|
-- Read STATUS
|
1603 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1604 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
|
1605 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1606 |
|
|
if( data(5)='1' ) then
|
1607 |
|
|
write( str, string'(" - DMA finished" ));
|
1608 |
|
|
dma_complete := 1;
|
1609 |
|
|
end if;
|
1610 |
|
|
writeline( log, str );
|
1611 |
|
|
-- Check "dma_complete"
|
1612 |
|
|
if( dma_complete=1 ) then
|
1613 |
|
|
exit; -- EXIT Loop on FINAL
|
1614 |
|
|
else
|
1615 |
|
|
wait for 1 us; -- DELAY in other case
|
1616 |
|
|
end if;
|
1617 |
|
|
end loop;
|
1618 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1619 |
|
|
|
1620 |
|
|
if( dma_complete=0 ) then -- check "dma_complete" after all
|
1621 |
|
|
write( str, string'("ERR - DMA not finished " ));
|
1622 |
|
|
writeline( log, str );
|
1623 |
|
|
error:=error+1;
|
1624 |
|
|
end if;
|
1625 |
|
|
|
1626 |
|
|
end if;
|
1627 |
|
|
--
|
1628 |
|
|
-- Print STATUS in ERR
|
1629 |
|
|
if (error /= 0 ) then
|
1630 |
|
|
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
|
1631 |
|
|
-- Read STATUS
|
1632 |
|
|
block_read( cmd, ret, 4, 16, data );
|
1633 |
|
|
-- Construct LOG MSG in accordance to STATUS value
|
1634 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
1635 |
|
|
-- upd LOGFILE
|
1636 |
|
|
writeline( log, str );
|
1637 |
|
|
wait for 500 ns;
|
1638 |
|
|
end loop;
|
1639 |
|
|
end if;
|
1640 |
|
|
--
|
1641 |
|
|
-- Now STOP Design
|
1642 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
1643 |
|
|
--
|
1644 |
|
|
-- Now print RX values:
|
1645 |
|
|
--
|
1646 |
|
|
-- Construct Header:
|
1647 |
|
|
writeline( log, str );
|
1648 |
|
|
write( str, string'("PRINT 1st 15 RX values: " ));
|
1649 |
|
|
writeline( log, str );
|
1650 |
|
|
-- Get first 15 DATA values and print it:
|
1651 |
|
|
for ii in 0 to 15 loop
|
1652 |
|
|
adr:= x"00800000"; -- init ADDR value
|
1653 |
|
|
adr:=adr + ii*4; -- upd addr to curr idx
|
1654 |
|
|
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
|
1655 |
|
|
-- Construct LOG MSG in accordance to HOST MEM Read value
|
1656 |
|
|
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
1657 |
|
|
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
|
1658 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1659 |
|
|
end loop;
|
1660 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1661 |
|
|
--
|
1662 |
|
|
-- Final CHECK errors:
|
1663 |
|
|
if( error=0 ) then
|
1664 |
|
|
write( str, string'(" stb SUCCSESSFULL FINAL " ));
|
1665 |
|
|
cnt_ok := cnt_ok + 1;
|
1666 |
|
|
else
|
1667 |
|
|
write( str, string'(" stb FAILED FINAL " ));
|
1668 |
|
|
cnt_error := cnt_error + 1;
|
1669 |
|
|
end if;
|
1670 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1671 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1672 |
|
|
--
|
1673 |
|
|
-- END
|
1674 |
|
|
end test_num_2;
|
1675 |
|
|
---------------------------------------------------------------------------------------------------
|
1676 |
|
|
--
|
1677 |
|
|
-- My procedure for test WB stuff in Design:
|
1678 |
|
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
1679 |
|
|
--
|
1680 |
|
|
procedure test_wb_1 (
|
1681 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
1682 |
|
|
signal ret: in bh_ret --! answer
|
1683 |
16 |
dsmv |
) is
|
1684 |
|
|
|
1685 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
1686 |
|
|
variable data32 : std_logic_vector( 31 downto 0 );
|
1687 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
1688 |
|
|
variable str : line;
|
1689 |
|
|
|
1690 |
|
|
variable error : integer:=0;
|
1691 |
|
|
variable dma_complete : integer:=0;
|
1692 |
|
|
|
1693 |
|
|
--
|
1694 |
|
|
--
|
1695 |
|
|
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
|
1696 |
|
|
type wb_cfg_slave_data is record
|
1697 |
|
|
const : wb_cfg_slave_value(7 downto 0);
|
1698 |
|
|
cmd : wb_cfg_slave_value(7 downto 0);
|
1699 |
|
|
sts : wb_cfg_slave_value(7 downto 0);
|
1700 |
|
|
end record;
|
1701 |
|
|
--
|
1702 |
|
|
--
|
1703 |
|
|
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
|
1704 |
|
|
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
|
1705 |
|
|
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
|
1706 |
|
|
|
1707 |
|
|
|
1708 |
|
|
begin
|
1709 |
|
|
-- Init Header
|
1710 |
|
|
write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
|
1711 |
|
|
writeline( log, str );
|
1712 |
|
|
--
|
1713 |
|
|
-- Read "TEST_CHECK.WB_CFG_SLAVE"
|
1714 |
|
|
write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
|
1715 |
|
|
writeline( log, str );
|
1716 |
|
|
adr := x"20000000";
|
1717 |
|
|
|
1718 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
|
1719 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
|
1720 |
|
|
-- PCIE RD
|
1721 |
|
|
data_read64(cmd, ret, adr, data64);
|
1722 |
|
|
-- Put RD_Value to apropriate holder
|
1723 |
|
|
if (i=0) then -- const
|
1724 |
|
|
st_wb_cfg_slave_data_0.const(j) := data64;
|
1725 |
|
|
elsif (i=1) then -- cmd
|
1726 |
|
|
st_wb_cfg_slave_data_0.cmd(j) := data64;
|
1727 |
|
|
else -- sts
|
1728 |
|
|
st_wb_cfg_slave_data_0.sts(j) := data64;
|
1729 |
|
|
end if;
|
1730 |
|
|
-- Incr ADDR
|
1731 |
|
|
adr := adr + x"00000008";
|
1732 |
|
|
-- Print RD_Value
|
1733 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1734 |
|
|
writeline( log, str );
|
1735 |
|
|
|
1736 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
|
1737 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
|
1738 |
|
|
|
1739 |
|
|
--
|
1740 |
|
|
-- Write
|
1741 |
|
|
write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
|
1742 |
|
|
writeline( log, str );
|
1743 |
|
|
adr := x"20000000";
|
1744 |
|
|
|
1745 |
|
|
TEST_CHECK_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
|
1746 |
|
|
TEST_CHECK_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
|
1747 |
|
|
-- Prepare WR_Value
|
1748 |
|
|
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
|
1749 |
|
|
-- PCIE WR
|
1750 |
|
|
data_write64(cmd, ret, adr, data64);
|
1751 |
|
|
-- Put WR_Value to apropriate holder
|
1752 |
|
|
if (i=0) then -- const
|
1753 |
|
|
st_wb_cfg_slave_data_1.const(j) := data64;
|
1754 |
|
|
elsif (i=1) then -- cmd
|
1755 |
|
|
st_wb_cfg_slave_data_1.cmd(j) := data64;
|
1756 |
|
|
else -- sts
|
1757 |
|
|
st_wb_cfg_slave_data_1.sts(j) := data64;
|
1758 |
|
|
end if;
|
1759 |
|
|
-- Incr ADDR
|
1760 |
|
|
adr := adr + x"00000008";
|
1761 |
|
|
-- Print WR_Value
|
1762 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1763 |
|
|
writeline( log, str );
|
1764 |
|
|
|
1765 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
|
1766 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
|
1767 |
|
|
|
1768 |
|
|
--
|
1769 |
|
|
-- Read
|
1770 |
|
|
write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
|
1771 |
|
|
writeline( log, str );
|
1772 |
|
|
adr := x"20000000";
|
1773 |
|
|
|
1774 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
|
1775 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
|
1776 |
|
|
-- PCIE RD
|
1777 |
|
|
data_read64(cmd, ret, adr, data64);
|
1778 |
|
|
-- Put RD_Value to apropriate holder
|
1779 |
|
|
if (i=0) then -- const
|
1780 |
|
|
st_wb_cfg_slave_data_2.const(j) := data64;
|
1781 |
|
|
elsif (i=1) then -- cmd
|
1782 |
|
|
st_wb_cfg_slave_data_2.cmd(j) := data64;
|
1783 |
|
|
else -- sts
|
1784 |
|
|
st_wb_cfg_slave_data_2.sts(j) := data64;
|
1785 |
|
|
end if;
|
1786 |
|
|
-- Incr ADDR
|
1787 |
|
|
adr := adr + x"00000008";
|
1788 |
|
|
-- Print RD_Value
|
1789 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1790 |
|
|
writeline( log, str );
|
1791 |
|
|
|
1792 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
|
1793 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
|
1794 |
|
|
|
1795 |
|
|
--
|
1796 |
|
|
-- Compare results
|
1797 |
|
|
write( str, string'("4) Process Results:"));
|
1798 |
|
|
writeline( log, str );
|
1799 |
|
|
-- cmp#0 - constants
|
1800 |
|
|
CMP_CONST : for i in 0 to 7 loop
|
1801 |
|
|
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
|
1802 |
|
|
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1803 |
|
|
writeline( log, str );
|
1804 |
|
|
error := error + 1;
|
1805 |
|
|
end if;
|
1806 |
|
|
end loop CMP_CONST;
|
1807 |
|
|
-- cmp#1 - commands
|
1808 |
|
|
CMP_CMD : for i in 0 to 7 loop
|
1809 |
|
|
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
|
1810 |
|
|
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1811 |
|
|
writeline( log, str );
|
1812 |
|
|
error := error + 1;
|
1813 |
|
|
end if;
|
1814 |
|
|
end loop CMP_CMD;
|
1815 |
|
|
-- cmp#2 - status
|
1816 |
|
|
CMP_STATUS : for i in 0 to 7 loop
|
1817 |
|
|
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
|
1818 |
|
|
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1819 |
|
|
writeline( log, str );
|
1820 |
|
|
error := error + 1;
|
1821 |
|
|
end if;
|
1822 |
|
|
end loop CMP_STATUS;
|
1823 |
|
|
-- print OK
|
1824 |
|
|
if (error = 0) then
|
1825 |
|
|
write( str, string'(" Results==OK"));
|
1826 |
|
|
writeline( log, str );
|
1827 |
|
|
cnt_ok := cnt_ok + 1;
|
1828 |
|
|
else
|
1829 |
|
|
cnt_error := cnt_error + 1;
|
1830 |
|
|
end if;
|
1831 |
|
|
|
1832 |
|
|
-- Final Header
|
1833 |
|
|
write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
|
1834 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1835 |
|
|
--
|
1836 |
|
|
-- END
|
1837 |
|
|
end test_wb_1;
|
1838 |
|
|
---------------------------------------------------------------------------------------------------
|
1839 |
|
|
--
|
1840 |
|
|
-- My procedure for test WB stuff in Design:
|
1841 |
|
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
1842 |
|
|
--
|
1843 |
|
|
procedure test_wb_2 (
|
1844 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
1845 |
|
|
signal ret: in bh_ret --! answer
|
1846 |
16 |
dsmv |
) is
|
1847 |
|
|
|
1848 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
1849 |
|
|
variable data32 : std_logic_vector( 31 downto 0 );
|
1850 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
1851 |
|
|
variable str : line;
|
1852 |
|
|
|
1853 |
|
|
variable error : integer:=0;
|
1854 |
|
|
variable dma_complete : integer:=0;
|
1855 |
|
|
|
1856 |
|
|
--
|
1857 |
|
|
--
|
1858 |
|
|
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
|
1859 |
|
|
type wb_cfg_slave_data is record
|
1860 |
|
|
const : wb_cfg_slave_value(7 downto 0);
|
1861 |
|
|
cmd : wb_cfg_slave_value(7 downto 0);
|
1862 |
|
|
sts : wb_cfg_slave_value(7 downto 0);
|
1863 |
|
|
end record;
|
1864 |
|
|
--
|
1865 |
|
|
--
|
1866 |
|
|
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
|
1867 |
|
|
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
|
1868 |
|
|
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
|
1869 |
|
|
|
1870 |
|
|
|
1871 |
|
|
begin
|
1872 |
|
|
-- Init Header
|
1873 |
|
|
write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
|
1874 |
|
|
writeline( log, str );
|
1875 |
|
|
--
|
1876 |
|
|
-- Read "TEST_CHECK.WB_CFG_SLAVE"
|
1877 |
|
|
write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
|
1878 |
|
|
writeline( log, str );
|
1879 |
|
|
adr := x"20002000";
|
1880 |
|
|
|
1881 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
|
1882 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
|
1883 |
|
|
-- PCIE RD
|
1884 |
|
|
data_read64(cmd, ret, adr, data64);
|
1885 |
|
|
-- Put RD_Value to apropriate holder
|
1886 |
|
|
if (i=0) then -- const
|
1887 |
|
|
st_wb_cfg_slave_data_0.const(j) := data64;
|
1888 |
|
|
elsif (i=1) then -- cmd
|
1889 |
|
|
st_wb_cfg_slave_data_0.cmd(j) := data64;
|
1890 |
|
|
else -- sts
|
1891 |
|
|
st_wb_cfg_slave_data_0.sts(j) := data64;
|
1892 |
|
|
end if;
|
1893 |
|
|
-- Incr ADDR
|
1894 |
|
|
adr := adr + x"00000008";
|
1895 |
|
|
-- Print RD_Value
|
1896 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1897 |
|
|
writeline( log, str );
|
1898 |
|
|
|
1899 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
|
1900 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
|
1901 |
|
|
|
1902 |
|
|
--
|
1903 |
|
|
-- Write
|
1904 |
|
|
write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
|
1905 |
|
|
writeline( log, str );
|
1906 |
|
|
adr := x"20002000";
|
1907 |
|
|
|
1908 |
|
|
TEST_GEN_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
|
1909 |
|
|
TEST_GEN_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
|
1910 |
|
|
-- Prepare WR_Value
|
1911 |
|
|
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
|
1912 |
|
|
-- PCIE WR
|
1913 |
|
|
data_write64(cmd, ret, adr, data64);
|
1914 |
|
|
-- Put WR_Value to apropriate holder
|
1915 |
|
|
if (i=0) then -- const
|
1916 |
|
|
st_wb_cfg_slave_data_1.const(j) := data64;
|
1917 |
|
|
elsif (i=1) then -- cmd
|
1918 |
|
|
st_wb_cfg_slave_data_1.cmd(j) := data64;
|
1919 |
|
|
else -- sts
|
1920 |
|
|
st_wb_cfg_slave_data_1.sts(j) := data64;
|
1921 |
|
|
end if;
|
1922 |
|
|
-- Incr ADDR
|
1923 |
|
|
adr := adr + x"00000008";
|
1924 |
|
|
-- Print WR_Value
|
1925 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1926 |
|
|
writeline( log, str );
|
1927 |
|
|
|
1928 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
|
1929 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
|
1930 |
|
|
|
1931 |
|
|
--
|
1932 |
|
|
-- Read
|
1933 |
|
|
write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
|
1934 |
|
|
writeline( log, str );
|
1935 |
|
|
adr := x"20002000";
|
1936 |
|
|
|
1937 |
|
|
TEST_GEN_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
|
1938 |
|
|
TEST_GEN_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
|
1939 |
|
|
-- PCIE RD
|
1940 |
|
|
data_read64(cmd, ret, adr, data64);
|
1941 |
|
|
-- Put RD_Value to apropriate holder
|
1942 |
|
|
if (i=0) then -- const
|
1943 |
|
|
st_wb_cfg_slave_data_2.const(j) := data64;
|
1944 |
|
|
elsif (i=1) then -- cmd
|
1945 |
|
|
st_wb_cfg_slave_data_2.cmd(j) := data64;
|
1946 |
|
|
else -- sts
|
1947 |
|
|
st_wb_cfg_slave_data_2.sts(j) := data64;
|
1948 |
|
|
end if;
|
1949 |
|
|
-- Incr ADDR
|
1950 |
|
|
adr := adr + x"00000008";
|
1951 |
|
|
-- Print RD_Value
|
1952 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
1953 |
|
|
writeline( log, str );
|
1954 |
|
|
|
1955 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
|
1956 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
|
1957 |
|
|
|
1958 |
|
|
--
|
1959 |
|
|
-- Compare results
|
1960 |
|
|
write( str, string'("4) Process Results:"));
|
1961 |
|
|
writeline( log, str );
|
1962 |
|
|
-- cmp#0 - constants
|
1963 |
|
|
CMP_CONST : for i in 0 to 7 loop
|
1964 |
|
|
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
|
1965 |
|
|
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1966 |
|
|
writeline( log, str );
|
1967 |
|
|
error := error + 1;
|
1968 |
|
|
end if;
|
1969 |
|
|
end loop CMP_CONST;
|
1970 |
|
|
-- cmp#1 - commands
|
1971 |
|
|
CMP_CMD : for i in 0 to 7 loop
|
1972 |
|
|
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
|
1973 |
|
|
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1974 |
|
|
writeline( log, str );
|
1975 |
|
|
error := error + 1;
|
1976 |
|
|
end if;
|
1977 |
|
|
end loop CMP_CMD;
|
1978 |
|
|
-- cmp#2 - status
|
1979 |
|
|
CMP_STATUS : for i in 0 to 7 loop
|
1980 |
|
|
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
|
1981 |
|
|
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
1982 |
|
|
writeline( log, str );
|
1983 |
|
|
error := error + 1;
|
1984 |
|
|
end if;
|
1985 |
|
|
end loop CMP_STATUS;
|
1986 |
|
|
-- print OK
|
1987 |
|
|
if (error = 0) then
|
1988 |
|
|
write( str, string'(" Results==OK"));
|
1989 |
|
|
writeline( log, str );
|
1990 |
|
|
cnt_ok := cnt_ok + 1;
|
1991 |
|
|
else
|
1992 |
|
|
cnt_error := cnt_error + 1;
|
1993 |
|
|
end if;
|
1994 |
|
|
|
1995 |
|
|
-- Final Header
|
1996 |
|
|
write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
|
1997 |
|
|
writeline( log, str ); -- upd LOGFILE
|
1998 |
|
|
--
|
1999 |
|
|
-- END
|
2000 |
|
|
end test_wb_2;
|
2001 |
|
|
---------------------------------------------------------------------------------------------------
|
2002 |
|
|
end package body test_pkg;
|