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---------------------------------------------------------------------------------------------------
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--
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-- Title : test_pkg.vhd
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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--
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-- Version : 1.0
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Ïàêåò äëÿ òåñòèðîâàíèÿ ambpex5.
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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library work;
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use work.cmd_sim_pkg.all;
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use work.block_pkg.all;
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use work.wb_block_pkg.all;
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package test_pkg is
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--! Initialising
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procedure test_init(
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fname: in string --! file name for report
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);
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--! Finished
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procedure test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Read block_test_check 8 kB
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procedure test_adm_read_8kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
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--procedure test_block_main (
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! answer
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-- );
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--
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----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
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--procedure test_adm_read_16kb (
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! answer
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-- );
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--
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--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
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procedure test_adm_write_16kb (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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---------------------------------------------------------------------------------------------------
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--
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--
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--
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procedure test_num_1(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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procedure test_num_2(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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-- ==> TEST_CHECK.WB_CFG_SLAVE
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procedure test_wb_1(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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-- ==> TEST_GEN.WB_CFG_SLAVE
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procedure test_wb_2(
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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end package test_pkg;
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---------------------------------------------------------------------------------------------------
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package body test_pkg is
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FILE log: text;
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shared variable cnt_ok, cnt_error: integer;
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-- Initialising
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procedure test_init(
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fname: in string
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) is
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begin
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file_open( log, fname, WRITE_MODE );
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cnt_ok:=0;
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cnt_error:=0;
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end test_init;
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--! Finished
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procedure test_close is
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variable str : LINE; -- pointer to string
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begin
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std.textio.write( str, string'(" " ));
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writeline( log, str );
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writeline( log, str );
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write( str, string'("check completed" ));
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writeline( log, str );
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write( str, string'("the number of successful tests: " ));
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write( str, cnt_ok );
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writeline( log, str );
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write( str, string'("the number of false test: " ));
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write( str, cnt_error );
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writeline( log, str );
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file_close( log );
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if( cnt_ok>0 and cnt_error=0 ) then
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write( str, string'("TEST finished successfully") );
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writeline( output, str );
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else
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write( str, string'("TEST finished with ERR") );
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writeline( output, str );
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end if;
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end test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data1 : std_logic_vector( 31 downto 0 );
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variable data2 : std_logic_vector( 31 downto 0 );
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variable str : line;
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begin
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write( str, string'("TEST_READ_REG" ));
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
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wait for 100 ns;
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--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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wb_read( cmd, ret, 16#1000#, data1 );
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wb_read( cmd, ret, 16#3000#, data1 );
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write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE
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wait for 100 ns;
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
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wait for 100 ns;
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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end test_read_reg;
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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dsmv |
signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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16 |
dsmv |
)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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begin
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write( str, string'("TEST_DSC_INCORRECT" ));
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writeline( log, str );
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---- Init block of descriptor ---
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"03020100" );
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int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" );
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---- DMA program ----
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block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 15 downto 0 )=x"A021" ) then
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write( str, string'(" - Ok" ));
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cnt_ok := cnt_ok + 1;
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else
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write( str, string'(" - Error" ));
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cnt_error := cnt_error + 1;
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end if;
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writeline( log, str );
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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end test_dsc_incorrect;
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
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18 |
dsmv |
signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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| 278 |
16 |
dsmv |
)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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variable error : integer:=0;
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variable dma_complete : integer;
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begin
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write( str, string'("TEST_READ_4KB" ));
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writeline( log, str );
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---- Init block of descriptor ---
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"00008000" );
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int_mem_write( cmd, ret, x"00100004", x"00000100" );
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int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001FC", x"762C4953" );
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--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
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write( str, string'("BLOCK TEST_GEN ID: " ));
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hwrite( str, data );
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writeline( log, str );
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
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---- DMA program ----
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block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - without request
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
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wait for 1 us;
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 8 )='1' ) then
|
| 340 |
|
|
write( str, string'(" - descriptor is correct" ));
|
| 341 |
|
|
else
|
| 342 |
|
|
write( str, string'(" - descriptor is incorrect" ));
|
| 343 |
|
|
error := error + 1;
|
| 344 |
|
|
end if;
|
| 345 |
|
|
|
| 346 |
|
|
writeline( log, str );
|
| 347 |
|
|
|
| 348 |
|
|
if( error=0 ) then
|
| 349 |
|
|
|
| 350 |
|
|
---- Wait for DMA finished ----
|
| 351 |
|
|
dma_complete := 0;
|
| 352 |
|
|
for ii in 0 to 100 loop
|
| 353 |
|
|
|
| 354 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 355 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 356 |
|
|
if( data(5)='1' ) then
|
| 357 |
|
|
write( str, string'(" - DMA finished " ));
|
| 358 |
|
|
dma_complete := 1;
|
| 359 |
|
|
end if;
|
| 360 |
|
|
writeline( log, str );
|
| 361 |
|
|
|
| 362 |
|
|
if( dma_complete=1 ) then
|
| 363 |
|
|
exit;
|
| 364 |
|
|
end if;
|
| 365 |
|
|
|
| 366 |
|
|
wait for 1 us;
|
| 367 |
|
|
|
| 368 |
|
|
end loop;
|
| 369 |
|
|
|
| 370 |
|
|
writeline( log, str );
|
| 371 |
|
|
|
| 372 |
|
|
if( dma_complete=0 ) then
|
| 373 |
|
|
write( str, string'("Error - DMA not finished" ));
|
| 374 |
|
|
writeline( log, str );
|
| 375 |
|
|
error:=error+1;
|
| 376 |
|
|
end if;
|
| 377 |
|
|
|
| 378 |
|
|
end if;
|
| 379 |
|
|
|
| 380 |
|
|
for ii in 0 to 3 loop
|
| 381 |
|
|
|
| 382 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 383 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 384 |
|
|
writeline( log, str );
|
| 385 |
|
|
wait for 500 ns;
|
| 386 |
|
|
|
| 387 |
|
|
end loop;
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 391 |
|
|
|
| 392 |
|
|
write( str, string'(" Read: " ));
|
| 393 |
|
|
writeline( log, str );
|
| 394 |
|
|
|
| 395 |
|
|
for ii in 0 to 15 loop
|
| 396 |
|
|
|
| 397 |
|
|
adr:= x"00800000";
|
| 398 |
|
|
adr:=adr + ii*4;
|
| 399 |
|
|
int_mem_read( cmd, ret, adr, data );
|
| 400 |
|
|
|
| 401 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 402 |
|
|
writeline( log, str );
|
| 403 |
|
|
|
| 404 |
|
|
end loop;
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 408 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
| 409 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
writeline( log, str );
|
| 413 |
|
|
if( error=0 ) then
|
| 414 |
|
|
write( str, string'("Test is correct" ));
|
| 415 |
|
|
cnt_ok := cnt_ok + 1;
|
| 416 |
|
|
else
|
| 417 |
|
|
write( str, string'("Test have ERRORS" ));
|
| 418 |
|
|
cnt_error := cnt_error + 1;
|
| 419 |
|
|
end if;
|
| 420 |
|
|
writeline( log, str );
|
| 421 |
|
|
writeline( log, str );
|
| 422 |
|
|
|
| 423 |
|
|
end test_read_4kb;
|
| 424 |
|
|
|
| 425 |
|
|
|
| 426 |
|
|
--! Read block_test_check 8 kB
|
| 427 |
|
|
procedure test_adm_read_8kb (
|
| 428 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 429 |
|
|
signal ret: in bh_ret --! answer
|
| 430 |
16 |
dsmv |
)
|
| 431 |
|
|
is
|
| 432 |
|
|
|
| 433 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 434 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
| 435 |
|
|
variable str : line;
|
| 436 |
|
|
|
| 437 |
|
|
variable error : integer:=0;
|
| 438 |
|
|
variable dma_complete : integer;
|
| 439 |
|
|
|
| 440 |
|
|
begin
|
| 441 |
|
|
|
| 442 |
|
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
| 443 |
|
|
writeline( log, str );
|
| 444 |
|
|
|
| 445 |
|
|
---- Init block of descriptor ---
|
| 446 |
|
|
for ii in 0 to 127 loop
|
| 447 |
|
|
adr:= x"00100000";
|
| 448 |
|
|
adr:=adr + ii*4;
|
| 449 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| 450 |
|
|
end loop;
|
| 451 |
|
|
|
| 452 |
|
|
--- Desctriptor 0 ---
|
| 453 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
| 454 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- jump to next descriptor
|
| 455 |
|
|
|
| 456 |
|
|
--- Desctriptor 1 ---
|
| 457 |
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
| 458 |
|
|
int_mem_write( cmd, ret, x"0010000C", x"00000110" ); -- stop
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
| 462 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
| 466 |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
| 467 |
|
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 468 |
|
|
|
| 469 |
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
| 470 |
|
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
| 471 |
|
|
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
|
| 475 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
|
| 476 |
|
|
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
|
| 477 |
|
|
write( str, string'("BLOCK TEST_GEN ID: " ));
|
| 478 |
|
|
hwrite( str, data );
|
| 479 |
|
|
writeline( log, str );
|
| 480 |
|
|
|
| 481 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
|
| 482 |
|
|
|
| 483 |
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 484 |
|
|
|
| 485 |
|
|
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
|
| 486 |
|
|
|
| 487 |
|
|
wait for 20 us;
|
| 488 |
|
|
|
| 489 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 490 |
|
|
|
| 491 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 492 |
|
|
if( data( 8 )='1' ) then
|
| 493 |
|
|
write( str, string'(" - descriptor is correct" ));
|
| 494 |
|
|
else
|
| 495 |
|
|
write( str, string'(" - descriptor is incorrect" ));
|
| 496 |
|
|
error := error + 1;
|
| 497 |
|
|
end if;
|
| 498 |
|
|
|
| 499 |
|
|
writeline( log, str );
|
| 500 |
|
|
|
| 501 |
|
|
if( error=0 ) then
|
| 502 |
|
|
|
| 503 |
|
|
---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
| 504 |
|
|
dma_complete := 0;
|
| 505 |
|
|
for ii in 0 to 100 loop
|
| 506 |
|
|
|
| 507 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 508 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 509 |
|
|
if( data(5)='1' ) then
|
| 510 |
|
|
write( str, string'(" - DMA finished " ));
|
| 511 |
|
|
dma_complete := 1;
|
| 512 |
|
|
|
| 513 |
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
|
| 514 |
|
|
|
| 515 |
|
|
end if;
|
| 516 |
|
|
writeline( log, str );
|
| 517 |
|
|
|
| 518 |
|
|
if( dma_complete=1 ) then
|
| 519 |
|
|
exit;
|
| 520 |
|
|
end if;
|
| 521 |
|
|
|
| 522 |
|
|
wait for 1 us;
|
| 523 |
|
|
|
| 524 |
|
|
end loop;
|
| 525 |
|
|
|
| 526 |
|
|
writeline( log, str );
|
| 527 |
|
|
|
| 528 |
|
|
if( dma_complete=0 ) then
|
| 529 |
|
|
write( str, string'("Error - DMA not finished " ));
|
| 530 |
|
|
writeline( log, str );
|
| 531 |
|
|
error:=error+1;
|
| 532 |
|
|
end if;
|
| 533 |
|
|
|
| 534 |
|
|
end if;
|
| 535 |
|
|
|
| 536 |
|
|
for ii in 0 to 3 loop
|
| 537 |
|
|
|
| 538 |
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 539 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 540 |
|
|
writeline( log, str );
|
| 541 |
|
|
wait for 500 ns;
|
| 542 |
|
|
|
| 543 |
|
|
end loop;
|
| 544 |
|
|
|
| 545 |
|
|
|
| 546 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 547 |
|
|
|
| 548 |
|
|
write( str, string'(" Block 0 - read: " ));
|
| 549 |
|
|
writeline( log, str );
|
| 550 |
|
|
|
| 551 |
|
|
for ii in 0 to 15 loop
|
| 552 |
|
|
|
| 553 |
|
|
adr:= x"00800000";
|
| 554 |
|
|
adr:=adr + ii*4;
|
| 555 |
|
|
int_mem_read( cmd, ret, adr, data );
|
| 556 |
|
|
|
| 557 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 558 |
|
|
writeline( log, str );
|
| 559 |
|
|
|
| 560 |
|
|
end loop;
|
| 561 |
|
|
|
| 562 |
|
|
writeline( log, str );
|
| 563 |
|
|
|
| 564 |
|
|
write( str, string'(" Block 1 - read: " ));
|
| 565 |
|
|
writeline( log, str );
|
| 566 |
|
|
|
| 567 |
|
|
for ii in 0 to 15 loop
|
| 568 |
|
|
|
| 569 |
|
|
adr:= x"00801000";
|
| 570 |
|
|
adr:=adr + ii*4;
|
| 571 |
|
|
int_mem_read( cmd, ret, adr, data );
|
| 572 |
|
|
|
| 573 |
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 574 |
|
|
writeline( log, str );
|
| 575 |
|
|
|
| 576 |
|
|
end loop;
|
| 577 |
|
|
|
| 578 |
|
|
|
| 579 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 580 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
| 581 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 582 |
|
|
|
| 583 |
|
|
|
| 584 |
|
|
writeline( log, str );
|
| 585 |
|
|
if( error=0 ) then
|
| 586 |
|
|
write( str, string'(" Test is correct " ));
|
| 587 |
|
|
cnt_ok := cnt_ok + 1;
|
| 588 |
|
|
else
|
| 589 |
|
|
write( str, string'(" Test have ERRORS " ));
|
| 590 |
|
|
cnt_error := cnt_error + 1;
|
| 591 |
|
|
end if;
|
| 592 |
|
|
writeline( log, str );
|
| 593 |
|
|
writeline( log, str );
|
| 594 |
|
|
|
| 595 |
|
|
end test_adm_read_8kb;
|
| 596 |
|
|
--
|
| 597 |
|
|
--
|
| 598 |
|
|
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
|
| 599 |
|
|
--procedure test_block_main (
|
| 600 |
18 |
dsmv |
-- signal cmd: out bh_cmd; --! command
|
| 601 |
|
|
-- signal ret: in bh_ret --! answer
|
| 602 |
16 |
dsmv |
-- )
|
| 603 |
|
|
--is
|
| 604 |
|
|
--
|
| 605 |
|
|
--variable adr : std_logic_vector( 31 downto 0 );
|
| 606 |
|
|
--variable data : std_logic_vector( 31 downto 0 );
|
| 607 |
|
|
--variable str : line;
|
| 608 |
|
|
--
|
| 609 |
|
|
--variable error : integer:=0;
|
| 610 |
|
|
--variable dma_complete : integer;
|
| 611 |
|
|
--
|
| 612 |
|
|
--begin
|
| 613 |
|
|
--
|
| 614 |
|
|
-- write( str, string'("TEST_BLOCK_MAIN" ));
|
| 615 |
|
|
-- writeline( log, str );
|
| 616 |
|
|
--
|
| 617 |
|
|
-- block_read( cmd, ret, 4, 16#00#, data );
|
| 618 |
|
|
-- write( str, string'("ÁËÎÊ 4: " )); hwrite( str, data ); writeline( log, str );
|
| 619 |
|
|
--
|
| 620 |
|
|
-- wait for 10 us;
|
| 621 |
|
|
--
|
| 622 |
|
|
---- write( str, "Êîíñòàíòû:" );
|
| 623 |
|
|
---- writeline( log, str );
|
| 624 |
|
|
---- for ii in 0 to 5 loop
|
| 625 |
|
|
---- write( str, "Áëîê " );
|
| 626 |
|
|
---- write( str, ii );
|
| 627 |
|
|
---- for jj in 0 to 7 loop
|
| 628 |
|
|
---- block_read( cmd, ret, ii, jj, data );
|
| 629 |
|
|
---- write( str, " " );
|
| 630 |
|
|
---- hwrite( str, data );
|
| 631 |
|
|
---- end loop;
|
| 632 |
|
|
---- writeline( log, str );
|
| 633 |
|
|
---- end loop;
|
| 634 |
|
|
----
|
| 635 |
|
|
----
|
| 636 |
|
|
---- writeline( log, str );
|
| 637 |
|
|
----
|
| 638 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
| 639 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
| 640 |
|
|
----
|
| 641 |
|
|
---- block_write( cmd, ret, 80, 16#08#, x"00000100" );
|
| 642 |
|
|
----
|
| 643 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
| 644 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
| 645 |
|
|
----
|
| 646 |
|
|
---- block_write( cmd, ret, 80, 16#08#, x"00000200" );
|
| 647 |
|
|
----
|
| 648 |
|
|
---- block_read( cmd, ret, 0, 16#10#, data );
|
| 649 |
|
|
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
| 650 |
|
|
----
|
| 651 |
|
|
----
|
| 652 |
|
|
---- writeline( log, str );
|
| 653 |
|
|
---- if( error=0 ) then
|
| 654 |
|
|
---- write( str, " Òåñò çàâåðø¸í óñïåøíî " );
|
| 655 |
|
|
---- cnt_ok := cnt_ok + 1;
|
| 656 |
|
|
---- else
|
| 657 |
|
|
---- write( str, " Òåñò íå âûïîëíåí " );
|
| 658 |
|
|
---- cnt_error := cnt_error + 1;
|
| 659 |
|
|
---- end if;
|
| 660 |
|
|
--
|
| 661 |
|
|
-- for ii in 0 to 127 loop
|
| 662 |
|
|
--
|
| 663 |
|
|
-- block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
| 664 |
|
|
-- block_read( cmd, ret, 4, 8, data );
|
| 665 |
|
|
-- write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
|
| 666 |
|
|
-- if( data/=x"0000AA55" ) then
|
| 667 |
|
|
-- error:=error+1;
|
| 668 |
|
|
-- end if;
|
| 669 |
|
|
--
|
| 670 |
|
|
-- end loop;
|
| 671 |
|
|
--
|
| 672 |
|
|
--
|
| 673 |
|
|
--
|
| 674 |
|
|
--
|
| 675 |
|
|
-- writeline( log, str );
|
| 676 |
|
|
-- writeline( log, str );
|
| 677 |
|
|
--
|
| 678 |
|
|
--end test_block_main;
|
| 679 |
|
|
--
|
| 680 |
|
|
--
|
| 681 |
|
|
--
|
| 682 |
|
|
--
|
| 683 |
|
|
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
|
| 684 |
|
|
--procedure test_adm_read_16kb (
|
| 685 |
18 |
dsmv |
-- signal cmd: out bh_cmd; --! command
|
| 686 |
|
|
-- signal ret: in bh_ret --! answer
|
| 687 |
16 |
dsmv |
-- )
|
| 688 |
|
|
--is
|
| 689 |
|
|
--
|
| 690 |
|
|
--variable adr : std_logic_vector( 31 downto 0 );
|
| 691 |
|
|
--variable data : std_logic_vector( 31 downto 0 );
|
| 692 |
|
|
--variable str : line;
|
| 693 |
|
|
--
|
| 694 |
|
|
--variable error : integer:=0;
|
| 695 |
|
|
--variable dma_complete : integer;
|
| 696 |
|
|
--variable kk : integer;
|
| 697 |
|
|
--variable status : std_logic_vector( 15 downto 0 );
|
| 698 |
|
|
--
|
| 699 |
|
|
--begin
|
| 700 |
|
|
--
|
| 701 |
|
|
-- write( str, string'("TEST_ADM_READ_16KB" ));
|
| 702 |
|
|
-- writeline( log, str );
|
| 703 |
|
|
--
|
| 704 |
|
|
-- ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
| 705 |
|
|
-- for ii in 0 to 256 loop
|
| 706 |
|
|
-- adr:= x"00100000";
|
| 707 |
|
|
-- adr:=adr + ii*4;
|
| 708 |
|
|
-- int_mem_write( cmd, ret, adr, x"00000000" );
|
| 709 |
|
|
-- end loop;
|
| 710 |
|
|
--
|
| 711 |
|
|
-- --- Áëîê 0 ---
|
| 712 |
|
|
--
|
| 713 |
|
|
-- --- Äåñêðèïòîð 0 ---
|
| 714 |
|
|
-- int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
| 715 |
|
|
-- int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
| 716 |
|
|
--
|
| 717 |
|
|
-- --- Äåñêðèïòîð 1 ---
|
| 718 |
|
|
-- int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
| 719 |
|
|
-- int_mem_write( cmd, ret, x"0010000C", x"00000112" ); -- ïåðåõîä ê ñëåäóþùåìó áëîêó
|
| 720 |
|
|
--
|
| 721 |
|
|
-- --- Äåñêðèïòîð 2 ---
|
| 722 |
|
|
-- int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
|
| 723 |
|
|
-- int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
| 724 |
|
|
--
|
| 725 |
|
|
--
|
| 726 |
|
|
-- int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
| 727 |
|
|
-- int_mem_write( cmd, ret, x"001001FC", x"14644953" );
|
| 728 |
|
|
--
|
| 729 |
|
|
--
|
| 730 |
|
|
-- --- Áëîê 1 ---
|
| 731 |
|
|
--
|
| 732 |
|
|
-- --- Äåñêðèïòîð 0 ---
|
| 733 |
|
|
-- int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
| 734 |
|
|
-- int_mem_write( cmd, ret, x"00100204", x"00000111" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
| 735 |
|
|
--
|
| 736 |
|
|
-- --- Äåñêðèïòîð 1 ---
|
| 737 |
|
|
-- int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
| 738 |
|
|
-- int_mem_write( cmd, ret, x"0010020C", x"00000110" ); -- îñòàíîâêà
|
| 739 |
|
|
--
|
| 740 |
|
|
--
|
| 741 |
|
|
-- int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
| 742 |
|
|
-- int_mem_write( cmd, ret, x"001003FC", x"D67C4953" );
|
| 743 |
|
|
--
|
| 744 |
|
|
--
|
| 745 |
|
|
--
|
| 746 |
|
|
-- ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
| 747 |
|
|
-- block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
| 748 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 749 |
|
|
--
|
| 750 |
|
|
-- block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
| 751 |
|
|
-- block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
| 752 |
|
|
-- block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
| 753 |
|
|
--
|
| 754 |
|
|
--
|
| 755 |
|
|
-- ---- Ïîäãîòîâêà òåòðàäû ----
|
| 756 |
|
|
-- trd_test_mode( cmd, ret, 0 ); -- ïåðåõîä â ðàáî÷èé ðåæèì --
|
| 757 |
|
|
-- trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - îò òåòðàäû 6 --
|
| 758 |
|
|
--
|
| 759 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Ðàçìåð áëîêà = 4 êÁ --
|
| 760 |
|
|
--
|
| 761 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 762 |
|
|
--
|
| 763 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
|
| 764 |
|
|
--
|
| 765 |
|
|
-- trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- çàïóñê òåòðàäû DIO_IN
|
| 766 |
|
|
--
|
| 767 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" ); -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
|
| 768 |
|
|
--
|
| 769 |
|
|
-- wait for 20 us;
|
| 770 |
|
|
--
|
| 771 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 772 |
|
|
--
|
| 773 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 774 |
|
|
-- if( data( 8 )='1' ) then
|
| 775 |
|
|
-- write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
|
| 776 |
|
|
-- else
|
| 777 |
|
|
-- write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
|
| 778 |
|
|
-- error := error + 1;
|
| 779 |
|
|
-- end if;
|
| 780 |
|
|
--
|
| 781 |
|
|
-- writeline( log, str );
|
| 782 |
|
|
--
|
| 783 |
|
|
-- if( error=0 ) then
|
| 784 |
|
|
--
|
| 785 |
|
|
-- kk:=0;
|
| 786 |
|
|
-- loop
|
| 787 |
|
|
--
|
| 788 |
|
|
-- trd_status( cmd, ret, 6, status );
|
| 789 |
|
|
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
| 790 |
|
|
--
|
| 791 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 792 |
|
|
-- write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 793 |
|
|
--
|
| 794 |
|
|
-- if( data(4)='1' ) then
|
| 795 |
|
|
-- write( str, string'(" - çàâåðøåíî ÷òåíèå áëîêà " ));
|
| 796 |
|
|
-- block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
| 797 |
|
|
-- kk:=kk+1;
|
| 798 |
|
|
-- if( kk=4 ) then
|
| 799 |
|
|
-- exit;
|
| 800 |
|
|
-- end if;
|
| 801 |
|
|
-- end if;
|
| 802 |
|
|
-- writeline( log, str );
|
| 803 |
|
|
--
|
| 804 |
|
|
-- wait for 500 ns;
|
| 805 |
|
|
--
|
| 806 |
|
|
--
|
| 807 |
|
|
-- end loop;
|
| 808 |
|
|
--
|
| 809 |
|
|
-- ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
| 810 |
|
|
-- dma_complete := 0;
|
| 811 |
|
|
-- for ii in 0 to 100 loop
|
| 812 |
|
|
--
|
| 813 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 814 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 815 |
|
|
-- if( data(5)='1' ) then
|
| 816 |
|
|
-- write( str, string'(" - DMA çàâåðø¸í " ));
|
| 817 |
|
|
-- dma_complete := 1;
|
| 818 |
|
|
--
|
| 819 |
|
|
-- block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
| 820 |
|
|
--
|
| 821 |
|
|
-- end if;
|
| 822 |
|
|
-- writeline( log, str );
|
| 823 |
|
|
--
|
| 824 |
|
|
-- if( dma_complete=1 ) then
|
| 825 |
|
|
-- exit;
|
| 826 |
|
|
-- end if;
|
| 827 |
|
|
--
|
| 828 |
|
|
-- wait for 1 us;
|
| 829 |
|
|
--
|
| 830 |
|
|
-- end loop;
|
| 831 |
|
|
--
|
| 832 |
|
|
-- writeline( log, str );
|
| 833 |
|
|
--
|
| 834 |
|
|
-- if( dma_complete=0 ) then
|
| 835 |
|
|
-- write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
|
| 836 |
|
|
-- writeline( log, str );
|
| 837 |
|
|
-- error:=error+1;
|
| 838 |
|
|
-- end if;
|
| 839 |
|
|
--
|
| 840 |
|
|
-- end if;
|
| 841 |
|
|
--
|
| 842 |
|
|
-- for ii in 0 to 3 loop
|
| 843 |
|
|
--
|
| 844 |
|
|
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
|
| 845 |
|
|
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 846 |
|
|
-- writeline( log, str );
|
| 847 |
|
|
-- wait for 500 ns;
|
| 848 |
|
|
--
|
| 849 |
|
|
-- end loop;
|
| 850 |
|
|
--
|
| 851 |
|
|
--
|
| 852 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 853 |
|
|
--
|
| 854 |
|
|
-- write( str, string'(" Áëîê 0 - ïðî÷èòàíî: " ));
|
| 855 |
|
|
-- writeline( log, str );
|
| 856 |
|
|
--
|
| 857 |
|
|
-- for ii in 0 to 15 loop
|
| 858 |
|
|
--
|
| 859 |
|
|
-- adr:= x"00800000";
|
| 860 |
|
|
-- adr:=adr + ii*4;
|
| 861 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
| 862 |
|
|
--
|
| 863 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 864 |
|
|
-- writeline( log, str );
|
| 865 |
|
|
--
|
| 866 |
|
|
-- end loop;
|
| 867 |
|
|
--
|
| 868 |
|
|
-- writeline( log, str );
|
| 869 |
|
|
--
|
| 870 |
|
|
-- write( str, string'(" Áëîê 1 - ïðî÷èòàíî: " ));
|
| 871 |
|
|
-- writeline( log, str );
|
| 872 |
|
|
--
|
| 873 |
|
|
-- for ii in 0 to 15 loop
|
| 874 |
|
|
--
|
| 875 |
|
|
-- adr:= x"00801000";
|
| 876 |
|
|
-- adr:=adr + ii*4;
|
| 877 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
| 878 |
|
|
--
|
| 879 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 880 |
|
|
-- writeline( log, str );
|
| 881 |
|
|
--
|
| 882 |
|
|
-- end loop;
|
| 883 |
|
|
--
|
| 884 |
|
|
-- write( str, string'(" Áëîê 2 - ïðî÷èòàíî: " ));
|
| 885 |
|
|
-- writeline( log, str );
|
| 886 |
|
|
--
|
| 887 |
|
|
-- for ii in 0 to 15 loop
|
| 888 |
|
|
--
|
| 889 |
|
|
-- adr:= x"00802000";
|
| 890 |
|
|
-- adr:=adr + ii*4;
|
| 891 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
| 892 |
|
|
--
|
| 893 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 894 |
|
|
-- writeline( log, str );
|
| 895 |
|
|
--
|
| 896 |
|
|
-- end loop;
|
| 897 |
|
|
--
|
| 898 |
|
|
--
|
| 899 |
|
|
-- write( str, string'(" Áëîê 3 - ïðî÷èòàíî: " ));
|
| 900 |
|
|
-- writeline( log, str );
|
| 901 |
|
|
--
|
| 902 |
|
|
-- for ii in 0 to 15 loop
|
| 903 |
|
|
--
|
| 904 |
|
|
-- adr:= x"00803000";
|
| 905 |
|
|
-- adr:=adr + ii*4;
|
| 906 |
|
|
-- int_mem_read( cmd, ret, adr, data );
|
| 907 |
|
|
--
|
| 908 |
|
|
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 909 |
|
|
-- writeline( log, str );
|
| 910 |
|
|
--
|
| 911 |
|
|
-- end loop;
|
| 912 |
|
|
--
|
| 913 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 914 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
| 915 |
|
|
---- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 916 |
|
|
--
|
| 917 |
|
|
--
|
| 918 |
|
|
-- writeline( log, str );
|
| 919 |
|
|
-- if( error=0 ) then
|
| 920 |
|
|
-- write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
|
| 921 |
|
|
-- cnt_ok := cnt_ok + 1;
|
| 922 |
|
|
-- else
|
| 923 |
|
|
-- write( str, string'(" Òåñò íå âûïîëíåí " ));
|
| 924 |
|
|
-- cnt_error := cnt_error + 1;
|
| 925 |
|
|
-- end if;
|
| 926 |
|
|
-- writeline( log, str );
|
| 927 |
|
|
-- writeline( log, str );
|
| 928 |
|
|
--
|
| 929 |
|
|
--end test_adm_read_16kb;
|
| 930 |
|
|
--
|
| 931 |
|
|
--
|
| 932 |
|
|
--
|
| 933 |
|
|
--
|
| 934 |
|
|
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
|
| 935 |
|
|
procedure test_adm_write_16kb (
|
| 936 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 937 |
|
|
signal ret: in bh_ret --! answer
|
| 938 |
16 |
dsmv |
)
|
| 939 |
|
|
is
|
| 940 |
|
|
|
| 941 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 942 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
| 943 |
|
|
variable str : line;
|
| 944 |
|
|
|
| 945 |
|
|
variable error : integer:=0;
|
| 946 |
|
|
variable dma_complete : integer;
|
| 947 |
|
|
variable kk : integer;
|
| 948 |
|
|
variable status : std_logic_vector( 15 downto 0 );
|
| 949 |
|
|
|
| 950 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| 951 |
|
|
variable data64n : std_logic_vector( 63 downto 0 );
|
| 952 |
|
|
|
| 953 |
|
|
begin
|
| 954 |
|
|
|
| 955 |
|
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
| 956 |
|
|
writeline( log, str );
|
| 957 |
|
|
|
| 958 |
|
|
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
| 959 |
|
|
for ii in 0 to 256 loop
|
| 960 |
|
|
adr:= x"00100000";
|
| 961 |
|
|
adr:=adr + ii*4;
|
| 962 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| 963 |
|
|
end loop;
|
| 964 |
|
|
|
| 965 |
|
|
|
| 966 |
|
|
data64 :=x"0000000000000000";
|
| 967 |
|
|
data64n := not data64;
|
| 968 |
|
|
|
| 969 |
|
|
---- Çàïîëíåíèå áëîêà 0 ----
|
| 970 |
|
|
adr:= x"00800000";
|
| 971 |
|
|
data:=x"A5A50123";
|
| 972 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 973 |
|
|
adr:=adr + 4;
|
| 974 |
|
|
|
| 975 |
|
|
data:=x"00000000";
|
| 976 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 977 |
|
|
adr:=adr + 4;
|
| 978 |
|
|
|
| 979 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 980 |
|
|
adr:=adr + 4;
|
| 981 |
|
|
|
| 982 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 983 |
|
|
adr:=adr + 4;
|
| 984 |
|
|
|
| 985 |
|
|
data64:=data64 + 1;
|
| 986 |
|
|
data64n := not data64;
|
| 987 |
|
|
|
| 988 |
|
|
for ii in 0 to 254 loop
|
| 989 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
| 990 |
|
|
adr:=adr + 4;
|
| 991 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
| 992 |
|
|
adr:=adr + 4;
|
| 993 |
|
|
|
| 994 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 995 |
|
|
adr:=adr + 4;
|
| 996 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 997 |
|
|
adr:=adr + 4;
|
| 998 |
|
|
|
| 999 |
|
|
data64:=data64 + 1;
|
| 1000 |
|
|
data64n := not data64;
|
| 1001 |
|
|
|
| 1002 |
|
|
end loop;
|
| 1003 |
|
|
|
| 1004 |
|
|
---- Çàïîëíåíèå áëîêà 1 ----
|
| 1005 |
|
|
adr:= x"00801000";
|
| 1006 |
|
|
data:=x"A5A50123";
|
| 1007 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1008 |
|
|
adr:=adr + 4;
|
| 1009 |
|
|
|
| 1010 |
|
|
data:=x"00000001";
|
| 1011 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1012 |
|
|
adr:=adr + 4;
|
| 1013 |
|
|
|
| 1014 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1015 |
|
|
adr:=adr + 4;
|
| 1016 |
|
|
|
| 1017 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1018 |
|
|
adr:=adr + 4;
|
| 1019 |
|
|
|
| 1020 |
|
|
data64:=data64 + 1;
|
| 1021 |
|
|
data64n := not data64;
|
| 1022 |
|
|
|
| 1023 |
|
|
for ii in 0 to 254 loop
|
| 1024 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
| 1025 |
|
|
adr:=adr + 4;
|
| 1026 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
| 1027 |
|
|
adr:=adr + 4;
|
| 1028 |
|
|
|
| 1029 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1030 |
|
|
adr:=adr + 4;
|
| 1031 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1032 |
|
|
adr:=adr + 4;
|
| 1033 |
|
|
|
| 1034 |
|
|
data64:=data64 + 1;
|
| 1035 |
|
|
data64n := not data64;
|
| 1036 |
|
|
|
| 1037 |
|
|
end loop;
|
| 1038 |
|
|
|
| 1039 |
|
|
---- Çàïîëíåíèå áëîêà 2 ----
|
| 1040 |
|
|
adr:= x"00802000";
|
| 1041 |
|
|
data:=x"A5A50123";
|
| 1042 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1043 |
|
|
adr:=adr + 4;
|
| 1044 |
|
|
|
| 1045 |
|
|
data:=x"00000002";
|
| 1046 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1047 |
|
|
adr:=adr + 4;
|
| 1048 |
|
|
|
| 1049 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1050 |
|
|
adr:=adr + 4;
|
| 1051 |
|
|
|
| 1052 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1053 |
|
|
adr:=adr + 4;
|
| 1054 |
|
|
|
| 1055 |
|
|
data64:=data64 + 1;
|
| 1056 |
|
|
data64n := not data64;
|
| 1057 |
|
|
|
| 1058 |
|
|
for ii in 0 to 254 loop
|
| 1059 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
| 1060 |
|
|
adr:=adr + 4;
|
| 1061 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
| 1062 |
|
|
adr:=adr + 4;
|
| 1063 |
|
|
|
| 1064 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1065 |
|
|
adr:=adr + 4;
|
| 1066 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1067 |
|
|
adr:=adr + 4;
|
| 1068 |
|
|
|
| 1069 |
|
|
data64:=data64 + 1;
|
| 1070 |
|
|
data64n := not data64;
|
| 1071 |
|
|
|
| 1072 |
|
|
end loop;
|
| 1073 |
|
|
|
| 1074 |
|
|
---- Çàïîëíåíèå áëîêà 3 ----
|
| 1075 |
|
|
adr:= x"00803000";
|
| 1076 |
|
|
data:=x"A5A50123";
|
| 1077 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1078 |
|
|
adr:=adr + 4;
|
| 1079 |
|
|
|
| 1080 |
|
|
data:=x"00000003";
|
| 1081 |
|
|
int_mem_write( cmd, ret, adr, data );
|
| 1082 |
|
|
adr:=adr + 4;
|
| 1083 |
|
|
|
| 1084 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1085 |
|
|
adr:=adr + 4;
|
| 1086 |
|
|
|
| 1087 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1088 |
|
|
adr:=adr + 4;
|
| 1089 |
|
|
|
| 1090 |
|
|
data64:=data64 + 1;
|
| 1091 |
|
|
data64n := not data64;
|
| 1092 |
|
|
|
| 1093 |
|
|
for ii in 0 to 254 loop
|
| 1094 |
|
|
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
|
| 1095 |
|
|
adr:=adr + 4;
|
| 1096 |
|
|
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
|
| 1097 |
|
|
adr:=adr + 4;
|
| 1098 |
|
|
|
| 1099 |
|
|
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
|
| 1100 |
|
|
adr:=adr + 4;
|
| 1101 |
|
|
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
|
| 1102 |
|
|
adr:=adr + 4;
|
| 1103 |
|
|
|
| 1104 |
|
|
data64:=data64 + 1;
|
| 1105 |
|
|
data64n := not data64;
|
| 1106 |
|
|
|
| 1107 |
|
|
end loop;
|
| 1108 |
|
|
-- for ii in 0 to 256 loop
|
| 1109 |
|
|
-- adr:= x"00802000";
|
| 1110 |
|
|
-- adr:=adr + ii*4;
|
| 1111 |
|
|
-- data:=x"00A20000";
|
| 1112 |
|
|
-- data:=data + ii;
|
| 1113 |
|
|
-- int_mem_write( cmd, ret, adr, data );
|
| 1114 |
|
|
-- end loop;
|
| 1115 |
|
|
--
|
| 1116 |
|
|
-- for ii in 0 to 256 loop
|
| 1117 |
|
|
-- adr:= x"00803000";
|
| 1118 |
|
|
-- adr:=adr + ii*4;
|
| 1119 |
|
|
-- data:=x"00A30000";
|
| 1120 |
|
|
-- data:=data + ii;
|
| 1121 |
|
|
-- int_mem_write( cmd, ret, adr, data );
|
| 1122 |
|
|
-- end loop;
|
| 1123 |
|
|
|
| 1124 |
|
|
--- Áëîê 0 ---
|
| 1125 |
|
|
|
| 1126 |
|
|
--- Äåñêðèïòîð 0 ---
|
| 1127 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
| 1128 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000011" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
| 1129 |
|
|
|
| 1130 |
|
|
--- Äåñêðèïòîð 1 ---
|
| 1131 |
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
| 1132 |
|
|
int_mem_write( cmd, ret, x"0010000C", x"00000012" ); -- ïåðåõîä ê ñëåäóþùåìó áëîêó
|
| 1133 |
|
|
|
| 1134 |
|
|
--- Äåñêðèïòîð 2 ---
|
| 1135 |
|
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
|
| 1136 |
|
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
| 1137 |
|
|
|
| 1138 |
|
|
|
| 1139 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
| 1140 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"14A44953" );
|
| 1141 |
|
|
|
| 1142 |
|
|
|
| 1143 |
|
|
--- Áëîê 1 ---
|
| 1144 |
|
|
|
| 1145 |
|
|
--- Äåñêðèïòîð 0 ---
|
| 1146 |
|
|
int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
| 1147 |
|
|
int_mem_write( cmd, ret, x"00100204", x"00000011" ); -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
|
| 1148 |
|
|
|
| 1149 |
|
|
--- Äåñêðèïòîð 1 ---
|
| 1150 |
|
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
| 1151 |
|
|
int_mem_write( cmd, ret, x"0010020C", x"00000010" ); -- îñòàíîâêà
|
| 1152 |
|
|
|
| 1153 |
|
|
|
| 1154 |
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
| 1155 |
|
|
int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" );
|
| 1156 |
|
|
|
| 1157 |
|
|
|
| 1158 |
|
|
|
| 1159 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
|
| 1160 |
|
|
block_write( cmd, ret, 5, 8, x"00000023" ); -- DMA_MODE - ñ çàïðîñàìè
|
| 1161 |
|
|
--block_write( cmd, ret, 5, 8, x"00000021" ); -- DMA_MODE - áåç çàïðîñîâ
|
| 1162 |
|
|
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 1163 |
|
|
|
| 1164 |
|
|
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
|
| 1165 |
|
|
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
|
| 1166 |
|
|
block_write( cmd, ret, 5, 23, x"00001000" ); -- LOCAL_ADR
|
| 1167 |
|
|
|
| 1168 |
|
|
|
| 1169 |
|
|
---- Ïîäãîòîâêà òåòðàäû ----
|
| 1170 |
|
|
-- trd_test_mode( cmd, ret, 0 ); -- ïåðåõîä â ðàáî÷èé ðåæèì --
|
| 1171 |
|
|
-- trd_wait_cmd( cmd, ret, 0, 16, x"1700" ); -- DMAR0 - îò òåòðàäû 7 --
|
| 1172 |
|
|
--
|
| 1173 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" ); -- Ðàçìåð áëîêà = 4 êÁ --
|
| 1174 |
|
|
|
| 1175 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000001" ); -- ñáðîñ
|
| 1176 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
|
| 1177 |
|
|
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data ); -- ÷òåíèå èäåíòèôèêàòîðà áëîêà
|
| 1178 |
|
|
write( str, string'("BLOCK TEST_CHECK ID: " ));
|
| 1179 |
|
|
hwrite( str, data );
|
| 1180 |
|
|
writeline( log, str );
|
| 1181 |
|
|
|
| 1182 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_SIZE, x"00000001" ); -- ðàçìåð áëîêà - 1 êèëîáàéò
|
| 1183 |
|
|
|
| 1184 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"000006A0" ); -- çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè
|
| 1185 |
|
|
--
|
| 1186 |
|
|
--
|
| 1187 |
|
|
--
|
| 1188 |
|
|
data:=wb_block_check_burst_ctrl_build('1', 40, 473);
|
| 1189 |
|
|
wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
|
| 1190 |
|
|
--
|
| 1191 |
|
|
--
|
| 1192 |
|
|
--
|
| 1193 |
|
|
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
|
| 1194 |
|
|
|
| 1195 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
|
| 1196 |
|
|
--
|
| 1197 |
|
|
-- trd_wait_cmd( cmd, ret, 7, 0, x"2038" ); -- çàïóñê òåòðàäû DIO_OUT
|
| 1198 |
|
|
--
|
| 1199 |
|
|
-- trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" ); -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
|
| 1200 |
|
|
|
| 1201 |
|
|
wait for 20 us;
|
| 1202 |
|
|
|
| 1203 |
|
|
|
| 1204 |
|
|
for ii in 0 to 20 loop
|
| 1205 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
| 1206 |
|
|
|
| 1207 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1208 |
|
|
if( data( 8 )='1' ) then
|
| 1209 |
|
|
write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
|
| 1210 |
|
|
error := 0;
|
| 1211 |
|
|
exit;
|
| 1212 |
|
|
else
|
| 1213 |
|
|
write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
|
| 1214 |
|
|
error := error + 1;
|
| 1215 |
|
|
wait for 10 us;
|
| 1216 |
|
|
end if;
|
| 1217 |
|
|
|
| 1218 |
|
|
writeline( log, str );
|
| 1219 |
|
|
end loop;
|
| 1220 |
|
|
|
| 1221 |
|
|
|
| 1222 |
|
|
if( error=0 ) then
|
| 1223 |
|
|
|
| 1224 |
|
|
kk:=0;
|
| 1225 |
|
|
loop
|
| 1226 |
|
|
|
| 1227 |
|
|
-- trd_status( cmd, ret, 6, status );
|
| 1228 |
|
|
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
| 1229 |
|
|
|
| 1230 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
| 1231 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1232 |
|
|
|
| 1233 |
|
|
if( data(4)='1' ) then
|
| 1234 |
|
|
write( str, string'(" - çàâåðøåíà ïåðåäà÷à áëîêà " ));
|
| 1235 |
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
| 1236 |
|
|
kk:=kk+1;
|
| 1237 |
|
|
if( kk=4 ) then
|
| 1238 |
|
|
exit;
|
| 1239 |
|
|
end if;
|
| 1240 |
|
|
end if;
|
| 1241 |
|
|
writeline( log, str );
|
| 1242 |
|
|
|
| 1243 |
|
|
wait for 500 ns;
|
| 1244 |
|
|
|
| 1245 |
|
|
|
| 1246 |
|
|
end loop;
|
| 1247 |
|
|
|
| 1248 |
|
|
---- Îæèäàíèå çàâåðøåíèÿ DMA ----
|
| 1249 |
|
|
dma_complete := 0;
|
| 1250 |
|
|
for ii in 0 to 100 loop
|
| 1251 |
|
|
|
| 1252 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
| 1253 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1254 |
|
|
|
| 1255 |
|
|
if( data(4)='1' ) then
|
| 1256 |
|
|
write( str, string'(" - çàâåðø¸íà ïåðåäà÷à áëîêà " ));
|
| 1257 |
|
|
|
| 1258 |
|
|
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
| 1259 |
|
|
|
| 1260 |
|
|
end if;
|
| 1261 |
|
|
writeline( log, str );
|
| 1262 |
|
|
|
| 1263 |
|
|
|
| 1264 |
|
|
if( data(5)='1' ) then
|
| 1265 |
|
|
write( str, string'(" - DMA çàâåðø¸í " ));
|
| 1266 |
|
|
dma_complete := 1;
|
| 1267 |
|
|
|
| 1268 |
|
|
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - ñáðîñ EOT
|
| 1269 |
|
|
|
| 1270 |
|
|
end if;
|
| 1271 |
|
|
writeline( log, str );
|
| 1272 |
|
|
|
| 1273 |
|
|
if( dma_complete=1 ) then
|
| 1274 |
|
|
exit;
|
| 1275 |
|
|
end if;
|
| 1276 |
|
|
|
| 1277 |
|
|
wait for 1 us;
|
| 1278 |
|
|
|
| 1279 |
|
|
end loop;
|
| 1280 |
|
|
|
| 1281 |
|
|
writeline( log, str );
|
| 1282 |
|
|
|
| 1283 |
|
|
if( dma_complete=0 ) then
|
| 1284 |
|
|
write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
|
| 1285 |
|
|
writeline( log, str );
|
| 1286 |
|
|
error:=error+1;
|
| 1287 |
|
|
end if;
|
| 1288 |
|
|
|
| 1289 |
|
|
end if;
|
| 1290 |
|
|
|
| 1291 |
|
|
for ii in 0 to 3 loop
|
| 1292 |
|
|
|
| 1293 |
|
|
block_read( cmd, ret, 5, 16, data ); -- STATUS
|
| 1294 |
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1295 |
|
|
writeline( log, str );
|
| 1296 |
|
|
wait for 500 ns;
|
| 1297 |
|
|
|
| 1298 |
|
|
end loop;
|
| 1299 |
|
|
|
| 1300 |
|
|
wait for 10 us;
|
| 1301 |
|
|
|
| 1302 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
|
| 1303 |
|
|
write( str, string'( "Ïðèíÿòî áëîêîâ: " ) );
|
| 1304 |
|
|
hwrite( str, data );
|
| 1305 |
|
|
kk := conv_integer( data );
|
| 1306 |
|
|
if( 4/=kk ) then
|
| 1307 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
| 1308 |
|
|
error := error + 1;
|
| 1309 |
|
|
else
|
| 1310 |
|
|
write( str, string'( " - Ok" ) );
|
| 1311 |
|
|
end if;
|
| 1312 |
|
|
writeline( log, str );
|
| 1313 |
|
|
|
| 1314 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
|
| 1315 |
|
|
write( str, string'( "TEST_CHECK_BL_OK: " ) );
|
| 1316 |
|
|
hwrite( str, data );
|
| 1317 |
|
|
kk := conv_integer( data );
|
| 1318 |
|
|
if( 3/=kk ) then
|
| 1319 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
| 1320 |
|
|
error := error + 1;
|
| 1321 |
|
|
else
|
| 1322 |
|
|
write( str, string'( " - Ok" ) );
|
| 1323 |
|
|
end if;
|
| 1324 |
|
|
writeline( log, str );
|
| 1325 |
|
|
|
| 1326 |
|
|
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
|
| 1327 |
|
|
write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
|
| 1328 |
|
|
hwrite( str, data );
|
| 1329 |
|
|
kk := conv_integer( data );
|
| 1330 |
|
|
if( 0/=kk ) then
|
| 1331 |
|
|
write( str, string'( " - Îøèáêà" ) );
|
| 1332 |
|
|
error := error + 1;
|
| 1333 |
|
|
else
|
| 1334 |
|
|
write( str, string'( " - Ok" ) );
|
| 1335 |
|
|
end if;
|
| 1336 |
|
|
writeline( log, str );
|
| 1337 |
|
|
|
| 1338 |
|
|
|
| 1339 |
|
|
|
| 1340 |
|
|
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 1341 |
|
|
|
| 1342 |
|
|
|
| 1343 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 1344 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
| 1345 |
|
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 1346 |
|
|
|
| 1347 |
|
|
|
| 1348 |
|
|
writeline( log, str );
|
| 1349 |
|
|
if( error=0 ) then
|
| 1350 |
|
|
write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
|
| 1351 |
|
|
cnt_ok := cnt_ok + 1;
|
| 1352 |
|
|
else
|
| 1353 |
|
|
write( str, string'(" Òåñò íå âûïîëíåí " ));
|
| 1354 |
|
|
cnt_error := cnt_error + 1;
|
| 1355 |
|
|
end if;
|
| 1356 |
|
|
writeline( log, str );
|
| 1357 |
|
|
writeline( log, str );
|
| 1358 |
|
|
|
| 1359 |
|
|
end test_adm_write_16kb;
|
| 1360 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1361 |
|
|
--
|
| 1362 |
|
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
| 1363 |
|
|
--
|
| 1364 |
|
|
procedure test_num_1 (
|
| 1365 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 1366 |
|
|
signal ret: in bh_ret --! answer
|
| 1367 |
16 |
dsmv |
) is
|
| 1368 |
|
|
|
| 1369 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 1370 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
| 1371 |
|
|
variable str : line;
|
| 1372 |
|
|
|
| 1373 |
|
|
variable error : integer:=0;
|
| 1374 |
|
|
variable dma_complete : integer:=0;
|
| 1375 |
|
|
|
| 1376 |
|
|
begin
|
| 1377 |
|
|
-- Init Header
|
| 1378 |
|
|
write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
|
| 1379 |
|
|
writeline( log, str );
|
| 1380 |
|
|
--
|
| 1381 |
|
|
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
| 1382 |
|
|
for ii in 0 to 127 loop
|
| 1383 |
|
|
adr:= x"00100000";
|
| 1384 |
|
|
adr:=adr + ii*4;
|
| 1385 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| 1386 |
|
|
end loop;
|
| 1387 |
|
|
-- HOST MEM Writes:
|
| 1388 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
|
| 1389 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
|
| 1390 |
|
|
|
| 1391 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
|
| 1392 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
|
| 1393 |
|
|
--
|
| 1394 |
|
|
---- Ïðîãðàììèðîâàíèå êàíàëà DMA ---- PE_EXT_FIFO module: have bug in PE_EXT_FIFO, for check WB we will make a trick:
|
| 1395 |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
|
| 1396 |
|
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 1397 |
|
|
|
| 1398 |
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
| 1399 |
|
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
| 1400 |
|
|
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
|
| 1401 |
|
|
|
| 1402 |
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 1403 |
|
|
--
|
| 1404 |
|
|
-- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
|
| 1405 |
|
|
wait for 1 us;
|
| 1406 |
|
|
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
|
| 1407 |
|
|
--
|
| 1408 |
|
|
-- Delay for design
|
| 1409 |
|
|
wait for 20 us;
|
| 1410 |
|
|
--
|
| 1411 |
|
|
-- Read STATUS
|
| 1412 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1413 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
|
| 1414 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1415 |
|
|
if( data( 8 )='1' ) then
|
| 1416 |
|
|
write( str, string'(" - Descriptor==OK" ));
|
| 1417 |
|
|
else
|
| 1418 |
|
|
write( str, string'(" - Descriptor RD ERR" ));
|
| 1419 |
|
|
error := error + 1;
|
| 1420 |
|
|
end if;
|
| 1421 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1422 |
|
|
--
|
| 1423 |
|
|
-- Deal with STATUS Results:
|
| 1424 |
|
|
if( error=0 ) then -- w8ing for DMA final
|
| 1425 |
|
|
dma_complete := 0;
|
| 1426 |
|
|
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
|
| 1427 |
|
|
-- Read STATUS
|
| 1428 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1429 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
|
| 1430 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1431 |
|
|
if( data(5)='1' ) then
|
| 1432 |
|
|
write( str, string'(" - DMA finished" ));
|
| 1433 |
|
|
dma_complete := 1;
|
| 1434 |
|
|
end if;
|
| 1435 |
|
|
writeline( log, str );
|
| 1436 |
|
|
-- Check "dma_complete"
|
| 1437 |
|
|
if( dma_complete=1 ) then
|
| 1438 |
|
|
exit; -- EXIT Loop on FINAL
|
| 1439 |
|
|
else
|
| 1440 |
|
|
wait for 1 us; -- DELAY in other case
|
| 1441 |
|
|
end if;
|
| 1442 |
|
|
end loop;
|
| 1443 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1444 |
|
|
|
| 1445 |
|
|
if( dma_complete=0 ) then -- check "dma_complete" after all
|
| 1446 |
|
|
write( str, string'("ERR - DMA not finished " ));
|
| 1447 |
|
|
writeline( log, str );
|
| 1448 |
|
|
error:=error+1;
|
| 1449 |
|
|
end if;
|
| 1450 |
|
|
|
| 1451 |
|
|
end if;
|
| 1452 |
|
|
--
|
| 1453 |
|
|
-- Print STATUS now
|
| 1454 |
|
|
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
|
| 1455 |
|
|
-- Read STATUS
|
| 1456 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1457 |
|
|
-- Construct LOG MSG in accordance to STATUS value
|
| 1458 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1459 |
|
|
-- upd LOGFILE
|
| 1460 |
|
|
writeline( log, str );
|
| 1461 |
|
|
wait for 500 ns;
|
| 1462 |
|
|
end loop;
|
| 1463 |
|
|
--
|
| 1464 |
|
|
-- Now STOP Design
|
| 1465 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 1466 |
|
|
--
|
| 1467 |
|
|
-- Now print RX values:
|
| 1468 |
|
|
--
|
| 1469 |
|
|
-- Construct Header:
|
| 1470 |
|
|
writeline( log, str );
|
| 1471 |
|
|
write( str, string'("PRINT 1st 15 RX values: " ));
|
| 1472 |
|
|
writeline( log, str );
|
| 1473 |
|
|
-- Get first 15 DATA values and print it:
|
| 1474 |
|
|
for ii in 0 to 15 loop
|
| 1475 |
|
|
adr:= x"00800000"; -- init ADDR value
|
| 1476 |
|
|
adr:=adr + ii*4; -- upd addr to curr idx
|
| 1477 |
|
|
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
|
| 1478 |
|
|
-- Construct LOG MSG in accordance to HOST MEM Read value
|
| 1479 |
|
|
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 1480 |
|
|
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
|
| 1481 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1482 |
|
|
end loop;
|
| 1483 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1484 |
|
|
--
|
| 1485 |
|
|
-- Final CHECK errors:
|
| 1486 |
|
|
if( error=0 ) then
|
| 1487 |
|
|
write( str, string'("SUCCSESSFULL FINAL " ));
|
| 1488 |
|
|
cnt_ok := cnt_ok + 1;
|
| 1489 |
|
|
else
|
| 1490 |
|
|
write( str, string'("FAILED FINAL " ));
|
| 1491 |
|
|
cnt_error := cnt_error + 1;
|
| 1492 |
|
|
end if;
|
| 1493 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1494 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1495 |
|
|
--
|
| 1496 |
|
|
-- END
|
| 1497 |
|
|
end test_num_1;
|
| 1498 |
|
|
--
|
| 1499 |
|
|
--
|
| 1500 |
|
|
--
|
| 1501 |
|
|
procedure test_num_2 (
|
| 1502 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 1503 |
|
|
signal ret: in bh_ret --! answer
|
| 1504 |
16 |
dsmv |
) is
|
| 1505 |
|
|
|
| 1506 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 1507 |
|
|
variable data : std_logic_vector( 31 downto 0 );
|
| 1508 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| 1509 |
|
|
variable str : line;
|
| 1510 |
|
|
|
| 1511 |
|
|
variable error : integer:=0;
|
| 1512 |
|
|
variable dma_complete : integer:=0;
|
| 1513 |
|
|
|
| 1514 |
|
|
begin
|
| 1515 |
|
|
-- Init Header
|
| 1516 |
|
|
write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
|
| 1517 |
|
|
writeline( log, str );
|
| 1518 |
|
|
--
|
| 1519 |
|
|
---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
|
| 1520 |
|
|
for ii in 0 to 127 loop
|
| 1521 |
|
|
adr:= x"00100000";
|
| 1522 |
|
|
adr:=adr + ii*4;
|
| 1523 |
|
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
| 1524 |
|
|
end loop;
|
| 1525 |
|
|
-- HOST MEM Writes:
|
| 1526 |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
|
| 1527 |
|
|
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
|
| 1528 |
|
|
|
| 1529 |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
|
| 1530 |
|
|
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
|
| 1531 |
|
|
--
|
| 1532 |
|
|
-- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
|
| 1533 |
|
|
adr :=x"20002048"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
|
| 1534 |
|
|
data64 :=x"0000000000000001"; -- TEST_GEN_SIZE=x01
|
| 1535 |
|
|
data_write64(cmd, ret, adr, data64);-- PCIE WR
|
| 1536 |
|
|
|
| 1537 |
|
|
adr :=x"20002040"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
|
| 1538 |
|
|
data64 :=x"0000000000000022"; -- TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
|
| 1539 |
|
|
data_write64(cmd, ret, adr, data64);-- PCIE WR
|
| 1540 |
|
|
|
| 1541 |
|
|
-- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
|
| 1542 |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
|
| 1543 |
|
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
| 1544 |
|
|
|
| 1545 |
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
| 1546 |
|
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
| 1547 |
|
|
block_write( cmd, ret, 4, 23, x"00003000" ); -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
|
| 1548 |
|
|
|
| 1549 |
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
| 1550 |
|
|
--
|
| 1551 |
|
|
-- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
|
| 1552 |
|
|
wait for 1 us;
|
| 1553 |
|
|
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
|
| 1554 |
|
|
--
|
| 1555 |
|
|
-- Delay for design
|
| 1556 |
|
|
wait for 20 us;
|
| 1557 |
|
|
--
|
| 1558 |
|
|
-- Read STATUS (check RD DESCR status):
|
| 1559 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1560 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
|
| 1561 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1562 |
|
|
if( data( 8 )='1' ) then
|
| 1563 |
|
|
write( str, string'(" - Descriptor==OK" ));
|
| 1564 |
|
|
else
|
| 1565 |
|
|
write( str, string'(" - Descriptor RD ERR" ));
|
| 1566 |
|
|
error := error + 1;
|
| 1567 |
|
|
end if;
|
| 1568 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1569 |
|
|
--
|
| 1570 |
|
|
-- W8ing for DMA finish:
|
| 1571 |
|
|
if( error=0 ) then -- w8ing for DMA final
|
| 1572 |
|
|
dma_complete := 0;
|
| 1573 |
|
|
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
|
| 1574 |
|
|
-- Read STATUS
|
| 1575 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1576 |
|
|
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
|
| 1577 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1578 |
|
|
if( data(5)='1' ) then
|
| 1579 |
|
|
write( str, string'(" - DMA finished" ));
|
| 1580 |
|
|
dma_complete := 1;
|
| 1581 |
|
|
end if;
|
| 1582 |
|
|
writeline( log, str );
|
| 1583 |
|
|
-- Check "dma_complete"
|
| 1584 |
|
|
if( dma_complete=1 ) then
|
| 1585 |
|
|
exit; -- EXIT Loop on FINAL
|
| 1586 |
|
|
else
|
| 1587 |
|
|
wait for 1 us; -- DELAY in other case
|
| 1588 |
|
|
end if;
|
| 1589 |
|
|
end loop;
|
| 1590 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1591 |
|
|
|
| 1592 |
|
|
if( dma_complete=0 ) then -- check "dma_complete" after all
|
| 1593 |
|
|
write( str, string'("ERR - DMA not finished " ));
|
| 1594 |
|
|
writeline( log, str );
|
| 1595 |
|
|
error:=error+1;
|
| 1596 |
|
|
end if;
|
| 1597 |
|
|
|
| 1598 |
|
|
end if;
|
| 1599 |
|
|
--
|
| 1600 |
|
|
-- Print STATUS in ERR
|
| 1601 |
|
|
if (error /= 0 ) then
|
| 1602 |
|
|
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
|
| 1603 |
|
|
-- Read STATUS
|
| 1604 |
|
|
block_read( cmd, ret, 4, 16, data );
|
| 1605 |
|
|
-- Construct LOG MSG in accordance to STATUS value
|
| 1606 |
|
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
| 1607 |
|
|
-- upd LOGFILE
|
| 1608 |
|
|
writeline( log, str );
|
| 1609 |
|
|
wait for 500 ns;
|
| 1610 |
|
|
end loop;
|
| 1611 |
|
|
end if;
|
| 1612 |
|
|
--
|
| 1613 |
|
|
-- Now STOP Design
|
| 1614 |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
| 1615 |
|
|
--
|
| 1616 |
|
|
-- Now print RX values:
|
| 1617 |
|
|
--
|
| 1618 |
|
|
-- Construct Header:
|
| 1619 |
|
|
writeline( log, str );
|
| 1620 |
|
|
write( str, string'("PRINT 1st 15 RX values: " ));
|
| 1621 |
|
|
writeline( log, str );
|
| 1622 |
|
|
-- Get first 15 DATA values and print it:
|
| 1623 |
|
|
for ii in 0 to 15 loop
|
| 1624 |
|
|
adr:= x"00800000"; -- init ADDR value
|
| 1625 |
|
|
adr:=adr + ii*4; -- upd addr to curr idx
|
| 1626 |
|
|
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
|
| 1627 |
|
|
-- Construct LOG MSG in accordance to HOST MEM Read value
|
| 1628 |
|
|
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
| 1629 |
|
|
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
|
| 1630 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1631 |
|
|
end loop;
|
| 1632 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1633 |
|
|
--
|
| 1634 |
|
|
-- Final CHECK errors:
|
| 1635 |
|
|
if( error=0 ) then
|
| 1636 |
|
|
write( str, string'(" stb SUCCSESSFULL FINAL " ));
|
| 1637 |
|
|
cnt_ok := cnt_ok + 1;
|
| 1638 |
|
|
else
|
| 1639 |
|
|
write( str, string'(" stb FAILED FINAL " ));
|
| 1640 |
|
|
cnt_error := cnt_error + 1;
|
| 1641 |
|
|
end if;
|
| 1642 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1643 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1644 |
|
|
--
|
| 1645 |
|
|
-- END
|
| 1646 |
|
|
end test_num_2;
|
| 1647 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1648 |
|
|
--
|
| 1649 |
|
|
-- My procedure for test WB stuff in Design:
|
| 1650 |
|
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
| 1651 |
|
|
--
|
| 1652 |
|
|
procedure test_wb_1 (
|
| 1653 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 1654 |
|
|
signal ret: in bh_ret --! answer
|
| 1655 |
16 |
dsmv |
) is
|
| 1656 |
|
|
|
| 1657 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 1658 |
|
|
variable data32 : std_logic_vector( 31 downto 0 );
|
| 1659 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| 1660 |
|
|
variable str : line;
|
| 1661 |
|
|
|
| 1662 |
|
|
variable error : integer:=0;
|
| 1663 |
|
|
variable dma_complete : integer:=0;
|
| 1664 |
|
|
|
| 1665 |
|
|
--
|
| 1666 |
|
|
--
|
| 1667 |
|
|
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
|
| 1668 |
|
|
type wb_cfg_slave_data is record
|
| 1669 |
|
|
const : wb_cfg_slave_value(7 downto 0);
|
| 1670 |
|
|
cmd : wb_cfg_slave_value(7 downto 0);
|
| 1671 |
|
|
sts : wb_cfg_slave_value(7 downto 0);
|
| 1672 |
|
|
end record;
|
| 1673 |
|
|
--
|
| 1674 |
|
|
--
|
| 1675 |
|
|
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
|
| 1676 |
|
|
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
|
| 1677 |
|
|
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
|
| 1678 |
|
|
|
| 1679 |
|
|
|
| 1680 |
|
|
begin
|
| 1681 |
|
|
-- Init Header
|
| 1682 |
|
|
write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
|
| 1683 |
|
|
writeline( log, str );
|
| 1684 |
|
|
--
|
| 1685 |
|
|
-- Read "TEST_CHECK.WB_CFG_SLAVE"
|
| 1686 |
|
|
write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
|
| 1687 |
|
|
writeline( log, str );
|
| 1688 |
|
|
adr := x"20000000";
|
| 1689 |
|
|
|
| 1690 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
|
| 1691 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
|
| 1692 |
|
|
-- PCIE RD
|
| 1693 |
|
|
data_read64(cmd, ret, adr, data64);
|
| 1694 |
|
|
-- Put RD_Value to apropriate holder
|
| 1695 |
|
|
if (i=0) then -- const
|
| 1696 |
|
|
st_wb_cfg_slave_data_0.const(j) := data64;
|
| 1697 |
|
|
elsif (i=1) then -- cmd
|
| 1698 |
|
|
st_wb_cfg_slave_data_0.cmd(j) := data64;
|
| 1699 |
|
|
else -- sts
|
| 1700 |
|
|
st_wb_cfg_slave_data_0.sts(j) := data64;
|
| 1701 |
|
|
end if;
|
| 1702 |
|
|
-- Incr ADDR
|
| 1703 |
|
|
adr := adr + x"00000008";
|
| 1704 |
|
|
-- Print RD_Value
|
| 1705 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1706 |
|
|
writeline( log, str );
|
| 1707 |
|
|
|
| 1708 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
|
| 1709 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
|
| 1710 |
|
|
|
| 1711 |
|
|
--
|
| 1712 |
|
|
-- Write
|
| 1713 |
|
|
write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
|
| 1714 |
|
|
writeline( log, str );
|
| 1715 |
|
|
adr := x"20000000";
|
| 1716 |
|
|
|
| 1717 |
|
|
TEST_CHECK_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
|
| 1718 |
|
|
TEST_CHECK_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
|
| 1719 |
|
|
-- Prepare WR_Value
|
| 1720 |
|
|
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
|
| 1721 |
|
|
-- PCIE WR
|
| 1722 |
|
|
data_write64(cmd, ret, adr, data64);
|
| 1723 |
|
|
-- Put WR_Value to apropriate holder
|
| 1724 |
|
|
if (i=0) then -- const
|
| 1725 |
|
|
st_wb_cfg_slave_data_1.const(j) := data64;
|
| 1726 |
|
|
elsif (i=1) then -- cmd
|
| 1727 |
|
|
st_wb_cfg_slave_data_1.cmd(j) := data64;
|
| 1728 |
|
|
else -- sts
|
| 1729 |
|
|
st_wb_cfg_slave_data_1.sts(j) := data64;
|
| 1730 |
|
|
end if;
|
| 1731 |
|
|
-- Incr ADDR
|
| 1732 |
|
|
adr := adr + x"00000008";
|
| 1733 |
|
|
-- Print WR_Value
|
| 1734 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1735 |
|
|
writeline( log, str );
|
| 1736 |
|
|
|
| 1737 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
|
| 1738 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
|
| 1739 |
|
|
|
| 1740 |
|
|
--
|
| 1741 |
|
|
-- Read
|
| 1742 |
|
|
write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
|
| 1743 |
|
|
writeline( log, str );
|
| 1744 |
|
|
adr := x"20000000";
|
| 1745 |
|
|
|
| 1746 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
|
| 1747 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
|
| 1748 |
|
|
-- PCIE RD
|
| 1749 |
|
|
data_read64(cmd, ret, adr, data64);
|
| 1750 |
|
|
-- Put RD_Value to apropriate holder
|
| 1751 |
|
|
if (i=0) then -- const
|
| 1752 |
|
|
st_wb_cfg_slave_data_2.const(j) := data64;
|
| 1753 |
|
|
elsif (i=1) then -- cmd
|
| 1754 |
|
|
st_wb_cfg_slave_data_2.cmd(j) := data64;
|
| 1755 |
|
|
else -- sts
|
| 1756 |
|
|
st_wb_cfg_slave_data_2.sts(j) := data64;
|
| 1757 |
|
|
end if;
|
| 1758 |
|
|
-- Incr ADDR
|
| 1759 |
|
|
adr := adr + x"00000008";
|
| 1760 |
|
|
-- Print RD_Value
|
| 1761 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1762 |
|
|
writeline( log, str );
|
| 1763 |
|
|
|
| 1764 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
|
| 1765 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
|
| 1766 |
|
|
|
| 1767 |
|
|
--
|
| 1768 |
|
|
-- Compare results
|
| 1769 |
|
|
write( str, string'("4) Process Results:"));
|
| 1770 |
|
|
writeline( log, str );
|
| 1771 |
|
|
-- cmp#0 - constants
|
| 1772 |
|
|
CMP_CONST : for i in 0 to 7 loop
|
| 1773 |
|
|
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
|
| 1774 |
|
|
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1775 |
|
|
writeline( log, str );
|
| 1776 |
|
|
error := error + 1;
|
| 1777 |
|
|
end if;
|
| 1778 |
|
|
end loop CMP_CONST;
|
| 1779 |
|
|
-- cmp#1 - commands
|
| 1780 |
|
|
CMP_CMD : for i in 0 to 7 loop
|
| 1781 |
|
|
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
|
| 1782 |
|
|
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1783 |
|
|
writeline( log, str );
|
| 1784 |
|
|
error := error + 1;
|
| 1785 |
|
|
end if;
|
| 1786 |
|
|
end loop CMP_CMD;
|
| 1787 |
|
|
-- cmp#2 - status
|
| 1788 |
|
|
CMP_STATUS : for i in 0 to 7 loop
|
| 1789 |
|
|
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
|
| 1790 |
|
|
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1791 |
|
|
writeline( log, str );
|
| 1792 |
|
|
error := error + 1;
|
| 1793 |
|
|
end if;
|
| 1794 |
|
|
end loop CMP_STATUS;
|
| 1795 |
|
|
-- print OK
|
| 1796 |
|
|
if (error = 0) then
|
| 1797 |
|
|
write( str, string'(" Results==OK"));
|
| 1798 |
|
|
writeline( log, str );
|
| 1799 |
|
|
cnt_ok := cnt_ok + 1;
|
| 1800 |
|
|
else
|
| 1801 |
|
|
cnt_error := cnt_error + 1;
|
| 1802 |
|
|
end if;
|
| 1803 |
|
|
|
| 1804 |
|
|
-- Final Header
|
| 1805 |
|
|
write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
|
| 1806 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1807 |
|
|
--
|
| 1808 |
|
|
-- END
|
| 1809 |
|
|
end test_wb_1;
|
| 1810 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1811 |
|
|
--
|
| 1812 |
|
|
-- My procedure for test WB stuff in Design:
|
| 1813 |
|
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
| 1814 |
|
|
--
|
| 1815 |
|
|
procedure test_wb_2 (
|
| 1816 |
18 |
dsmv |
signal cmd: out bh_cmd; --! command
|
| 1817 |
|
|
signal ret: in bh_ret --! answer
|
| 1818 |
16 |
dsmv |
) is
|
| 1819 |
|
|
|
| 1820 |
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
| 1821 |
|
|
variable data32 : std_logic_vector( 31 downto 0 );
|
| 1822 |
|
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| 1823 |
|
|
variable str : line;
|
| 1824 |
|
|
|
| 1825 |
|
|
variable error : integer:=0;
|
| 1826 |
|
|
variable dma_complete : integer:=0;
|
| 1827 |
|
|
|
| 1828 |
|
|
--
|
| 1829 |
|
|
--
|
| 1830 |
|
|
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
|
| 1831 |
|
|
type wb_cfg_slave_data is record
|
| 1832 |
|
|
const : wb_cfg_slave_value(7 downto 0);
|
| 1833 |
|
|
cmd : wb_cfg_slave_value(7 downto 0);
|
| 1834 |
|
|
sts : wb_cfg_slave_value(7 downto 0);
|
| 1835 |
|
|
end record;
|
| 1836 |
|
|
--
|
| 1837 |
|
|
--
|
| 1838 |
|
|
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
|
| 1839 |
|
|
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
|
| 1840 |
|
|
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
|
| 1841 |
|
|
|
| 1842 |
|
|
|
| 1843 |
|
|
begin
|
| 1844 |
|
|
-- Init Header
|
| 1845 |
|
|
write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
|
| 1846 |
|
|
writeline( log, str );
|
| 1847 |
|
|
--
|
| 1848 |
|
|
-- Read "TEST_CHECK.WB_CFG_SLAVE"
|
| 1849 |
|
|
write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
|
| 1850 |
|
|
writeline( log, str );
|
| 1851 |
|
|
adr := x"20002000";
|
| 1852 |
|
|
|
| 1853 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
|
| 1854 |
|
|
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
|
| 1855 |
|
|
-- PCIE RD
|
| 1856 |
|
|
data_read64(cmd, ret, adr, data64);
|
| 1857 |
|
|
-- Put RD_Value to apropriate holder
|
| 1858 |
|
|
if (i=0) then -- const
|
| 1859 |
|
|
st_wb_cfg_slave_data_0.const(j) := data64;
|
| 1860 |
|
|
elsif (i=1) then -- cmd
|
| 1861 |
|
|
st_wb_cfg_slave_data_0.cmd(j) := data64;
|
| 1862 |
|
|
else -- sts
|
| 1863 |
|
|
st_wb_cfg_slave_data_0.sts(j) := data64;
|
| 1864 |
|
|
end if;
|
| 1865 |
|
|
-- Incr ADDR
|
| 1866 |
|
|
adr := adr + x"00000008";
|
| 1867 |
|
|
-- Print RD_Value
|
| 1868 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1869 |
|
|
writeline( log, str );
|
| 1870 |
|
|
|
| 1871 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
|
| 1872 |
|
|
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
|
| 1873 |
|
|
|
| 1874 |
|
|
--
|
| 1875 |
|
|
-- Write
|
| 1876 |
|
|
write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
|
| 1877 |
|
|
writeline( log, str );
|
| 1878 |
|
|
adr := x"20002000";
|
| 1879 |
|
|
|
| 1880 |
|
|
TEST_GEN_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
|
| 1881 |
|
|
TEST_GEN_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
|
| 1882 |
|
|
-- Prepare WR_Value
|
| 1883 |
|
|
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
|
| 1884 |
|
|
-- PCIE WR
|
| 1885 |
|
|
data_write64(cmd, ret, adr, data64);
|
| 1886 |
|
|
-- Put WR_Value to apropriate holder
|
| 1887 |
|
|
if (i=0) then -- const
|
| 1888 |
|
|
st_wb_cfg_slave_data_1.const(j) := data64;
|
| 1889 |
|
|
elsif (i=1) then -- cmd
|
| 1890 |
|
|
st_wb_cfg_slave_data_1.cmd(j) := data64;
|
| 1891 |
|
|
else -- sts
|
| 1892 |
|
|
st_wb_cfg_slave_data_1.sts(j) := data64;
|
| 1893 |
|
|
end if;
|
| 1894 |
|
|
-- Incr ADDR
|
| 1895 |
|
|
adr := adr + x"00000008";
|
| 1896 |
|
|
-- Print WR_Value
|
| 1897 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1898 |
|
|
writeline( log, str );
|
| 1899 |
|
|
|
| 1900 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
|
| 1901 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
|
| 1902 |
|
|
|
| 1903 |
|
|
--
|
| 1904 |
|
|
-- Read
|
| 1905 |
|
|
write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
|
| 1906 |
|
|
writeline( log, str );
|
| 1907 |
|
|
adr := x"20002000";
|
| 1908 |
|
|
|
| 1909 |
|
|
TEST_GEN_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
|
| 1910 |
|
|
TEST_GEN_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
|
| 1911 |
|
|
-- PCIE RD
|
| 1912 |
|
|
data_read64(cmd, ret, adr, data64);
|
| 1913 |
|
|
-- Put RD_Value to apropriate holder
|
| 1914 |
|
|
if (i=0) then -- const
|
| 1915 |
|
|
st_wb_cfg_slave_data_2.const(j) := data64;
|
| 1916 |
|
|
elsif (i=1) then -- cmd
|
| 1917 |
|
|
st_wb_cfg_slave_data_2.cmd(j) := data64;
|
| 1918 |
|
|
else -- sts
|
| 1919 |
|
|
st_wb_cfg_slave_data_2.sts(j) := data64;
|
| 1920 |
|
|
end if;
|
| 1921 |
|
|
-- Incr ADDR
|
| 1922 |
|
|
adr := adr + x"00000008";
|
| 1923 |
|
|
-- Print RD_Value
|
| 1924 |
|
|
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
|
| 1925 |
|
|
writeline( log, str );
|
| 1926 |
|
|
|
| 1927 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
|
| 1928 |
|
|
end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
|
| 1929 |
|
|
|
| 1930 |
|
|
--
|
| 1931 |
|
|
-- Compare results
|
| 1932 |
|
|
write( str, string'("4) Process Results:"));
|
| 1933 |
|
|
writeline( log, str );
|
| 1934 |
|
|
-- cmp#0 - constants
|
| 1935 |
|
|
CMP_CONST : for i in 0 to 7 loop
|
| 1936 |
|
|
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
|
| 1937 |
|
|
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1938 |
|
|
writeline( log, str );
|
| 1939 |
|
|
error := error + 1;
|
| 1940 |
|
|
end if;
|
| 1941 |
|
|
end loop CMP_CONST;
|
| 1942 |
|
|
-- cmp#1 - commands
|
| 1943 |
|
|
CMP_CMD : for i in 0 to 7 loop
|
| 1944 |
|
|
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
|
| 1945 |
|
|
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1946 |
|
|
writeline( log, str );
|
| 1947 |
|
|
error := error + 1;
|
| 1948 |
|
|
end if;
|
| 1949 |
|
|
end loop CMP_CMD;
|
| 1950 |
|
|
-- cmp#2 - status
|
| 1951 |
|
|
CMP_STATUS : for i in 0 to 7 loop
|
| 1952 |
|
|
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
|
| 1953 |
|
|
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
|
| 1954 |
|
|
writeline( log, str );
|
| 1955 |
|
|
error := error + 1;
|
| 1956 |
|
|
end if;
|
| 1957 |
|
|
end loop CMP_STATUS;
|
| 1958 |
|
|
-- print OK
|
| 1959 |
|
|
if (error = 0) then
|
| 1960 |
|
|
write( str, string'(" Results==OK"));
|
| 1961 |
|
|
writeline( log, str );
|
| 1962 |
|
|
cnt_ok := cnt_ok + 1;
|
| 1963 |
|
|
else
|
| 1964 |
|
|
cnt_error := cnt_error + 1;
|
| 1965 |
|
|
end if;
|
| 1966 |
|
|
|
| 1967 |
|
|
-- Final Header
|
| 1968 |
|
|
write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
|
| 1969 |
|
|
writeline( log, str ); -- upd LOGFILE
|
| 1970 |
|
|
--
|
| 1971 |
|
|
-- END
|
| 1972 |
|
|
end test_wb_2;
|
| 1973 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1974 |
|
|
end package body test_pkg;
|
