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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [ambpex5_sx50t_wishbone/] [src/] [testbench/] [test_pkg.vhd] - Blame information for rev 21

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Line No. Rev Author Line
1 16 dsmv 
---------------------------------------------------------------------------------------------------
2 
--
3 
-- Title       : test_pkg.vhd
4 
-- Author      : Dmitry Smekhov
5 
-- Company     : Instrumental System
6 
--
7 
-- Version     : 1.0
8 
--
9 
---------------------------------------------------------------------------------------------------
10 
--
11 
-- Description : Ïàêåò äëÿ òåñòèðîâàíèÿ ambpex5.
12 
--
13 
---------------------------------------------------------------------------------------------------
14 
--
15 
--  Version 1.1 (25.10.2011) Kuzmi4
16 
--      Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
17 
--
18 
---------------------------------------------------------------------------------------------------
19 
library ieee;
20 
use ieee.std_logic_1164.all;
21 
use ieee.std_logic_arith.all;
22 
use ieee.std_logic_unsigned.all;
23 
use ieee.std_logic_textio.all;
24 
use std.textio.all;
25 
 
26 
library work;
27 
use work.cmd_sim_pkg.all;
28 
use work.block_pkg.all;
29 
use work.wb_block_pkg.all;
30 
 
31 
package test_pkg is
32 
 
33 
--! Initialising
34 
procedure test_init(
35 18 dsmv 
                fname: in string        --! file name for report
36 16 dsmv 
        );
37 
 
38 
--! Finished
39 
procedure test_close;
40 
 
41 18 dsmv 
 
42 
--! Read registers
43 
procedure test_read_reg (
44 
                signal  cmd:    out bh_cmd; --! command
45 
                signal  ret:    in  bh_ret  --! answer
46 
                );
47 16 dsmv 
 
48 
--! Start DMA with incorrect descriptor
49 
procedure test_dsc_incorrect (
50 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
51 
                signal  ret:    in  bh_ret  --! answer
52 16 dsmv 
                );
53 
 
54 
--! Start DMA for one block 4 kB
55 
procedure test_read_4kb (
56 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
57 
                signal  ret:    in  bh_ret  --! answer
58 16 dsmv 
                );
59 
 
60 
 
61 
--! Read block_test_check 8 kB
62 
procedure test_adm_read_8kb (
63 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
64 
                signal  ret:    in  bh_ret  --! answer
65 16 dsmv 
                );
66 
 
67 
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
68 
--procedure test_block_main (
69 18 dsmv 
--              signal  cmd:    out bh_cmd; --! command
70 
--              signal  ret:    in  bh_ret  --! answer
71 16 dsmv 
--              );
72 
--
73 
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
74 
--procedure test_adm_read_16kb (
75 18 dsmv 
--              signal  cmd:    out bh_cmd; --! command
76 
--              signal  ret:    in  bh_ret  --! answer
77 16 dsmv 
--              );
78 
--
79 
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
80 
procedure test_adm_write_16kb (
81 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
82 
                signal  ret:    in  bh_ret  --! answer
83 16 dsmv 
                );
84 
---------------------------------------------------------------------------------------------------
85 
--
86 
--
87 
--
88 
procedure test_num_1(
89 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
90 
                            signal  ret:    in  bh_ret  --! answer
91 16 dsmv 
                    );
92 
procedure test_num_2(
93 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
94 
                            signal  ret:    in  bh_ret  --! answer
95 16 dsmv 
                    );
96 
-- ==> TEST_CHECK.WB_CFG_SLAVE
97 
procedure test_wb_1(
98 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
99 
                            signal  ret:    in  bh_ret  --! answer
100 16 dsmv 
                    );
101 
-- ==> TEST_GEN.WB_CFG_SLAVE
102 
procedure test_wb_2(
103 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
104 
                            signal  ret:    in  bh_ret  --! answer
105 16 dsmv 
                    );
106 
end package     test_pkg;
107 
---------------------------------------------------------------------------------------------------
108 
package body test_pkg is
109 
 
110 
        FILE   log: text;
111 
 
112 
        shared variable cnt_ok, cnt_error: integer;
113 
 
114 
        -- Initialising
115 
        procedure test_init(
116 
                fname: in string
117 
                ) is
118 
        begin
119 
 
120 
                file_open( log, fname, WRITE_MODE );
121 
                cnt_ok:=0;
122 
                cnt_error:=0;
123 
 
124 
        end test_init;
125 
 
126 
        --! Finished
127 
        procedure test_close is
128 
                variable str : LINE;            -- pointer to string
129 
        begin
130 
 
131 
                std.textio.write( str, string'(" " ));
132 
                writeline( log, str );
133 
                writeline( log, str );
134 
 
135 
                write( str, string'("check completed" ));
136 
                writeline( log, str );
137 
                write( str, string'("the number of successful tests:  " ));
138 
                write( str, cnt_ok );
139 
                writeline( log, str );
140 
                write( str, string'("the number of false test: " ));
141 
                write( str, cnt_error );
142 
                writeline( log, str );
143 
 
144 
 
145 
                file_close( log );
146 
 
147 
                if( cnt_ok>0 and cnt_error=0 ) then
148 
                        write( str, string'("TEST finished successfully") );
149 
                        writeline( output, str );
150 
                else
151 
                        write( str, string'("TEST finished with ERR") );
152 
                        writeline( output, str );
153 
 
154 
                end if;
155 
 
156 
        end test_close;
157 
 
158 
 
159 18 dsmv 
--! Read registers
160 
procedure test_read_reg (
161 
                signal  cmd:    out bh_cmd; --! command
162 
                signal  ret:    in  bh_ret  --! answer
163 
                )
164 
is
165 
 
166 
variable        adr             : std_logic_vector( 31 downto 0 );
167 
variable        data1   : std_logic_vector( 31 downto 0 );
168 
variable        data2   : std_logic_vector( 31 downto 0 );
169 
variable        str             : line;
170 
begin
171 
 
172 
        write( str, string'("TEST_READ_REG" ));
173 
        writeline( log, str );
174 16 dsmv 
 
175 21 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
176 18 dsmv 
        wait for 100 ns;
177 
 
178 
 
179 
        --block_read( cmd, ret, 4, 23, x"0000A400" );   -- LOCAL_ADR
180 
        wb_block_gen_read( cmd, ret,    REG_BLOCK_ID, data1 ); -- read block id
181 
        wb_block_check_read( cmd, ret,  REG_BLOCK_ID, data2 ); -- read block id
182 
 
183 
        write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
184 
        writeline( log, str );
185 
 
186 
        write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
187 
        writeline( log, str );
188 
 
189 
        wb_read( cmd, ret, 16#1000#, data1 );
190 
 
191 
        wb_read( cmd, ret, 16#3000#, data1 );
192 
 
193 
        write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
194 
        writeline( log, str );
195 
 
196 
        write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
197 
        writeline( log, str );
198 
 
199 
        block_write( cmd, ret, 0, 8, x"00000000" );              -- BRD_MODE
200 
        wait for 100 ns;
201 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE
202 
        wait for 100 ns;
203 
 
204 
        wb_block_gen_read( cmd, ret,    REG_BLOCK_ID, data1 ); -- read block id
205 
        wb_block_check_read( cmd, ret,  REG_BLOCK_ID, data2 ); -- read block id
206 
 
207 
        write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
208 
        writeline( log, str );
209 
 
210 
        write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
211 
        writeline( log, str );
212 
 
213 
end test_read_reg;
214 
 
215 
 
216 
 
217 
 
218 
 
219 16 dsmv 
--! Start DMA with incorrect descriptor
220 
procedure test_dsc_incorrect (
221 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
222 
                signal  ret:    in  bh_ret  --! answer
223 16 dsmv 
                )
224 
is
225 
 
226 
variable        adr             : std_logic_vector( 31 downto 0 );
227 
variable        data    : std_logic_vector( 31 downto 0 );
228 
variable        str             : line;
229 
begin
230 
 
231 
        write( str, string'("TEST_DSC_INCORRECT" ));
232 
        writeline( log, str );
233 
 
234 21 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
235 
        wait for 100 ns;
236 
 
237 16 dsmv 
        ---- Init block of descriptor ---
238 
        for ii in 0 to 127 loop
239 
                adr:= x"00100000";
240 
                adr:=adr + ii*4;
241 
                int_mem_write( cmd, ret, adr,  x"00000000" );
242 
        end loop;
243 
 
244 
        int_mem_write( cmd, ret, x"00100000",  x"03020100" );
245 
        int_mem_write( cmd, ret, x"001001FC",  x"FF00AA00" );
246 
 
247 
        ---- DMA program ----
248 
        block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
249 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
250 
 
251 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
252 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
253 
        block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR
254 
 
255 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
256 
 
257 
        wait for 20 us;
258 
 
259 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
260 
 
261 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
262 
        if( data( 15 downto 0 )=x"A021" ) then
263 
                write( str, string'(" - Ok" ));
264 
                cnt_ok := cnt_ok + 1;
265 
        else
266 
                write( str, string'(" - Error" ));
267 
                cnt_error := cnt_error + 1;
268 
        end if;
269 
 
270 
        writeline( log, str );
271 
 
272 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
273 
 
274 
end test_dsc_incorrect;
275 
 
276 
 
277 
--! Start DMA for one block 4 kB
278 
procedure test_read_4kb (
279 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
280 
                signal  ret:    in  bh_ret  --! answer
281 16 dsmv 
                )
282 
is
283 
 
284 
variable        adr                             : std_logic_vector( 31 downto 0 );
285 
variable        data                    : std_logic_vector( 31 downto 0 );
286 
variable        str                             : line;
287 
 
288 
variable        error                   : integer:=0;
289 
variable        dma_complete    : integer;
290 
 
291 
begin
292 
 
293 
        write( str, string'("TEST_READ_4KB" ));
294 
        writeline( log, str );
295 
 
296 21 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
297 
        wait for 100 ns;
298 
 
299 
 
300 16 dsmv 
        ---- Init block of descriptor ---
301 
        for ii in 0 to 127 loop
302 
                adr:= x"00100000";
303 
                adr:=adr + ii*4;
304 
                int_mem_write( cmd, ret, adr,  x"00000000" );
305 
        end loop;
306 
 
307 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
308 
        int_mem_write( cmd, ret, x"00100004",  x"00000100" );
309 
 
310 
 
311 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
312 
        int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );
313 
 
314 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
315 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
316 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
317 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
318 
        hwrite( str, data );
319 
        writeline( log, str );
320 
 
321 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
322 
 
323 
 
324 
        ---- DMA program ----
325 
        block_write( cmd, ret, 4, 8, x"00000025" );             -- DMA_MODE - without request
326 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
327 
 
328 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
329 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
330 
        block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
331 
 
332 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
333 
 
334 
        wait for 1 us;
335 
 
336 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
337 
 
338 
 
339 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
340 
 
341 
        wait for 20 us;
342 
 
343 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
344 
 
345 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
346 
        if( data( 8 )='1' ) then
347 
                write( str, string'(" - descriptor is correct" ));
348 
        else
349 
                write( str, string'(" - descriptor is incorrect" ));
350 
                error := error + 1;
351 
        end if;
352 
 
353 
        writeline( log, str );
354 
 
355 
        if( error=0 ) then
356 
 
357 
                ---- Wait for DMA finished ----
358 
                dma_complete := 0;
359 
                for ii in 0 to 100 loop
360 
 
361 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
362 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
363 
                        if( data(5)='1' ) then
364 
                                write( str, string'(" - DMA finished " ));
365 
                                dma_complete := 1;
366 
                        end if;
367 
                        writeline( log, str );
368 
 
369 
                        if( dma_complete=1 ) then
370 
                                exit;
371 
                        end if;
372 
 
373 
                        wait for 1 us;
374 
 
375 
                end loop;
376 
 
377 
                writeline( log, str );
378 
 
379 
                if( dma_complete=0 ) then
380 
                        write( str, string'("Error - DMA not finished" ));
381 
                        writeline( log, str );
382 
                        error:=error+1;
383 
                end if;
384 
 
385 
        end if;
386 
 
387 
        for ii in 0 to 3 loop
388 
 
389 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
390 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
391 
                writeline( log, str );
392 
                wait for 500 ns;
393 
 
394 
        end loop;
395 
 
396 
 
397 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
398 
 
399 
        write( str, string'(" Read: " ));
400 
        writeline( log, str );
401 
 
402 
        for ii in 0 to 15 loop
403 
 
404 
                adr:= x"00800000";
405 
                adr:=adr + ii*4;
406 
                int_mem_read( cmd, ret, adr,  data );
407 
 
408 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
409 
                writeline( log, str );
410 
 
411 
        end loop;
412 
 
413 
 
414 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
415 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
416 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
417 
 
418 
 
419 
        writeline( log, str );
420 
        if( error=0 ) then
421 
                write( str, string'("Test is correct" ));
422 
                cnt_ok := cnt_ok + 1;
423 
        else
424 
                write( str, string'("Test have ERRORS" ));
425 
                cnt_error := cnt_error + 1;
426 
        end if;
427 
        writeline( log, str );
428 
        writeline( log, str );
429 
 
430 
end test_read_4kb;
431 
 
432 
 
433 
--! Read block_test_check 8 kB
434 
procedure test_adm_read_8kb (
435 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
436 
                signal  ret:    in  bh_ret  --! answer
437 16 dsmv 
                )
438 
is
439 
 
440 
variable        adr                             : std_logic_vector( 31 downto 0 );
441 
variable        data                    : std_logic_vector( 31 downto 0 );
442 
variable        str                             : line;
443 
 
444 
variable        error                   : integer:=0;
445 
variable        dma_complete    : integer;
446 
 
447 
begin
448 
 
449 
        write( str, string'("TEST_ADM_READ_8KB" ));
450 
        writeline( log, str );
451 
 
452 21 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
453 
        wait for 100 ns;
454 
 
455 16 dsmv 
        ---- Init block of descriptor ---
456 
        for ii in 0 to 127 loop
457 
                adr:= x"00100000";
458 
                adr:=adr + ii*4;
459 
                int_mem_write( cmd, ret, adr,  x"00000000" );
460 
        end loop;
461 
 
462 
        --- Desctriptor 0 ---
463 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
464 
        int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- jump to next descriptor
465 
 
466 
        --- Desctriptor 1 ---
467 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
468 
        int_mem_write( cmd, ret, x"0010000C",  x"00000110" );   -- stop
469 
 
470 
 
471 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
472 
        int_mem_write( cmd, ret, x"001001FC",  x"D6644953" );
473 
 
474 
 
475 
        ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
476 
        block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
477 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
478 
 
479 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
480 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
481 
        block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
482 
 
483 
 
484 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
485 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
486 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
487 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
488 
        hwrite( str, data );
489 
        writeline( log, str );
490 
 
491 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
492 
 
493 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
494 
 
495 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
496 
 
497 
        wait for 20 us;
498 
 
499 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
500 
 
501 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
502 
        if( data( 8 )='1' ) then
503 
                write( str, string'(" - descriptor is correct" ));
504 
        else
505 
                write( str, string'(" - descriptor is incorrect" ));
506 
                error := error + 1;
507 
        end if;
508 
 
509 
        writeline( log, str );
510 
 
511 
        if( error=0 ) then
512 
 
513 
                ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
514 
                dma_complete := 0;
515 
                for ii in 0 to 100 loop
516 
 
517 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
518 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
519 
                        if( data(5)='1' ) then
520 
                                write( str, string'(" - DMA finished " ));
521 
                                dma_complete := 1;
522 
 
523 
                                block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - reset EOT
524 
 
525 
                        end if;
526 
                        writeline( log, str );
527 
 
528 
                        if( dma_complete=1 ) then
529 
                                exit;
530 
                        end if;
531 
 
532 
                        wait for 1 us;
533 
 
534 
                end loop;
535 
 
536 
                writeline( log, str );
537 
 
538 
                if( dma_complete=0 ) then
539 
                        write( str, string'("Error - DMA not finished " ));
540 
                        writeline( log, str );
541 
                        error:=error+1;
542 
                end if;
543 
 
544 
        end if;
545 
 
546 
        for ii in 0 to 3 loop
547 
 
548 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
549 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
550 
                writeline( log, str );
551 
                wait for 500 ns;
552 
 
553 
        end loop;
554 
 
555 
 
556 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
557 
 
558 
        write( str, string'(" Block 0 - read: " ));
559 
        writeline( log, str );
560 
 
561 
        for ii in 0 to 15 loop
562 
 
563 
                adr:= x"00800000";
564 
                adr:=adr + ii*4;
565 
                int_mem_read( cmd, ret, adr,  data );
566 
 
567 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
568 
                writeline( log, str );
569 
 
570 
        end loop;
571 
 
572 
        writeline( log, str );
573 
 
574 
        write( str, string'(" Block 1 - read: " ));
575 
        writeline( log, str );
576 
 
577 
        for ii in 0 to 15 loop
578 
 
579 
                adr:= x"00801000";
580 
                adr:=adr + ii*4;
581 
                int_mem_read( cmd, ret, adr,  data );
582 
 
583 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
584 
                writeline( log, str );
585 
 
586 
        end loop;
587 
 
588 
 
589 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
590 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
591 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
592 
 
593 
 
594 
        writeline( log, str );
595 
        if( error=0 ) then
596 
                write( str, string'(" Test is correct " ));
597 
                cnt_ok := cnt_ok + 1;
598 
        else
599 
                write( str, string'(" Test have ERRORS " ));
600 
                cnt_error := cnt_error + 1;
601 
        end if;
602 
        writeline( log, str );
603 
        writeline( log, str );
604 
 
605 
end test_adm_read_8kb;
606 
--
607 
--
608 
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
609 
--procedure test_block_main (
610 18 dsmv 
--              signal  cmd:    out bh_cmd; --! command
611 
--              signal  ret:    in  bh_ret  --! answer
612 16 dsmv 
--              )
613 
--is
614 
--
615 
--variable      adr                             : std_logic_vector( 31 downto 0 );
616 
--variable      data                    : std_logic_vector( 31 downto 0 );
617 
--variable      str                             : line;
618 
--
619 
--variable      error                   : integer:=0;
620 
--variable      dma_complete    : integer;
621 
--
622 
--begin
623 
--
624 
--      write( str, string'("TEST_BLOCK_MAIN" ));
625 
--      writeline( log, str );
626 
--
627 
--      block_read( cmd, ret, 4, 16#00#, data );
628 
--      write( str,  string'("ÁËÎÊ 4: " )); hwrite( str, data ); writeline( log, str );
629 
--
630 
--      wait for 10 us;
631 
--
632 
----    write( str, "Êîíñòàíòû:" );
633 
----    writeline( log, str );
634 
----    for ii in 0 to 5 loop
635 
----            write( str, "Áëîê " );
636 
----            write( str, ii );
637 
----            for jj in 0 to 7 loop
638 
----                    block_read( cmd, ret, ii, jj, data );
639 
----                    write( str, "   " );
640 
----                    hwrite( str, data );
641 
----            end loop;
642 
----            writeline( log, str );
643 
----    end loop;
644 
----
645 
----
646 
----    writeline( log, str );
647 
----
648 
----    block_read( cmd, ret, 0, 16#10#, data );
649 
----    write( str,  "STATUS: " ); hwrite( str, data ); writeline( log, str );
650 
----
651 
----    block_write( cmd, ret, 80, 16#08#, x"00000100" );
652 
----
653 
----    block_read( cmd, ret, 0, 16#10#, data );
654 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
655 
----
656 
----    block_write( cmd, ret, 80, 16#08#, x"00000200" );
657 
----
658 
----    block_read( cmd, ret, 0, 16#10#, data );
659 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
660 
----
661 
----
662 
----    writeline( log, str );
663 
----    if( error=0 ) then
664 
----            write( str, " Òåñò çàâåðø¸í óñïåøíî " );
665 
----            cnt_ok := cnt_ok + 1;
666 
----    else
667 
----            write( str, " Òåñò íå âûïîëíåí " );
668 
----            cnt_error := cnt_error + 1;
669 
----    end if;
670 
--
671 
--      for ii in 0 to 127 loop
672 
--
673 
--              block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
674 
--              block_read( cmd, ret, 4, 8, data );
675 
--              write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
676 
--              if( data/=x"0000AA55" ) then
677 
--                      error:=error+1;
678 
--              end if;
679 
--
680 
--      end loop;
681 
--
682 
--
683 
--
684 
--
685 
--      writeline( log, str );
686 
--      writeline( log, str );
687 
--
688 
--end test_block_main;
689 
--
690 
--
691 
--
692 
--
693 
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
694 
--procedure test_adm_read_16kb (
695 18 dsmv 
--              signal  cmd:    out bh_cmd; --! command
696 
--              signal  ret:    in  bh_ret  --! answer
697 16 dsmv 
--              )
698 
--is
699 
--
700 
--variable      adr                             : std_logic_vector( 31 downto 0 );
701 
--variable      data                    : std_logic_vector( 31 downto 0 );
702 
--variable      str                             : line;
703 
--
704 
--variable      error                   : integer:=0;
705 
--variable      dma_complete    : integer;
706 
--variable      kk                              : integer;
707 
--variable      status                  : std_logic_vector( 15 downto 0 );
708 
--
709 
--begin
710 
--
711 
--      write( str, string'("TEST_ADM_READ_16KB" ));
712 
--      writeline( log, str );
713 
--
714 
--      ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
715 
--      for ii in 0 to 256 loop
716 
--              adr:= x"00100000";
717 
--              adr:=adr + ii*4;
718 
--              int_mem_write( cmd, ret, adr,  x"00000000" );
719 
--      end loop;
720 
--
721 
--      --- Áëîê 0 ---
722 
--
723 
--      --- Äåñêðèïòîð 0 ---
724 
--      int_mem_write( cmd, ret, x"00100000",  x"00008000" );
725 
--      int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
726 
--
727 
--      --- Äåñêðèïòîð 1 ---
728 
--      int_mem_write( cmd, ret, x"00100008",  x"00008010" );
729 
--      int_mem_write( cmd, ret, x"0010000C",  x"00000112" );   -- ïåðåõîä ê ñëåäóþùåìó áëîêó
730 
--
731 
--      --- Äåñêðèïòîð 2 ---
732 
--      int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
733 
--      int_mem_write( cmd, ret, x"00100014",  x"00000000" );
734 
--
735 
--
736 
--      int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
737 
--      int_mem_write( cmd, ret, x"001001FC",  x"14644953" );
738 
--
739 
--
740 
--      --- Áëîê 1 ---
741 
--
742 
--      --- Äåñêðèïòîð 0 ---
743 
--      int_mem_write( cmd, ret, x"00100200",  x"00008020" );
744 
--      int_mem_write( cmd, ret, x"00100204",  x"00000111" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
745 
--
746 
--      --- Äåñêðèïòîð 1 ---
747 
--      int_mem_write( cmd, ret, x"00100208",  x"00008030" );
748 
--      int_mem_write( cmd, ret, x"0010020C",  x"00000110" );   -- îñòàíîâêà
749 
--
750 
--
751 
--      int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
752 
--      int_mem_write( cmd, ret, x"001003FC",  x"D67C4953" );
753 
--
754 
--
755 
--
756 
--      ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
757 
--      block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
758 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
759 
--
760 
--      block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
761 
--      block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
762 
--      block_write( cmd, ret, 4, 23, x"00019000" );    -- LOCAL_ADR
763 
--
764 
--
765 
--      ---- Ïîäãîòîâêà òåòðàäû ----
766 
--      trd_test_mode( cmd, ret, 0 );   -- ïåðåõîä â ðàáî÷èé ðåæèì --
767 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1600" );               -- DMAR0 - îò òåòðàäû 6 --
768 
--
769 
--      trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" );   -- Ðàçìåð áëîêà = 4 êÁ --
770 
--
771 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
772 
--
773 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
774 
--
775 
--      trd_wait_cmd( cmd, ret, 6,      0, x"2038" );           -- çàïóñê òåòðàäû DIO_IN
776 
--
777 
--      trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" );   -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
778 
--
779 
--      wait for 20 us;
780 
--
781 
--      block_read( cmd, ret, 4, 16, data );                    -- STATUS
782 
--
783 
--      write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
784 
--      if( data( 8 )='1' ) then
785 
--              write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
786 
--      else
787 
--              write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
788 
--              error := error + 1;
789 
--      end if;
790 
--
791 
--      writeline( log, str );
792 
--
793 
--      if( error=0 ) then
794 
--
795 
--              kk:=0;
796 
--              loop
797 
--
798 
--              trd_status( cmd, ret, 6, status );
799 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
800 
--
801 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
802 
--              write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
803 
--
804 
--                      if( data(4)='1' ) then
805 
--                              write( str, string'(" - çàâåðøåíî ÷òåíèå áëîêà " ));
806 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
807 
--                              kk:=kk+1;
808 
--                              if( kk=4 ) then
809 
--                                      exit;
810 
--                              end if;
811 
--                      end if;
812 
--                      writeline( log, str );
813 
--
814 
--                      wait for 500 ns;
815 
--
816 
--
817 
--              end loop;
818 
--
819 
--              ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
820 
--              dma_complete := 0;
821 
--              for ii in 0 to 100 loop
822 
--
823 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
824 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
825 
--                      if( data(5)='1' ) then
826 
--                              write( str, string'(" - DMA çàâåðø¸í " ));
827 
--                              dma_complete := 1;
828 
--
829 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
830 
--
831 
--                      end if;
832 
--                      writeline( log, str );
833 
--
834 
--                      if( dma_complete=1 ) then
835 
--                              exit;
836 
--                      end if;
837 
--
838 
--                      wait for 1 us;
839 
--
840 
--              end loop;
841 
--
842 
--              writeline( log, str );
843 
--
844 
--              if( dma_complete=0 ) then
845 
--                      write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
846 
--                      writeline( log, str );
847 
--                      error:=error+1;
848 
--              end if;
849 
--
850 
--      end if;
851 
--
852 
--      for ii in 0 to 3 loop
853 
--
854 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
855 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
856 
--              writeline( log, str );
857 
--              wait for 500 ns;
858 
--
859 
--      end loop;
860 
--
861 
--
862 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
863 
--
864 
--      write( str, string'(" Áëîê 0 - ïðî÷èòàíî: " ));
865 
--      writeline( log, str );
866 
--
867 
--      for ii in 0 to 15 loop
868 
--
869 
--              adr:= x"00800000";
870 
--              adr:=adr + ii*4;
871 
--              int_mem_read( cmd, ret, adr,  data );
872 
--
873 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
874 
--              writeline( log, str );
875 
--
876 
--      end loop;
877 
--
878 
--      writeline( log, str );
879 
--
880 
--      write( str, string'(" Áëîê 1 - ïðî÷èòàíî: " ));
881 
--      writeline( log, str );
882 
--
883 
--      for ii in 0 to 15 loop
884 
--
885 
--              adr:= x"00801000";
886 
--              adr:=adr + ii*4;
887 
--              int_mem_read( cmd, ret, adr,  data );
888 
--
889 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
890 
--              writeline( log, str );
891 
--
892 
--      end loop;
893 
--
894 
--      write( str, string'(" Áëîê 2 - ïðî÷èòàíî: " ));
895 
--      writeline( log, str );
896 
--
897 
--      for ii in 0 to 15 loop
898 
--
899 
--              adr:= x"00802000";
900 
--              adr:=adr + ii*4;
901 
--              int_mem_read( cmd, ret, adr,  data );
902 
--
903 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
904 
--              writeline( log, str );
905 
--
906 
--      end loop;
907 
--
908 
--
909 
--      write( str, string'(" Áëîê 3 - ïðî÷èòàíî: " ));
910 
--      writeline( log, str );
911 
--
912 
--      for ii in 0 to 15 loop
913 
--
914 
--              adr:= x"00803000";
915 
--              adr:=adr + ii*4;
916 
--              int_mem_read( cmd, ret, adr,  data );
917 
--
918 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
919 
--              writeline( log, str );
920 
--
921 
--      end loop;
922 
--
923 
----    block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
924 
----    block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
925 
----    block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
926 
--
927 
--
928 
--      writeline( log, str );
929 
--      if( error=0 ) then
930 
--              write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
931 
--              cnt_ok := cnt_ok + 1;
932 
--      else
933 
--              write( str, string'(" Òåñò íå âûïîëíåí " ));
934 
--              cnt_error := cnt_error + 1;
935 
--      end if;
936 
--      writeline( log, str );
937 
--      writeline( log, str );
938 
--
939 
--end test_adm_read_16kb;
940 
--
941 
--
942 
--
943 
--
944 
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
945 
procedure test_adm_write_16kb (
946 18 dsmv 
                signal  cmd:    out bh_cmd; --! command
947 
                signal  ret:    in  bh_ret  --! answer
948 16 dsmv 
                )
949 
is
950 
 
951 
variable        adr                             : std_logic_vector( 31 downto 0 );
952 
variable        data                    : std_logic_vector( 31 downto 0 );
953 
variable        str                             : line;
954 
 
955 
variable        error                   : integer:=0;
956 
variable        dma_complete    : integer;
957 
variable        kk                              : integer;
958 
variable        status                  : std_logic_vector( 15 downto 0 );
959 
 
960 
variable        data64                  : std_logic_vector( 63 downto 0 );
961 
variable        data64n                 : std_logic_vector( 63 downto 0 );
962 
 
963 
begin
964 
 
965 
        write( str, string'("TEST_ADM_WRITE_16KB" ));
966 
        writeline( log, str );
967 
 
968 21 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
969 
        wait for 100 ns;
970 
 
971 16 dsmv 
        ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
972 
        for ii in 0 to 256 loop
973 
                adr:= x"00100000";
974 
                adr:=adr + ii*4;
975 
                int_mem_write( cmd, ret, adr,  x"00000000" );
976 
        end loop;
977 
 
978 
 
979 
        data64 :=x"0000000000000000";
980 
        data64n := not data64;
981 
 
982 
        ---- Çàïîëíåíèå áëîêà 0 ----
983 
        adr:= x"00800000";
984 
    data:=x"A5A50123";
985 
        int_mem_write( cmd, ret, adr,  data );
986 
        adr:=adr + 4;
987 
 
988 
        data:=x"00000000";
989 
        int_mem_write( cmd, ret, adr,  data );
990 
        adr:=adr + 4;
991 
 
992 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
993 
        adr:=adr + 4;
994 
 
995 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
996 
        adr:=adr + 4;
997 
 
998 
        data64:=data64 + 1;
999 
        data64n := not data64;
1000 
 
1001 
        for ii in 0 to 254 loop
1002 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1003 
                adr:=adr + 4;
1004 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1005 
                adr:=adr + 4;
1006 
 
1007 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1008 
                adr:=adr + 4;
1009 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1010 
                adr:=adr + 4;
1011 
 
1012 
                data64:=data64 + 1;
1013 
                data64n := not data64;
1014 
 
1015 
        end loop;
1016 
 
1017 
        ---- Çàïîëíåíèå áëîêà 1 ----
1018 
        adr:= x"00801000";
1019 
    data:=x"A5A50123";
1020 
        int_mem_write( cmd, ret, adr,  data );
1021 
        adr:=adr + 4;
1022 
 
1023 
        data:=x"00000001";
1024 
        int_mem_write( cmd, ret, adr,  data );
1025 
        adr:=adr + 4;
1026 
 
1027 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1028 
        adr:=adr + 4;
1029 
 
1030 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1031 
        adr:=adr + 4;
1032 
 
1033 
        data64:=data64 + 1;
1034 
        data64n := not data64;
1035 
 
1036 
        for ii in 0 to 254 loop
1037 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1038 
                adr:=adr + 4;
1039 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1040 
                adr:=adr + 4;
1041 
 
1042 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1043 
                adr:=adr + 4;
1044 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1045 
                adr:=adr + 4;
1046 
 
1047 
                data64:=data64 + 1;
1048 
                data64n := not data64;
1049 
 
1050 
        end loop;
1051 
 
1052 
        ---- Çàïîëíåíèå áëîêà 2 ----
1053 
        adr:= x"00802000";
1054 
    data:=x"A5A50123";
1055 
        int_mem_write( cmd, ret, adr,  data );
1056 
        adr:=adr + 4;
1057 
 
1058 
        data:=x"00000002";
1059 
        int_mem_write( cmd, ret, adr,  data );
1060 
        adr:=adr + 4;
1061 
 
1062 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1063 
        adr:=adr + 4;
1064 
 
1065 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1066 
        adr:=adr + 4;
1067 
 
1068 
        data64:=data64 + 1;
1069 
        data64n := not data64;
1070 
 
1071 
        for ii in 0 to 254 loop
1072 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1073 
                adr:=adr + 4;
1074 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1075 
                adr:=adr + 4;
1076 
 
1077 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1078 
                adr:=adr + 4;
1079 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1080 
                adr:=adr + 4;
1081 
 
1082 
                data64:=data64 + 1;
1083 
                data64n := not data64;
1084 
 
1085 
        end loop;
1086 
 
1087 
        ---- Çàïîëíåíèå áëîêà 3 ----
1088 
        adr:= x"00803000";
1089 
    data:=x"A5A50123";
1090 
        int_mem_write( cmd, ret, adr,  data );
1091 
        adr:=adr + 4;
1092 
 
1093 
        data:=x"00000003";
1094 
        int_mem_write( cmd, ret, adr,  data );
1095 
        adr:=adr + 4;
1096 
 
1097 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1098 
        adr:=adr + 4;
1099 
 
1100 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1101 
        adr:=adr + 4;
1102 
 
1103 
        data64:=data64 + 1;
1104 
        data64n := not data64;
1105 
 
1106 
        for ii in 0 to 254 loop
1107 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1108 
                adr:=adr + 4;
1109 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1110 
                adr:=adr + 4;
1111 
 
1112 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1113 
                adr:=adr + 4;
1114 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1115 
                adr:=adr + 4;
1116 
 
1117 
                data64:=data64 + 1;
1118 
                data64n := not data64;
1119 
 
1120 
        end loop;
1121 
--      for ii in 0 to 256 loop
1122 
--              adr:= x"00802000";
1123 
--              adr:=adr + ii*4;
1124 
--              data:=x"00A20000";
1125 
--              data:=data + ii;
1126 
--              int_mem_write( cmd, ret, adr,  data );
1127 
--      end loop;
1128 
--
1129 
--      for ii in 0 to 256 loop
1130 
--              adr:= x"00803000";
1131 
--              adr:=adr + ii*4;
1132 
--              data:=x"00A30000";
1133 
--              data:=data + ii;
1134 
--              int_mem_write( cmd, ret, adr,  data );
1135 
--      end loop;
1136 
 
1137 
        --- Áëîê 0 ---
1138 
 
1139 
        --- Äåñêðèïòîð 0 ---
1140 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
1141 
        int_mem_write( cmd, ret, x"00100004",  x"00000011" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
1142 
 
1143 
        --- Äåñêðèïòîð 1 ---
1144 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
1145 
        int_mem_write( cmd, ret, x"0010000C",  x"00000012" );   -- ïåðåõîä ê ñëåäóþùåìó áëîêó
1146 
 
1147 
        --- Äåñêðèïòîð 2 ---
1148 
        int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
1149 
        int_mem_write( cmd, ret, x"00100014",  x"00000000" );
1150 
 
1151 
 
1152 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
1153 
        int_mem_write( cmd, ret, x"001001FC",  x"14A44953" );
1154 
 
1155 
 
1156 
        --- Áëîê 1 ---
1157 
 
1158 
        --- Äåñêðèïòîð 0 ---
1159 
        int_mem_write( cmd, ret, x"00100200",  x"00008020" );
1160 
        int_mem_write( cmd, ret, x"00100204",  x"00000011" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
1161 
 
1162 
        --- Äåñêðèïòîð 1 ---
1163 
        int_mem_write( cmd, ret, x"00100208",  x"00008030" );
1164 
        int_mem_write( cmd, ret, x"0010020C",  x"00000010" );   -- îñòàíîâêà
1165 
 
1166 
 
1167 
        int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
1168 
        int_mem_write( cmd, ret, x"001003FC",  x"D6BC4953" );
1169 
 
1170 
 
1171 
 
1172 
        ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
1173 
        block_write( cmd, ret, 5, 8, x"00000023" );             -- DMA_MODE  - ñ çàïðîñàìè
1174 
        --block_write( cmd, ret, 5, 8, x"00000021" );           -- DMA_MODE - áåç çàïðîñîâ
1175 
        block_write( cmd, ret, 5, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1176 
 
1177 
        block_write( cmd, ret, 5, 20, x"00100000" );    -- PCI_ADRL
1178 
        block_write( cmd, ret, 5, 21, x"00100000" );    -- PCI_ADRH
1179 
        block_write( cmd, ret, 5, 23, x"00001000" );    -- LOCAL_ADR
1180 
 
1181 
 
1182 
        ---- Ïîäãîòîâêà òåòðàäû ----
1183 
--      trd_test_mode( cmd, ret, 0 );   -- ïåðåõîä â ðàáî÷èé ðåæèì --
1184 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1700" );               -- DMAR0 - îò òåòðàäû 7 --
1185 
--
1186 
--      trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" );   -- Ðàçìåð áëîêà = 4 êÁ --
1187 
 
1188 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000001" ); -- ñáðîñ
1189 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
1190 
        wb_block_check_read( cmd, ret, REG_BLOCK_ID, data ); -- ÷òåíèå èäåíòèôèêàòîðà áëîêà
1191 
        write( str, string'("BLOCK TEST_CHECK  ID: " ));
1192 
        hwrite( str, data );
1193 
        writeline( log, str );
1194 
 
1195 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_SIZE, x"00000001" ); -- ðàçìåð áëîêà - 1 êèëîáàéò
1196 
 
1197 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"000006A0" ); -- çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè
1198 
        --
1199 
        --
1200 
        --
1201 
        data:=wb_block_check_burst_ctrl_build('1', 40, 473);
1202 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
1203 
        --
1204 
        --
1205 
        --
1206 
        block_write( cmd, ret, 5, 9, x"00000001" );             -- DMA_CTRL - START
1207 
 
1208 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
1209 
--
1210 
--      trd_wait_cmd( cmd, ret, 7,      0, x"2038" );           -- çàïóñê òåòðàäû DIO_OUT
1211 
--
1212 
--      trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" );   -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
1213 
 
1214 
        wait for 20 us;
1215 
 
1216 
 
1217 
        for ii in 0 to 20 loop
1218 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1219 
 
1220 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1221 
                if( data( 8 )='1' ) then
1222 
                        write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
1223 
                        error := 0;
1224 
                        exit;
1225 
                else
1226 
                        write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
1227 
                        error := error + 1;
1228 
                        wait for 10 us;
1229 
                end if;
1230 
 
1231 
                writeline( log, str );
1232 
        end loop;
1233 
 
1234 
 
1235 
        if( error=0 ) then
1236 
 
1237 
                kk:=0;
1238 
                loop
1239 
 
1240 
--              trd_status( cmd, ret, 6, status );
1241 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
1242 
 
1243 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1244 
                write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1245 
 
1246 
                        if( data(4)='1' ) then
1247 
                                write( str, string'(" - çàâåðøåíà ïåðåäà÷à áëîêà " ));
1248 
                                block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1249 
                                kk:=kk+1;
1250 
                                if( kk=4 ) then
1251 
                                        exit;
1252 
                                end if;
1253 
                        end if;
1254 
                        writeline( log, str );
1255 
 
1256 
                        wait for 500 ns;
1257 
 
1258 
 
1259 
                end loop;
1260 
 
1261 
                ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
1262 
                dma_complete := 0;
1263 
                for ii in 0 to 100 loop
1264 
 
1265 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1266 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1267 
 
1268 
                        if( data(4)='1' ) then
1269 
                                write( str, string'(" - çàâåðø¸íà ïåðåäà÷à áëîêà " ));
1270 
 
1271 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1272 
 
1273 
                        end if;
1274 
                        writeline( log, str );
1275 
 
1276 
 
1277 
                        if( data(5)='1' ) then
1278 
                                write( str, string'(" - DMA çàâåðø¸í " ));
1279 
                                dma_complete := 1;
1280 
 
1281 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1282 
 
1283 
                        end if;
1284 
                        writeline( log, str );
1285 
 
1286 
                        if( dma_complete=1 ) then
1287 
                                exit;
1288 
                        end if;
1289 
 
1290 
                        wait for 1 us;
1291 
 
1292 
                end loop;
1293 
 
1294 
                writeline( log, str );
1295 
 
1296 
                if( dma_complete=0 ) then
1297 
                        write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
1298 
                        writeline( log, str );
1299 
                        error:=error+1;
1300 
                end if;
1301 
 
1302 
        end if;
1303 
 
1304 
        for ii in 0 to 3 loop
1305 
 
1306 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1307 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1308 
                writeline( log, str );
1309 
                wait for 500 ns;
1310 
 
1311 
        end loop;
1312 
 
1313 
        wait for 10 us;
1314 
 
1315 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
1316 
        write( str, string'( "Ïðèíÿòî áëîêîâ: " ) );
1317 
        hwrite( str, data );
1318 
        kk := conv_integer( data );
1319 
        if( 4/=kk ) then
1320 
                write( str, string'( " - Îøèáêà" ) );
1321 
                error := error + 1;
1322 
        else
1323 
                write( str, string'( " - Ok" ) );
1324 
        end if;
1325 
        writeline( log, str );
1326 
 
1327 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
1328 
        write( str, string'( "TEST_CHECK_BL_OK: " ) );
1329 
        hwrite( str, data );
1330 
        kk := conv_integer( data );
1331 
        if( 3/=kk ) then
1332 
                write( str, string'( " - Îøèáêà" ) );
1333 
                error := error + 1;
1334 
        else
1335 
                write( str, string'( " - Ok" ) );
1336 
        end if;
1337 
        writeline( log, str );
1338 
 
1339 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
1340 
        write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
1341 
        hwrite( str, data );
1342 
        kk := conv_integer( data );
1343 
        if( 0/=kk ) then
1344 
                write( str, string'( " - Îøèáêà" ) );
1345 
                error := error + 1;
1346 
        else
1347 
                write( str, string'( " - Ok" ) );
1348 
        end if;
1349 
        writeline( log, str );
1350 
 
1351 
 
1352 
 
1353 
        block_write( cmd, ret, 5, 9, x"00000000" );             -- DMA_CTRL - STOP
1354 
 
1355 
 
1356 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1357 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
1358 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
1359 
 
1360 
 
1361 
        writeline( log, str );
1362 
        if( error=0 ) then
1363 
                write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
1364 
                cnt_ok := cnt_ok + 1;
1365 
        else
1366 
                write( str, string'(" Òåñò íå âûïîëíåí " ));
1367 
                cnt_error := cnt_error + 1;
1368 
        end if;
1369 
        writeline( log, str );
1370 
        writeline( log, str );
1371 
 
1372 
end test_adm_write_16kb;
1373 
---------------------------------------------------------------------------------------------------
1374 
--
1375 
-- My procedure for test Updated Design (test_read_4kb like refenernce)
1376 
--
1377 
procedure test_num_1 (
1378 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1379 
                            signal  ret:    in  bh_ret  --! answer
1380 16 dsmv 
                        ) is
1381 
 
1382 
    variable    adr             : std_logic_vector( 31 downto 0 );
1383 
    variable    data            : std_logic_vector( 31 downto 0 );
1384 
    variable    str             : line;
1385 
 
1386 
    variable    error           : integer:=0;
1387 
    variable    dma_complete    : integer:=0;
1388 
 
1389 
begin
1390 
    -- Init Header
1391 
    write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
1392 
    writeline( log, str );
1393 
    --
1394 
    ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
1395 
    for ii in 0 to 127 loop
1396 
        adr:= x"00100000";
1397 
        adr:=adr + ii*4;
1398 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1399 
    end loop;
1400 
    -- HOST MEM Writes:
1401 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1402 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1403 
 
1404 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1405 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1406 
    --
1407 
    ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ---- PE_EXT_FIFO module: have bug in PE_EXT_FIFO, for check WB we will make a trick:
1408 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1409 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1410 
 
1411 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1412 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1413 
    block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
1414 
 
1415 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1416 
    --
1417 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
1418 
    wait for 1 us;
1419 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1420 
    --
1421 
    -- Delay for design
1422 
    wait for 20 us;
1423 
    --
1424 
    -- Read STATUS
1425 
    block_read( cmd, ret, 4, 16, data );
1426 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1427 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1428 
    if( data( 8 )='1' ) then
1429 
        write( str, string'(" - Descriptor==OK" ));
1430 
    else
1431 
        write( str, string'(" - Descriptor RD ERR" ));
1432 
        error := error + 1;
1433 
    end if;
1434 
    writeline( log, str );  -- upd LOGFILE
1435 
    --
1436 
    -- Deal with STATUS Results:
1437 
    if( error=0 ) then  -- w8ing for DMA final
1438 
        dma_complete := 0;
1439 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1440 
            -- Read STATUS
1441 
            block_read( cmd, ret, 4, 16, data );
1442 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1443 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1444 
            if( data(5)='1' ) then
1445 
                write( str, string'(" - DMA finished" ));
1446 
                dma_complete := 1;
1447 
            end if;
1448 
            writeline( log, str );
1449 
            -- Check "dma_complete"
1450 
            if( dma_complete=1 ) then
1451 
                exit;           -- EXIT Loop on FINAL
1452 
            else
1453 
                wait for 1 us;  -- DELAY in other case
1454 
            end if;
1455 
        end loop;
1456 
        writeline( log, str );  -- upd LOGFILE
1457 
 
1458 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1459 
            write( str, string'("ERR - DMA not finished " ));
1460 
            writeline( log, str );
1461 
            error:=error+1;
1462 
        end if;
1463 
 
1464 
    end if;
1465 
    --
1466 
    -- Print STATUS now
1467 
    for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1468 
        -- Read STATUS
1469 
        block_read( cmd, ret, 4, 16, data );
1470 
        -- Construct LOG MSG in accordance to STATUS value
1471 
        write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1472 
        -- upd LOGFILE
1473 
        writeline( log, str );
1474 
        wait for 500 ns;
1475 
    end loop;
1476 
    --
1477 
    -- Now STOP Design
1478 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1479 
    --
1480 
    -- Now print RX values:
1481 
    --
1482 
    -- Construct Header:
1483 
    writeline( log, str );
1484 
    write( str, string'("PRINT 1st 15 RX values: " ));
1485 
    writeline( log, str );
1486 
    -- Get first 15 DATA values and print it:
1487 
    for ii in 0 to 15 loop
1488 
        adr:= x"00800000";                      -- init ADDR value
1489 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1490 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1491 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1492 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1493 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1494 
        writeline( log, str );  -- upd LOGFILE
1495 
    end loop;
1496 
    writeline( log, str );      -- upd LOGFILE
1497 
    --
1498 
    -- Final CHECK errors:
1499 
    if( error=0 ) then
1500 
        write( str, string'("SUCCSESSFULL FINAL " ));
1501 
        cnt_ok := cnt_ok + 1;
1502 
    else
1503 
        write( str, string'("FAILED FINAL " ));
1504 
        cnt_error := cnt_error + 1;
1505 
    end if;
1506 
    writeline( log, str );  -- upd LOGFILE
1507 
    writeline( log, str );  -- upd LOGFILE
1508 
    --
1509 
    -- END
1510 
end test_num_1;
1511 
--
1512 
--
1513 
--
1514 
procedure test_num_2 (
1515 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1516 
                            signal  ret:    in  bh_ret  --! answer
1517 16 dsmv 
                        ) is
1518 
 
1519 
    variable    adr             : std_logic_vector( 31 downto 0 );
1520 
    variable    data            : std_logic_vector( 31 downto 0 );
1521 
    variable    data64          : std_logic_vector( 63 downto 0 );
1522 
    variable    str             : line;
1523 
 
1524 
    variable    error           : integer:=0;
1525 
    variable    dma_complete    : integer:=0;
1526 
 
1527 
begin
1528 
    -- Init Header
1529 
    write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
1530 
    writeline( log, str );
1531 
    --
1532 
    ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
1533 
    for ii in 0 to 127 loop
1534 
        adr:= x"00100000";
1535 
        adr:=adr + ii*4;
1536 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1537 
    end loop;
1538 
    -- HOST MEM Writes:
1539 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1540 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1541 
 
1542 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1543 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1544 
    --
1545 
    -- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
1546 
    adr     :=x"20002048";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
1547 
    data64  :=x"0000000000000001";      --  TEST_GEN_SIZE=x01
1548 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1549 
 
1550 
    adr     :=x"20002040";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
1551 
    data64  :=x"0000000000000022";      --  TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
1552 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1553 
 
1554 
    -- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
1555 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1556 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1557 
 
1558 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1559 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1560 
    block_write( cmd, ret, 4, 23, x"00003000" );    -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
1561 
 
1562 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1563 
    --
1564 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
1565 
    wait for 1 us;
1566 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1567 
    --
1568 
    -- Delay for design
1569 
    wait for 20 us;
1570 
    --
1571 
    -- Read STATUS (check RD DESCR status):
1572 
    block_read( cmd, ret, 4, 16, data );
1573 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1574 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1575 
    if( data( 8 )='1' ) then
1576 
        write( str, string'(" - Descriptor==OK" ));
1577 
    else
1578 
        write( str, string'(" - Descriptor RD ERR" ));
1579 
        error := error + 1;
1580 
    end if;
1581 
    writeline( log, str );  -- upd LOGFILE
1582 
    --
1583 
    -- W8ing for DMA finish:
1584 
    if( error=0 ) then  -- w8ing for DMA final
1585 
        dma_complete := 0;
1586 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1587 
            -- Read STATUS
1588 
            block_read( cmd, ret, 4, 16, data );
1589 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1590 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1591 
            if( data(5)='1' ) then
1592 
                write( str, string'(" - DMA finished" ));
1593 
                dma_complete := 1;
1594 
            end if;
1595 
            writeline( log, str );
1596 
            -- Check "dma_complete"
1597 
            if( dma_complete=1 ) then
1598 
                exit;           -- EXIT Loop on FINAL
1599 
            else
1600 
                wait for 1 us;  -- DELAY in other case
1601 
            end if;
1602 
        end loop;
1603 
        writeline( log, str );  -- upd LOGFILE
1604 
 
1605 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1606 
            write( str, string'("ERR - DMA not finished " ));
1607 
            writeline( log, str );
1608 
            error:=error+1;
1609 
        end if;
1610 
 
1611 
    end if;
1612 
    --
1613 
    -- Print STATUS in ERR
1614 
    if (error /= 0 ) then
1615 
        for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1616 
            -- Read STATUS
1617 
            block_read( cmd, ret, 4, 16, data );
1618 
            -- Construct LOG MSG in accordance to STATUS value
1619 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1620 
            -- upd LOGFILE
1621 
            writeline( log, str );
1622 
            wait for 500 ns;
1623 
        end loop;
1624 
    end if;
1625 
    --
1626 
    -- Now STOP Design
1627 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1628 
    --
1629 
    -- Now print RX values:
1630 
    --
1631 
    -- Construct Header:
1632 
    writeline( log, str );
1633 
    write( str, string'("PRINT 1st 15 RX values: " ));
1634 
    writeline( log, str );
1635 
    -- Get first 15 DATA values and print it:
1636 
    for ii in 0 to 15 loop
1637 
        adr:= x"00800000";                      -- init ADDR value
1638 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1639 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1640 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1641 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1642 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1643 
        writeline( log, str );  -- upd LOGFILE
1644 
    end loop;
1645 
    writeline( log, str );      -- upd LOGFILE
1646 
    --
1647 
    -- Final CHECK errors:
1648 
    if( error=0 ) then
1649 
        write( str, string'(" stb SUCCSESSFULL FINAL " ));
1650 
        cnt_ok := cnt_ok + 1;
1651 
    else
1652 
        write( str, string'(" stb FAILED FINAL " ));
1653 
        cnt_error := cnt_error + 1;
1654 
    end if;
1655 
    writeline( log, str );  -- upd LOGFILE
1656 
    writeline( log, str );  -- upd LOGFILE
1657 
    --
1658 
    -- END
1659 
end test_num_2;
1660 
---------------------------------------------------------------------------------------------------
1661 
--
1662 
-- My procedure for test WB stuff in Design:
1663 
--  ==> TEST_CHECK.WB_CFG_SLAVE
1664 
--
1665 
procedure test_wb_1 (
1666 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1667 
                            signal  ret:    in  bh_ret  --! answer
1668 16 dsmv 
                    ) is
1669 
 
1670 
    variable    adr             : std_logic_vector( 31 downto 0 );
1671 
    variable    data32          : std_logic_vector( 31 downto 0 );
1672 
    variable    data64          : std_logic_vector( 63 downto 0 );
1673 
    variable    str             : line;
1674 
 
1675 
    variable    error           : integer:=0;
1676 
    variable    dma_complete    : integer:=0;
1677 
 
1678 
    --
1679 
    --
1680 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1681 
    type wb_cfg_slave_data is record
1682 
        const   :   wb_cfg_slave_value(7 downto 0);
1683 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1684 
        sts     :   wb_cfg_slave_value(7 downto 0);
1685 
    end record;
1686 
    --
1687 
    --
1688 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1689 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1690 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1691 
 
1692 
 
1693 
begin
1694 
    -- Init Header
1695 
    write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
1696 
    writeline( log, str );
1697 
    --
1698 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1699 
    write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1700 
    writeline( log, str );
1701 
    adr     := x"20000000";
1702 
 
1703 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1704 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1705 
            -- PCIE RD
1706 
            data_read64(cmd, ret, adr, data64);
1707 
            -- Put RD_Value to apropriate holder
1708 
            if (i=0) then       -- const
1709 
                st_wb_cfg_slave_data_0.const(j) := data64;
1710 
            elsif (i=1) then    -- cmd
1711 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1712 
            else                -- sts
1713 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1714 
            end if;
1715 
            -- Incr ADDR
1716 
            adr := adr + x"00000008";
1717 
            -- Print RD_Value
1718 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1719 
            writeline( log, str );
1720 
 
1721 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1722 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1723 
 
1724 
    --
1725 
    -- Write
1726 
    write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
1727 
    writeline( log, str );
1728 
    adr     := x"20000000";
1729 
 
1730 
    TEST_CHECK_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1731 
        TEST_CHECK_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1732 
            -- Prepare WR_Value
1733 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1734 
            -- PCIE WR
1735 
            data_write64(cmd, ret, adr, data64);
1736 
            -- Put WR_Value to apropriate holder
1737 
            if (i=0) then       -- const
1738 
                st_wb_cfg_slave_data_1.const(j) := data64;
1739 
            elsif (i=1) then    -- cmd
1740 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1741 
            else                -- sts
1742 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1743 
            end if;
1744 
            -- Incr ADDR
1745 
            adr := adr + x"00000008";
1746 
            -- Print WR_Value
1747 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1748 
            writeline( log, str );
1749 
 
1750 
        end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
1751 
    end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
1752 
 
1753 
    --
1754 
    -- Read
1755 
    write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1756 
    writeline( log, str );
1757 
    adr     := x"20000000";
1758 
 
1759 
    TEST_CHECK_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1760 
        TEST_CHECK_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1761 
            -- PCIE RD
1762 
            data_read64(cmd, ret, adr, data64);
1763 
            -- Put RD_Value to apropriate holder
1764 
            if (i=0) then       -- const
1765 
                st_wb_cfg_slave_data_2.const(j) := data64;
1766 
            elsif (i=1) then    -- cmd
1767 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1768 
            else                -- sts
1769 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1770 
            end if;
1771 
            -- Incr ADDR
1772 
            adr := adr + x"00000008";
1773 
            -- Print RD_Value
1774 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1775 
            writeline( log, str );
1776 
 
1777 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
1778 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
1779 
 
1780 
    --
1781 
    -- Compare results
1782 
    write( str, string'("4) Process Results:"));
1783 
    writeline( log, str );
1784 
    --  cmp#0 - constants
1785 
    CMP_CONST   :   for i in 0 to 7 loop
1786 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1787 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1788 
            writeline( log, str );
1789 
            error := error + 1;
1790 
        end if;
1791 
    end loop CMP_CONST;
1792 
    --  cmp#1 - commands
1793 
    CMP_CMD     :   for i in 0 to 7 loop
1794 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1795 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1796 
            writeline( log, str );
1797 
            error := error + 1;
1798 
        end if;
1799 
    end loop CMP_CMD;
1800 
    --  cmp#2 - status
1801 
    CMP_STATUS  :   for i in 0 to 7 loop
1802 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
1803 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1804 
            writeline( log, str );
1805 
            error := error + 1;
1806 
        end if;
1807 
    end loop CMP_STATUS;
1808 
    --  print OK
1809 
    if (error = 0) then
1810 
        write( str, string'("   Results==OK"));
1811 
        writeline( log, str );
1812 
        cnt_ok := cnt_ok + 1;
1813 
    else
1814 
        cnt_error := cnt_error + 1;
1815 
    end if;
1816 
 
1817 
    -- Final Header
1818 
    write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
1819 
    writeline( log, str );  -- upd LOGFILE
1820 
    --
1821 
    -- END
1822 
end test_wb_1;
1823 
---------------------------------------------------------------------------------------------------
1824 
--
1825 
-- My procedure for test WB stuff in Design:
1826 
--  ==> TEST_GEN.WB_CFG_SLAVE
1827 
--
1828 
procedure test_wb_2 (
1829 18 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1830 
                            signal  ret:    in  bh_ret  --! answer
1831 16 dsmv 
                    ) is
1832 
 
1833 
    variable    adr             : std_logic_vector( 31 downto 0 );
1834 
    variable    data32          : std_logic_vector( 31 downto 0 );
1835 
    variable    data64          : std_logic_vector( 63 downto 0 );
1836 
    variable    str             : line;
1837 
 
1838 
    variable    error           : integer:=0;
1839 
    variable    dma_complete    : integer:=0;
1840 
 
1841 
    --
1842 
    --
1843 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1844 
    type wb_cfg_slave_data is record
1845 
        const   :   wb_cfg_slave_value(7 downto 0);
1846 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1847 
        sts     :   wb_cfg_slave_value(7 downto 0);
1848 
    end record;
1849 
    --
1850 
    --
1851 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1852 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1853 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1854 
 
1855 
 
1856 
begin
1857 
    -- Init Header
1858 
    write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
1859 
    writeline( log, str );
1860 
    --
1861 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1862 
    write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1863 
    writeline( log, str );
1864 
    adr     := x"20002000";
1865 
 
1866 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1867 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1868 
            -- PCIE RD
1869 
            data_read64(cmd, ret, adr, data64);
1870 
            -- Put RD_Value to apropriate holder
1871 
            if (i=0) then       -- const
1872 
                st_wb_cfg_slave_data_0.const(j) := data64;
1873 
            elsif (i=1) then    -- cmd
1874 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1875 
            else                -- sts
1876 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1877 
            end if;
1878 
            -- Incr ADDR
1879 
            adr := adr + x"00000008";
1880 
            -- Print RD_Value
1881 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1882 
            writeline( log, str );
1883 
 
1884 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1885 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1886 
 
1887 
    --
1888 
    -- Write
1889 
    write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
1890 
    writeline( log, str );
1891 
    adr     := x"20002000";
1892 
 
1893 
    TEST_GEN_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1894 
        TEST_GEN_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1895 
            -- Prepare WR_Value
1896 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1897 
            -- PCIE WR
1898 
            data_write64(cmd, ret, adr, data64);
1899 
            -- Put WR_Value to apropriate holder
1900 
            if (i=0) then       -- const
1901 
                st_wb_cfg_slave_data_1.const(j) := data64;
1902 
            elsif (i=1) then    -- cmd
1903 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1904 
            else                -- sts
1905 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1906 
            end if;
1907 
            -- Incr ADDR
1908 
            adr := adr + x"00000008";
1909 
            -- Print WR_Value
1910 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1911 
            writeline( log, str );
1912 
 
1913 
        end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
1914 
    end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
1915 
 
1916 
    --
1917 
    -- Read
1918 
    write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1919 
    writeline( log, str );
1920 
    adr     := x"20002000";
1921 
 
1922 
    TEST_GEN_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1923 
        TEST_GEN_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1924 
            -- PCIE RD
1925 
            data_read64(cmd, ret, adr, data64);
1926 
            -- Put RD_Value to apropriate holder
1927 
            if (i=0) then       -- const
1928 
                st_wb_cfg_slave_data_2.const(j) := data64;
1929 
            elsif (i=1) then    -- cmd
1930 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1931 
            else                -- sts
1932 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1933 
            end if;
1934 
            -- Incr ADDR
1935 
            adr := adr + x"00000008";
1936 
            -- Print RD_Value
1937 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1938 
            writeline( log, str );
1939 
 
1940 
        end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
1941 
    end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
1942 
 
1943 
    --
1944 
    -- Compare results
1945 
    write( str, string'("4) Process Results:"));
1946 
    writeline( log, str );
1947 
    --  cmp#0 - constants
1948 
    CMP_CONST   :   for i in 0 to 7 loop
1949 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1950 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1951 
            writeline( log, str );
1952 
            error := error + 1;
1953 
        end if;
1954 
    end loop CMP_CONST;
1955 
    --  cmp#1 - commands
1956 
    CMP_CMD     :   for i in 0 to 7 loop
1957 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1958 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1959 
            writeline( log, str );
1960 
            error := error + 1;
1961 
        end if;
1962 
    end loop CMP_CMD;
1963 
    --  cmp#2 - status
1964 
    CMP_STATUS  :   for i in 0 to 7 loop
1965 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
1966 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1967 
            writeline( log, str );
1968 
            error := error + 1;
1969 
        end if;
1970 
    end loop CMP_STATUS;
1971 
    --  print OK
1972 
    if (error = 0) then
1973 
        write( str, string'("   Results==OK"));
1974 
        writeline( log, str );
1975 
        cnt_ok := cnt_ok + 1;
1976 
    else
1977 
        cnt_error := cnt_error + 1;
1978 
    end if;
1979 
 
1980 
    -- Final Header
1981 
    write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
1982 
    writeline( log, str );  -- upd LOGFILE
1983 
    --
1984 
    -- END
1985 
end test_wb_2;
1986 
---------------------------------------------------------------------------------------------------
1987 
end package     body test_pkg;

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