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-------------------------------------------------------------------------------
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--
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-- Title : pcie_core64_m1
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Top-level module for PCIE_CORE64 WB SoPC
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-- (System have 32Bit ADDR BUS and 64bit DATA BUS)
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--
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-- Memory Map for SoPC (based on WB_CROSS setup):
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-- 1) TEST_CHECK.WB_CFG_SLAVE:
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-- ADDR Range ==> 0x0000_0000 : 0x0000_0FFF ( Valid 1st 256B only, detailed MM at test_check_wb_config_slave.vhd)
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--
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-- 2) TEST_CHECK.WB_BURST_SLAVE
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-- ADDR Range ==> 0x0000_1000 : 0x0000_1FFF (support only Constant-Addr-Burst for 512x64bit cell (full 4KB range), Input ONLY)
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--
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-- 3) TEST_GEN.WB_CFG_SLAVE
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-- ADDR Range ==> 0x0000_2000 : 0x0000_2FFF ( Valid 1st 256B only, detailed MM at test_generate_wb_config_slave.vhd)
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--
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-- 4) TEST_GEN.WB_BURST_SLAVE
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-- ADDR Range ==> 0x0000_3000 : 0x0000_3FFF (support only Constant-Addr-Burst for 512x64bit cell (full 4KB range), Output ONLY)
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.0 20.04.2013
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-- Created from sp605_lx45t_wishbone_sopc_wb
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package ambpex5_sx50t_wishbone_sopc_wb_pkg is
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component ambpex5_sx50t_wishbone_sopc_wb is
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generic
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(
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is_simulation : integer --! 0 - synthesis, 1 - simulation
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);
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port
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(
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---- PCI-Express ----
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txp : out std_logic_vector( 7 downto 0 );
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txn : out std_logic_vector( 7 downto 0 );
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rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
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rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
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mgt250 : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
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perst : in std_logic:='0'; -- 0 - reset
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tp : out std_logic_vector(3 downto 1); -- testpoint
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---- Led ----
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led : out std_logic_vector( 4 downto 1 )
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);
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end component ambpex5_sx50t_wishbone_sopc_wb;
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end package ambpex5_sx50t_wishbone_sopc_wb_pkg;
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.wb_conmax_top_pkg.all;
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use work.pcie_core64_wishbone_m8_pkg.all;
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use work.block_test_check_wb_pkg.all;
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use work.block_test_generate_wb_pkg.all;
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entity ambpex5_sx50t_wishbone_sopc_wb is
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generic
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(
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is_simulation : integer --! 0 - synthesis, 1 - simulation
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);
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port
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(
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---- PCI-Express ----
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txp : out std_logic_vector( 7 downto 0 );
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txn : out std_logic_vector( 7 downto 0 );
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rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
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rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
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mgt250 : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
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perst : in std_logic:='0'; -- 0 - reset
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tp : out std_logic_vector(3 downto 1); -- testpoint
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---- Led ----
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led : out std_logic_vector( 4 downto 1 )
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);
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end ambpex5_sx50t_wishbone_sopc_wb;
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architecture rtl of ambpex5_sx50t_wishbone_sopc_wb is
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----------------------------------------------------------------------------------
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--
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-- Declare PCIE_CORE64_WB stuff:
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signal sv_control_points : std_logic_vector( 7 downto 0 );
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signal sv_pcie_lstatus : std_logic_vector( 15 downto 0 );
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signal s_pcie_link_up_n : std_logic;
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-------------------------------------------------------------------------------
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--
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-- Declare WB_CROSS stuff:
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signal st_master_port_data_in : wb_master_port_data;
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signal st_master_port_data_out : wb_master_port_data;
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signal st_master_port_addr : wb_master_port_addr;
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signal st_master_port_sel : wb_master_port_sel;
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signal st_master_port_we : wb_master_port_we;
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signal st_master_port_cyc : wb_master_port_cyc;
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signal st_master_port_stb : wb_master_port_stb;
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signal st_master_port_ack : wb_master_port_ack;
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signal st_master_port_err : wb_master_port_err;
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signal st_master_port_rty : wb_master_port_rty;
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signal st_master_port_cti : wb_master_port_cti;
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signal st_master_port_bte : wb_master_port_bte;
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signal st_slave_port_data_in : wb_slave_port_data;
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signal st_slave_port_data_out : wb_slave_port_data;
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signal st_slave_port_addr : wb_slave_port_addr;
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signal st_slave_port_sel : wb_slave_port_sel;
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signal st_slave_port_we : wb_slave_port_we;
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signal st_slave_port_cyc : wb_slave_port_cyc;
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signal st_slave_port_stb : wb_slave_port_stb;
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signal st_slave_port_ack : wb_slave_port_ack;
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signal st_slave_port_err : wb_slave_port_err;
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signal st_slave_port_rty : wb_slave_port_rty;
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signal st_slave_port_cti : wb_slave_port_cti;
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signal st_slave_port_bte : wb_slave_port_bte;
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-------------------------------------------------------------------------------
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--
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-- Declare Module Output Req stuff:
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signal sv_pcie_line_num : std_logic_vector(2 downto 0);
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-------------------------------------------------------------------------------
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--
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-- Declare WB stuff
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-- SYS_CON
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signal s_wb_clk : std_logic;
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signal s_wb_rst : std_logic;
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-- PCIE_CORE64 wb
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signal sv_wbm_addr_pcie_core64_wb : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
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signal sv_wbm_data_out_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal sv_wbm_sel_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
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signal s_wbm_we_pcie_core64_wb : std_logic;
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signal s_wbm_cyc_pcie_core64_wb : std_logic;
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signal s_wbm_stb_pcie_core64_wb : std_logic;
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signal sv_wbm_cti_pcie_core64_wb : std_logic_vector(2 downto 0);
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signal sv_wbm_bte_pcie_core64_wb : std_logic_vector(1 downto 0);
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signal sv_wbm_data_in_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal s_wbm_ack_pcie_core64_wb : std_logic;
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signal s_wbm_err_pcie_core64_wb : std_logic;
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signal s_wbm_rty_pcie_core64_wb : std_logic;
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signal sv_wbm_dmar_irq_pcie_core64_wb : std_logic_vector(1 downto 0);
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-- TEST_CHECK.WB_CFG_SLAVE
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signal sv_wbs_cfg_addr_test_check : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
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signal sv_wbs_cfg_data_in_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal sv_wbs_cfg_sel_test_check : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
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signal s_wbs_cfg_we_test_check : std_logic;
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signal s_wbs_cfg_cyc_test_check : std_logic;
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signal s_wbs_cfg_stb_test_check : std_logic;
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signal sv_wbs_cfg_cti_test_check : std_logic_vector(2 downto 0);
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signal sv_wbs_cfg_bte_test_check : std_logic_vector(1 downto 0);
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signal sv_wbs_cfg_data_out_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal s_wbs_cfg_ack_test_check : std_logic;
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signal s_wbs_cfg_err_test_check : std_logic;
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signal s_wbs_cfg_rty_test_check : std_logic;
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signal s_wbs_irq_dmar_test_check : std_logic; -- TEST_CHECK WB DMAR IRQ
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-- TEST_CHECK.WB_BURST_SLAVE
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signal sv_wbs_burst_addr_test_check : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
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signal sv_wbs_burst_data_in_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal sv_wbs_burst_sel_test_check : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
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signal s_wbs_burst_we_test_check : std_logic;
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signal s_wbs_burst_cyc_test_check : std_logic;
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signal s_wbs_burst_stb_test_check : std_logic;
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signal sv_wbs_burst_cti_test_check : std_logic_vector(2 downto 0);
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signal sv_wbs_burst_bte_test_check : std_logic_vector(1 downto 0);
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signal s_wbs_burst_ack_test_check : std_logic;
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signal s_wbs_burst_err_test_check : std_logic;
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signal s_wbs_burst_rty_test_check : std_logic;
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-- TEST_GEN.WB_CFG_SLAVE
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signal sv_wbs_cfg_addr_test_gen : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
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signal sv_wbs_cfg_data_in_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal sv_wbs_cfg_sel_test_gen : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
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signal s_wbs_cfg_we_test_gen : std_logic;
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signal s_wbs_cfg_cyc_test_gen : std_logic;
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signal s_wbs_cfg_stb_test_gen : std_logic;
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signal sv_wbs_cfg_cti_test_gen : std_logic_vector(2 downto 0);
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signal sv_wbs_cfg_bte_test_gen : std_logic_vector(1 downto 0);
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signal sv_wbs_cfg_data_out_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal s_wbs_cfg_ack_test_gen : std_logic;
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signal s_wbs_cfg_err_test_gen : std_logic;
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signal s_wbs_cfg_rty_test_gen : std_logic;
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signal s_wbs_irq_dmar_test_gen : std_logic; -- TEST_GEN WB DMAR IRQ
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-- TEST_GEN.WB_BURST_SLAVE
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signal sv_wbs_burst_addr_test_gen : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
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signal sv_wbs_burst_data_out_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
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signal sv_wbs_burst_sel_test_gen : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
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signal s_wbs_burst_we_test_gen : std_logic;
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signal s_wbs_burst_cyc_test_gen : std_logic;
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signal s_wbs_burst_stb_test_gen : std_logic;
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signal sv_wbs_burst_cti_test_gen : std_logic_vector(2 downto 0);
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signal sv_wbs_burst_bte_test_gen : std_logic_vector(1 downto 0);
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signal s_wbs_burst_ack_test_gen : std_logic;
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signal s_wbs_burst_err_test_gen : std_logic;
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signal s_wbs_burst_rty_test_gen : std_logic;
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----------------------------------------------------------------------------------
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begin
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-------------------------------------------------------------------------------
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--
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-- Instantiate PCIE_CORE64_WB module (provide main PCIE finctionality):
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--
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PCIE_CORE64_WB : pcie_core64_wishbone_m8
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generic map
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(
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Device_ID => x"0000", -- èäåíòèôèêàòîð ìîäóëÿ
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Revision => x"0000", -- âåðñèÿ ìîäóëÿ
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dsmv |
PLD_VER => x"0001", -- âåðñèÿ ÏËÈÑ
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dsmv |
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is_simulation => is_simulation --! 0 - ñèíòåç, 1 - ìîäåëèðîâàíèå
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)
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port map
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(
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---- PCI-Express ----
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txp => txp,
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txn => txn,
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rxp => rxp,
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rxn => rxn,
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mgt250 => mgt250, -- òàêòîâàÿ ÷àñòîòà 125 MHz îò PCI_Express
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perst => perst, -- 0 - ñáðîñ
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--px => px, --! êîíòðîëüíûå òî÷êè
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pcie_lstatus => sv_pcie_lstatus, -- ðåãèñòð LSTATUS
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pcie_link_up => s_pcie_link_up_n, -- 0 - çàâåðøåíà èíèöèàëèçàöèÿ PCI-Express
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---- Wishbone SYS_CON -----
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o_wb_clk => s_wb_clk,
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o_wb_rst => s_wb_rst,
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---- Wishbone BUS -----
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ov_wbm_addr => sv_wbm_addr_pcie_core64_wb,
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ov_wbm_data => sv_wbm_data_out_pcie_core64_wb,
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ov_wbm_sel => sv_wbm_sel_pcie_core64_wb,
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o_wbm_we => s_wbm_we_pcie_core64_wb,
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o_wbm_cyc => s_wbm_cyc_pcie_core64_wb,
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o_wbm_stb => s_wbm_stb_pcie_core64_wb,
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ov_wbm_cti => sv_wbm_cti_pcie_core64_wb, -- Cycle Type Identifier Address Tag
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ov_wbm_bte => sv_wbm_bte_pcie_core64_wb, -- Burst Type Extension Address Tag
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iv_wbm_data => sv_wbm_data_in_pcie_core64_wb,
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i_wbm_ack => s_wbm_ack_pcie_core64_wb,
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i_wbm_err => s_wbm_err_pcie_core64_wb, -- error input - abnormal cycle termination
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i_wbm_rty => s_wbm_rty_pcie_core64_wb, -- retry input - interface is not ready
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i_wdm_irq_0 => '0', -- NC for now
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iv_wbm_irq_dmar => sv_wbm_dmar_irq_pcie_core64_wb --
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);
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-- Construct DMAR WB IR Input:
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dsmv |
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_gen & s_wbs_irq_dmar_test_check; -- Bit#1 - TEST_GEN, Bit#0 - TEST_CHECK
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dsmv |
-------------------------------------------------------------------------------
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--
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|
|
-- Instantiate TEST_CHECK (provide check of input data):
|
281 |
|
|
--
|
282 |
|
|
TEST_CHECK : block_test_check_wb
|
283 |
|
|
port map
|
284 |
|
|
(
|
285 |
|
|
--
|
286 |
|
|
-- SYS_CON
|
287 |
|
|
i_clk => s_wb_clk,
|
288 |
|
|
i_rst => s_wb_rst,
|
289 |
|
|
--
|
290 |
|
|
-- WB CFG SLAVE IF
|
291 |
|
|
iv_wbs_cfg_addr => sv_wbs_cfg_addr_test_check( 7 downto 0), -- Route only req addr wires: 256B ADDR Range
|
292 |
|
|
iv_wbs_cfg_data => sv_wbs_cfg_data_in_test_check,
|
293 |
|
|
iv_wbs_cfg_sel => sv_wbs_cfg_sel_test_check,
|
294 |
|
|
i_wbs_cfg_we => s_wbs_cfg_we_test_check,
|
295 |
|
|
i_wbs_cfg_cyc => s_wbs_cfg_cyc_test_check,
|
296 |
|
|
i_wbs_cfg_stb => s_wbs_cfg_stb_test_check,
|
297 |
|
|
iv_wbs_cfg_cti => sv_wbs_cfg_cti_test_check,
|
298 |
|
|
iv_wbs_cfg_bte => sv_wbs_cfg_bte_test_check,
|
299 |
|
|
|
300 |
|
|
ov_wbs_cfg_data => sv_wbs_cfg_data_out_test_check,
|
301 |
|
|
o_wbs_cfg_ack => s_wbs_cfg_ack_test_check,
|
302 |
|
|
o_wbs_cfg_err => s_wbs_cfg_err_test_check,
|
303 |
|
|
o_wbs_cfg_rty => s_wbs_cfg_rty_test_check,
|
304 |
|
|
--
|
305 |
|
|
-- WB BURST SLAVE IF (WRITE-ONLY IF)
|
306 |
|
|
iv_wbs_burst_addr => sv_wbs_burst_addr_test_check( 11 downto 0), -- Route only req addr wires: 4KB ADDR Range
|
307 |
|
|
iv_wbs_burst_data => sv_wbs_burst_data_in_test_check,
|
308 |
|
|
iv_wbs_burst_sel => sv_wbs_burst_sel_test_check,
|
309 |
|
|
i_wbs_burst_we => s_wbs_burst_we_test_check,
|
310 |
|
|
i_wbs_burst_cyc => s_wbs_burst_cyc_test_check,
|
311 |
|
|
i_wbs_burst_stb => s_wbs_burst_stb_test_check,
|
312 |
|
|
iv_wbs_burst_cti => sv_wbs_burst_cti_test_check,
|
313 |
|
|
iv_wbs_burst_bte => sv_wbs_burst_bte_test_check,
|
314 |
|
|
|
315 |
|
|
o_wbs_burst_ack => s_wbs_burst_ack_test_check,
|
316 |
|
|
o_wbs_burst_err => s_wbs_burst_err_test_check,
|
317 |
|
|
o_wbs_burst_rty => s_wbs_burst_rty_test_check,
|
318 |
|
|
--
|
319 |
|
|
-- WB IRQ lines
|
320 |
|
|
o_wbs_irq_0 => OPEN, -- NC for now
|
321 |
|
|
o_wbs_irq_dmar => s_wbs_irq_dmar_test_check --
|
322 |
|
|
);
|
323 |
|
|
-------------------------------------------------------------------------------
|
324 |
|
|
--
|
325 |
|
|
-- Instantiate TEST_GEN (provide generation of test data):
|
326 |
|
|
--
|
327 |
|
|
TEST_GEN : block_test_generate_wb
|
328 |
|
|
port map
|
329 |
|
|
(
|
330 |
|
|
--
|
331 |
|
|
-- SYS_CON
|
332 |
|
|
i_clk => s_wb_clk,
|
333 |
|
|
i_rst => s_wb_rst,
|
334 |
|
|
--
|
335 |
|
|
-- WB CFG SLAVE IF
|
336 |
|
|
iv_wbs_cfg_addr => sv_wbs_cfg_addr_test_gen( 7 downto 0), -- Route only req addr wires: 256B ADDR Range
|
337 |
|
|
iv_wbs_cfg_data => sv_wbs_cfg_data_in_test_gen,
|
338 |
|
|
iv_wbs_cfg_sel => sv_wbs_cfg_sel_test_gen,
|
339 |
|
|
i_wbs_cfg_we => s_wbs_cfg_we_test_gen,
|
340 |
|
|
i_wbs_cfg_cyc => s_wbs_cfg_cyc_test_gen,
|
341 |
|
|
i_wbs_cfg_stb => s_wbs_cfg_stb_test_gen,
|
342 |
|
|
iv_wbs_cfg_cti => sv_wbs_cfg_cti_test_gen,
|
343 |
|
|
iv_wbs_cfg_bte => sv_wbs_cfg_bte_test_gen,
|
344 |
|
|
|
345 |
|
|
ov_wbs_cfg_data => sv_wbs_cfg_data_out_test_gen,
|
346 |
|
|
o_wbs_cfg_ack => s_wbs_cfg_ack_test_gen,
|
347 |
|
|
o_wbs_cfg_err => s_wbs_cfg_err_test_gen,
|
348 |
|
|
o_wbs_cfg_rty => s_wbs_cfg_rty_test_gen,
|
349 |
|
|
--
|
350 |
|
|
-- WB BURST SLAVE IF (READ-ONLY IF)
|
351 |
|
|
iv_wbs_burst_addr => sv_wbs_burst_addr_test_gen( 11 downto 0), -- Route only req addr wires: 4KB ADDR Range
|
352 |
|
|
iv_wbs_burst_sel => sv_wbs_burst_sel_test_gen,
|
353 |
|
|
i_wbs_burst_we => s_wbs_burst_we_test_gen,
|
354 |
|
|
i_wbs_burst_cyc => s_wbs_burst_cyc_test_gen,
|
355 |
|
|
i_wbs_burst_stb => s_wbs_burst_stb_test_gen,
|
356 |
|
|
iv_wbs_burst_cti => sv_wbs_burst_cti_test_gen,
|
357 |
|
|
iv_wbs_burst_bte => sv_wbs_burst_bte_test_gen,
|
358 |
|
|
|
359 |
|
|
ov_wbs_burst_data => sv_wbs_burst_data_out_test_gen,
|
360 |
|
|
o_wbs_burst_ack => s_wbs_burst_ack_test_gen,
|
361 |
|
|
o_wbs_burst_err => s_wbs_burst_err_test_gen,
|
362 |
|
|
o_wbs_burst_rty => s_wbs_burst_rty_test_gen,
|
363 |
|
|
--
|
364 |
|
|
-- WB IRQ lines
|
365 |
|
|
o_wbs_irq_0 => OPEN, -- NC for now
|
366 |
|
|
o_wbs_irq_dmar => s_wbs_irq_dmar_test_gen --
|
367 |
|
|
);
|
368 |
|
|
-------------------------------------------------------------------------------
|
369 |
|
|
--
|
370 |
|
|
-- Instantiate WB_CROSS
|
371 |
|
|
-- ==> MOST HEAVY PART of DESIGN (from port-quantity point of view)
|
372 |
|
|
--
|
373 |
|
|
WB_CROSS : wb_conmax_top
|
374 |
|
|
generic map
|
375 |
|
|
(
|
376 |
|
|
dw => p_WB_CROSS_DATA_W, -- WB_DATA_WIDTH==64bit (defined at wb_conmax_top_pkg.vhd)
|
377 |
|
|
aw => p_WB_CROSS_ADDR_W -- WB_ADDR_WIDTH==32bit (defined at wb_conmax_top_pkg.vhd)
|
378 |
|
|
)
|
379 |
|
|
port map
|
380 |
|
|
(
|
381 |
|
|
--
|
382 |
|
|
-- SYS_CON
|
383 |
|
|
clk_i => s_wb_clk,
|
384 |
|
|
rst_i => s_wb_rst,
|
385 |
|
|
--
|
386 |
|
|
-- Master 0 Interface
|
387 |
|
|
m0_data_i => st_master_port_data_in(0),
|
388 |
|
|
m0_data_o => st_master_port_data_out(0),
|
389 |
|
|
m0_addr_i => st_master_port_addr(0),
|
390 |
|
|
m0_sel_i => st_master_port_sel(0),
|
391 |
|
|
m0_we_i => st_master_port_we(0),
|
392 |
|
|
m0_cyc_i => st_master_port_cyc(0),
|
393 |
|
|
m0_stb_i => st_master_port_stb(0),
|
394 |
|
|
m0_ack_o => st_master_port_ack(0),
|
395 |
|
|
m0_err_o => st_master_port_err(0),
|
396 |
|
|
m0_rty_o => st_master_port_rty(0),
|
397 |
|
|
m0_cti_i => st_master_port_cti(0),
|
398 |
|
|
m0_bte_i => st_master_port_bte(0),
|
399 |
|
|
--
|
400 |
|
|
-- Master 1 Interface
|
401 |
|
|
m1_data_i => st_master_port_data_in(1),
|
402 |
|
|
m1_data_o => st_master_port_data_out(1),
|
403 |
|
|
m1_addr_i => st_master_port_addr(1),
|
404 |
|
|
m1_sel_i => st_master_port_sel(1),
|
405 |
|
|
m1_we_i => st_master_port_we(1),
|
406 |
|
|
m1_cyc_i => st_master_port_cyc(1),
|
407 |
|
|
m1_stb_i => st_master_port_stb(1),
|
408 |
|
|
m1_ack_o => st_master_port_ack(1),
|
409 |
|
|
m1_err_o => st_master_port_err(1),
|
410 |
|
|
m1_rty_o => st_master_port_rty(1),
|
411 |
|
|
m1_cti_i => st_master_port_cti(1),
|
412 |
|
|
m1_bte_i => st_master_port_bte(1),
|
413 |
|
|
--
|
414 |
|
|
-- Master 2 Interface
|
415 |
|
|
m2_data_i => st_master_port_data_in(2),
|
416 |
|
|
m2_data_o => st_master_port_data_out(2),
|
417 |
|
|
m2_addr_i => st_master_port_addr(2),
|
418 |
|
|
m2_sel_i => st_master_port_sel(2),
|
419 |
|
|
m2_we_i => st_master_port_we(2),
|
420 |
|
|
m2_cyc_i => st_master_port_cyc(2),
|
421 |
|
|
m2_stb_i => st_master_port_stb(2),
|
422 |
|
|
m2_ack_o => st_master_port_ack(2),
|
423 |
|
|
m2_err_o => st_master_port_err(2),
|
424 |
|
|
m2_rty_o => st_master_port_rty(2),
|
425 |
|
|
m2_cti_i => st_master_port_cti(2),
|
426 |
|
|
m2_bte_i => st_master_port_bte(2),
|
427 |
|
|
--
|
428 |
|
|
-- Master 3 Interface
|
429 |
|
|
m3_data_i => st_master_port_data_in(3),
|
430 |
|
|
m3_data_o => st_master_port_data_out(3),
|
431 |
|
|
m3_addr_i => st_master_port_addr(3),
|
432 |
|
|
m3_sel_i => st_master_port_sel(3),
|
433 |
|
|
m3_we_i => st_master_port_we(3),
|
434 |
|
|
m3_cyc_i => st_master_port_cyc(3),
|
435 |
|
|
m3_stb_i => st_master_port_stb(3),
|
436 |
|
|
m3_ack_o => st_master_port_ack(3),
|
437 |
|
|
m3_err_o => st_master_port_err(3),
|
438 |
|
|
m3_rty_o => st_master_port_rty(3),
|
439 |
|
|
m3_cti_i => st_master_port_cti(3),
|
440 |
|
|
m3_bte_i => st_master_port_bte(3),
|
441 |
|
|
--
|
442 |
|
|
-- Master 4 Interface
|
443 |
|
|
m4_data_i => st_master_port_data_in(4),
|
444 |
|
|
m4_data_o => st_master_port_data_out(4),
|
445 |
|
|
m4_addr_i => st_master_port_addr(4),
|
446 |
|
|
m4_sel_i => st_master_port_sel(4),
|
447 |
|
|
m4_we_i => st_master_port_we(4),
|
448 |
|
|
m4_cyc_i => st_master_port_cyc(4),
|
449 |
|
|
m4_stb_i => st_master_port_stb(4),
|
450 |
|
|
m4_ack_o => st_master_port_ack(4),
|
451 |
|
|
m4_err_o => st_master_port_err(4),
|
452 |
|
|
m4_rty_o => st_master_port_rty(4),
|
453 |
|
|
m4_cti_i => st_master_port_cti(4),
|
454 |
|
|
m4_bte_i => st_master_port_bte(4),
|
455 |
|
|
--
|
456 |
|
|
-- Master 5 Interface
|
457 |
|
|
m5_data_i => st_master_port_data_in(5),
|
458 |
|
|
m5_data_o => st_master_port_data_out(5),
|
459 |
|
|
m5_addr_i => st_master_port_addr(5),
|
460 |
|
|
m5_sel_i => st_master_port_sel(5),
|
461 |
|
|
m5_we_i => st_master_port_we(5),
|
462 |
|
|
m5_cyc_i => st_master_port_cyc(5),
|
463 |
|
|
m5_stb_i => st_master_port_stb(5),
|
464 |
|
|
m5_ack_o => st_master_port_ack(5),
|
465 |
|
|
m5_err_o => st_master_port_err(5),
|
466 |
|
|
m5_rty_o => st_master_port_rty(5),
|
467 |
|
|
m5_cti_i => st_master_port_cti(5),
|
468 |
|
|
m5_bte_i => st_master_port_bte(5),
|
469 |
|
|
--
|
470 |
|
|
-- Master 6 Interface
|
471 |
|
|
m6_data_i => st_master_port_data_in(6),
|
472 |
|
|
m6_data_o => st_master_port_data_out(6),
|
473 |
|
|
m6_addr_i => st_master_port_addr(6),
|
474 |
|
|
m6_sel_i => st_master_port_sel(6),
|
475 |
|
|
m6_we_i => st_master_port_we(6),
|
476 |
|
|
m6_cyc_i => st_master_port_cyc(6),
|
477 |
|
|
m6_stb_i => st_master_port_stb(6),
|
478 |
|
|
m6_ack_o => st_master_port_ack(6),
|
479 |
|
|
m6_err_o => st_master_port_err(6),
|
480 |
|
|
m6_rty_o => st_master_port_rty(6),
|
481 |
|
|
m6_cti_i => st_master_port_cti(6),
|
482 |
|
|
m6_bte_i => st_master_port_bte(6),
|
483 |
|
|
--
|
484 |
|
|
-- Master 7 Interface
|
485 |
|
|
m7_data_i => st_master_port_data_in(7),
|
486 |
|
|
m7_data_o => st_master_port_data_out(7),
|
487 |
|
|
m7_addr_i => st_master_port_addr(7),
|
488 |
|
|
m7_sel_i => st_master_port_sel(7),
|
489 |
|
|
m7_we_i => st_master_port_we(7),
|
490 |
|
|
m7_cyc_i => st_master_port_cyc(7),
|
491 |
|
|
m7_stb_i => st_master_port_stb(7),
|
492 |
|
|
m7_ack_o => st_master_port_ack(7),
|
493 |
|
|
m7_err_o => st_master_port_err(7),
|
494 |
|
|
m7_rty_o => st_master_port_rty(7),
|
495 |
|
|
m7_cti_i => st_master_port_cti(7),
|
496 |
|
|
m7_bte_i => st_master_port_bte(7),
|
497 |
|
|
--
|
498 |
|
|
--
|
499 |
|
|
-- Slave 0 Interface
|
500 |
|
|
s0_data_i => st_slave_port_data_in(0),
|
501 |
|
|
s0_data_o => st_slave_port_data_out(0),
|
502 |
|
|
s0_addr_o => st_slave_port_addr(0),
|
503 |
|
|
s0_sel_o => st_slave_port_sel(0),
|
504 |
|
|
s0_we_o => st_slave_port_we(0),
|
505 |
|
|
s0_cyc_o => st_slave_port_cyc(0),
|
506 |
|
|
s0_stb_o => st_slave_port_stb(0),
|
507 |
|
|
s0_ack_i => st_slave_port_ack(0),
|
508 |
|
|
s0_err_i => st_slave_port_err(0),
|
509 |
|
|
s0_rty_i => st_slave_port_rty(0),
|
510 |
|
|
s0_cti_o => st_slave_port_cti(0),
|
511 |
|
|
s0_bte_o => st_slave_port_bte(0),
|
512 |
|
|
--
|
513 |
|
|
-- Slave 1 Interface
|
514 |
|
|
s1_data_i => st_slave_port_data_in(1),
|
515 |
|
|
s1_data_o => st_slave_port_data_out(1),
|
516 |
|
|
s1_addr_o => st_slave_port_addr(1),
|
517 |
|
|
s1_sel_o => st_slave_port_sel(1),
|
518 |
|
|
s1_we_o => st_slave_port_we(1),
|
519 |
|
|
s1_cyc_o => st_slave_port_cyc(1),
|
520 |
|
|
s1_stb_o => st_slave_port_stb(1),
|
521 |
|
|
s1_ack_i => st_slave_port_ack(1),
|
522 |
|
|
s1_err_i => st_slave_port_err(1),
|
523 |
|
|
s1_rty_i => st_slave_port_rty(1),
|
524 |
|
|
s1_cti_o => st_slave_port_cti(1),
|
525 |
|
|
s1_bte_o => st_slave_port_bte(1),
|
526 |
|
|
--
|
527 |
|
|
-- Slave 2 Interface
|
528 |
|
|
s2_data_i => st_slave_port_data_in(2),
|
529 |
|
|
s2_data_o => st_slave_port_data_out(2),
|
530 |
|
|
s2_addr_o => st_slave_port_addr(2),
|
531 |
|
|
s2_sel_o => st_slave_port_sel(2),
|
532 |
|
|
s2_we_o => st_slave_port_we(2),
|
533 |
|
|
s2_cyc_o => st_slave_port_cyc(2),
|
534 |
|
|
s2_stb_o => st_slave_port_stb(2),
|
535 |
|
|
s2_ack_i => st_slave_port_ack(2),
|
536 |
|
|
s2_err_i => st_slave_port_err(2),
|
537 |
|
|
s2_rty_i => st_slave_port_rty(2),
|
538 |
|
|
s2_cti_o => st_slave_port_cti(2),
|
539 |
|
|
s2_bte_o => st_slave_port_bte(2),
|
540 |
|
|
--
|
541 |
|
|
-- Slave 3 Interface
|
542 |
|
|
s3_data_i => st_slave_port_data_in(3),
|
543 |
|
|
s3_data_o => st_slave_port_data_out(3),
|
544 |
|
|
s3_addr_o => st_slave_port_addr(3),
|
545 |
|
|
s3_sel_o => st_slave_port_sel(3),
|
546 |
|
|
s3_we_o => st_slave_port_we(3),
|
547 |
|
|
s3_cyc_o => st_slave_port_cyc(3),
|
548 |
|
|
s3_stb_o => st_slave_port_stb(3),
|
549 |
|
|
s3_ack_i => st_slave_port_ack(3),
|
550 |
|
|
s3_err_i => st_slave_port_err(3),
|
551 |
|
|
s3_rty_i => st_slave_port_rty(3),
|
552 |
|
|
s3_cti_o => st_slave_port_cti(3),
|
553 |
|
|
s3_bte_o => st_slave_port_bte(3),
|
554 |
|
|
--
|
555 |
|
|
-- Slave 4 Interface
|
556 |
|
|
s4_data_i => st_slave_port_data_in(4),
|
557 |
|
|
s4_data_o => st_slave_port_data_out(4),
|
558 |
|
|
s4_addr_o => st_slave_port_addr(4),
|
559 |
|
|
s4_sel_o => st_slave_port_sel(4),
|
560 |
|
|
s4_we_o => st_slave_port_we(4),
|
561 |
|
|
s4_cyc_o => st_slave_port_cyc(4),
|
562 |
|
|
s4_stb_o => st_slave_port_stb(4),
|
563 |
|
|
s4_ack_i => st_slave_port_ack(4),
|
564 |
|
|
s4_err_i => st_slave_port_err(4),
|
565 |
|
|
s4_rty_i => st_slave_port_rty(4),
|
566 |
|
|
s4_cti_o => st_slave_port_cti(4),
|
567 |
|
|
s4_bte_o => st_slave_port_bte(4),
|
568 |
|
|
--
|
569 |
|
|
-- Slave 5 Interface
|
570 |
|
|
s5_data_i => st_slave_port_data_in(5),
|
571 |
|
|
s5_data_o => st_slave_port_data_out(5),
|
572 |
|
|
s5_addr_o => st_slave_port_addr(5),
|
573 |
|
|
s5_sel_o => st_slave_port_sel(5),
|
574 |
|
|
s5_we_o => st_slave_port_we(5),
|
575 |
|
|
s5_cyc_o => st_slave_port_cyc(5),
|
576 |
|
|
s5_stb_o => st_slave_port_stb(5),
|
577 |
|
|
s5_ack_i => st_slave_port_ack(5),
|
578 |
|
|
s5_err_i => st_slave_port_err(5),
|
579 |
|
|
s5_rty_i => st_slave_port_rty(5),
|
580 |
|
|
s5_cti_o => st_slave_port_cti(5),
|
581 |
|
|
s5_bte_o => st_slave_port_bte(5),
|
582 |
|
|
--
|
583 |
|
|
-- Slave 6 Interface
|
584 |
|
|
s6_data_i => st_slave_port_data_in(6),
|
585 |
|
|
s6_data_o => st_slave_port_data_out(6),
|
586 |
|
|
s6_addr_o => st_slave_port_addr(6),
|
587 |
|
|
s6_sel_o => st_slave_port_sel(6),
|
588 |
|
|
s6_we_o => st_slave_port_we(6),
|
589 |
|
|
s6_cyc_o => st_slave_port_cyc(6),
|
590 |
|
|
s6_stb_o => st_slave_port_stb(6),
|
591 |
|
|
s6_ack_i => st_slave_port_ack(6),
|
592 |
|
|
s6_err_i => st_slave_port_err(6),
|
593 |
|
|
s6_rty_i => st_slave_port_rty(6),
|
594 |
|
|
s6_cti_o => st_slave_port_cti(6),
|
595 |
|
|
s6_bte_o => st_slave_port_bte(6),
|
596 |
|
|
--
|
597 |
|
|
-- Slave 7 Interface
|
598 |
|
|
s7_data_i => st_slave_port_data_in(7),
|
599 |
|
|
s7_data_o => st_slave_port_data_out(7),
|
600 |
|
|
s7_addr_o => st_slave_port_addr(7),
|
601 |
|
|
s7_sel_o => st_slave_port_sel(7),
|
602 |
|
|
s7_we_o => st_slave_port_we(7),
|
603 |
|
|
s7_cyc_o => st_slave_port_cyc(7),
|
604 |
|
|
s7_stb_o => st_slave_port_stb(7),
|
605 |
|
|
s7_ack_i => st_slave_port_ack(7),
|
606 |
|
|
s7_err_i => st_slave_port_err(7),
|
607 |
|
|
s7_rty_i => st_slave_port_rty(7),
|
608 |
|
|
s7_cti_o => st_slave_port_cti(7),
|
609 |
|
|
s7_bte_o => st_slave_port_bte(7),
|
610 |
|
|
--
|
611 |
|
|
-- Slave 8 Interface
|
612 |
|
|
s8_data_i => st_slave_port_data_in(8),
|
613 |
|
|
s8_data_o => st_slave_port_data_out(8),
|
614 |
|
|
s8_addr_o => st_slave_port_addr(8),
|
615 |
|
|
s8_sel_o => st_slave_port_sel(8),
|
616 |
|
|
s8_we_o => st_slave_port_we(8),
|
617 |
|
|
s8_cyc_o => st_slave_port_cyc(8),
|
618 |
|
|
s8_stb_o => st_slave_port_stb(8),
|
619 |
|
|
s8_ack_i => st_slave_port_ack(8),
|
620 |
|
|
s8_err_i => st_slave_port_err(8),
|
621 |
|
|
s8_rty_i => st_slave_port_rty(8),
|
622 |
|
|
s8_cti_o => st_slave_port_cti(8),
|
623 |
|
|
s8_bte_o => st_slave_port_bte(8),
|
624 |
|
|
--
|
625 |
|
|
-- Slave 9 Interface
|
626 |
|
|
s9_data_i => st_slave_port_data_in(9),
|
627 |
|
|
s9_data_o => st_slave_port_data_out(9),
|
628 |
|
|
s9_addr_o => st_slave_port_addr(9),
|
629 |
|
|
s9_sel_o => st_slave_port_sel(9),
|
630 |
|
|
s9_we_o => st_slave_port_we(9),
|
631 |
|
|
s9_cyc_o => st_slave_port_cyc(9),
|
632 |
|
|
s9_stb_o => st_slave_port_stb(9),
|
633 |
|
|
s9_ack_i => st_slave_port_ack(9),
|
634 |
|
|
s9_err_i => st_slave_port_err(9),
|
635 |
|
|
s9_rty_i => st_slave_port_rty(9),
|
636 |
|
|
s9_cti_o => st_slave_port_cti(9),
|
637 |
|
|
s9_bte_o => st_slave_port_bte(9),
|
638 |
|
|
--
|
639 |
|
|
-- Slave 10 Interface
|
640 |
|
|
s10_data_i => st_slave_port_data_in(10),
|
641 |
|
|
s10_data_o => st_slave_port_data_out(10),
|
642 |
|
|
s10_addr_o => st_slave_port_addr(10),
|
643 |
|
|
s10_sel_o => st_slave_port_sel(10),
|
644 |
|
|
s10_we_o => st_slave_port_we(10),
|
645 |
|
|
s10_cyc_o => st_slave_port_cyc(10),
|
646 |
|
|
s10_stb_o => st_slave_port_stb(10),
|
647 |
|
|
s10_ack_i => st_slave_port_ack(10),
|
648 |
|
|
s10_err_i => st_slave_port_err(10),
|
649 |
|
|
s10_rty_i => st_slave_port_rty(10),
|
650 |
|
|
s10_cti_o => st_slave_port_cti(10),
|
651 |
|
|
s10_bte_o => st_slave_port_bte(10),
|
652 |
|
|
--
|
653 |
|
|
-- Slave 11 Interface
|
654 |
|
|
s11_data_i => st_slave_port_data_in(11),
|
655 |
|
|
s11_data_o => st_slave_port_data_out(11),
|
656 |
|
|
s11_addr_o => st_slave_port_addr(11),
|
657 |
|
|
s11_sel_o => st_slave_port_sel(11),
|
658 |
|
|
s11_we_o => st_slave_port_we(11),
|
659 |
|
|
s11_cyc_o => st_slave_port_cyc(11),
|
660 |
|
|
s11_stb_o => st_slave_port_stb(11),
|
661 |
|
|
s11_ack_i => st_slave_port_ack(11),
|
662 |
|
|
s11_err_i => st_slave_port_err(11),
|
663 |
|
|
s11_rty_i => st_slave_port_rty(11),
|
664 |
|
|
s11_cti_o => st_slave_port_cti(11),
|
665 |
|
|
s11_bte_o => st_slave_port_bte(11),
|
666 |
|
|
--
|
667 |
|
|
-- Slave 12 Interface
|
668 |
|
|
s12_data_i => st_slave_port_data_in(12),
|
669 |
|
|
s12_data_o => st_slave_port_data_out(12),
|
670 |
|
|
s12_addr_o => st_slave_port_addr(12),
|
671 |
|
|
s12_sel_o => st_slave_port_sel(12),
|
672 |
|
|
s12_we_o => st_slave_port_we(12),
|
673 |
|
|
s12_cyc_o => st_slave_port_cyc(12),
|
674 |
|
|
s12_stb_o => st_slave_port_stb(12),
|
675 |
|
|
s12_ack_i => st_slave_port_ack(12),
|
676 |
|
|
s12_err_i => st_slave_port_err(12),
|
677 |
|
|
s12_rty_i => st_slave_port_rty(12),
|
678 |
|
|
s12_cti_o => st_slave_port_cti(12),
|
679 |
|
|
s12_bte_o => st_slave_port_bte(12),
|
680 |
|
|
--
|
681 |
|
|
-- Slave 13 Interface
|
682 |
|
|
s13_data_i => st_slave_port_data_in(13),
|
683 |
|
|
s13_data_o => st_slave_port_data_out(13),
|
684 |
|
|
s13_addr_o => st_slave_port_addr(13),
|
685 |
|
|
s13_sel_o => st_slave_port_sel(13),
|
686 |
|
|
s13_we_o => st_slave_port_we(13),
|
687 |
|
|
s13_cyc_o => st_slave_port_cyc(13),
|
688 |
|
|
s13_stb_o => st_slave_port_stb(13),
|
689 |
|
|
s13_ack_i => st_slave_port_ack(13),
|
690 |
|
|
s13_err_i => st_slave_port_err(13),
|
691 |
|
|
s13_rty_i => st_slave_port_rty(13),
|
692 |
|
|
s13_cti_o => st_slave_port_cti(13),
|
693 |
|
|
s13_bte_o => st_slave_port_bte(13),
|
694 |
|
|
--
|
695 |
|
|
-- Slave 14 Interface
|
696 |
|
|
s14_data_i => st_slave_port_data_in(14),
|
697 |
|
|
s14_data_o => st_slave_port_data_out(14),
|
698 |
|
|
s14_addr_o => st_slave_port_addr(14),
|
699 |
|
|
s14_sel_o => st_slave_port_sel(14),
|
700 |
|
|
s14_we_o => st_slave_port_we(14),
|
701 |
|
|
s14_cyc_o => st_slave_port_cyc(14),
|
702 |
|
|
s14_stb_o => st_slave_port_stb(14),
|
703 |
|
|
s14_ack_i => st_slave_port_ack(14),
|
704 |
|
|
s14_err_i => st_slave_port_err(14),
|
705 |
|
|
s14_rty_i => st_slave_port_rty(14),
|
706 |
|
|
s14_cti_o => st_slave_port_cti(14),
|
707 |
|
|
s14_bte_o => st_slave_port_bte(14),
|
708 |
|
|
--
|
709 |
|
|
-- Slave 15 Interface
|
710 |
|
|
s15_data_i => st_slave_port_data_in(15),
|
711 |
|
|
s15_data_o => st_slave_port_data_out(15),
|
712 |
|
|
s15_addr_o => st_slave_port_addr(15),
|
713 |
|
|
s15_sel_o => st_slave_port_sel(15),
|
714 |
|
|
s15_we_o => st_slave_port_we(15),
|
715 |
|
|
s15_cyc_o => st_slave_port_cyc(15),
|
716 |
|
|
s15_stb_o => st_slave_port_stb(15),
|
717 |
|
|
s15_ack_i => st_slave_port_ack(15),
|
718 |
|
|
s15_err_i => st_slave_port_err(15),
|
719 |
|
|
s15_rty_i => st_slave_port_rty(15),
|
720 |
|
|
s15_cti_o => st_slave_port_cti(15),
|
721 |
|
|
s15_bte_o => st_slave_port_bte(15)
|
722 |
|
|
);
|
723 |
|
|
-------------------------------------------------------------------------------
|
724 |
|
|
--
|
725 |
|
|
-- Module Inner route:
|
726 |
|
|
--
|
727 |
|
|
-- 1st route WB_CROSS MASTER signals:
|
728 |
|
|
-- ==> Deal with PCIE_CORE64_WB Ports:
|
729 |
|
|
st_master_port_data_in(0) <= sv_wbm_data_out_pcie_core64_wb; -- from WBM to WB_CROSS
|
730 |
|
|
st_master_port_addr(0) <= sv_wbm_addr_pcie_core64_wb; -- ...
|
731 |
|
|
st_master_port_sel(0) <= sv_wbm_sel_pcie_core64_wb; -- ...
|
732 |
|
|
st_master_port_we(0) <= s_wbm_we_pcie_core64_wb; -- ...
|
733 |
|
|
st_master_port_cyc(0) <= s_wbm_cyc_pcie_core64_wb; -- ...
|
734 |
|
|
st_master_port_stb(0) <= s_wbm_stb_pcie_core64_wb; -- ...
|
735 |
|
|
st_master_port_cti(0) <= sv_wbm_cti_pcie_core64_wb; -- ...
|
736 |
|
|
st_master_port_bte(0) <= sv_wbm_bte_pcie_core64_wb; -- ...
|
737 |
|
|
|
738 |
|
|
sv_wbm_data_in_pcie_core64_wb <= st_master_port_data_out(0); -- from WB_CROSS to WBM
|
739 |
|
|
s_wbm_ack_pcie_core64_wb <= st_master_port_ack(0); -- ...
|
740 |
|
|
s_wbm_err_pcie_core64_wb <= st_master_port_err(0); -- ...
|
741 |
|
|
s_wbm_rty_pcie_core64_wb <= st_master_port_rty(0); -- ...
|
742 |
|
|
-- ==> Deal with Unused Ports:
|
743 |
|
|
gen_conn_to_unused_mports : for i in (0+1) to p_WB_CROSS_MASTER_Q-1 generate
|
744 |
|
|
st_master_port_data_in(i) <= (others => '0');
|
745 |
|
|
st_master_port_addr(i) <= (others => '0');
|
746 |
|
|
st_master_port_sel(i) <= (others => '0');
|
747 |
|
|
st_master_port_we(i) <= '0';
|
748 |
|
|
st_master_port_cyc(i) <= '0';
|
749 |
|
|
st_master_port_stb(i) <= '0';
|
750 |
|
|
st_master_port_cti(i) <= (others => '0');
|
751 |
|
|
st_master_port_bte(i) <= (others => '0');
|
752 |
|
|
--st_master_port_data_out(i) <= ;
|
753 |
|
|
--st_master_port_ack(i) <= ;
|
754 |
|
|
--st_master_port_err(i) <= ;
|
755 |
|
|
--st_master_port_rty(i) <= ;
|
756 |
|
|
end generate gen_conn_to_unused_mports;
|
757 |
|
|
--
|
758 |
|
|
-- 2nd route WB_CROSS SLAVE signals:
|
759 |
|
|
-- Deal with TEST_CHECK.WB_CFG_SLAVE
|
760 |
|
|
sv_wbs_cfg_data_in_test_check <= st_slave_port_data_out(0); -- from WB_CROSS to WBS
|
761 |
|
|
sv_wbs_cfg_addr_test_check <= st_slave_port_addr(0); -- ...
|
762 |
|
|
sv_wbs_cfg_sel_test_check <= st_slave_port_sel(0); -- ...
|
763 |
|
|
s_wbs_cfg_we_test_check <= st_slave_port_we(0); -- ...
|
764 |
|
|
s_wbs_cfg_cyc_test_check <= st_slave_port_cyc(0); -- ...
|
765 |
|
|
s_wbs_cfg_stb_test_check <= st_slave_port_stb(0); -- ...
|
766 |
|
|
sv_wbs_cfg_cti_test_check <= st_slave_port_cti(0); -- ...
|
767 |
|
|
sv_wbs_cfg_bte_test_check <= st_slave_port_bte(0); -- ...
|
768 |
|
|
|
769 |
|
|
st_slave_port_data_in(0) <= sv_wbs_cfg_data_out_test_check; -- from WBS to WB_CROSS
|
770 |
|
|
st_slave_port_ack(0) <= s_wbs_cfg_ack_test_check; -- ...
|
771 |
|
|
st_slave_port_err(0) <= s_wbs_cfg_err_test_check; -- ...
|
772 |
|
|
st_slave_port_rty(0) <= s_wbs_cfg_rty_test_check; -- ...
|
773 |
|
|
-- Deal with TEST_CHECK.WB_BURST_SLAVE
|
774 |
|
|
sv_wbs_burst_data_in_test_check <= st_slave_port_data_out(1); -- from WB_CROSS to WBS
|
775 |
|
|
sv_wbs_burst_addr_test_check <= st_slave_port_addr(1); -- ...
|
776 |
|
|
sv_wbs_burst_sel_test_check <= st_slave_port_sel(1); -- ...
|
777 |
|
|
s_wbs_burst_we_test_check <= st_slave_port_we(1); -- ...
|
778 |
|
|
s_wbs_burst_cyc_test_check <= st_slave_port_cyc(1); -- ...
|
779 |
|
|
s_wbs_burst_stb_test_check <= st_slave_port_stb(1); -- ...
|
780 |
|
|
sv_wbs_burst_cti_test_check <= st_slave_port_cti(1);
|
781 |
|
|
sv_wbs_burst_bte_test_check <= st_slave_port_bte(1);
|
782 |
|
|
|
783 |
|
|
st_slave_port_data_in(1) <= (others => '0'); -- from WBS to WB_CROSS
|
784 |
|
|
st_slave_port_ack(1) <= s_wbs_burst_ack_test_check; -- ...
|
785 |
|
|
st_slave_port_err(1) <= s_wbs_burst_err_test_check; -- ...
|
786 |
|
|
st_slave_port_rty(1) <= s_wbs_burst_rty_test_check; -- ...
|
787 |
|
|
-- Deal with TEST_GEN.WB_CFG_SLAVE
|
788 |
|
|
sv_wbs_cfg_data_in_test_gen <= st_slave_port_data_out(2); -- from WB_CROSS to WBS
|
789 |
|
|
sv_wbs_cfg_addr_test_gen <= st_slave_port_addr(2); -- ...
|
790 |
|
|
sv_wbs_cfg_sel_test_gen <= st_slave_port_sel(2); -- ...
|
791 |
|
|
s_wbs_cfg_we_test_gen <= st_slave_port_we(2); -- ...
|
792 |
|
|
s_wbs_cfg_cyc_test_gen <= st_slave_port_cyc(2); -- ...
|
793 |
|
|
s_wbs_cfg_stb_test_gen <= st_slave_port_stb(2); -- ...
|
794 |
|
|
sv_wbs_cfg_cti_test_gen <= st_slave_port_cti(2); -- ...
|
795 |
|
|
sv_wbs_cfg_bte_test_gen <= st_slave_port_bte(2); -- ...
|
796 |
|
|
|
797 |
|
|
st_slave_port_data_in(2) <= sv_wbs_cfg_data_out_test_gen; -- from WBS to WB_CROSS
|
798 |
|
|
st_slave_port_ack(2) <= s_wbs_cfg_ack_test_gen; -- ...
|
799 |
|
|
st_slave_port_err(2) <= s_wbs_cfg_err_test_gen; -- ...
|
800 |
|
|
st_slave_port_rty(2) <= s_wbs_cfg_rty_test_gen; -- ...
|
801 |
|
|
-- Deal with TEST_GEN.WB_BURST_SLAVE
|
802 |
|
|
--st_slave_port_data_out(3)
|
803 |
|
|
sv_wbs_burst_addr_test_gen <= st_slave_port_addr(3);
|
804 |
|
|
sv_wbs_burst_sel_test_gen <= st_slave_port_sel(3);
|
805 |
|
|
s_wbs_burst_we_test_gen <= st_slave_port_we(3);
|
806 |
|
|
s_wbs_burst_cyc_test_gen <= st_slave_port_cyc(3);
|
807 |
|
|
s_wbs_burst_stb_test_gen <= st_slave_port_stb(3);
|
808 |
|
|
sv_wbs_burst_cti_test_gen <= st_slave_port_cti(3);
|
809 |
|
|
sv_wbs_burst_bte_test_gen <= st_slave_port_bte(3);
|
810 |
|
|
|
811 |
|
|
st_slave_port_data_in(3) <= sv_wbs_burst_data_out_test_gen;
|
812 |
|
|
st_slave_port_ack(3) <= s_wbs_burst_ack_test_gen;
|
813 |
|
|
st_slave_port_err(3) <= s_wbs_burst_err_test_gen;
|
814 |
|
|
st_slave_port_rty(3) <= s_wbs_burst_rty_test_gen;
|
815 |
|
|
-- Deal with Unused SALVE Ports
|
816 |
|
|
gen_conn_to_unused_sports : for i in (3+1) to p_WB_CROSS_SLAVE_Q-1 generate
|
817 |
|
|
--st_slave_port_data_out(i) <= ;
|
818 |
|
|
--st_slave_port_addr(i) <= ;
|
819 |
|
|
--st_slave_port_sel(i) <= ;
|
820 |
|
|
--st_slave_port_we(i) <= ;
|
821 |
|
|
--st_slave_port_cyc(i) <= ;
|
822 |
|
|
--st_slave_port_stb(i) <= ;
|
823 |
|
|
--st_slave_port_cti(i) <= ;
|
824 |
|
|
--st_slave_port_bte(i) <= ;
|
825 |
|
|
st_slave_port_data_in(i) <= p_TEST_DATA_64BIT;
|
826 |
|
|
st_slave_port_ack(i) <= '1'; -- ALWAYS READY (always answer to MASTER with "p_TEST_DATA_64BIT" value)
|
827 |
|
|
st_slave_port_err(i) <= '0';
|
828 |
|
|
st_slave_port_rty(i) <= '0';
|
829 |
|
|
|
830 |
|
|
end generate gen_conn_to_unused_sports;
|
831 |
|
|
--
|
832 |
|
|
-- Construct PCIE Line-width value:
|
833 |
|
|
sv_pcie_line_num <= sv_pcie_lstatus(6 downto 4) when s_pcie_link_up_n='0'
|
834 |
|
|
else "000";
|
835 |
|
|
|
836 |
|
|
-------------------------------------------------------------------------------
|
837 |
|
|
--
|
838 |
|
|
-- Module Outputs deal:
|
839 |
|
|
--
|
840 |
|
|
led(1) <= s_pcie_link_up_n after 1ns when rising_edge(s_wb_clk); -- LED#0 - PCIE_LINK_UP
|
841 |
|
|
--
|
842 |
|
|
led(3 downto 2) <= sv_pcie_line_num( 1 downto 0 ) after 1ns when rising_edge(s_wb_clk); -- LED#1 - show PCIE line-width: x1->1, x2->2, etc...
|
843 |
|
|
|
844 |
|
|
-------------------------------------------------------------------------------
|
845 |
|
|
end rtl;
|