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[/] [pcie_ds_dma/] [trunk/] [projects/] [ambpex5_v20_sx50t_core/] [src/] [testbench/] [stend_ambpex5_core.vhd] - Blame information for rev 2

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1 2 dsmv
-------------------------------------------------------------------------------
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--
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-- Title       : stend_ambpex5_core
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-- Author      : Dmitry Smekhov
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-- Company     : Instrumental Systems
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-- E-mail      : dsmv@insys.ru
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--
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-- Version     : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : 
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.ambpex5_v20_sx50t_core_pkg.all;
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entity stend_ambpex5_core is
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end stend_ambpex5_core;
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architecture stend_ambpex5_core of stend_ambpex5_core is
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component xilinx_pcie_2_0_rport_v6 is
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generic (
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          REF_CLK_FREQ   : integer;          -- 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz
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          ALLOW_X8_GEN2  : boolean;
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          PL_FAST_TRAIN  : boolean;
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          LINK_CAP_MAX_LINK_SPEED : bit_vector;
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          DEVICE_ID : bit_vector;
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          LINK_CAP_MAX_LINK_WIDTH  : bit_vector;
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          LINK_CAP_MAX_LINK_WIDTH_int  : integer;
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          LINK_CTRL2_TARGET_LINK_SPEED  : bit_vector;
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          LTSSM_MAX_LINK_WIDTH  : bit_vector;
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          DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
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          USER_CLK_FREQ : integer;
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          VC0_TX_LASTPACKET : integer;
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          VC0_RX_RAM_LIMIT : bit_vector;
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          VC0_TOTAL_CREDITS_PD : integer;
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          VC0_TOTAL_CREDITS_CD : integer
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);
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port  (
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  sys_clk : in std_logic;
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  sys_reset_n : in std_logic;
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  pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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  pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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  pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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  pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
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);
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end component;
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signal  clk250                  : std_logic:='0';
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signal  clk250p                 : std_logic;
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signal  clk250n                 : std_logic;
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signal  clk100                  : std_logic:='0';
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signal  reset                   : std_logic;
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signal  txp                             : std_logic_vector( 7 downto 0 ):=(others=>'0');
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signal  txn                             : std_logic_vector( 7 downto 0 ):=(others=>'1');
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signal  rxp                             : std_logic_vector( 7 downto 0 ):=(others=>'0');
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signal  rxn                             : std_logic_vector( 7 downto 0 ):=(others=>'1');
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signal  rp_txp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal  rp_txn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal  rp_rxp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal  rp_rxn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal  tp                              : std_logic_vector( 3 downto 1 );
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signal  led1                    : std_logic;
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signal  led2                    : std_logic;
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signal  led3                    : std_logic;
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signal  led4                    : std_logic;
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begin
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 amb: ambpex5_v20_sx50t_core
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        generic map(
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                is_simulation   => 1    -- 0 - синтез, 1 - моделирование ADM
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        )
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        port map(
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                ---- PCI-Express ----
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                txp                                     => txp,
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                txn                                     => txn,
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                rxp                                     => rxp,
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                rxn                                     => rxn,
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                mgt251_p                        => clk250p,   -- тактовая частота 250 MHz от PCI_Express
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                mgt251_n                        => clk250n,
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                bperst                          => reset,       -- 0 - сброс                                               
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                btp                                     => tp, -- контрольные точки
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                ---- Светодиоды ----
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                bled1                           => led1,
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                bled2                           => led2,
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                bled3                           => led3,
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                bled4                           => led4
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        );
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rp : xilinx_pcie_2_0_rport_v6
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generic map (
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      REF_CLK_FREQ => 0,
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      ALLOW_X8_GEN2 => FALSE,
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      PL_FAST_TRAIN => TRUE,
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      LINK_CAP_MAX_LINK_SPEED => X"1",
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      DEVICE_ID => X"6011",
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      LINK_CAP_MAX_LINK_WIDTH => X"01",
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      LINK_CAP_MAX_LINK_WIDTH_int => 1,
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      LINK_CTRL2_TARGET_LINK_SPEED => X"1",
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      LTSSM_MAX_LINK_WIDTH => X"01",
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      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
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      VC0_TX_LASTPACKET => 29,
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      VC0_RX_RAM_LIMIT => X"7FF",
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      VC0_TOTAL_CREDITS_PD => (308),
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      VC0_TOTAL_CREDITS_CD => (308),
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      USER_CLK_FREQ => 1
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)
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port map (
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  sys_clk => clk100,
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  sys_reset_n => reset,
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  pci_exp_txn => rp_txn,
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  pci_exp_txp => rp_txp,
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  pci_exp_rxn => rp_rxn,
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  pci_exp_rxp => rp_rxp
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);
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clk100 <= not clk100 after 5 ns;
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clk250 <= not clk250 after 2 ns;
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clk250p <= clk250;
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clk250n <= not clk250;
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rxp(0) <= rp_txp(0);
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rxn(0) <= rp_txn(0);
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rp_rxp(0) <= txp(0);
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rp_rxn(0) <= txn(0);
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reset <= '0', '1' after 5002 ns;
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end stend_ambpex5_core;

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