OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [ambpex5_v20_sx50t_core/] [src/] [top/] [ambpex5_v20_sx50t_core.ucf] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dsmv
 
2
 
3
NET "btp<3>"        LOC = "AC9"    | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
4
NET "btp<2>"        LOC = "AC8"    | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
5
NET "btp<1>"        LOC = "AB8"    | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
6
 
7
 
8
 
9
# PIOX
10
 
11
NET "backwri"    LOC = "N10";
12
NET "backrdi"    LOC = "L11";
13
NET "bpiowri"    LOC = "M10";
14
NET "bpiordi"    LOC = "N9";
15
NET "bpio<9>"       LOC = "E12";
16
NET "bpio<8>"       LOC = "G11";
17
NET "bpio<7>"       LOC = "H10";
18
NET "bpio<6>"       LOC = "F13";
19
NET "bpio<5>"       LOC = "G12";
20
NET "bpio<4>"       LOC = "E13";
21
NET "bpio<3>"       LOC = "G13";
22
NET "bpio<2>"       LOC = "J10";
23
NET "bpio<15>"       LOC = "G10";
24
NET "bpio<14>"       LOC = "E11";
25
NET "bpio<13>"       LOC = "D11";
26
NET "bpio<12>"       LOC = "F11";
27
NET "bpio<11>"       LOC = "D12";
28
NET "bpio<10>"       LOC = "C13";
29
NET "bpio<1>"       LOC = "J11";
30
NET "bpio<0>"       LOC = "K11";
31
NET "bpen1"      LOC = "F10";
32
NET "bpen0"      LOC = "L10";
33
 
34
NET  "txp<7>"  LOC = "AN4";
35
NET  "txn<7>"  LOC = "AN3";
36
NET  "txp<6>"  LOC = "AK2";
37
NET  "txn<6>"  LOC = "AL2";
38
NET  "txp<5>"  LOC = "AJ2";
39
NET  "txn<5>"  LOC = "AH2";
40
NET  "txp<4>"  LOC = "AD2";
41
NET  "txn<4>"  LOC = "AE2";
42
NET  "txp<3>"  LOC = "AC2";
43
NET  "txn<3>"  LOC = "AB2";
44
NET  "txp<2>"  LOC = "V2";
45
NET  "txn<2>"  LOC = "W2";
46
NET  "txp<1>"  LOC = "U2";
47
NET  "txn<1>"  LOC = "T2";
48
NET  "txp<0>"  LOC = "M2";
49
NET  "txn<0>"  LOC = "N2";
50
 
51
 
52
NET  "bperst"  LOC = "AF11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12;
53
 
54
 
55
NET  "rxp<7>"  LOC = "AP3";
56
NET  "rxn<7>"  LOC = "AP2";
57
NET  "rxp<6>"  LOC = "AL1";
58
NET  "rxn<6>"  LOC = "AM1";
59
NET  "rxp<5>"  LOC = "AH1";
60
NET  "rxn<5>"  LOC = "AG1";
61
NET  "rxp<4>"  LOC = "AE1";
62
NET  "rxn<4>"  LOC = "AF1";
63
NET  "rxp<3>"  LOC = "AB1";
64
NET  "rxn<3>"  LOC = "AA1";
65
NET  "rxp<2>"  LOC = "W1";
66
NET  "rxn<2>"  LOC = "Y1";
67
NET  "rxp<1>"  LOC = "T1";
68
NET  "rxn<1>"  LOC = "R1";
69
NET  "rxp<0>"  LOC = "N1";
70
NET  "rxn<0>"  LOC = "P1";
71
 
72
 
73
 
74
NET "bmgtrefclk_p"       LOC = "H4";
75
NET "bmgtrefclk_n"       LOC = "H3";
76
NET "bmgtavtttx_112_0"   LOC = "M3";
77
NET "bmgtavtttx_112_0"   LOC = "U3";
78
NET "bmgt252_p"          LOC = "AG18";
79
NET "bmgt252_n"          LOC = "AF19";
80
 
81
NET  "mgt251_p"  LOC = "P4";
82
NET  "mgt251_n"  LOC = "P3";
83
 
84
NET "bmgt100_p"          LOC = "AH20";
85
NET "bmgt100_n"          LOC = "AH19";
86
NET "bled4"      LOC = "AF20";
87
NET "bled3"      LOC = "AF21";
88
NET "bled2"      LOC = "AF23";
89
NET "bled1"      LOC = "AG23";
90
 
91
NET "bclkosc_p"          LOC = "J14";
92
NET "bclkosc_n"          LOC = "H13";
93
 
94
#INST  "bclkosc*"  DIFF_TERM = TRUE;
95
 
96
 
97
# PCIe Lanes 0, 1
98
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y3;
99
 
100
# PCIe Lanes 2, 3
101
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y2;
102
 
103
# PCIe Lanes 4, 5
104
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTP_DUAL_X0Y1;
105
 
106
# PCIe Lanes 6, 7
107
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTP_DUAL_X0Y0;
108
 
109
 
110
 
111
###############################################################################
112
# Physical Constraints
113
###############################################################################
114
#
115
# BlockRAM placement
116
#
117
 
118
 
119
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC =RAMB36_X4Y7 ;
120
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC =RAMB36_X4Y6 ;
121
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC =RAMB36_X4Y5 ;
122
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC =RAMB36_X4Y4 ;
123
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC =RAMB36_X4Y8 ;
124
 
125
 
126
###############################################################################
127
# Timing Constraints
128
###############################################################################
129
#
130
# Timing requirements and related constraints.
131
#
132
 
133
 
134
NET "clk" buffer_type = "none";
135
 
136
#NET "*mgt250*"  TNM_NET = "MGTCLK";
137
 
138
NET "amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/clocking_i/clkout0" TNM_NET = "MGTCLK";
139
 
140
TIMESPEC "TS_MGTCLK"  = PERIOD "MGTCLK" 250.00 MHz HIGH 50 % ;
141
 
142
 
143
 
144
INST "core/core/fifo" AREA_GROUP = "pblock_fifo";
145
INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
146
AREA_GROUP "pblock_fifo" RANGE=SLICE_X24Y0:SLICE_X35Y39;
147
AREA_GROUP "pblock_fifo" RANGE=DSP48_X3Y0:DSP48_X3Y15;
148
AREA_GROUP "pblock_fifo" RANGE=RAMB36_X2Y0:RAMB36_X2Y7;
149
INST "core/core/tx" AREA_GROUP = "pblock_tx";
150
INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
151
AREA_GROUP "pblock_tx" RANGE=SLICE_X36Y25:SLICE_X45Y43;
152
INST "core/core/rx" AREA_GROUP = "pblock_rx";
153
INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
154
AREA_GROUP "pblock_rx" RANGE=SLICE_X36Y0:SLICE_X45Y24;
155
INST "core/core/disp" AREA_GROUP = "pblock_disp";
156
INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
157
AREA_GROUP "pblock_disp" RANGE=SLICE_X28Y40:SLICE_X35Y49;
158
INST "core/core/reg" AREA_GROUP = "pblock_reg";
159
INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
160
AREA_GROUP "pblock_reg" RANGE=SLICE_X36Y44:SLICE_X41Y49;
161
INST "core/tz" AREA_GROUP = "pblock_tz";
162
INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
163
AREA_GROUP "pblock_tz" RANGE=SLICE_X32Y50:SLICE_X45Y53;
164
INST "core/core/ep" AREA_GROUP = "pblock_ep";
165
INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
166
AREA_GROUP "pblock_ep" RANGE=SLICE_X46Y0:SLICE_X67Y49;
167
AREA_GROUP "pblock_ep" RANGE=RAMB36_X4Y0:RAMB36_X4Y9;
168
INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
169
AREA_GROUP "pblock_main" RANGE=SLICE_X42Y44:SLICE_X45Y49;
170
INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
171
AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X32Y54:SLICE_X51Y69;
172
AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB36_X3Y11:RAMB36_X3Y13;
173
INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
174
AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X64Y50:SLICE_X67Y56;
175
INST "dio_out" AREA_GROUP = "pblock_dio_out";
176
AREA_GROUP "pblock_dio_out" RANGE=SLICE_X22Y70:SLICE_X35Y89;
177
AREA_GROUP "pblock_dio_out" RANGE=RAMB36_X2Y14:RAMB36_X2Y17;
178
INST "dio_in" AREA_GROUP = "pblock_dio_in";
179
AREA_GROUP "pblock_dio_in" RANGE=SLICE_X36Y70:SLICE_X51Y89;
180
AREA_GROUP "pblock_dio_in" RANGE=RAMB36_X3Y14:RAMB36_X3Y17;
181
INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
182
AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X20Y90:SLICE_X59Y119;
183
AREA_GROUP "pblock_test_ctrl" RANGE=DSP48_X2Y36:DSP48_X5Y47;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.