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[/] [pcie_ds_dma/] [trunk/] [projects/] [ml605_lx240t_core/] [src/] [top/] [ml605_lx240t_core.ucf] - Blame information for rev 2

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##-----------------------------------------------------------------------------
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##
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## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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##
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## This file contains confidential and proprietary information
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## of Xilinx, Inc. and is protected under U.S. and
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## international copyright and other intellectual property
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## laws.
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##
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## DISCLAIMER
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## This disclaimer is not a license and does not grant any
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## rights to the materials distributed herewith. Except as
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## otherwise provided in a valid license issued to you by
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## Xilinx, and to the maximum extent permitted by applicable
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## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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## (2) Xilinx shall not be liable (whether in contract or tort,
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## including negligence, or under any other theory of
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## liability) for any loss or damage of any kind or nature
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## materials, including for any direct, or any indirect,
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## special, incidental, or consequential loss or damage
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## (including loss of data, profits, goodwill, or any type of
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## loss or damage suffered as a result of any action brought
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## by a third party) even if such damage or loss was
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## reasonably foreseeable or Xilinx had been advised of the
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## possibility of the same.
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##
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## CRITICAL APPLICATIONS
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## Xilinx products are not designed or intended to be fail-
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## safe, or for use in any application requiring fail-safe
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## injury, or severe property or environmental damage
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## (individually and collectively, "Critical
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## Applications"). Customer assumes the sole risk and
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## liability of any use of Xilinx products in Critical
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## Applications, subject only to applicable laws and
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## regulations governing limitations on product liability.
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##
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## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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## PART OF THIS FILE AT ALL TIMES.
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##
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##-----------------------------------------------------------------------------
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## Project    : Virtex-6 Integrated Block for PCI Express
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## File       : xilinx_pcie_2_0_ep_v6_04_lane_gen2_xc6vlx240t-ff1156-1_ML605.ucf
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## Version    : 2.3
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#
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###############################################################################
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# Define Device, Package And Speed Grade
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###############################################################################
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CONFIG PART = xc6vlx240t-ff1156-1;
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###############################################################################
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# User Time Names / User Time Groups / Time Specs
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###############################################################################
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###############################################################################
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# User Physical Constraints
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###############################################################################
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###############################################################################
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# Pinout and Related I/O Constraints
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###############################################################################
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#
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# SYS reset (input) signal.  The sys_reset_n signal should be
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# obtained from the PCI Express interface if possible.  For
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# slot based form factors, a system reset signal is usually
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# present on the connector.  For cable based form factors, a
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# system reset signal may not be available.  In this case, the
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# system reset signal must be generated locally by some form of
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# supervisory circuit.  You may change the IOSTANDARD and LOC
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# to suit your requirements and VCCO voltage banking rules.
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#
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NET "sys_reset_n" TIG;
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NET "sys_reset_n" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
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#
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#
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# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
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# signals are the PCI Express reference clock. Virtex-6 GT
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# Transceiver architecture requires the use of a dedicated clock
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# resources (FPGA input pins) associated with each GT Transceiver.
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# To use these pins an IBUFDS primitive (refclk_ibuf) is
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# instantiated in user's design.
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# Please refer to the Virtex-6 GT Transceiver User Guide
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# (UG) for guidelines regarding clock resource selection.
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#
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NET "sys_clk_p" LOC = P6;
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NET "sys_clk_n" LOC = P5;
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INST "amb/refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;
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#
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# Transceiver instance placement.  This constraint selects the
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# transceivers to be used, which also dictates the pinout for the
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# transmit and receive differential pairs.  Please refer to the
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# Virtex-6 GT Transceiver User Guide (UG) for more information.
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#
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# PCIe Lane 0
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INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;
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# PCIe Lane 1
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INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14;
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# PCIe Lane 2
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INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13;
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# PCIe Lane 3
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INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12;
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#
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# PCI Express Block placement. This constraint selects the PCI Express
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# Block to be used.
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#
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INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;
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#NET  "led_0"           LOC = "AC22"   ;
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#NET  "led_1"           LOC = "AC24"   ;
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#NET  "led_2"           LOC = "AE22"  ;
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#
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NET "gpio_led0"                 LOC = "AC22";
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NET "gpio_led1"                 LOC = "AC24";
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NET "gpio_led2"                 LOC = "AE22";
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NET "gpio_led3"                 LOC = "AE23";
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NET "gpio_led4"                 LOC = "AB23";
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# MMCM Placment. This constraint selects the MMCM Placement
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#
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INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;
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###############################################################################
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# Timing Constraints
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###############################################################################
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#
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# Timing requirements and related constraints.
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#
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NET "sys_clk_p" TNM_NET = "SYSCLK" ;
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NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;
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NET "*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";
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NET "*/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
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TIMESPEC "TS_SYSCLK"  = PERIOD "SYSCLK" 100 MHz HIGH 50 % ;
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TIMESPEC "TS_CLK_125"  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 100 ;
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TIMESPEC "TS_TXOUTCLKBUFG"  = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ;
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TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;
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NET "*/pcie_clocking_i/sel_lnk_rate_d" TIG ;
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PIN "*/trn_reset_n_int_i.CLR" TIG ;
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PIN "*/trn_reset_n_i.CLR" TIG ;
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PIN "*/pcie_clocking_i/mmcm_adv_i.RST" TIG ;
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#TIMESPEC "TS_RESETN" = FROM FFS(*) TO FFS(user_reset_n_i) 8 ns;
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###############################################################################
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# Physical Constraints
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###############################################################################
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###############################################################################
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# End
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###############################################################################
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INST "amb/gen_syn.pcie/core/int" AREA_GROUP = "pblock_int";
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AREA_GROUP "pblock_int" RANGE=SLICE_X132Y148:SLICE_X135Y151;
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INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
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AREA_GROUP "pblock_rx" RANGE=SLICE_X136Y140:SLICE_X143Y159;
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INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
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AREA_GROUP "pblock_tx" RANGE=SLICE_X136Y121:SLICE_X143Y139;
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INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
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AREA_GROUP "pblock_fifo" RANGE=SLICE_X132Y121:SLICE_X135Y139, SLICE_X126Y121:SLICE_X131Y159;
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AREA_GROUP "pblock_fifo" RANGE=DSP48_X6Y50:DSP48_X6Y55;
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AREA_GROUP "pblock_fifo" RANGE=RAMB18_X6Y50:RAMB18_X6Y63;
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AREA_GROUP "pblock_fifo" RANGE=RAMB36_X6Y25:RAMB36_X6Y31;
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INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
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AREA_GROUP "pblock_disp" RANGE=SLICE_X132Y152:SLICE_X135Y159;
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INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
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AREA_GROUP "pblock_reg" RANGE=SLICE_X132Y140:SLICE_X135Y147;
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INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
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AREA_GROUP "pblock_main" RANGE=SLICE_X144Y161:SLICE_X147Y168;
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INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
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AREA_GROUP "pblock_tz" RANGE=SLICE_X132Y161:SLICE_X143Y165;
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INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
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AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X158Y162:SLICE_X161Y166;
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INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
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AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X116Y166:SLICE_X143Y179;
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AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB18_X6Y68:RAMB18_X6Y71;
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AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB36_X6Y34:RAMB36_X6Y35;
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INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
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AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X108Y200:SLICE_X135Y239;
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INST "dio_in" AREA_GROUP = "pblock_dio_in";
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AREA_GROUP "pblock_dio_in" RANGE=SLICE_X112Y180:SLICE_X121Y199;
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AREA_GROUP "pblock_dio_in" RANGE=RAMB18_X5Y72:RAMB18_X5Y79;
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AREA_GROUP "pblock_dio_in" RANGE=RAMB36_X5Y36:RAMB36_X5Y39;
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INST "main" AREA_GROUP = "pblock_main_1";
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AREA_GROUP "pblock_main_1" RANGE=SLICE_X150Y180:SLICE_X161Y199;
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INST "dio_out" AREA_GROUP = "pblock_dio_out";
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AREA_GROUP "pblock_dio_out" RANGE=SLICE_X128Y180:SLICE_X135Y199;
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AREA_GROUP "pblock_dio_out" RANGE=RAMB18_X6Y72:RAMB18_X6Y79;
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AREA_GROUP "pblock_dio_out" RANGE=RAMB36_X6Y36:RAMB36_X6Y39;
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INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
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AREA_GROUP "pblock_ep" RANGE=SLICE_X144Y122:SLICE_X161Y158;
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AREA_GROUP "pblock_ep" RANGE=RAMB18_X7Y50:RAMB18_X7Y61;
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AREA_GROUP "pblock_ep" RANGE=RAMB36_X7Y25:RAMB36_X7Y30;

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