Subversion Repositories pcie_ds_dma

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## Project    : Virtex-6 Integrated Block for PCI Express

## File       : xilinx_pcie_2_0_ep_v6_04_lane_gen2_xc6vlx240t-ff1156-1_ML605.ucf

## Version    : 2.3

#

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# Define Device, Package And Speed Grade

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CONFIG PART = xc6vlx240t-ff1156-1;

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# User Time Names / User Time Groups / Time Specs

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# User Physical Constraints

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# Pinout and Related I/O Constraints

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#

# SYS reset (input) signal.  The sys_reset_n signal should be

# obtained from the PCI Express interface if possible.  For

# slot based form factors, a system reset signal is usually

# present on the connector.  For cable based form factors, a

# system reset signal may not be available.  In this case, the

# system reset signal must be generated locally by some form of

# supervisory circuit.  You may change the IOSTANDARD and LOC

# to suit your requirements and VCCO voltage banking rules.

#

NET "sys_reset_n" TIG;

NET "sys_reset_n" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#

#

# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n

# signals are the PCI Express reference clock. Virtex-6 GT

# Transceiver architecture requires the use of a dedicated clock

# resources (FPGA input pins) associated with each GT Transceiver.

# To use these pins an IBUFDS primitive (refclk_ibuf) is

# instantiated in user's design.

# Please refer to the Virtex-6 GT Transceiver User Guide

# (UG) for guidelines regarding clock resource selection.

#

NET "sys_clk_p" LOC = P6;

NET "sys_clk_n" LOC = P5;

INST "amb/refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;

#

# Transceiver instance placement.  This constraint selects the

# transceivers to be used, which also dictates the pinout for the

# transmit and receive differential pairs.  Please refer to the

# Virtex-6 GT Transceiver User Guide (UG) for more information.

#

# PCIe Lane 0

INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;

# PCIe Lane 1

INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14;

# PCIe Lane 2

INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13;

# PCIe Lane 3

INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12;

#

# PCI Express Block placement. This constraint selects the PCI Express

# Block to be used.

#

INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;

#NET  "led_0"           LOC = "AC22"   ;

#NET  "led_1"           LOC = "AC24"   ;

#NET  "led_2"           LOC = "AE22"  ;

#

NET "gpio_led0"                 LOC = "AC22";

NET "gpio_led1"                 LOC = "AC24";

NET "gpio_led2"                 LOC = "AE22";

NET "gpio_led3"                 LOC = "AE23";

NET "gpio_led4"                 LOC = "AB23";

# MMCM Placment. This constraint selects the MMCM Placement

#

INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;

###############################################################################

# Timing Constraints

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#

# Timing requirements and related constraints.

#

NET "sys_clk_p" TNM_NET = "SYSCLK" ;

NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;

NET "*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";

NET "*/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;

TIMESPEC "TS_SYSCLK"  = PERIOD "SYSCLK" 100 MHz HIGH 50 % ;

TIMESPEC "TS_CLK_125"  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 100 ;

TIMESPEC "TS_TXOUTCLKBUFG"  = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ;

TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;

NET "*/pcie_clocking_i/sel_lnk_rate_d" TIG ;

PIN "*/trn_reset_n_int_i.CLR" TIG ;

PIN "*/trn_reset_n_i.CLR" TIG ;

PIN "*/pcie_clocking_i/mmcm_adv_i.RST" TIG ;

#TIMESPEC "TS_RESETN" = FROM FFS(*) TO FFS(user_reset_n_i) 8 ns;

###############################################################################

# Physical Constraints

###############################################################################

###############################################################################

# End

###############################################################################

INST "amb/gen_syn.pcie/core/int" AREA_GROUP = "pblock_int";

AREA_GROUP "pblock_int" RANGE=SLICE_X132Y148:SLICE_X135Y151;

INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";

AREA_GROUP "pblock_rx" RANGE=SLICE_X136Y140:SLICE_X143Y159;

INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";

AREA_GROUP "pblock_tx" RANGE=SLICE_X136Y121:SLICE_X143Y139;

INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";

AREA_GROUP "pblock_fifo" RANGE=SLICE_X132Y121:SLICE_X135Y139, SLICE_X126Y121:SLICE_X131Y159;

AREA_GROUP "pblock_fifo" RANGE=DSP48_X6Y50:DSP48_X6Y55;

AREA_GROUP "pblock_fifo" RANGE=RAMB18_X6Y50:RAMB18_X6Y63;

AREA_GROUP "pblock_fifo" RANGE=RAMB36_X6Y25:RAMB36_X6Y31;

INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";

AREA_GROUP "pblock_disp" RANGE=SLICE_X132Y152:SLICE_X135Y159;

INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";

AREA_GROUP "pblock_reg" RANGE=SLICE_X132Y140:SLICE_X135Y147;

INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";

AREA_GROUP "pblock_main" RANGE=SLICE_X144Y161:SLICE_X147Y168;

INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";

AREA_GROUP "pblock_tz" RANGE=SLICE_X132Y161:SLICE_X143Y165;

INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";

AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X158Y162:SLICE_X161Y166;

INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";

AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X116Y166:SLICE_X143Y179;

AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB18_X6Y68:RAMB18_X6Y71;

AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB36_X6Y34:RAMB36_X6Y35;

INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";

AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X108Y200:SLICE_X135Y239;

INST "dio_in" AREA_GROUP = "pblock_dio_in";

AREA_GROUP "pblock_dio_in" RANGE=SLICE_X112Y180:SLICE_X121Y199;

AREA_GROUP "pblock_dio_in" RANGE=RAMB18_X5Y72:RAMB18_X5Y79;

AREA_GROUP "pblock_dio_in" RANGE=RAMB36_X5Y36:RAMB36_X5Y39;

INST "main" AREA_GROUP = "pblock_main_1";

AREA_GROUP "pblock_main_1" RANGE=SLICE_X150Y180:SLICE_X161Y199;

INST "dio_out" AREA_GROUP = "pblock_dio_out";

AREA_GROUP "pblock_dio_out" RANGE=SLICE_X128Y180:SLICE_X135Y199;

AREA_GROUP "pblock_dio_out" RANGE=RAMB18_X6Y72:RAMB18_X6Y79;

AREA_GROUP "pblock_dio_out" RANGE=RAMB36_X6Y36:RAMB36_X6Y39;

INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";

AREA_GROUP "pblock_ep" RANGE=SLICE_X144Y122:SLICE_X161Y158;

AREA_GROUP "pblock_ep" RANGE=RAMB18_X7Y50:RAMB18_X7Y61;

AREA_GROUP "pblock_ep" RANGE=RAMB36_X7Y25:RAMB36_X7Y30;