URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_core/] [sim/] [transcript] - Blame information for rev 2

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# //  ModelSim SE 10.0c Jul 21 2011
# //
# //  Copyright 1991-2011 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# do zz_do/setup_sim.do
# Cre WORK lib
# Compile SRC:
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
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# ** Warning: [4] ../src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd(179): (vcom-1207) An abstract literal and an identifier must have a separator between them.
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# -- Compiling architecture ctrl_freq of ctrl_freq
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package adm2_pkg
# -- Loading package cl_chn_v3_pkg
# -- Compiling package trd_test_ctrl_m1_pkg
# -- Loading package VCOMPONENTS
# -- Loading package cl_test_generate_pkg
# -- Loading package cl_test_check_pkg
# -- Loading package ctrl_freq_pkg
# -- Compiling entity trd_test_ctrl_m1
# -- Compiling architecture trd_test_ctrl_m1 of trd_test_ctrl_m1
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package sp605_lx45t_core_pkg
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Loading package adm2_pkg
# -- Loading package cl_sp605_pkg
# -- Loading package trd_main_v8_pkg
# -- Loading package trd_pio_std_v4_pkg
# -- Loading package cl_chn_v3_pkg
# -- Loading package trd_admdio64_out_v4_pkg
# -- Loading package trd_admdio64_in_v6_pkg
# -- Loading package trd_test_ctrl_m1_pkg
# -- Compiling entity sp605_lx45t_core
# -- Compiling architecture sp605_lx45t_core of sp605_lx45t_core
# Compile TB:
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling package cmd_sim_pkg
# -- Compiling package body cmd_sim_pkg
# -- Loading package cmd_sim_pkg
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package cmd_sim_pkg
# -- Compiling package block_pkg
# -- Compiling package body block_pkg
# -- Loading package block_pkg
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_textio
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package cmd_sim_pkg
# -- Compiling package trd_pkg
# -- Compiling package body trd_pkg
# -- Loading package trd_pkg
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package std_logic_textio
# -- Loading package cmd_sim_pkg
# -- Loading package block_pkg
# -- Loading package trd_pkg
# -- Compiling package test_pkg
# -- Compiling package body test_pkg
# -- Loading package test_pkg
# ** Warning: ../src/testbench/test_pkg.vhd(86): (vcom-1236) Shared variables must be of a protected type.
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package std_logic_textio
# -- Compiling package root_memory_pkg
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(30): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(31): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(34): (vcom-1236) Shared variables must be of a protected type.
# -- Compiling package body root_memory_pkg
# -- Loading package root_memory_pkg
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(86): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(87): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(88): (vcom-1236) Shared variables must be of a protected type.
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package NUMERIC_STD
# -- Compiling package test_interface
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(99): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(100): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(101): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(102): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(103): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(104): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(105): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(106): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(107): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(108): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(109): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(110): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(111): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(112): (vcom-1236) Shared variables must be of a protected type.
# -- Compiling package body test_interface
# -- Loading package test_interface
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package cmd_sim_pkg
# -- Compiling package pci_exp_usrapp_tx_m2_pkg
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package std_logic_textio
# -- Loading package NUMERIC_STD
# -- Loading package test_interface
# -- Loading package root_memory_pkg
# -- Compiling entity pci_exp_usrapp_tx_m2
# -- Compiling architecture rtl of pci_exp_usrapp_tx_m2
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package pci_exp_usrapp_rx_m2_pkg
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package std_logic_textio
# -- Loading package NUMERIC_STD
# -- Loading package root_memory_pkg
# -- Compiling entity pci_exp_usrapp_rx_m2
# -- Compiling architecture rtl of pci_exp_usrapp_rx_m2
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(179): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(180): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(181): (vcom-1236) Shared variables must be of a protected type.
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity pcie_reset_delay_v6
# -- Compiling architecture v6_pcie of pcie_reset_delay_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VCOMPONENTS
# -- Compiling entity pcie_clocking_v6
# -- Compiling architecture v6_pcie of pcie_clocking_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pcie_pipe_misc_v6
# -- Compiling architecture v6_pcie of pcie_pipe_misc_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pcie_pipe_lane_v6
# -- Compiling architecture v6_pcie of pcie_pipe_lane_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pcie_pipe_v6
# -- Compiling architecture v6_pcie of pcie_pipe_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity GTX_DRP_CHANALIGN_FIX_3752_V6
# -- Compiling architecture v6_pcie of GTX_DRP_CHANALIGN_FIX_3752_V6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Compiling entity GTX_RX_VALID_FILTER_V6
# -- Compiling architecture v6_pcie of GTX_RX_VALID_FILTER_V6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity GTX_TX_SYNC_RATE_V6
# -- Compiling architecture v6_pcie of GTX_TX_SYNC_RATE_V6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Compiling entity gtx_wrapper_v6
# -- Compiling architecture v6_pcie of gtx_wrapper_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity pcie_gtx_v6
# -- Compiling architecture v6_pcie of pcie_gtx_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Compiling entity pcie_bram_v6
# -- Compiling architecture v6_pcie of pcie_bram_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity pcie_brams_v6
# -- Compiling architecture v6_pcie of pcie_brams_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity pcie_bram_top_v6
# -- Compiling architecture v6_pcie of pcie_bram_top_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity pcie_upconfig_fix_3451_v6
# -- Compiling architecture v6_pcie of pcie_upconfig_fix_3451_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Compiling entity pcie_2_0_v6_rp
# -- Compiling architecture v6_pcie of pcie_2_0_v6_rp
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package VCOMPONENTS
# -- Compiling entity pcie_2_0_rport_v6
# -- Compiling architecture v6_pcie of pcie_2_0_rport_v6
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package NUMERIC_STD
# -- Loading package test_interface
# -- Compiling entity pci_exp_usrapp_cfg
# -- Compiling architecture rtl of pci_exp_usrapp_cfg
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pci_exp_usrapp_pl
# -- Compiling architecture rtl of pci_exp_usrapp_pl
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package cmd_sim_pkg
# -- Compiling package xilinx_pcie_rport_m2_pkg
# -- Loading package pci_exp_usrapp_tx_m2_pkg
# -- Loading package pci_exp_usrapp_rx_m2_pkg
# -- Compiling entity xilinx_pcie_rport_m2
# -- Compiling architecture rtl of xilinx_pcie_rport_m2
# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package cmd_sim_pkg
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package block_pkg
# -- Loading package sp605_lx45t_core_pkg
# -- Loading package xilinx_pcie_rport_m2_pkg
# -- Loading package trd_pkg
# -- Loading package test_pkg
# -- Compiling entity stend_ambpex5_core_m2
# -- Compiling architecture stend_ambpex5_core_m2 of stend_ambpex5_core_m2
# vsim -t ps -novopt work.stend_ambpex5_core_m2
# Loading std.standard
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.stend_ambpex5_core_m2(stend_ambpex5_core_m2)
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_textio(body)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cmd_sim_pkg(body)
# Loading ieee.std_logic_arith(body)
# Loading work.cmd_sim_pkg(body)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.block_pkg(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.block_pkg(body)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.sp605_lx45t_core_pkg
# Loading work.sp605_lx45t_core_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.xilinx_pcie_rport_m2_pkg
# Loading work.xilinx_pcie_rport_m2_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.test_pkg(body)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_pkg(body)
# Loading work.trd_pkg(body)
# Loading work.test_pkg(body)
# Loading work.stend_ambpex5_core_m2(stend_ambpex5_core_m2)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.sp605_lx45t_core(sp605_lx45t_core)
# Loading unisim.vcomponents
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.adm2_pkg
# Loading work.adm2_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_sp605_pkg
# Loading work.cl_sp605_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_main_v8_pkg
# Loading work.trd_main_v8_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_pio_std_v4_pkg
# Loading work.trd_pio_std_v4_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_admdio64_out_v4_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_chn_v3_pkg
# Loading work.cl_chn_v3_pkg
# Loading work.trd_admdio64_out_v4_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_admdio64_in_v6_pkg
# Loading work.trd_admdio64_in_v6_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_test_ctrl_m1_pkg
# Loading work.trd_test_ctrl_m1_pkg
# Loading work.sp605_lx45t_core(sp605_lx45t_core)
# Loading unisim.obuf_s_16(obuf_s_16_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_sp605(cl_sp605)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pb_adm_ctrl_m2_pkg
# Loading work.pb_adm_ctrl_m2_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_blink_pkg
# Loading work.ctrl_blink_pkg
# Loading work.cl_sp605(cl_sp605)
# Loading unisim.bufg(bufg_v)
# Loading unisim.ibufds(ibufds_v)
# Loading ieee.vital_timing(body)
# Loading unisim.ibuf(ibuf_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_core64_m7(pcie_core64_m7)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_type_pkg
# Loading work.core64_type_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_core64_m6_pkg
# Loading work.pcie_core64_m6_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_pb_transaction_pkg
# Loading work.core64_pb_transaction_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.block_pe_main_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.host_pkg
# Loading work.host_pkg
# Loading work.block_pe_main_pkg
# Loading work.pcie_core64_m7(pcie_core64_m7)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_core64_m6(pcie_core64_m6)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_rx_engine_m4_pkg
# Loading work.core64_rx_engine_m4_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_tx_engine_m4_pkg
# Loading work.core64_tx_engine_m4_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_reg_access_pkg
# Loading work.core64_reg_access_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_pb_disp_pkg
# Loading work.core64_pb_disp_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.block_pe_fifo_ext_pkg
# Loading work.block_pe_fifo_ext_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_interrupt_pkg
# Loading work.core64_interrupt_pkg
# Loading work.pcie_core64_m6(pcie_core64_m6)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_s6pcie_m2(rtl)
# Loading ieee.numeric_bit(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading work.cl_s6pcie_m2(rtl)
# Loading unisim.bufio2(bufio2_v)
# Loading ieee.std_logic_signed(body)
# Loading unisim.pll_base(pll_base_v)
# Loading ieee.numeric_std(body)
# Loading unisim.pll_adv(pll_adv_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_bram_top_s6(rtl)
# Loading work.pcie_bram_top_s6(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_brams_s6(rtl)
# Loading work.pcie_brams_s6(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_bram_s6(rtl)
# Loading work.pcie_bram_s6(rtl)
# Loading unisim.ramb16bwer(ramb16bwer_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtpa1_dual_wrapper(rtl)
# Loading work.gtpa1_dual_wrapper(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtpa1_dual_wrapper_tile(rtl)
# Loading work.gtpa1_dual_wrapper_tile(rtl)
# Loading unisim.gtpa1_dual(gtpa1_dual_v)
# Loading secureip.GTPA1_DUAL_WRAP
# Loading secureip.B_GTPA1_DUAL
# Loading unisim.pcie_a1(pcie_a1_v)
# Loading secureip.PCIE_A1_WRAP
# Loading secureip.B_PCIE_A1
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_rx_engine_m4(core64_rx_engine_m4)
# Loading work.core64_rx_engine_m4(core64_rx_engine_m4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_fifo64x37st(ctrl_fifo64x37st_a)
# Loading work.ctrl_fifo64x37st(ctrl_fifo64x37st_a)
# Loading xilinxcorelib.fifo_generator_v8_1(behavioral)
# Loading xilinxcorelib.fifo_generator_v8_1_conv(behavioral)
# Loading xilinxcorelib.fifo_generator_v8_1_bhv_ss(behavioral)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_tx_engine_m4(core64_tx_engine_m4)
# Loading work.core64_tx_engine_m4(core64_tx_engine_m4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_fifo64x34fw(ctrl_fifo64x34fw_a)
# Loading work.ctrl_fifo64x34fw(ctrl_fifo64x34fw_a)
# Loading xilinxcorelib.fifo_generator_v8_1_bhv_preload0(behavioral)
# Loading unisim.srlc32e(srlc32e_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_reg_access(core64_reg_access)
# Loading work.core64_reg_access(core64_reg_access)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_pb_disp(core64_pb_disp)
# Loading work.core64_pb_disp(core64_pb_disp)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.block_pe_fifo_ext(block_pe_fifo_ext)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_dma_ext_cmd_pkg
# Loading work.ctrl_dma_ext_cmd_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ext_descriptor_pkg
# Loading work.ctrl_ext_descriptor_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ext_ram_pkg
# Loading work.ctrl_ext_ram_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_main_pkg
# Loading work.ctrl_main_pkg
# Loading work.block_pe_fifo_ext(block_pe_fifo_ext)
# Loading unisim.ramb16_s36_s36(ramb16_s36_s36_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_main(ctrl_main)
# Loading work.ctrl_main(ctrl_main)
# Loading unisim.srl16(srl16_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_dma_ext_cmd(ctrl_dma_ext_cmd)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_dma_adr_pkg
# Loading work.ctrl_dma_adr_pkg
# Loading work.ctrl_dma_ext_cmd(ctrl_dma_ext_cmd)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_dma_adr(ctrl_dma_adr)
# Loading work.ctrl_dma_adr(ctrl_dma_adr)
# Loading unisim.ram16x1d(ram16x1d_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ext_descriptor(ctrl_ext_descriptor)
# Loading work.ctrl_ext_descriptor(ctrl_ext_descriptor)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ext_ram(ctrl_ext_ram)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram_cmd_pkg
# Loading work.ctrl_ram_cmd_pkg
# Loading work.ctrl_ext_ram(ctrl_ext_ram)
# Loading unisim.ramb16_s9_s9(ramb16_s9_s9_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram_cmd(ctrl_ram_cmd)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram_cmd_pb_pkg
# Loading work.ctrl_ram_cmd_pb_pkg
# Loading work.ctrl_ram_cmd(ctrl_ram_cmd)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram_cmd_pb(ctrl_ram_cmd_pb)
# Loading work.ctrl_ram_cmd_pb(ctrl_ram_cmd_pb)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_interrupt(core64_interrupt)
# Loading work.core64_interrupt(core64_interrupt)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.core64_pb_transaction(core64_pb_transaction)
# Loading work.core64_pb_transaction(core64_pb_transaction)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.block_pe_main(block_pe_main)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram16_v1_pkg
# Loading work.ctrl_ram16_v1_pkg
# Loading work.block_pe_main(block_pe_main)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_ram16_v1(ctrl_ram16_v1)
# Loading work.ctrl_ram16_v1(ctrl_ram16_v1)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_blink(ctrl_blink)
# Loading work.ctrl_blink(ctrl_blink)
# Loading unisim.fd(fd_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pb_adm_ctrl_m2(pb_adm_ctrl_m2)
# Loading work.pb_adm_ctrl_m2(pb_adm_ctrl_m2)
# Loading unisim.ramb16_s18(ramb16_s18_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_adsp_v2_decode_data_cs(ctrl_adsp_v2_decode_data_cs)
# Loading work.ctrl_adsp_v2_decode_data_cs(ctrl_adsp_v2_decode_data_cs)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_adsp_v2_decode_data_we(ctrl_adsp_v2_decode_data_we)
# Loading work.ctrl_adsp_v2_decode_data_we(ctrl_adsp_v2_decode_data_we)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_adsp_v2_decode_ram_cs(ctrl_adsp_v2_decode_ram_cs)
# Loading work.ctrl_adsp_v2_decode_ram_cs(ctrl_adsp_v2_decode_ram_cs)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_adsp_v2_decode_cmd_adr_cs(ctrl_adsp_v2_decode_cmd_adr_cs)
# Loading work.ctrl_adsp_v2_decode_cmd_adr_cs(ctrl_adsp_v2_decode_cmd_adr_cs)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_mux8x48(ctrl_mux8x48_a)
# Loading xilinxcorelib.prims_constants_v6_0
# Loading xilinxcorelib.prims_utils_v6_0(body)
# Loading xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.ctrl_mux8x48(ctrl_mux8x48_a)
# Loading xilinxcorelib.c_mux_bus_v6_0(behavioral)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_mux16x16(ctrl_mux16x16_a)
# Loading work.ctrl_mux16x16(ctrl_mux16x16_a)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_mux8x16r(ctrl_mux8x16r_a)
# Loading work.ctrl_mux8x16r(ctrl_mux8x16r_a)
# Loading xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_main_v8(trd_main_v8)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_start_v2_pkg
# Loading work.ctrl_start_v2_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test0_v4_pkg
# Loading work.cl_test0_v4_pkg
# Loading work.trd_main_v8(trd_main_v8)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test0_v4(cl_test0_v4)
# Loading work.cl_test0_v4(cl_test0_v4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_start_v2(ctrl_start_v2)
# Loading work.ctrl_start_v2(ctrl_start_v2)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_thdac(ctrl_thdac)
# Loading work.ctrl_thdac(ctrl_thdac)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_admdio64_in_v6(trd_admdio64_in_v6)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_fifo1024x65_v5_pkg
# Loading work.cl_fifo1024x65_v5_pkg
# Loading work.trd_admdio64_in_v6(trd_admdio64_in_v6)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_buft16(ctrl_buft16)
# Loading work.ctrl_buft16(ctrl_buft16)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_buft64(ctrl_buft64)
# Loading work.ctrl_buft64(ctrl_buft64)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_chn_v3(cl_chn_v3)
# Loading work.cl_chn_v3(cl_chn_v3)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_fifo1024x65_v5(cl_fifo1024x65_v5)
# Loading work.cl_fifo1024x65_v5(cl_fifo1024x65_v5)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_fifo1024x65_v5(ctrl_fifo1024x65_v5_a)
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.ctrl_fifo1024x65_v5(ctrl_fifo1024x65_v5_a)
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_fifo_control_v2(cl_fifo_control_v2)
# Loading work.cl_fifo_control_v2(cl_fifo_control_v2)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_admdio64_out_v4(trd_admdio64_out_v4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_chn_v4_pkg
# Loading work.cl_chn_v4_pkg
# Loading work.trd_admdio64_out_v4(trd_admdio64_out_v4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_chn_v4(cl_chn_v4)
# Loading work.cl_chn_v4(cl_chn_v4)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.trd_test_ctrl_m1(trd_test_ctrl_m1)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test_generate_pkg
# Loading work.cl_test_generate_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test_check_pkg
# Loading work.cl_test_check_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_freq_pkg
# Loading work.ctrl_freq_pkg
# Loading work.trd_test_ctrl_m1(trd_test_ctrl_m1)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test_generate(cl_test_generate)
# Loading work.cl_test_generate(cl_test_generate)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.cl_test_check(cl_test_check)
# Loading work.cl_test_check(cl_test_check)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_freq(ctrl_freq)
# Loading work.ctrl_freq(ctrl_freq)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.ctrl_multiplier_v1_0(ctrl_multiplier_v1_0_a)
# Loading xilinxcorelib.prims_constants_v9_0
# Loading xilinxcorelib.prims_utils_v9_0(body)
# Loading xilinxcorelib.pkg_baseblox_v9_0(body)
# Loading xilinxcorelib.pkg_mult_gen_v9_0(body)
# Loading work.ctrl_multiplier_v1_0(ctrl_multiplier_v1_0_a)
# Loading xilinxcorelib.mult_gen_v9_0(behavioral)
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr0/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr1/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr2/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.xilinx_pcie_rport_m2(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_tx_m2_pkg
# Loading work.pci_exp_usrapp_tx_m2_pkg
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_rx_m2_pkg
# Loading work.pci_exp_usrapp_rx_m2_pkg
# Loading work.xilinx_pcie_rport_m2(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_2_0_rport_v6(v6_pcie)
# Loading work.pcie_2_0_rport_v6(v6_pcie)
# Loading unisim.fdcp(fdcp_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_reset_delay_v6(v6_pcie)
# Loading work.pcie_reset_delay_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_clocking_v6(v6_pcie)
# Loading work.pcie_clocking_v6(v6_pcie)
# Loading unisim.mmcm_adv(mmcm_adv_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_2_0_v6_rp(v6_pcie)
# Loading work.pcie_2_0_v6_rp(v6_pcie)
# Loading unisim.pcie_2_0(pcie_2_0_v)
# Loading secureip.PCIE_2_0_WRAP
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_pipe_v6(v6_pcie)
# Loading work.pcie_pipe_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_pipe_misc_v6(v6_pcie)
# Loading work.pcie_pipe_misc_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_pipe_lane_v6(v6_pcie)
# Loading work.pcie_pipe_lane_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_gtx_v6(v6_pcie)
# Loading work.pcie_gtx_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtx_wrapper_v6(v6_pcie)
# Loading work.gtx_wrapper_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtx_drp_chanalign_fix_3752_v6(v6_pcie)
# Loading work.gtx_drp_chanalign_fix_3752_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtx_rx_valid_filter_v6(v6_pcie)
# Loading work.gtx_rx_valid_filter_v6(v6_pcie)
# Loading unisim.srl16e(srl16e_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.gtx_tx_sync_rate_v6(v6_pcie)
# Loading work.gtx_tx_sync_rate_v6(v6_pcie)
# Loading unisim.gtxe1(gtxe1_v)
# Loading secureip.GTXE1_WRAP
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_bram_top_v6(v6_pcie)
# Loading work.pcie_bram_top_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_brams_v6(v6_pcie)
# Loading work.pcie_brams_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_bram_v6(v6_pcie)
# Loading work.pcie_bram_v6(v6_pcie)
# Loading unisim.ramb36(ramb36_v)
# Loading unisim.aramb36_internal(aramb36_internal_v)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pcie_upconfig_fix_3451_v6(v6_pcie)
# Loading work.pcie_upconfig_fix_3451_v6(v6_pcie)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_cfg(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.test_interface(body)
# Loading work.test_interface(body)
# Loading work.pci_exp_usrapp_cfg(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_rx_m2(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.root_memory_pkg(body)
# Loading work.root_memory_pkg(body)
# Loading work.pci_exp_usrapp_rx_m2(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_tx_m2(rtl)
# Loading work.pci_exp_usrapp_tx_m2(rtl)
# Refreshing D:\TMP\08\SVN\sp605_lx45t_core\sim\work.pci_exp_usrapp_pl(rtl)
# Loading work.pci_exp_usrapp_pl(rtl)
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(5 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo0_reg/U0/DATA_COUNT(5 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo1_cmpl/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(5 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo1_cmpl/U0/DATA_COUNT(5 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/gen_ss/fgss/VALID, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/valid_fifo_out.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/gen_ss/fgss/UNDERFLOW, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/underflow_fifo_out.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(6 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/DATA_COUNT(6 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/trn_tx.trn_td(63 downto 32), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/trn_tx.trn_td(63 downto 32).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/trn_tx.trn_trem_n(7 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/trn_tx.trn_trem_n(7 downto 0).
# ** Warning: (vsim-8683) Uninitialized out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/main/pb_reset has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_adr(15 downto 7), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_adr(15 downto 7).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(15)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(15)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(14)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(14)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(13)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(13)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(12)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(12)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(11)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(11)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(10)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(10)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(9)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(9)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(8)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(8)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(15)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(15)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(14)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(14)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(13)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(13)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(12)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(12)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(11)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(11)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(10)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(10)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(9)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(9)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(8)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(8)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).adr(9 downto 0).
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/dio_out/x_fifo/ctrl_fifo/U0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/dio_in/x_fifo/ctrl_fifo/U0
# [ 1000 ns ] : Init start
# [ 15923.246 ns ] : Transaction Reset is De-asserted
# [ 25603.246 ns ] : Transaction Link is Up
# [ 25603.246 ns ] : PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN..
#             BAR 0 = 0x10000000 RANGE = 0xFFE00000 MEM32 MAPPED
#             BAR 1 = 0x20000000 RANGE = 0xFFE00000 MEM32 MAPPED
#             BAR 2 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 3 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 4 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 5 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 6 = 0x00000000 RANGE = 0x00000000 DISABLED
# [ 25603.246 ns ] : Setting Core Configuration Space...
# [ 73651.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 75299.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 76595.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 76947.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 78227.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 78595.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 79891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 80243.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 81523.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 81891.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 83187.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 83539.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 84819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 85187.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 86483.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 86835.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 88115.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 89779.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 107635.146 ns ] : BUS Master Enable
# [ 107635.146 ns ] : Reading Config space
#   Addr: [0x001]
#   Cfg Addr [0x001] -> Data [0x00100000]
# [ 107795.146 ns ] : Writing Config space
#   Addr: [0x001] -> Data [0x00000007]
# [ 107955.146 ns ] : Reading Config space
#   Addr: [0x001]
#   Cfg Addr [0x001] -> Data [0x00100007]
# [ 113083.146 ns ] : Init complete
# [ 186003.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186067.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186131.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186195.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186259.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186323.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186387.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186451.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 197971.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 198083.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 198147.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 198211.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 206227.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 206339.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 206403.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 206467.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 206531.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214483.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214643.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214707.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214803.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214899.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214931.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215107.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215155.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215331.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215507.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215555.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215731.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215907.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 215955.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 223155.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 223379.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 223555.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 223603.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 223667.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 223731.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 231379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 231491.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 251555.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 257619.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 258227.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 258803.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 259411.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 259987.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 260019.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 260131.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 260755.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 261331.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 261939.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 262515.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 263123.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 263795.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264403.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264979.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 265587.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 266163.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 266771.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 267347.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 267955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 268531.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 268563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 268675.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 269235.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 269811.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 270483.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 271059.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 271667.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 272307.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 272915.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 273491.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 274099.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 274675.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 275283.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 275859.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 276499.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 277171.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 277203.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 277315.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 277875.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 277875.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 278451.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 279059.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 279635.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 280243.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 280883.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 281555.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 282131.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 282803.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 283379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 283987.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 284563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 285171.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 285747.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 286451.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 286483.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 286595.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 287123.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 287731.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 288307.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 288947.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 289523.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 290195.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 290771.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 291379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 291955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 292563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 293203.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 293811.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 294387.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 295059.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 295091.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 295699.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 295731.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296339.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296371.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296435.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296467.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296499.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 305203.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 305427.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 305603.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 305651.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 313459.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 313683.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 313859.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 313907.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 314083.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 314259.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 314435.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 314611.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 314659.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 321715.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 321827.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 322611.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 323219.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 323795.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 324403.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 325075.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 325747.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 326355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 326963.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 327539.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 327571.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 328179.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 328243.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 328851.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 329459.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 330035.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 330643.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 331219.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 331891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 332467.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 333075.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 333651.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 333683.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 333795.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 334355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 334995.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 335603.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 336179.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 336787.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 337427.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 338035.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 338611.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 339219.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 339251.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 339859.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 339891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 340499.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 341107.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 341715.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 342387.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 342995.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 343635.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 344243.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 344819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 353587.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 353699.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 354451.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 355027.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 355635.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 356211.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 356819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 357459.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 358067.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 358707.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 359315.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 359891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 360531.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 361107.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 361715.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 362291.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 362323.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 362435.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 362995.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 362995.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 363571.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 364179.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 364755.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 365363.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 366003.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 366739.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 367315.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 367923.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 368499.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 369107.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 369683.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 370291.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 378899.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 379011.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 387123.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 387235.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 387299.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 395379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 395491.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 395555.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 403955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 404563.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 412147.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 412755.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 420403.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 421011.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 428627.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 429235.146 ns ] : PROC_PARSE_FRAME on Transmit
# ** Failure: RX Simulation Timeout.
#    Time: 505619146 ps  Iteration: 12  Process: /stend_ambpex5_core_m2/rp/RX_APP/#MERGED#line__998,864 File: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd
# Break in Architecture rtl at ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd line 1012
# Simulation Breakpoint: Break in Architecture rtl at ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd line 1012
# MACRO ./zz_do/setup_sim.do PAUSED at line 137

Line No.	Rev	Author	Line
1	2	dsmv	`# // ModelSim SE 10.0c Jul 21 2011`
2			`# //`
3			`# // Copyright 1991-2011 Mentor Graphics Corporation`
4			`# // All Rights Reserved.`
5			`# //`
6			`# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION`
7			`# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS`
8			`# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.`
9			`# //`
10			`# do zz_do/setup_sim.do`
11			`# Cre WORK lib`
12			`# Compile SRC:`
13			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
14			`# -- Loading package STANDARD`
15			`# -- Loading package TEXTIO`
16			`# -- Loading package std_logic_1164`
17			`# -- Compiling package adm2_pkg`
18			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
19			`# -- Loading package STANDARD`
20			`# -- Loading package TEXTIO`
21			`# -- Loading package std_logic_1164`
22			`# -- Loading package std_logic_arith`
23			`# -- Loading package VITAL_Timing`
24			`# -- Loading package VCOMPONENTS`
25			`# -- Compiling entity ctrl_adsp_v2_decode_data_cs`
26			`# -- Compiling architecture ctrl_adsp_v2_decode_data_cs of ctrl_adsp_v2_decode_data_cs`
27			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
28			`# -- Loading package STANDARD`
29			`# -- Loading package TEXTIO`
30			`# -- Loading package std_logic_1164`
31			`# -- Loading package std_logic_arith`
32			`# -- Loading package VITAL_Timing`
33			`# -- Loading package VCOMPONENTS`
34			`# -- Compiling entity ctrl_adsp_v2_decode_data_we`
35			`# -- Compiling architecture ctrl_adsp_v2_decode_data_we of ctrl_adsp_v2_decode_data_we`
36			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
37			`# -- Loading package STANDARD`
38			`# -- Loading package TEXTIO`
39			`# -- Loading package std_logic_1164`
40			`# -- Loading package std_logic_arith`
41			`# -- Loading package VITAL_Timing`
42			`# -- Loading package VCOMPONENTS`
43			`# -- Compiling entity ctrl_adsp_v2_decode_ram_cs`
44			`# -- Compiling architecture ctrl_adsp_v2_decode_ram_cs of ctrl_adsp_v2_decode_ram_cs`
45			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
46			`# -- Loading package STANDARD`
47			`# -- Loading package TEXTIO`
48			`# -- Loading package std_logic_1164`
49			`# -- Loading package std_logic_arith`
50			`# -- Loading package VITAL_Timing`
51			`# -- Loading package VCOMPONENTS`
52			`# -- Compiling entity ctrl_adsp_v2_decode_cmd_adr_cs`
53			`# -- Compiling architecture ctrl_adsp_v2_decode_cmd_adr_cs of ctrl_adsp_v2_decode_cmd_adr_cs`
54			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
55			`# -- Loading package STANDARD`
56			`# -- Loading package TEXTIO`
57			`# -- Loading package std_logic_1164`
58			`# -- Compiling entity ctrl_mux8x48`
59			`# -- Compiling architecture ctrl_mux8x48_a of ctrl_mux8x48`
60			`# -- Loading package prims_utils_v6_0`
61			`# -- Loading package NUMERIC_STD`
62			`# -- Loading package prims_constants_v6_0`
63			`# -- Loading package c_reg_fd_v6_0_comp`
64			`# -- Loading entity C_MUX_BUS_V6_0`
65			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
66			`# -- Loading package STANDARD`
67			`# -- Loading package TEXTIO`
68			`# -- Loading package std_logic_1164`
69			`# -- Compiling entity ctrl_mux16x16`
70			`# -- Compiling architecture ctrl_mux16x16_a of ctrl_mux16x16`
71			`# -- Loading package prims_utils_v6_0`
72			`# -- Loading package NUMERIC_STD`
73			`# -- Loading package prims_constants_v6_0`
74			`# -- Loading package c_reg_fd_v6_0_comp`
75			`# -- Loading entity C_MUX_BUS_V6_0`
76			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
77			`# -- Loading package STANDARD`
78			`# -- Loading package TEXTIO`
79			`# -- Loading package std_logic_1164`
80			`# -- Compiling entity ctrl_mux8x16r`
81			`# -- Compiling architecture ctrl_mux8x16r_a of ctrl_mux8x16r`
82			`# -- Loading package prims_utils_v6_0`
83			`# -- Loading package NUMERIC_STD`
84			`# -- Loading package prims_constants_v6_0`
85			`# -- Loading package c_reg_fd_v6_0_comp`
86			`# -- Loading entity C_MUX_BUS_V6_0`
87			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
88			`# -- Loading package STANDARD`
89			`# -- Loading package TEXTIO`
90			`# -- Loading package std_logic_1164`
91			`# -- Loading package std_logic_arith`
92			`# -- Loading package adm2_pkg`
93			`# -- Compiling package pb_adm_ctrl_m2_pkg`
94			`# -- Loading package VITAL_Timing`
95			`# -- Loading package VCOMPONENTS`
96			`# -- Compiling entity pb_adm_ctrl_m2`
97			`# -- Compiling architecture pb_adm_ctrl_m2 of pb_adm_ctrl_m2`
98			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
99			`# -- Loading package STANDARD`
100			`# -- Loading package TEXTIO`
101			`# -- Loading package std_logic_1164`
102			`# -- Compiling package ctrl_blink_pkg`
103			`# -- Loading package std_logic_arith`
104			`# -- Loading package STD_LOGIC_UNSIGNED`
105			`# -- Loading package VCOMPONENTS`
106			`# -- Compiling entity ctrl_blink`
107			`# -- Compiling architecture ctrl_blink of ctrl_blink`
108			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
109			`# -- Loading package STANDARD`
110			`# -- Loading package TEXTIO`
111			`# -- Loading package std_logic_1164`
112			`# -- Compiling package core64_type_pkg`
113			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
114			`# -- Loading package STANDARD`
115			`# -- Loading package TEXTIO`
116			`# -- Loading package std_logic_1164`
117			`# -- Compiling entity ctrl_fifo64x37st`
118			`# -- Compiling architecture ctrl_fifo64x37st_a of ctrl_fifo64x37st`
119			`# -- Loading package std_logic_arith`
120			`# -- Loading package STD_LOGIC_UNSIGNED`
121			`# -- Loading entity fifo_generator_v8_1_bhv_as`
122			`# -- Loading entity fifo_generator_v8_1_bhv_ss`
123			`# -- Loading entity fifo_generator_v8_1_conv`
124			`# -- Loading entity fifo_generator_v8_1`
125			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
126			`# -- Loading package STANDARD`
127			`# -- Loading package TEXTIO`
128			`# -- Loading package std_logic_1164`
129			`# -- Loading package core64_type_pkg`
130			`# -- Compiling package core64_rx_engine_m4_pkg`
131			`# -- Loading package std_logic_arith`
132			`# -- Loading package STD_LOGIC_UNSIGNED`
133			`# -- Compiling entity core64_rx_engine_m4`
134			`# -- Compiling architecture core64_rx_engine_m4 of core64_rx_engine_m4`
135			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
136			`# -- Loading package STANDARD`
137			`# -- Loading package TEXTIO`
138			`# -- Loading package std_logic_1164`
139			`# -- Compiling entity ctrl_fifo64x34fw`
140			`# -- Compiling architecture ctrl_fifo64x34fw_a of ctrl_fifo64x34fw`
141			`# -- Loading package std_logic_arith`
142			`# -- Loading package STD_LOGIC_UNSIGNED`
143			`# -- Loading entity fifo_generator_v8_1_bhv_as`
144			`# -- Loading entity fifo_generator_v8_1_bhv_ss`
145			`# -- Loading entity fifo_generator_v8_1_conv`
146			`# -- Loading entity fifo_generator_v8_1`
147			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
148			`# -- Loading package STANDARD`
149			`# -- Loading package TEXTIO`
150			`# -- Loading package std_logic_1164`
151			`# -- Loading package core64_type_pkg`
152			`# -- Compiling package core64_tx_engine_m4_pkg`
153			`# -- Loading package std_logic_arith`
154			`# -- Loading package STD_LOGIC_UNSIGNED`
155			`# -- Loading package VCOMPONENTS`
156			`# -- Compiling entity core64_tx_engine_m4`
157			`# -- Compiling architecture core64_tx_engine_m4 of core64_tx_engine_m4`
158			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
159			`# -- Loading package STANDARD`
160			`# -- Loading package TEXTIO`
161			`# -- Loading package std_logic_1164`
162			`# -- Loading package core64_type_pkg`
163			`# -- Compiling package core64_reg_access_pkg`
164			`# -- Compiling entity core64_reg_access`
165			`# -- Compiling architecture core64_reg_access of core64_reg_access`
166			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
167			`# -- Loading package STANDARD`
168			`# -- Loading package TEXTIO`
169			`# -- Loading package std_logic_1164`
170			`# -- Loading package core64_type_pkg`
171			`# -- Compiling package core64_pb_disp_pkg`
172			`# -- Compiling entity core64_pb_disp`
173			`# -- Compiling architecture core64_pb_disp of core64_pb_disp`
174			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
175			`# -- Loading package STANDARD`
176			`# -- Loading package TEXTIO`
177			`# -- Loading package std_logic_1164`
178			`# -- Compiling package core64_interrupt_pkg`
179			`# -- Loading package std_logic_arith`
180			`# -- Loading package STD_LOGIC_UNSIGNED`
181			`# -- Compiling entity core64_interrupt`
182			`# -- Compiling architecture core64_interrupt of core64_interrupt`
183			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
184			`# -- Loading package STANDARD`
185			`# -- Loading package TEXTIO`
186			`# -- Loading package std_logic_1164`
187			`# -- Loading package VCOMPONENTS`
188			`# -- Compiling package ctrl_dma_adr_pkg`
189			`# -- Loading package std_logic_arith`
190			`# -- Loading package STD_LOGIC_UNSIGNED`
191			`# -- Compiling entity ctrl_dma_adr`
192			`# -- Compiling architecture ctrl_dma_adr of ctrl_dma_adr`
193			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
194			`# -- Loading package STANDARD`
195			`# -- Loading package TEXTIO`
196			`# -- Loading package std_logic_1164`
197			`# -- Loading package core64_type_pkg`
198			`# -- Compiling package ctrl_dma_ext_cmd_pkg`
199			`# -- Loading package std_logic_arith`
200			`# -- Loading package STD_LOGIC_UNSIGNED`
201			`# -- Loading package VCOMPONENTS`
202			`# -- Loading package ctrl_dma_adr_pkg`
203			`# -- Compiling entity ctrl_dma_ext_cmd`
204			`# -- Compiling architecture ctrl_dma_ext_cmd of ctrl_dma_ext_cmd`
205			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
206			`# -- Loading package STANDARD`
207			`# -- Loading package TEXTIO`
208			`# -- Loading package std_logic_1164`
209			`# -- Compiling package ctrl_ext_descriptor_pkg`
210			`# -- Loading package std_logic_arith`
211			`# -- Loading package STD_LOGIC_UNSIGNED`
212			`# -- Loading package VCOMPONENTS`
213			`# -- Compiling entity ctrl_ext_descriptor`
214			`# -- Compiling architecture ctrl_ext_descriptor of ctrl_ext_descriptor`
215			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
216			`# -- Loading package STANDARD`
217			`# -- Loading package TEXTIO`
218			`# -- Loading package std_logic_1164`
219			`# -- Compiling package ctrl_ram_cmd_pb_pkg`
220			`# -- Loading package std_logic_arith`
221			`# -- Loading package STD_LOGIC_UNSIGNED`
222			`# -- Compiling entity ctrl_ram_cmd_pb`
223			`# -- Compiling architecture ctrl_ram_cmd_pb of ctrl_ram_cmd_pb`
224			`# ** Warning: [4] ../src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd(179): (vcom-1207) An abstract literal and an identifier must have a separator between them.`
225			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
226			`# -- Loading package STANDARD`
227			`# -- Loading package TEXTIO`
228			`# -- Loading package std_logic_1164`
229			`# -- Compiling package ctrl_ram_cmd_pkg`
230			`# -- Loading package std_logic_arith`
231			`# -- Loading package STD_LOGIC_UNSIGNED`
232			`# -- Loading package VCOMPONENTS`
233			`# -- Loading package ctrl_ram_cmd_pb_pkg`
234			`# -- Compiling entity ctrl_ram_cmd`
235			`# -- Compiling architecture ctrl_ram_cmd of ctrl_ram_cmd`
236			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
237			`# -- Loading package STANDARD`
238			`# -- Loading package TEXTIO`
239			`# -- Loading package std_logic_1164`
240			`# -- Loading package core64_type_pkg`
241			`# -- Compiling package ctrl_ext_ram_pkg`
242			`# -- Loading package std_logic_arith`
243			`# -- Loading package STD_LOGIC_UNSIGNED`
244			`# -- Loading package VCOMPONENTS`
245			`# -- Loading package ctrl_ram_cmd_pkg`
246			`# -- Compiling entity ctrl_ext_ram`
247			`# -- Compiling architecture ctrl_ext_ram of ctrl_ext_ram`
248			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
249			`# -- Loading package STANDARD`
250			`# -- Loading package TEXTIO`
251			`# -- Loading package std_logic_1164`
252			`# -- Compiling package ctrl_main_pkg`
253			`# -- Loading package std_logic_arith`
254			`# -- Loading package STD_LOGIC_UNSIGNED`
255			`# -- Loading package VCOMPONENTS`
256			`# -- Compiling entity ctrl_main`
257			`# -- Compiling architecture ctrl_main of ctrl_main`
258			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
259			`# -- Loading package STANDARD`
260			`# -- Loading package TEXTIO`
261			`# -- Loading package std_logic_1164`
262			`# -- Loading package core64_type_pkg`
263			`# -- Compiling package block_pe_fifo_ext_pkg`
264			`# -- Loading package std_logic_arith`
265			`# -- Loading package STD_LOGIC_UNSIGNED`
266			`# -- Loading package ctrl_dma_ext_cmd_pkg`
267			`# -- Loading package ctrl_ext_descriptor_pkg`
268			`# -- Loading package ctrl_ext_ram_pkg`
269			`# -- Loading package ctrl_main_pkg`
270			`# -- Loading package VCOMPONENTS`
271			`# -- Compiling entity block_pe_fifo_ext`
272			`# -- Compiling architecture block_pe_fifo_ext of block_pe_fifo_ext`
273			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
274			`# -- Loading package STANDARD`
275			`# -- Loading package TEXTIO`
276			`# -- Loading package std_logic_1164`
277			`# -- Loading package std_logic_arith`
278			`# -- Loading package STD_LOGIC_UNSIGNED`
279			`# -- Loading package VCOMPONENTS`
280			`# -- Compiling entity pcie_bram_s6`
281			`# -- Compiling architecture rtl of pcie_bram_s6`
282			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
283			`# -- Loading package STANDARD`
284			`# -- Loading package TEXTIO`
285			`# -- Loading package std_logic_1164`
286			`# -- Loading package std_logic_arith`
287			`# -- Loading package STD_LOGIC_UNSIGNED`
288			`# -- Compiling entity pcie_brams_s6`
289			`# -- Compiling architecture rtl of pcie_brams_s6`
290			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
291			`# -- Loading package STANDARD`
292			`# -- Loading package TEXTIO`
293			`# -- Loading package std_logic_1164`
294			`# -- Loading package std_logic_arith`
295			`# -- Loading package STD_LOGIC_UNSIGNED`
296			`# -- Compiling entity pcie_bram_top_s6`
297			`# -- Compiling architecture rtl of pcie_bram_top_s6`
298			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
299			`# -- Loading package STANDARD`
300			`# -- Loading package TEXTIO`
301			`# -- Loading package std_logic_1164`
302			`# -- Loading package NUMERIC_STD`
303			`# -- Loading package VCOMPONENTS`
304			`# -- Compiling entity GTPA1_DUAL_WRAPPER_TILE`
305			`# -- Compiling architecture RTL of GTPA1_DUAL_WRAPPER_TILE`
306			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
307			`# -- Loading package STANDARD`
308			`# -- Loading package TEXTIO`
309			`# -- Loading package std_logic_1164`
310			`# -- Loading package NUMERIC_STD`
311			`# -- Loading package VCOMPONENTS`
312			`# -- Compiling entity GTPA1_DUAL_WRAPPER`
313			`# -- Compiling architecture RTL of GTPA1_DUAL_WRAPPER`
314			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
315			`# -- Loading package STANDARD`
316			`# -- Loading package TEXTIO`
317			`# -- Loading package std_logic_1164`
318			`# -- Loading package std_logic_arith`
319			`# -- Loading package STD_LOGIC_UNSIGNED`
320			`# -- Loading package NUMERIC_BIT`
321			`# -- Loading package VCOMPONENTS`
322			`# -- Loading package VITAL_Timing`
323			`# -- Loading package VITAL_Primitives`
324			`# -- Loading package VPKG`
325			`# -- Compiling entity cl_s6pcie_m2`
326			`# -- Compiling architecture rtl of cl_s6pcie_m2`
327			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
328			`# -- Loading package STANDARD`
329			`# -- Loading package TEXTIO`
330			`# -- Loading package std_logic_1164`
331			`# -- Loading package core64_type_pkg`
332			`# -- Compiling package pcie_core64_m6_pkg`
333			`# -- Loading package core64_rx_engine_m4_pkg`
334			`# -- Loading package core64_tx_engine_m4_pkg`
335			`# -- Loading package core64_reg_access_pkg`
336			`# -- Loading package core64_pb_disp_pkg`
337			`# -- Loading package block_pe_fifo_ext_pkg`
338			`# -- Loading package core64_interrupt_pkg`
339			`# -- Compiling entity pcie_core64_m6`
340			`# -- Compiling architecture pcie_core64_m6 of pcie_core64_m6`
341			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
342			`# -- Loading package STANDARD`
343			`# -- Loading package TEXTIO`
344			`# -- Loading package std_logic_1164`
345			`# -- Loading package core64_type_pkg`
346			`# -- Compiling package core64_pb_transaction_pkg`
347			`# -- Loading package std_logic_arith`
348			`# -- Loading package STD_LOGIC_UNSIGNED`
349			`# -- Loading package VCOMPONENTS`
350			`# -- Compiling entity core64_pb_transaction`
351			`# -- Compiling architecture core64_pb_transaction of core64_pb_transaction`
352			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
353			`# -- Loading package STANDARD`
354			`# -- Loading package TEXTIO`
355			`# -- Loading package std_logic_1164`
356			`# -- Compiling package host_pkg`
357			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
358			`# -- Loading package STANDARD`
359			`# -- Loading package TEXTIO`
360			`# -- Loading package std_logic_1164`
361			`# -- Loading package host_pkg`
362			`# -- Compiling package ctrl_ram16_v1_pkg`
363			`# -- Loading package VCOMPONENTS`
364			`# -- Compiling entity ctrl_ram16_v1`
365			`# -- Compiling architecture ctrl_ram16_v1 of ctrl_ram16_v1`
366			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
367			`# -- Loading package STANDARD`
368			`# -- Loading package TEXTIO`
369			`# -- Loading package std_logic_1164`
370			`# -- Loading package host_pkg`
371			`# -- Compiling package block_pe_main_pkg`
372			`# -- Loading package ctrl_ram16_v1_pkg`
373			`# -- Loading package VCOMPONENTS`
374			`# -- Compiling entity block_pe_main`
375			`# -- Compiling architecture block_pe_main of block_pe_main`
376			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
377			`# -- Loading package STANDARD`
378			`# -- Loading package TEXTIO`
379			`# -- Loading package std_logic_1164`
380			`# -- Compiling package pcie_core64_m7_pkg`
381			`# -- Loading package core64_type_pkg`
382			`# -- Loading package pcie_core64_m6_pkg`
383			`# -- Loading package core64_pb_transaction_pkg`
384			`# -- Loading package host_pkg`
385			`# -- Loading package block_pe_main_pkg`
386			`# -- Compiling entity pcie_core64_m7`
387			`# -- Compiling architecture pcie_core64_m7 of pcie_core64_m7`
388			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
389			`# -- Loading package STANDARD`
390			`# -- Loading package TEXTIO`
391			`# -- Loading package std_logic_1164`
392			`# -- Loading package adm2_pkg`
393			`# -- Compiling package cl_sp605_pkg`
394			`# -- Loading package std_logic_arith`
395			`# -- Loading package STD_LOGIC_UNSIGNED`
396			`# -- Loading package VCOMPONENTS`
397			`# -- Loading package pb_adm_ctrl_m2_pkg`
398			`# -- Loading package ctrl_blink_pkg`
399			`# -- Compiling entity cl_sp605`
400			`# -- Compiling architecture cl_sp605 of cl_sp605`
401			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
402			`# -- Loading package STANDARD`
403			`# -- Loading package TEXTIO`
404			`# -- Loading package std_logic_1164`
405			`# -- Loading package std_logic_arith`
406			`# -- Loading package STD_LOGIC_UNSIGNED`
407			`# -- Compiling package ctrl_start_v2_pkg`
408			`# -- Compiling entity ctrl_start_v2`
409			`# -- Compiling architecture ctrl_start_v2 of ctrl_start_v2`
410			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
411			`# -- Loading package STANDARD`
412			`# -- Loading package TEXTIO`
413			`# -- Loading package std_logic_1164`
414			`# -- Compiling package cl_test0_v4_pkg`
415			`# -- Compiling entity cl_test0_v4`
416			`# -- Compiling architecture cl_test0_v4 of cl_test0_v4`
417			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
418			`# -- Loading package STANDARD`
419			`# -- Loading package TEXTIO`
420			`# -- Loading package std_logic_1164`
421			`# -- Loading package std_logic_arith`
422			`# -- Loading package STD_LOGIC_UNSIGNED`
423			`# -- Compiling entity ctrl_thdac`
424			`# -- Compiling architecture ctrl_thdac of ctrl_thdac`
425			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
426			`# -- Loading package STANDARD`
427			`# -- Loading package TEXTIO`
428			`# -- Loading package std_logic_1164`
429			`# -- Loading package adm2_pkg`
430			`# -- Compiling package trd_main_v8_pkg`
431			`# -- Loading package std_logic_arith`
432			`# -- Loading package STD_LOGIC_UNSIGNED`
433			`# -- Loading package ctrl_start_v2_pkg`
434			`# -- Loading package cl_test0_v4_pkg`
435			`# -- Compiling entity trd_main_v8`
436			`# -- Compiling architecture trd_main_v8 of trd_main_v8`
437			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
438			`# -- Loading package STANDARD`
439			`# -- Loading package TEXTIO`
440			`# -- Loading package std_logic_1164`
441			`# -- Loading package adm2_pkg`
442			`# -- Compiling package trd_pio_std_v4_pkg`
443			`# -- Loading package std_logic_arith`
444			`# -- Loading package STD_LOGIC_UNSIGNED`
445			`# -- Compiling entity trd_pio_std_v4`
446			`# -- Compiling architecture trd_pio_std_v4 of trd_pio_std_v4`
447			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
448			`# -- Loading package STANDARD`
449			`# -- Loading package TEXTIO`
450			`# -- Loading package std_logic_1164`
451			`# -- Compiling entity ctrl_buft16`
452			`# -- Compiling architecture ctrl_buft16 of ctrl_buft16`
453			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
454			`# -- Loading package STANDARD`
455			`# -- Loading package TEXTIO`
456			`# -- Loading package std_logic_1164`
457			`# -- Compiling entity ctrl_buft64`
458			`# -- Compiling architecture ctrl_buft64 of ctrl_buft64`
459			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
460			`# -- Loading package STANDARD`
461			`# -- Loading package TEXTIO`
462			`# -- Loading package std_logic_1164`
463			`# -- Loading package adm2_pkg`
464			`# -- Compiling package cl_chn_v3_pkg`
465			`# -- Compiling entity cl_chn_v3`
466			`# -- Compiling architecture cl_chn_v3 of cl_chn_v3`
467			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
468			`# -- Loading package STANDARD`
469			`# -- Loading package TEXTIO`
470			`# -- Loading package std_logic_1164`
471			`# -- Loading package adm2_pkg`
472			`# -- Compiling package cl_chn_v4_pkg`
473			`# -- Compiling entity cl_chn_v4`
474			`# -- Compiling architecture cl_chn_v4 of cl_chn_v4`
475			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
476			`# -- Loading package STANDARD`
477			`# -- Loading package TEXTIO`
478			`# -- Loading package std_logic_1164`
479			`# -- Compiling entity cl_fifo_control_v2`
480			`# -- Compiling architecture cl_fifo_control_v2 of cl_fifo_control_v2`
481			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
482			`# -- Loading package STANDARD`
483			`# -- Loading package TEXTIO`
484			`# -- Loading package std_logic_1164`
485			`# -- Loading package adm2_pkg`
486			`# -- Compiling package cl_fifo1024x65_v5_pkg`
487			`# -- Compiling entity cl_fifo1024x65_v5`
488			`# -- Compiling architecture cl_fifo1024x65_v5 of cl_fifo1024x65_v5`
489			`# Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011`
490			`# -- Loading package STANDARD`
491			`# -- Loading package TEXTIO`
492			`# -- Loading package std_logic_1164`
493			`# -- Compiling entity ctrl_fifo1024x65_v5`
494			`# -- Compiling architecture ctrl_fifo1024x65_v5_a of ctrl_fifo1024x65_v5`
495			`# -- Loading package iputils_std_logic_arith`
496			`# -- Loading package iputils_std_logic_unsigned`
497			`# -- Loading package iputils_conv`
498			`# -- Loading package iputils_misc`
499			`# -- Loading entity fifo_generator_v3_3_bhv_as`
500			`# -- Loading entity fifo_generator_v3_3_bhv_ss`

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[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_core/] [sim/] [transcript] - Blame information for rev 2