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##-----------------------------------------------------------------------------
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##
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## (c) Copyright 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
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##
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## This file contains confidential and proprietary information
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## of Xilinx, Inc. and is protected under U.S. and
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## international copyright and other intellectual property
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## laws.
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##
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## DISCLAIMER
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## This disclaimer is not a license and does not grant any
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## rights to the materials distributed herewith. Except as
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## otherwise provided in a valid license issued to you by
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## Xilinx, and to the maximum extent permitted by applicable
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## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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## (2) Xilinx shall not be liable (whether in contract or tort,
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## including negligence, or under any other theory of
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## liability) for any loss or damage of any kind or nature
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## related to, arising under or in connection with these
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## materials, including for any direct, or any indirect,
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## special, incidental, or consequential loss or damage
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## (including loss of data, profits, goodwill, or any type of
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## loss or damage suffered as a result of any action brought
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## by a third party) even if such damage or loss was
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## reasonably foreseeable or Xilinx had been advised of the
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## possibility of the same.
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##
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## CRITICAL APPLICATIONS
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## Xilinx products are not designed or intended to be fail-
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## safe, or for use in any application requiring fail-safe
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## performance, such as life-support or safety devices or
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## systems, Class III medical devices, nuclear facilities,
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## applications related to the deployment of airbags, or any
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## other applications that could lead to death, personal
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## injury, or severe property or environmental damage
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## (individually and collectively, "Critical
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## Applications"). Customer assumes the sole risk and
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## liability of any use of Xilinx products in Critical
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## Applications, subject only to applicable laws and
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## regulations governing limitations on product liability.
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##
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## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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## PART OF THIS FILE AT ALL TIMES.
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##
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##-----------------------------------------------------------------------------
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## Project : Spartan-6 Integrated Block for PCI Express
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## File : xilinx_pcie_1_lane_ep_xc6slx150t-fgg676-2.ucf
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## Description: Example User Constraints File
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##
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## Use this file only with the device listed below. Any other
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## combination is invalid. Do not modify this file except in
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## regions designated for "User" constraints.
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##-----------------------------------------------------------------------------
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###############################################################################
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# Define Device, Package And Speed Grade
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###############################################################################
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#CONFIG PART = xc6slx150t-fgg676-2;
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###############################################################################
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# User Time Names / User Time Groups / Time Specs
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###############################################################################
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###############################################################################
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# User Physical Constraints
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###############################################################################
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###############################################################################
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# Pinout and Related I/O Constraints
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###############################################################################
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#
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# SYS reset (input) signal. The sys_reset_n signal should be
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# obtained from the PCI Express interface if possible. For
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# slot based form factors, a system reset signal is usually
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# present on the connector. For cable based form factors, a
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# system reset signal may not be available. In this case, the
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# system reset signal must be generated locally by some form of
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# supervisory circuit. You may change the IOSTANDARD and LOC
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# to suit your requirements and VCCO voltage banking rules.
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#
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NET sys_reset_n LOC = J7 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;
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# SYS clock 100 or 125 MHz (input) signal. The sys_clk_p and sys_clk_n
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# signals are the PCI Express reference clock. Spartan-6 GTP
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# Transceiver architecture requires the use of dedicated clock
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# resources (FPGA input pins) associated with each GTP Transceiver Tile.
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# To use these pins an IBUFDS primitive (refclk_ibuf) is
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# instantiated in the example design.
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# Please refer to the Spartan-6 GTP Transceiver User Guide
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# for guidelines regarding clock resource selection.
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#
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#NET sys_clk_n LOC = A10;
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#NET sys_clk_p LOC = B10;
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#
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# Transceiver instance placement. This constraint selects the
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# transceiver to be used, which also dictates the pinout for the
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# transmit and receive differential pairs. Please refer to the
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# Spartan-6 GTP Transceiver User Guide for more
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# information.
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#
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# PCIe Lane 0
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INST cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y1;
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NET pci_exp_txp<0> LOC = B6;
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NET pci_exp_txn<0> LOC = A6;
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NET pci_exp_rxp<0> LOC = D7;
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NET pci_exp_rxn<0> LOC = C7;
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NET "gpio_led0" LOC = D17;
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NET "gpio_led1" LOC = AB4;
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NET "gpio_led2" LOC = D21;
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NET "gpio_led3" LOC = W15;
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###############################################################################
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# Physical Constraints
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###############################################################################
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###############################################################################
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# Timing Constraints
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###############################################################################
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#
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# Ignore timing on asynchronous signals.
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#
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NET sys_reset_n TIG;
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#
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# Timing requirements and related constraints.
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#
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#NET sys_clk_c PERIOD = 8ns;
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NET sys_clk_p TNM_NET = GT_REFCLK_OUT;
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NET */ep/gt_refclk_out(0) TNM_NET = GT_REFCLK_OUT;
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TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 8ns HIGH 50 % ;
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###############################################################################
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# End
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###############################################################################
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INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
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AREA_GROUP "pblock_reg" RANGE=SLICE_X20Y89:SLICE_X25Y95;
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INST "amb/gen_syn.pcie/core/int" AREA_GROUP = "pblock_int";
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AREA_GROUP "pblock_int" RANGE=SLICE_X26Y88:SLICE_X29Y95;
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INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
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AREA_GROUP "pblock_tx" RANGE=SLICE_X8Y96:SLICE_X13Y111;
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INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
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AREA_GROUP "pblock_disp" RANGE=SLICE_X20Y80:SLICE_X25Y87;
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INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
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AREA_GROUP "pblock_fifo" RANGE=SLICE_X8Y80:SLICE_X19Y95, SLICE_X0Y64:SLICE_X7Y95;
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AREA_GROUP "pblock_fifo" RANGE=DSP48_X0Y16:DSP48_X0Y23;
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AREA_GROUP "pblock_fifo" RANGE=RAMB16_X1Y40:RAMB16_X1Y46, RAMB16_X0Y32:RAMB16_X0Y46;
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AREA_GROUP "pblock_fifo" RANGE=RAMB8_X1Y40:RAMB8_X1Y47, RAMB8_X0Y32:RAMB8_X0Y47;
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INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
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AREA_GROUP "pblock_ep" RANGE=SLICE_X0Y112:SLICE_X3Y125;
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AREA_GROUP "pblock_ep" RANGE=RAMB16_X0Y48:RAMB16_X0Y62;
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AREA_GROUP "pblock_ep" RANGE=RAMB8_X0Y48:RAMB8_X0Y63;
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INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
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AREA_GROUP "pblock_main" RANGE=SLICE_X26Y80:SLICE_X29Y86;
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INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
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AREA_GROUP "pblock_tz" RANGE=SLICE_X20Y75:SLICE_X29Y79;
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INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
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AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X4Y112:SLICE_X7Y119;
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INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
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AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X20Y64:SLICE_X29Y74, SLICE_X8Y64:SLICE_X19Y79;
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AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB16_X1Y38:RAMB16_X1Y38, RAMB16_X1Y32:RAMB16_X1Y34;
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AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB8_X1Y38:RAMB8_X1Y39, RAMB8_X1Y32:RAMB8_X1Y35;
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INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
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AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X0Y16:SLICE_X27Y47;
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INST "dio_in" AREA_GROUP = "pblock_dio_in";
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AREA_GROUP "pblock_dio_in" RANGE=SLICE_X0Y48:SLICE_X9Y63;
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AREA_GROUP "pblock_dio_in" RANGE=DSP48_X0Y12:DSP48_X0Y15;
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AREA_GROUP "pblock_dio_in" RANGE=RAMB16_X0Y24:RAMB16_X0Y30;
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AREA_GROUP "pblock_dio_in" RANGE=RAMB8_X0Y24:RAMB8_X0Y31;
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INST "main" AREA_GROUP = "pblock_main_1";
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AREA_GROUP "pblock_main_1" RANGE=SLICE_X24Y48:SLICE_X29Y63;
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INST "dio_out" AREA_GROUP = "pblock_dio_out";
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AREA_GROUP "pblock_dio_out" RANGE=SLICE_X14Y48:SLICE_X23Y63;
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AREA_GROUP "pblock_dio_out" RANGE=RAMB16_X1Y24:RAMB16_X1Y30;
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AREA_GROUP "pblock_dio_out" RANGE=RAMB8_X1Y24:RAMB8_X1Y31;
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INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
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AREA_GROUP "pblock_rx" RANGE=SLICE_X0Y96:SLICE_X7Y111;
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