OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [compile.cfg] - Blame information for rev 53

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dsmv
[View]
2
Entity=stend_sp605_wishbone
3
Architecture=stend_sp605_wishbone
4
TopLevelType=1
5
[file:.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd]
6
Enabled=1
7
[file:.\src\top\sp605_lx45t_wishbone.vhd]
8
Enabled=1
9
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_type_pkg.vhd]
10
Enabled=1
11
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_interrupt.vhd]
12
Enabled=1
13
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_pb_disp.vhd]
14
Enabled=1
15
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_reg_access.vhd]
16
Enabled=1
17
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine.vhd]
18 10 dsmv
Enabled=0
19 4 dsmv
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m2.vhd]
20 10 dsmv
Enabled=0
21 4 dsmv
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m4.vhd]
22
Enabled=1
23
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine.vhd]
24 10 dsmv
Enabled=0
25 4 dsmv
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m2.vhd]
26 10 dsmv
Enabled=0
27 4 dsmv
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m4.vhd]
28
Enabled=1
29
[file:.\src\pcie_src\pcie_core64_m1\source_s6\cl_s6pcie_m2.vhd]
30
Enabled=1
31
[file:.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper.vhd]
32
Enabled=1
33
[file:.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper_tile.vhd]
34
Enabled=1
35
[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_brams_s6.vhd]
36
Enabled=1
37
[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_s6.vhd]
38
Enabled=1
39
[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_top_s6.vhd]
40
Enabled=1
41
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx.vhd]
42
Enabled=1
43
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_null_gen.vhd]
44
Enabled=1
45
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_pipeline.vhd]
46
Enabled=1
47
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_top.vhd]
48
Enabled=1
49
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx.vhd]
50
Enabled=1
51
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_pipeline.vhd]
52
Enabled=1
53
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_thrtl_ctl.vhd]
54
Enabled=1
55
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_m1.vhd]
56
Enabled=1
57
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.vhd]
58
Enabled=1
59
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.xco]
60
Enabled=1
61
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_drp_chanalign_fix_3752_v6.vhd]
62
Enabled=1
63
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_rx_valid_filter_v6.vhd]
64
Enabled=1
65
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_tx_sync_rate_v6.vhd]
66
Enabled=1
67
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_wrapper_v6.vhd]
68
Enabled=1
69
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_2_0_v6.vhd]
70
Enabled=1
71
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_brams_v6.vhd]
72
Enabled=1
73
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_top_v6.vhd]
74
Enabled=1
75
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_v6.vhd]
76
Enabled=1
77
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_clocking_v6.vhd]
78
Enabled=1
79
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_gtx_v6.vhd]
80
Enabled=1
81
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_lane_v6.vhd]
82
Enabled=1
83
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_misc_v6.vhd]
84
Enabled=1
85
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_v6.vhd]
86
Enabled=1
87
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_reset_delay_v6.vhd]
88
Enabled=1
89
[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_upconfig_fix_3451_v6.vhd]
90
Enabled=1
91
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd]
92
Enabled=1
93
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.vhd]
94
Enabled=1
95
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.vhd]
96
Enabled=1
97
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.vhd]
98
Enabled=1
99
[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.vhd]
100
Enabled=1
101
[file:.\src\pcie_src\components\rtl\host_pkg.vhd]
102
Enabled=1
103
[file:.\src\pcie_src\components\rtl\core64_pb_transaction.vhd]
104
Enabled=1
105
[file:.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd]
106
Enabled=1
107
[file:.\src\pcie_src\components\rtl\core64_pb_wishbone.vhd]
108
Enabled=1
109
[file:.\src\pcie_src\components\rtl\core64_pb_wishbone_ctrl.v]
110
Enabled=1
111
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_adr.vhd]
112
Enabled=1
113
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_ext_cmd.vhd]
114
Enabled=1
115
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_descriptor.vhd]
116
Enabled=1
117
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_main.vhd]
118
Enabled=1
119
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd_pb.vhd]
120
Enabled=1
121
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd.vhd]
122
Enabled=1
123
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_ram.vhd]
124
Enabled=1
125
[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\block_pe_fifo_ext.vhd]
126
Enabled=1
127
[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m1.vhd]
128
Enabled=0
129
[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m4.vhd]
130
Enabled=0
131
[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m6.vhd]
132
Enabled=1
133
[file:.\src\pcie_src\components\block_main\block_pe_main.vhd]
134
Enabled=1
135
[file:.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd]
136
Enabled=0
137
[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd]
138
Enabled=1
139
[file:.\src\pcie_src\pcie_sim\sim\block_pkg.vhd]
140
Enabled=1
141
[file:.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd]
142
Enabled=1
143
[file:.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd]
144
Enabled=1
145
[file:.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd]
146
Enabled=1
147
[file:.\src\pcie_src\pcie_sim\dsport\glbl.v]
148
Enabled=1
149
[file:.\src\pcie_src\pcie_sim\dsport\pcie_2_0_rport_v6.vhd]
150
Enabled=1
151
[file:.\src\pcie_src\pcie_sim\dsport\pcie_2_0_v6_rp.vhd]
152
Enabled=1
153
[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_cfg.vhd]
154
Enabled=1
155
[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_pl.vhd]
156
Enabled=1
157
[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_rx_m2.vhd]
158
Enabled=1
159
[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_tx_m2.vhd]
160
Enabled=1
161
[file:.\src\pcie_src\pcie_sim\dsport\test_interface.vhd]
162
Enabled=1
163
[file:.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd]
164
Enabled=1
165
[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd]
166
Enabled=1
167
[file:.\src\wishbone\cross\wb_conmax_arb.v]
168
Enabled=1
169
[file:.\src\wishbone\cross\wb_conmax_defines.v]
170
Enabled=1
171
[file:.\src\wishbone\cross\wb_conmax_master_if.v]
172
Enabled=1
173
[file:.\src\wishbone\cross\wb_conmax_msel.v]
174
Enabled=1
175
[file:.\src\wishbone\cross\wb_conmax_pri_dec.v]
176
Enabled=1
177
[file:.\src\wishbone\cross\wb_conmax_pri_enc.v]
178
Enabled=1
179
[file:.\src\wishbone\cross\wb_conmax_rf.v]
180
Enabled=1
181
[file:.\src\wishbone\cross\wb_conmax_slave_if.v]
182
Enabled=1
183
[file:.\src\wishbone\cross\wb_conmax_top.v]
184
Enabled=1
185
[file:.\src\wishbone\cross\wb_conmax_top_pkg.vhd]
186
Enabled=1
187
[file:.\src\wishbone\block_test_generate\block_generate_wb_burst_slave.v]
188
Enabled=1
189
[file:.\src\wishbone\block_test_generate\block_generate_wb_config_slave.vhd]
190
Enabled=1
191
[file:.\src\wishbone\block_test_generate\block_generate_wb_pkg.vhd]
192
Enabled=1
193
[file:.\src\wishbone\block_test_generate\cl_test_generate.vhd]
194
Enabled=1
195
[file:.\src\wishbone\block_test_generate\block_test_generate_wb.vhd]
196
Enabled=1
197
[file:.\src\wishbone\block_test_check\block_check_wb_pkg.vhd]
198
Enabled=1
199
[file:.\src\wishbone\block_test_check\block_check_wb_burst_slave.v]
200
Enabled=1
201
[file:.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd]
202
Enabled=1
203
[file:.\src\wishbone\block_test_check\cl_test_check.vhd]
204
Enabled=1
205
[file:.\src\wishbone\block_test_check\block_test_check_wb.vhd]
206
Enabled=1
207
[file:.\src\testbench\stend_sp605_wishbone.vhd]
208
Enabled=1
209
[file:.\src\testbench\test_pkg.vhd]
210
Enabled=1
211
[file:.\src\testbench\wb_block_pkg.vhd]
212
Enabled=1
213
[file:.\src\testbench\ahdl\test_gen.awf]
214
Enabled=1
215
[file:.\src\testbench\ahdl\pb_wishbone.awf]
216
Enabled=1
217
[file:.\src\testbench\ahdl\rx.awf]
218
Enabled=1
219
[file:.\src\testbench\ahdl\tx.awf]
220
Enabled=1
221 10 dsmv
[file:.\src\testbench\ahdl\run_ahdl.tcl]
222
Enabled=1
223 38 dsmv
[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd]
224
Enabled=0
225
[file:.\src\testbench\log\console_test_adm_read_8kb.log]
226
Enabled=1
227
[file:.\src\testbench\log\console_test_dsc_incorrect.log]
228
Enabled=1
229
[file:.\src\testbench\log\console_test_read 4 kB.log]
230
Enabled=1
231
[file:.\src\testbench\log\console_test_read_4kB.log]
232
Enabled=1
233
[file:.\src\testbench\log\file_id_0.log]
234
Enabled=1
235
[file:.\src\testbench\log\file_id_1.log]
236
Enabled=1
237
[file:.\src\testbench\log\file_id_2.log]
238
Enabled=1
239
[file:.\src\testbench\log\global_tc_summary.log]
240
Enabled=1
241
[file:.\synthesis\sp605_lx45t_wishbone.vhd]
242
Enabled=1
243
LIB=sp605_lx45t_wishbone_post_synthesis
244
SIM.POST.INCLUDED=1
245
SIM.FUNC.INCLUDED=0
246
SIM.POST.AUTO=1
247
SIM.POST.INDEX=0
248
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt]
249
Enabled=1
250
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt]
251
Enabled=1
252
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt]
253
Enabled=1
254
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt]
255
Enabled=1
256
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml]
257
Enabled=1
258
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml]
259
Enabled=1
260 51 dsmv
[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.ngc]
261
Enabled=1
262
[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.xco]
263
Enabled=1
264
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc]
265
Enabled=1
266
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.xco]
267
Enabled=1
268
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.ngc]
269
Enabled=1
270
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.xco]
271
Enabled=1
272
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.ngc]
273
Enabled=1
274
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.xco]
275
Enabled=1
276
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.ngc]
277
Enabled=1
278
[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.xco]
279
Enabled=1
280
[file:.\src\pcie_src\components\coregen\read.me]
281
Enabled=1
282
[file:.\src\pcie_src\components\pcie_core\pcie_core64_m2.vhd]
283
Enabled=0
284
[file:.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd]
285
Enabled=0
286
[file:.\src\pcie_src\pcie_core64_m1\source\bram_common.v]
287
Enabled=1
288
[file:.\src\pcie_src\pcie_core64_m1\source\cfg_wr_enable.v]
289
Enabled=1
290
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_decoder.v]
291
Enabled=1
292
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_en.v]
293
Enabled=1
294
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_nfl_en.v]
295
Enabled=1
296
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cor.v]
297
Enabled=1
298
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cpl.v]
299
Enabled=1
300
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ftl.v]
301
Enabled=1
302
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_nfl.v]
303
Enabled=1
304
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram4x26.v]
305
Enabled=1
306
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram8x26.v]
307
Enabled=1
308
[file:.\src\pcie_src\pcie_core64_m1\source\cmm_intr.v]
309
Enabled=1
310
[file:.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.v]
311
Enabled=1
312
[file:.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.xco]
313
Enabled=1
314
[file:.\src\pcie_src\pcie_core64_m1\source\extend_clk.v]
315
Enabled=1
316
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf.v]
317
Enabled=1
318
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_arb.v]
319
Enabled=1
320
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_err.v]
321
Enabled=1
322
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_mgmt.v]
323
Enabled=1
324
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_pwr.v]
325
Enabled=1
326
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_if.v]
327
Enabled=1
328
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll.v]
329
Enabled=1
330
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_arb.v]
331
Enabled=1
332
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_credit.v]
333
Enabled=1
334
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_oqbqfifo.v]
335
Enabled=1
336
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx.v]
337
Enabled=1
338
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx_arb.v]
339
Enabled=1
340
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_rx.v]
341
Enabled=1
342
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_tx.v]
343
Enabled=1
344
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_clocking.v]
345
Enabled=1
346
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_ep.v]
347
Enabled=1
348
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gtx_wrapper.v]
349
Enabled=1
350
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper.v]
351
Enabled=1
352
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper_top.v]
353
Enabled=1
354
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_mim_wrapper.v]
355
Enabled=1
356
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_reset_logic.v]
357
Enabled=1
358
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_soft_int.v]
359
Enabled=1
360
[file:.\src\pcie_src\pcie_core64_m1\source\pcie_top.v]
361
Enabled=1
362
[file:.\src\pcie_src\pcie_core64_m1\source\prod_fixes.v]
363
Enabled=1
364
[file:.\src\pcie_src\pcie_core64_m1\source\sync_fifo.v]
365
Enabled=1
366
[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk.v]
367
Enabled=1
368
[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_bar.v]
369
Enabled=1
370
[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_mal.v]
371
Enabled=1
372
[file:.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_pwr_mgmt.v]
373
Enabled=1
374
[file:.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtp.v]
375
Enabled=1
376
[file:.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtx.v]
377
Enabled=1
378
[file:.\src\pcie_src\pcie_core64_m1\source\use_newinterrupt.v]
379
Enabled=1
380
[file:.\src\top\ambpex5_sx50t_wishbone.vhd]
381
Enabled=1
382
[file:.\src\top\ambpex5_sx50t_wishbone_sopc_wb.vhd]
383
Enabled=1
384
[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.ngc]
385
Enabled=1
386
[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.xco]
387
Enabled=1
388
[file:.\src\wishbone\cross\read.me]
389
Enabled=1
390
[file:.\src\wishbone\doc\en\block_test_check_en.htm]
391
Enabled=1
392
[file:.\src\wishbone\doc\en\block_test_generate_en.htm]
393
Enabled=1
394
[file:.\src\wishbone\doc\en\style.css]
395
Enabled=1
396
[file:.\src\wishbone\doc\en\wishbone_test_en.htm]
397
Enabled=1
398
[file:.\src\wishbone\doc\ru\block_test_check.htm]
399
Enabled=1
400
[file:.\src\wishbone\doc\ru\block_test_generate.htm]
401
Enabled=1
402
[file:.\src\wishbone\doc\ru\style.css]
403
Enabled=1
404
[file:.\src\wishbone\doc\ru\wishbonbe_test.htm]
405
Enabled=1
406
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\SciTE.session]
407
Enabled=1
408
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\delete.bat]
409
Enabled=1
410
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\ds_dma_pb_if.v]
411
Enabled=1
412
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\start.bat]
413
Enabled=1
414
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\tb.v]
415
Enabled=1
416
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wave.do]
417
Enabled=1
418
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_simple_ram_slave_if.v]
419
Enabled=1
420
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_slave_if.v]
421
Enabled=1
422
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\delete.do]
423
Enabled=1
424
[file:.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\setup_sim.do]
425
Enabled=1
426
[file:.\src\wishbone\testbecnh\dev_test_check\SciTE.session]
427
Enabled=1
428
[file:.\src\wishbone\testbecnh\dev_test_check\sim\delete.bat]
429
Enabled=1
430
[file:.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.v]
431
Enabled=1
432
[file:.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.vPreview]
433
Enabled=1
434
[file:.\src\wishbone\testbecnh\dev_test_check\sim\start.bat]
435
Enabled=1
436
[file:.\src\wishbone\testbecnh\dev_test_check\sim\tb.v]
437
Enabled=1
438
[file:.\src\wishbone\testbecnh\dev_test_check\sim\wave.do]
439
Enabled=1
440
[file:.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\delete.do]
441
Enabled=1
442
[file:.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\setup_sim.do]
443
Enabled=1
444
[file:.\src\wishbone\testbecnh\dev_test_gen\SciTE.session]
445
Enabled=1
446
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\delete.bat]
447
Enabled=1
448
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\ds_dma_test_gen_burst_master_if.v]
449
Enabled=1
450
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\start.bat]
451
Enabled=1
452
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\tb.v]
453
Enabled=1
454
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\wave.do]
455
Enabled=1
456
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\delete.do]
457
Enabled=1
458
[file:.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\setup_sim.do]
459
Enabled=1
460
[file:.\src\wishbone\testbecnh\dev_wb_cross\SciTE.session]
461
Enabled=1
462
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\delete.bat]
463
Enabled=1
464
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\start.bat]
465
Enabled=1
466
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\tb.v]
467
Enabled=1
468
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wave.do]
469
Enabled=1
470
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv]
471
Enabled=1
472
VerilogLanguage=7
473
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv]
474
Enabled=1
475
VerilogLanguage=7
476
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v]
477
Enabled=1
478
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do]
479
Enabled=1
480
[file:.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do]
481
Enabled=1
482
[file:.\src\testbench\stend_ambpex5_wishbone.vhd]
483
Enabled=1
484
[file:.\src\testbench\ahdl\log_example\console_test_adm_read_8kb.log]
485
Enabled=1
486
[file:.\src\testbench\ahdl\log_example\console_test_dsc_incorrect.log]
487
Enabled=1
488
[file:.\src\testbench\ahdl\log_example\console_test_read_4kB.log]
489
Enabled=1
490
[file:.\src\testbench\ahdl\log_example\file_id_0.log]
491
Enabled=1
492
[file:.\src\testbench\ahdl\log_example\file_id_1.log]
493
Enabled=1
494
[file:.\src\testbench\ahdl\log_example\file_id_2.log]
495
Enabled=1
496
[file:.\src\testbench\ahdl\log_example\global_tc_summary.log]
497
Enabled=1
498
[file:.\src\testbench\log\file_id_3.log]
499
Enabled=1
500
[file:.\src\testbench\modelsim\delete.bat]
501
Enabled=1
502
[file:.\src\testbench\modelsim\start.bat]
503
Enabled=1
504
[file:.\src\testbench\modelsim\wave.do]
505
Enabled=1
506
[file:.\src\testbench\modelsim\required_tests\SciTE.session]
507
Enabled=1
508
[file:.\src\testbench\modelsim\required_tests\test0\block_check_wb_burst_slave_0.v]
509
Enabled=1
510
[file:.\src\testbench\modelsim\required_tests\test0\delete.bat]
511
Enabled=1
512
[file:.\src\testbench\modelsim\required_tests\test0\read.me]
513
Enabled=1
514
[file:.\src\testbench\modelsim\required_tests\test0\start.bat]
515
Enabled=1
516
[file:.\src\testbench\modelsim\required_tests\test0\wave.do]
517
Enabled=1
518
[file:.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do]
519
Enabled=1
520
[file:.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do]
521
Enabled=1
522
[file:.\src\testbench\modelsim\zz_do\delete.do]
523
Enabled=1
524
[file:.\src\testbench\modelsim\zz_do\setup_sim.do]
525
Enabled=1
526
[file:.\synthesis\ambpex5_sx50t_wishbone.vhd]
527
LIB=ambpex5_sx50t_wishbone_post_synthesis
528
Enabled=1
529
SIM.FUNC.INCLUDED=0
530
SIM.POST.INCLUDED=1
531
SIM.POST.AUTO=1
532
SIM.POST.INDEX=0
533
[file:.\src\adm\adm2_pkg.vhd]
534
Enabled=1
535
[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]
536
Enabled=1
537
[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_cs.vhd]
538
Enabled=1
539
[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]
540
Enabled=1
541
[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_data_we.vhd]
542
Enabled=1
543
[file:.\src\adm\cl_ambpex5\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]
544
Enabled=1
545
[file:.\src\adm\cl_ambpex5\rtl\ctrl_blink.vhd]
546
Enabled=1
547
[file:.\src\adm\cl_ambpex5\rtl\pb_adm_ctrl_m2.vhd]
548
Enabled=1
549
[file:.\src\adm\cl_ambpex5\top\cl_ambpex5_m5.vhd]
550
Enabled=1
551
[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]
552
Enabled=1
553
[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_cs.vhd]
554
Enabled=1
555
[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]
556
Enabled=1
557
[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_data_we.vhd]
558
Enabled=1
559
[file:.\src\adm\cl_ml605\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]
560
Enabled=1
561
[file:.\src\adm\cl_ml605\rtl\ctrl_blink.vhd]
562
Enabled=1
563
[file:.\src\adm\cl_ml605\rtl\pb_adm_ctrl_m2.vhd]
564
Enabled=1
565
[file:.\src\adm\cl_ml605\top\cl_ml605.vhd]
566
Enabled=1
567
[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_cmd_adr_cs.vhd]
568
Enabled=1
569
[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_cs.vhd]
570
Enabled=1
571
[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_in_cs.vhd]
572
Enabled=1
573
[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_data_we.vhd]
574
Enabled=1
575
[file:.\src\adm\cl_sp605\rtl\ctrl_adsp_v2_decode_ram_cs.vhd]
576
Enabled=1
577
[file:.\src\adm\cl_sp605\rtl\ctrl_blink.vhd]
578
Enabled=1
579
[file:.\src\adm\cl_sp605\rtl\pb_adm_ctrl_m2.vhd]
580
Enabled=1
581
[file:.\src\adm\cl_sp605\top\cl_sp605.vhd]
582
Enabled=1
583
[file:.\src\adm\coregen\ctrl_fifo1024x65_v5.edn]
584
Enabled=1
585
[file:.\src\adm\coregen\ctrl_fifo1024x65_v5.vhd]
586
Enabled=1
587
[file:.\src\adm\coregen\ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1.ngc]
588
Enabled=1
589
[file:.\src\adm\coregen\ctrl_multiplier_v1_0.ngc]
590
Enabled=1
591
[file:.\src\adm\coregen\ctrl_multiplier_v1_0.vhd]
592
Enabled=1
593
[file:.\src\adm\coregen\ctrl_mux16x16.edn]
594
Enabled=1
595
[file:.\src\adm\coregen\ctrl_mux16x16.vhd]
596
Enabled=1
597
[file:.\src\adm\coregen\ctrl_mux16x64.edn]
598
Enabled=1
599
[file:.\src\adm\coregen\ctrl_mux16x64.vhd]
600
Enabled=1
601
[file:.\src\adm\coregen\ctrl_mux8x16r.edn]
602
Enabled=1
603
[file:.\src\adm\coregen\ctrl_mux8x16r.vhd]
604
Enabled=1
605
[file:.\src\adm\coregen\ctrl_mux8x48.edn]
606
Enabled=1
607
[file:.\src\adm\coregen\ctrl_mux8x48.vhd]
608
Enabled=1
609
[file:.\src\adm\core_s3_empty\ctrl_buft16.vhd]
610
Enabled=1
611
[file:.\src\adm\core_s3_empty\ctrl_buft32.vhd]
612
Enabled=1
613
[file:.\src\adm\core_s3_empty\ctrl_buft64.vhd]
614
Enabled=1
615
[file:.\src\adm\dio64\trd_admdio64_in_v6.vhd]
616
Enabled=1
617
[file:.\src\adm\dio64\trd_admdio64_out_v4.vhd]
618
Enabled=1
619
[file:.\src\adm\main\cl_chn_v3.vhd]
620
Enabled=1
621
[file:.\src\adm\main\cl_chn_v4.vhd]
622
Enabled=1
623
[file:.\src\adm\main\cl_test0_v4.vhd]
624
Enabled=1
625
[file:.\src\adm\main\cl_test_check.vhd]
626
Enabled=1
627
[file:.\src\adm\main\cl_test_generate.vhd]
628
Enabled=1
629
[file:.\src\adm\main\ctrl_thdac.vhd]
630
Enabled=1
631
[file:.\src\adm\main\trd_main_v8.vhd]
632
Enabled=1
633
[file:.\src\adm\main\trd_pio_std_v4.vhd]
634
Enabled=1
635
[file:.\src\adm\rtl\cl_fifo1024x65_v5.vhd]
636
Enabled=1
637
[file:.\src\adm\rtl\cl_fifo_control_v2.vhd]
638
Enabled=1
639
[file:.\src\adm\rtl\ctrl_start_v2.vhd]
640
Enabled=1
641
[file:.\src\adm\trd_test_ctrl\ctrl_freq.vhd]
642
Enabled=1
643
[file:.\src\adm\trd_test_ctrl\trd_test_ctrl_m1.vhd]
644
Enabled=1
645
[file:.\src\testbench\stend_ambpex5_core.vhd]
646
Enabled=1
647
[file:.\src\testbench\stend_ambpex5_core_m2.vhd]
648
Enabled=1
649
[file:.\src\testbench\modelsim\zz_do\files_coregen_vhdl.f]
650
Enabled=1
651
[file:.\src\testbench\modelsim\zz_do\files_design_verilog.f]
652
Enabled=1
653
[file:.\src\testbench\modelsim\zz_do\files_design_vhdl.f]
654
Enabled=1
655
[file:.\src\testbench\modelsim\zz_do\files_verification_vhdl.f]
656
Enabled=1
657
[file:.\src\top\ambpex5_v20_sx50t_core.ucf]
658
Enabled=1
659
[file:.\src\top\ambpex5_v20_sx50t_core.vhd]
660
Enabled=1
661
[file:.\src\testbench\stend_sp605_core_m2.vhd]
662
Enabled=1
663
[file:.\src\testbench\rx.awf]
664
Enabled=1
665
[file:.\src\testbench\tx.awf]
666
Enabled=1
667
[file:.\src\testbench\disp.awf]
668
Enabled=1
669
[file:.\src\testbench\descriptor.awf]
670
Enabled=1
671
[file:.\src\top\sp605_lx45t_core.ucf]
672
Enabled=1
673
[file:.\src\top\sp605_lx45t_core.vhd]
674
Enabled=1
675
[file:.\src\log\test.log]
676
Enabled=1
677
[file:.\synthesis\sp605_lx45t_core.vhd]
678
LIB=sp605_lx45t_core_post_synthesis
679
Enabled=1
680
SIM.FUNC.INCLUDED=0
681
SIM.POST.INCLUDED=1
682
SIM.POST.AUTO=1
683
SIM.POST.INDEX=0
684
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\ComputerInformation.txt]
685
Enabled=1
686
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\DesignInformation.txt]
687
Enabled=1
688
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\DesignFiles.txt]
689
Enabled=1
690
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\LibrariesList.txt]
691
Enabled=1
692
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\synthesis_synthesis.dfml]
693
Enabled=1
694
[file:.\src\DESIGN_STATUS\2013_07_17_00_56\implement_ver1_rev1_implementation.dfml]
695
Enabled=1
696
[file:.\src\testbench\log\console_test_read_reg.log]
697
Enabled=1
698
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\ComputerInformation.txt]
699
Enabled=1
700
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\DesignInformation.txt]
701
Enabled=1
702
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\DesignFiles.txt]
703
Enabled=1
704
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\LibrariesList.txt]
705
Enabled=1
706
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml]
707
Enabled=1
708
[file:.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml]
709
Enabled=1
710 53 dsmv
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.ngc]
711
Enabled=1
712
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.vhd]
713
Enabled=1
714
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.xco]
715
Enabled=1
716
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.ngc]
717
Enabled=1
718
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.vhd]
719
Enabled=1
720
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.xco]
721
Enabled=1
722
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.ngc]
723
Enabled=1
724
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.vhd]
725
Enabled=1
726
[file:.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.xco]
727
Enabled=1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.