| 1 |
4 |
dsmv |
[View]
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| 2 |
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Entity=stend_sp605_wishbone
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| 3 |
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Architecture=stend_sp605_wishbone
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| 4 |
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TopLevelType=1
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| 5 |
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[file:.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd]
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| 6 |
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Enabled=1
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| 7 |
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[file:.\src\top\sp605_lx45t_wishbone.vhd]
|
| 8 |
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Enabled=1
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| 9 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_type_pkg.vhd]
|
| 10 |
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Enabled=1
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| 11 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_interrupt.vhd]
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| 12 |
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Enabled=1
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| 13 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_pb_disp.vhd]
|
| 14 |
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Enabled=1
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| 15 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_reg_access.vhd]
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| 16 |
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Enabled=1
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| 17 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine.vhd]
|
| 18 |
10 |
dsmv |
Enabled=0
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| 19 |
4 |
dsmv |
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m2.vhd]
|
| 20 |
10 |
dsmv |
Enabled=0
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| 21 |
4 |
dsmv |
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m4.vhd]
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| 22 |
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Enabled=1
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| 23 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine.vhd]
|
| 24 |
10 |
dsmv |
Enabled=0
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| 25 |
4 |
dsmv |
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m2.vhd]
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| 26 |
10 |
dsmv |
Enabled=0
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| 27 |
4 |
dsmv |
[file:.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m4.vhd]
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| 28 |
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Enabled=1
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| 29 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\cl_s6pcie_m2.vhd]
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| 30 |
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Enabled=1
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| 31 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper.vhd]
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| 32 |
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Enabled=1
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| 33 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper_tile.vhd]
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| 34 |
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Enabled=1
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| 35 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_brams_s6.vhd]
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| 36 |
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Enabled=1
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| 37 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_s6.vhd]
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| 38 |
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Enabled=1
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| 39 |
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[file:.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_top_s6.vhd]
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| 40 |
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Enabled=1
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| 41 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx.vhd]
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| 42 |
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Enabled=1
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| 43 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_null_gen.vhd]
|
| 44 |
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Enabled=1
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| 45 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_pipeline.vhd]
|
| 46 |
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Enabled=1
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| 47 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_top.vhd]
|
| 48 |
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Enabled=1
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| 49 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx.vhd]
|
| 50 |
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Enabled=1
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| 51 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_pipeline.vhd]
|
| 52 |
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Enabled=1
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| 53 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_thrtl_ctl.vhd]
|
| 54 |
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Enabled=1
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| 55 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_m1.vhd]
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| 56 |
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Enabled=1
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| 57 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.vhd]
|
| 58 |
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Enabled=1
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| 59 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.xco]
|
| 60 |
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Enabled=1
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| 61 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_drp_chanalign_fix_3752_v6.vhd]
|
| 62 |
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Enabled=1
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| 63 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_rx_valid_filter_v6.vhd]
|
| 64 |
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Enabled=1
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| 65 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_tx_sync_rate_v6.vhd]
|
| 66 |
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Enabled=1
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| 67 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_wrapper_v6.vhd]
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| 68 |
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Enabled=1
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| 69 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_2_0_v6.vhd]
|
| 70 |
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Enabled=1
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| 71 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_brams_v6.vhd]
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| 72 |
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Enabled=1
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| 73 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_top_v6.vhd]
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| 74 |
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Enabled=1
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| 75 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_v6.vhd]
|
| 76 |
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Enabled=1
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| 77 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_clocking_v6.vhd]
|
| 78 |
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Enabled=1
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| 79 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_gtx_v6.vhd]
|
| 80 |
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Enabled=1
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| 81 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_lane_v6.vhd]
|
| 82 |
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Enabled=1
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| 83 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_misc_v6.vhd]
|
| 84 |
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Enabled=1
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| 85 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_v6.vhd]
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| 86 |
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Enabled=1
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| 87 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_reset_delay_v6.vhd]
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| 88 |
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Enabled=1
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| 89 |
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[file:.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_upconfig_fix_3451_v6.vhd]
|
| 90 |
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Enabled=1
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| 91 |
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[file:.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd]
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| 92 |
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Enabled=1
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| 93 |
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[file:.\src\pcie_src\components\coregen\ctrl_fifo64x37st.vhd]
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| 94 |
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Enabled=1
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| 95 |
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[file:.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.vhd]
|
| 96 |
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Enabled=1
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| 97 |
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[file:.\src\pcie_src\components\coregen\ctrl_fifo64x70st.vhd]
|
| 98 |
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Enabled=1
|
| 99 |
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[file:.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.vhd]
|
| 100 |
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Enabled=1
|
| 101 |
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[file:.\src\pcie_src\components\rtl\host_pkg.vhd]
|
| 102 |
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Enabled=1
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| 103 |
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[file:.\src\pcie_src\components\rtl\core64_pb_transaction.vhd]
|
| 104 |
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Enabled=1
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| 105 |
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[file:.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd]
|
| 106 |
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Enabled=1
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| 107 |
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[file:.\src\pcie_src\components\rtl\core64_pb_wishbone.vhd]
|
| 108 |
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Enabled=1
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| 109 |
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[file:.\src\pcie_src\components\rtl\core64_pb_wishbone_ctrl.v]
|
| 110 |
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Enabled=1
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| 111 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_adr.vhd]
|
| 112 |
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Enabled=1
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| 113 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_ext_cmd.vhd]
|
| 114 |
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Enabled=1
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| 115 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_descriptor.vhd]
|
| 116 |
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Enabled=1
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| 117 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_main.vhd]
|
| 118 |
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Enabled=1
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| 119 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd_pb.vhd]
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| 120 |
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Enabled=1
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| 121 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd.vhd]
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| 122 |
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Enabled=1
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| 123 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_ram.vhd]
|
| 124 |
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Enabled=1
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| 125 |
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[file:.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\block_pe_fifo_ext.vhd]
|
| 126 |
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Enabled=1
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| 127 |
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[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m1.vhd]
|
| 128 |
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Enabled=0
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| 129 |
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[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m4.vhd]
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| 130 |
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Enabled=0
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| 131 |
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[file:.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m6.vhd]
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| 132 |
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Enabled=1
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| 133 |
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[file:.\src\pcie_src\components\block_main\block_pe_main.vhd]
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| 134 |
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Enabled=1
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| 135 |
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[file:.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd]
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| 136 |
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Enabled=0
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| 137 |
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[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd]
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| 138 |
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Enabled=1
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| 139 |
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[file:.\src\pcie_src\pcie_sim\sim\block_pkg.vhd]
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| 140 |
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Enabled=1
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| 141 |
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[file:.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd]
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| 142 |
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Enabled=1
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| 143 |
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[file:.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd]
|
| 144 |
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Enabled=1
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| 145 |
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[file:.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd]
|
| 146 |
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Enabled=1
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| 147 |
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[file:.\src\pcie_src\pcie_sim\dsport\glbl.v]
|
| 148 |
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Enabled=1
|
| 149 |
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[file:.\src\pcie_src\pcie_sim\dsport\pcie_2_0_rport_v6.vhd]
|
| 150 |
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Enabled=1
|
| 151 |
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[file:.\src\pcie_src\pcie_sim\dsport\pcie_2_0_v6_rp.vhd]
|
| 152 |
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Enabled=1
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| 153 |
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[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_cfg.vhd]
|
| 154 |
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Enabled=1
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| 155 |
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[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_pl.vhd]
|
| 156 |
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Enabled=1
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| 157 |
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[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_rx_m2.vhd]
|
| 158 |
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Enabled=1
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| 159 |
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[file:.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_tx_m2.vhd]
|
| 160 |
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Enabled=1
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| 161 |
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[file:.\src\pcie_src\pcie_sim\dsport\test_interface.vhd]
|
| 162 |
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Enabled=1
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| 163 |
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[file:.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd]
|
| 164 |
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Enabled=1
|
| 165 |
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[file:.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd]
|
| 166 |
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Enabled=1
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| 167 |
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[file:.\src\wishbone\cross\wb_conmax_arb.v]
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| 168 |
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Enabled=1
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| 169 |
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[file:.\src\wishbone\cross\wb_conmax_defines.v]
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| 170 |
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Enabled=1
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| 171 |
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[file:.\src\wishbone\cross\wb_conmax_master_if.v]
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| 172 |
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Enabled=1
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| 173 |
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[file:.\src\wishbone\cross\wb_conmax_msel.v]
|
| 174 |
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Enabled=1
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| 175 |
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[file:.\src\wishbone\cross\wb_conmax_pri_dec.v]
|
| 176 |
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Enabled=1
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| 177 |
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[file:.\src\wishbone\cross\wb_conmax_pri_enc.v]
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| 178 |
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Enabled=1
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| 179 |
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[file:.\src\wishbone\cross\wb_conmax_rf.v]
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| 180 |
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Enabled=1
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| 181 |
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[file:.\src\wishbone\cross\wb_conmax_slave_if.v]
|
| 182 |
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Enabled=1
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| 183 |
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[file:.\src\wishbone\cross\wb_conmax_top.v]
|
| 184 |
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Enabled=1
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| 185 |
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[file:.\src\wishbone\cross\wb_conmax_top_pkg.vhd]
|
| 186 |
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Enabled=1
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| 187 |
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[file:.\src\wishbone\block_test_generate\block_generate_wb_burst_slave.v]
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| 188 |
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Enabled=1
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| 189 |
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[file:.\src\wishbone\block_test_generate\block_generate_wb_config_slave.vhd]
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| 190 |
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Enabled=1
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| 191 |
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[file:.\src\wishbone\block_test_generate\block_generate_wb_pkg.vhd]
|
| 192 |
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Enabled=1
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| 193 |
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[file:.\src\wishbone\block_test_generate\cl_test_generate.vhd]
|
| 194 |
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Enabled=1
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| 195 |
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[file:.\src\wishbone\block_test_generate\block_test_generate_wb.vhd]
|
| 196 |
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Enabled=1
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| 197 |
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[file:.\src\wishbone\block_test_check\block_check_wb_pkg.vhd]
|
| 198 |
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Enabled=1
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| 199 |
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[file:.\src\wishbone\block_test_check\block_check_wb_burst_slave.v]
|
| 200 |
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Enabled=1
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| 201 |
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[file:.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd]
|
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Enabled=1
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| 203 |
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[file:.\src\wishbone\block_test_check\cl_test_check.vhd]
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Enabled=1
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[file:.\src\wishbone\block_test_check\block_test_check_wb.vhd]
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Enabled=1
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| 207 |
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[file:.\src\testbench\stend_sp605_wishbone.vhd]
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Enabled=1
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| 209 |
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[file:.\src\testbench\test_pkg.vhd]
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Enabled=1
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[file:.\src\testbench\wb_block_pkg.vhd]
|
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Enabled=1
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[file:.\src\testbench\ahdl\test_gen.awf]
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Enabled=1
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| 215 |
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[file:.\src\testbench\ahdl\pb_wishbone.awf]
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| 216 |
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Enabled=1
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| 217 |
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[file:.\src\testbench\ahdl\rx.awf]
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| 218 |
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Enabled=1
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| 219 |
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[file:.\src\testbench\ahdl\tx.awf]
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Enabled=1
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| 221 |
10 |
dsmv |
[file:.\src\testbench\ahdl\run_ahdl.tcl]
|
| 222 |
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Enabled=1
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| 223 |
38 |
dsmv |
[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd]
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| 224 |
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Enabled=0
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| 225 |
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[file:.\src\testbench\log\console_test_adm_read_8kb.log]
|
| 226 |
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Enabled=1
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| 227 |
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[file:.\src\testbench\log\console_test_dsc_incorrect.log]
|
| 228 |
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Enabled=1
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[file:.\src\testbench\log\console_test_read 4 kB.log]
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Enabled=1
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[file:.\src\testbench\log\console_test_read_4kB.log]
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Enabled=1
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[file:.\src\testbench\log\file_id_0.log]
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Enabled=1
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[file:.\src\testbench\log\file_id_1.log]
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Enabled=1
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[file:.\src\testbench\log\file_id_2.log]
|
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Enabled=1
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[file:.\src\testbench\log\global_tc_summary.log]
|
| 240 |
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Enabled=1
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[file:.\synthesis\sp605_lx45t_wishbone.vhd]
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| 242 |
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Enabled=1
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| 243 |
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LIB=sp605_lx45t_wishbone_post_synthesis
|
| 244 |
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SIM.POST.INCLUDED=1
|
| 245 |
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SIM.FUNC.INCLUDED=0
|
| 246 |
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SIM.POST.AUTO=1
|
| 247 |
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SIM.POST.INDEX=0
|
| 248 |
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|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt]
|
| 249 |
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Enabled=1
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| 250 |
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt]
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Enabled=1
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| 256 |
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml]
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Enabled=1
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