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dsmv |
[Project]
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Current Flow=Multivendor
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VCS=0
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version=3
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Current Config=compile
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[Configurations]
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compile=sp605_lx45t_wishbone
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[Library]
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sp605_lx45t_wishbone=.\sp605_lx45t_wishbone.LIB
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13 |
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[Settings]
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14 |
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AccessRead=0
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15 |
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AccessReadWrite=0
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AccessACCB=0
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17 |
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AccessACCR=0
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18 |
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AccessReadWriteSLP=0
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AccessReadTopLevel=1
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DisableC=1
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21 |
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ENABLE_ADV_DATAFLOW=0
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22 |
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SYNTH_TOOL=MV_XST122
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23 |
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IMPL_TOOL=MV_ISE122
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CSYNTH_TOOL=
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PHYSSYNTH_TOOL=
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FLOW_TYPE=HDL
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LANGUAGE=VHDL
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28 |
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FLOWTOOLS=IMPL_WITH_SYNTH
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ON_SERVERFARM_SYNTH=0
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ON_SERVERFARM_IMPL=0
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31 |
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ON_SERVERFARM_SIM=0
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DVM_DISPLAY=NO
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REFRESH_FLOW=1
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FAMILY=Xilinx12x VIRTEX5
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RUN_MODE_SYNTH=0
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36 |
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VerilogDirsChanged=1
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WireDelay=2
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NoTchkMsg=0
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NoTimingChecks=0
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HESPrepare=0
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41 |
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EnableXtrace=0
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42 |
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SplitNetVectors=0
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StackMemorySize=32
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44 |
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RetvalMemorySize=32
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VsimAdditionalOptions=-relax
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ReportAssertionsActivations=0
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47 |
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TrackAssertionFailures=1
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ReportAssertionsFailures=1
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AssertionFailureLimit=0
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AssertionFailureAction=Continue
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TrackAssertionPasses=1
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ReportAssertionPasses=0
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AssertionPassLimit=0
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ReportUnfinishedAssertions=1
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TrackCoverMatches=1
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ReportCoverMatches=1
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CoverAction=Continue
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ReportDroppedCoverEvaluations=0
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ReportActivatedCoverEvaluations=0
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fileopeninsrc=1
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fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
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[LocalVerilogSets]
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EnableSLP=1
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EnableDebug=1
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VerilogLanguage=4
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Strict=0
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Strict2001=
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SystemVerilog3=
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StrictLRMMode=
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VerilogNoSpecify=0
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WarningPrnLevel=1
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ErrorOutputLimit=0
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OptimizationLevel=2
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ProtectLevel=0
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AdditionalOptions=
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MonitoringOfEventsUDP=0
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DisablePulseError=0
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HasInitialRegsValue=0
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InitialRegsValue=X
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PriorityLibNames=ovi_unisim;ovi_xilinxcorelib;ovi_unimacro;
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[LocalVhdlSets]
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CompileWithDebug=1
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[$LibMap$]
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sp605_lx45t_wishbone=.
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Active_lib=VIRTEX5
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xilinxun=VIRTEX5
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UnlinkedDesignLibrary=VIRTEX5
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DESIGNS=VIRTEX5
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[IMPLEMENTATION]
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UCF=
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FLOW_STEPS_RESET=0
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[IMPLEMENTATION_XILINX12]
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impl_opt(dont_run_translate)=0
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impl_opt(dont_run_map)=0
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impl_opt(dont_run_place)=0
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impl_opt(dont_run_trace)=0
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impl_opt(dont_run_simulation)=0
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impl_opt(dont_run_fit)=0
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impl_opt(dont_run_bitgen)=1
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105 |
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106 |
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[HierarchyViewer]
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SortInfo=u
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HierarchyInformation=ctrl_fifo64x37st|ctrl_fifo64x37st_a|0 stend_sp605_wishbone|stend_sp605_wishbone|0
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ShowHide=ShowTopLevel
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Selected=
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[DefineMacro]
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113 |
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Global=
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114 |
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[Verilog Library]
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ovi_unimacro=
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ovi_unisim=
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ovi_xilinxcorelib=
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119 |
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120 |
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[Folders]
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Name3=Makefiles
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Directory3=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
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Extension3=mak
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Name4=Memory
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125 |
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Directory4=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\src
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Extension4=mem;mif;hex
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Name5=Dll Libraries
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128 |
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Directory5=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
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129 |
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Extension5=dll
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130 |
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Name6=PDF
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131 |
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Directory6=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
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132 |
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Extension6=pdf
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133 |
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Name7=HTML
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134 |
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Directory7=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
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135 |
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Extension7=
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136 |
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137 |
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[Groups]
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138 |
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pcie_src=1
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139 |
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pcie_src\components=1
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140 |
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pcie_src\components\block_main=1
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141 |
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pcie_src\components\coregen=1
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142 |
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pcie_src\components\pcie_core=1
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143 |
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pcie_src\components\rtl=1
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144 |
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pcie_src\pcie_core64_m1=1
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145 |
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pcie_src\pcie_core64_m1\pcie_ctrl=1
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146 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext=1
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147 |
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pcie_src\pcie_core64_m1\source=0
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148 |
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pcie_src\pcie_core64_m1\source_s6=1
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149 |
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pcie_src\pcie_core64_m1\source_virtex6=1
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150 |
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pcie_src\pcie_core64_m1\top=1
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151 |
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pcie_src\pcie_sim=1
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152 |
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pcie_src\pcie_sim\dsport=1
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153 |
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pcie_src\pcie_sim\sim=1
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154 |
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testbench=1
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155 |
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testbench\modelsim=1
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156 |
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testbench\modelsim\zz_do=1
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157 |
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top=1
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158 |
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log=1
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159 |
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wishbone=1
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160 |
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wishbone\block_test_check=1
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161 |
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wishbone\block_test_generate=1
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162 |
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wishbone\cross=1
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163 |
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wishbone\doc=1
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164 |
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wishbone\coregen=1
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165 |
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wishbone\testbecnh=1
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166 |
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wishbone\testbecnh\dev_pb_wishbone_ctrl=1
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167 |
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wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
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168 |
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wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
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169 |
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wishbone\testbecnh\dev_test_check=1
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170 |
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wishbone\testbecnh\dev_test_check\sim=1
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171 |
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wishbone\testbecnh\dev_test_check\sim\zz_do=1
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172 |
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wishbone\testbecnh\dev_test_gen=1
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173 |
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wishbone\testbecnh\dev_test_gen\sim=1
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174 |
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wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
175 |
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wishbone\testbecnh\dev_wb_cross=1
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176 |
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wishbone\testbecnh\dev_wb_cross\sim=1
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177 |
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wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
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178 |
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testbench\ahdl=1
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179 |
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testbench\modelsim\required_tests=1
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180 |
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testbench\modelsim\required_tests\test0=1
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181 |
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testbench\modelsim\required_tests\test0\zz_do=1
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182 |
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183 |
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[Files]
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184 |
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pcie_src\components\block_main/block_pe_main.vhd=-1
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185 |
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pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
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186 |
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pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
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187 |
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pcie_src\components\coregen/ctrl_fifo64x34fw.xco=-1
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188 |
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pcie_src\components\coregen/ctrl_fifo64x37st.ngc=-1
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189 |
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pcie_src\components\coregen/ctrl_fifo64x37st.vhd=-1
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190 |
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pcie_src\components\coregen/ctrl_fifo64x37st.xco=-1
|
191 |
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pcie_src\components\coregen/ctrl_fifo64x67fw.ngc=-1
|
192 |
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pcie_src\components\coregen/ctrl_fifo64x67fw.vhd=-1
|
193 |
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pcie_src\components\coregen/ctrl_fifo64x67fw.xco=-1
|
194 |
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pcie_src\components\coregen/ctrl_fifo64x70st.ngc=-1
|
195 |
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pcie_src\components\coregen/ctrl_fifo64x70st.vhd=-1
|
196 |
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pcie_src\components\coregen/ctrl_fifo64x70st.xco=-1
|
197 |
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pcie_src\components\coregen/ctrl_fifo512x64st_v0.ngc=-1
|
198 |
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pcie_src\components\coregen/ctrl_fifo512x64st_v0.vhd=-1
|
199 |
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pcie_src\components\coregen/ctrl_fifo512x64st_v0.xco=-1
|
200 |
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pcie_src\components\coregen/read.me=-1
|
201 |
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pcie_src\components\pcie_core/pcie_core64_m2.vhd=-1
|
202 |
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pcie_src\components\pcie_core/pcie_core64_m5.vhd=-1
|
203 |
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pcie_src\components\pcie_core/pcie_core64_m7.vhd=-1
|
204 |
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pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
|
205 |
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pcie_src\components\rtl/host_pkg.vhd=-1
|
206 |
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pcie_src\components\rtl/core64_pb_transaction.vhd=-1
|
207 |
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pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
|
208 |
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pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
|
209 |
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pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
|
210 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
|
211 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
|
212 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
|
213 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
|
214 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
|
215 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m2.vhd=-1
|
216 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m4.vhd=-1
|
217 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine.vhd=-1
|
218 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m2.vhd=-1
|
219 |
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pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m4.vhd=-1
|
220 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_adr.vhd=-1
|
221 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_ext_cmd.vhd=-1
|
222 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_descriptor.vhd=-1
|
223 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_main.vhd=-1
|
224 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd_pb.vhd=-1
|
225 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd.vhd=-1
|
226 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_ram.vhd=-1
|
227 |
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pcie_src\pcie_core64_m1\pcie_fifo_ext/block_pe_fifo_ext.vhd=-1
|
228 |
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pcie_src\pcie_core64_m1\source/bram_common.v=-1
|
229 |
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pcie_src\pcie_core64_m1\source/cfg_wr_enable.v=-1
|
230 |
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pcie_src\pcie_core64_m1\source/cmm_decoder.v=-1
|
231 |
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pcie_src\pcie_core64_m1\source/cmm_errman_cnt_en.v=-1
|
232 |
|
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pcie_src\pcie_core64_m1\source/cmm_errman_cnt_nfl_en.v=-1
|
233 |
|
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pcie_src\pcie_core64_m1\source/cmm_errman_cor.v=-1
|
234 |
|
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pcie_src\pcie_core64_m1\source/cmm_errman_cpl.v=-1
|
235 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ftl.v=-1
|
236 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_nfl.v=-1
|
237 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram4x26.v=-1
|
238 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram8x26.v=-1
|
239 |
|
|
pcie_src\pcie_core64_m1\source/cmm_intr.v=-1
|
240 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.v=-1
|
241 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.xco=-1
|
242 |
|
|
pcie_src\pcie_core64_m1\source/extend_clk.v=-1
|
243 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf.v=-1
|
244 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_arb.v=-1
|
245 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_err.v=-1
|
246 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_mgmt.v=-1
|
247 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_pwr.v=-1
|
248 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_if.v=-1
|
249 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll.v=-1
|
250 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_arb.v=-1
|
251 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_credit.v=-1
|
252 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_oqbqfifo.v=-1
|
253 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx.v=-1
|
254 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx_arb.v=-1
|
255 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_rx.v=-1
|
256 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_tx.v=-1
|
257 |
|
|
pcie_src\pcie_core64_m1\source/pcie_clocking.v=-1
|
258 |
|
|
pcie_src\pcie_core64_m1\source/pcie_ep.v=-1
|
259 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gtx_wrapper.v=-1
|
260 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper.v=-1
|
261 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper_top.v=-1
|
262 |
|
|
pcie_src\pcie_core64_m1\source/pcie_mim_wrapper.v=-1
|
263 |
|
|
pcie_src\pcie_core64_m1\source/pcie_reset_logic.v=-1
|
264 |
|
|
pcie_src\pcie_core64_m1\source/pcie_soft_int.v=-1
|
265 |
|
|
pcie_src\pcie_core64_m1\source/pcie_top.v=-1
|
266 |
|
|
pcie_src\pcie_core64_m1\source/prod_fixes.v=-1
|
267 |
|
|
pcie_src\pcie_core64_m1\source/sync_fifo.v=-1
|
268 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk.v=-1
|
269 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_bar.v=-1
|
270 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_mal.v=-1
|
271 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_pwr_mgmt.v=-1
|
272 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtp.v=-1
|
273 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtx.v=-1
|
274 |
|
|
pcie_src\pcie_core64_m1\source/use_newinterrupt.v=-1
|
275 |
|
|
pcie_src\pcie_core64_m1\source_s6/cl_s6pcie_m2.vhd=-1
|
276 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper.vhd=-1
|
277 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper_tile.vhd=-1
|
278 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_brams_s6.vhd=-1
|
279 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_s6.vhd=-1
|
280 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_top_s6.vhd=-1
|
281 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx.vhd=-1
|
282 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_null_gen.vhd=-1
|
283 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_pipeline.vhd=-1
|
284 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_top.vhd=-1
|
285 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx.vhd=-1
|
286 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_pipeline.vhd=-1
|
287 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_thrtl_ctl.vhd=-1
|
288 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_m1.vhd=-1
|
289 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.vhd=-1
|
290 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.xco=-1
|
291 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd=-1
|
292 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_rx_valid_filter_v6.vhd=-1
|
293 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_tx_sync_rate_v6.vhd=-1
|
294 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_wrapper_v6.vhd=-1
|
295 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_2_0_v6.vhd=-1
|
296 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_brams_v6.vhd=-1
|
297 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_top_v6.vhd=-1
|
298 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_v6.vhd=-1
|
299 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_clocking_v6.vhd=-1
|
300 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_gtx_v6.vhd=-1
|
301 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_lane_v6.vhd=-1
|
302 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_misc_v6.vhd=-1
|
303 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_v6.vhd=-1
|
304 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_reset_delay_v6.vhd=-1
|
305 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_upconfig_fix_3451_v6.vhd=-1
|
306 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m1.vhd=-1
|
307 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m4.vhd=-1
|
308 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m6.vhd=-1
|
309 |
|
|
pcie_src\pcie_sim\dsport/glbl.v=-1
|
310 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_rport_v6.vhd=-1
|
311 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_v6_rp.vhd=-1
|
312 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_cfg.vhd=-1
|
313 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_pl.vhd=-1
|
314 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_rx_m2.vhd=-1
|
315 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_tx_m2.vhd=-1
|
316 |
|
|
pcie_src\pcie_sim\dsport/test_interface.vhd=-1
|
317 |
|
|
pcie_src\pcie_sim\dsport/xilinx_pcie_rport_m2.vhd=-1
|
318 |
|
|
pcie_src\pcie_sim\sim/block_pkg.vhd=-1
|
319 |
|
|
pcie_src\pcie_sim\sim/cmd_sim_pkg.vhd=-1
|
320 |
|
|
pcie_src\pcie_sim\sim/root_memory_pkg.vhd=-1
|
321 |
|
|
pcie_src\pcie_sim\sim/trd_pcie_pkg.vhd=-1
|
322 |
|
|
testbench/stend_sp605_wishbone.vhd=-1
|
323 |
|
|
testbench/test_pkg.vhd=-1
|
324 |
|
|
testbench/wb_block_pkg.vhd=-1
|
325 |
|
|
testbench\modelsim/delete.bat=-1
|
326 |
|
|
testbench\modelsim/start.bat=-1
|
327 |
|
|
testbench\modelsim/wave.do=-1
|
328 |
|
|
testbench\modelsim\zz_do/delete.do=-1
|
329 |
|
|
testbench\modelsim\zz_do/setup_sim.do=-1
|
330 |
|
|
testbench\modelsim\required_tests/SciTE.session=-1
|
331 |
|
|
testbench\modelsim\required_tests\test0/block_check_wb_burst_slave_0.v=-1
|
332 |
|
|
testbench\modelsim\required_tests\test0/delete.bat=-1
|
333 |
|
|
testbench\modelsim\required_tests\test0/read.me=-1
|
334 |
|
|
testbench\modelsim\required_tests\test0/start.bat=-1
|
335 |
|
|
testbench\modelsim\required_tests\test0/wave.do=-1
|
336 |
|
|
testbench\modelsim\required_tests\test0\zz_do/delete.do=-1
|
337 |
|
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
338 |
|
|
top/sp605_lx45t_wishbone.ucf=-1
|
339 |
|
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
340 |
|
|
top/sp605_lx45t_wishbone.vhd=-1
|
341 |
|
|
log/..\..\test.log=-1
|
342 |
|
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
343 |
|
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
344 |
|
|
wishbone\block_test_check/block_check_wb_config_slave.vhd=-1
|
345 |
|
|
wishbone\block_test_check/cl_test_check.vhd=-1
|
346 |
|
|
wishbone\block_test_check/block_test_check_wb.vhd=-1
|
347 |
|
|
wishbone\block_test_generate/block_generate_wb_burst_slave.v=-1
|
348 |
|
|
wishbone\block_test_generate/block_generate_wb_config_slave.vhd=-1
|
349 |
|
|
wishbone\block_test_generate/block_generate_wb_pkg.vhd=-1
|
350 |
|
|
wishbone\block_test_generate/cl_test_generate.vhd=-1
|
351 |
|
|
wishbone\block_test_generate/block_test_generate_wb.vhd=-1
|
352 |
|
|
wishbone\cross/read.me=-1
|
353 |
|
|
wishbone\cross/wb_conmax_arb.v=-1
|
354 |
|
|
wishbone\cross/wb_conmax_defines.v=-1
|
355 |
|
|
wishbone\cross/wb_conmax_master_if.v=-1
|
356 |
|
|
wishbone\cross/wb_conmax_msel.v=-1
|
357 |
|
|
wishbone\cross/wb_conmax_pri_dec.v=-1
|
358 |
|
|
wishbone\cross/wb_conmax_pri_enc.v=-1
|
359 |
|
|
wishbone\cross/wb_conmax_rf.v=-1
|
360 |
|
|
wishbone\cross/wb_conmax_slave_if.v=-1
|
361 |
|
|
wishbone\cross/wb_conmax_top.v=-1
|
362 |
|
|
wishbone\cross/wb_conmax_top_pkg.vhd=-1
|
363 |
|
|
wishbone\doc/block_test_generate.htm=-1
|
364 |
|
|
wishbone\doc/style.css=-1
|
365 |
|
|
wishbone\doc/block_test_check.htm=-1
|
366 |
|
|
wishbone\doc/wishbonbe_test.htm=-1
|
367 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.ngc=-1
|
368 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.vhd=-1
|
369 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.xco=-1
|
370 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl/SciTE.session=-1
|
371 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/delete.bat=-1
|
372 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/ds_dma_pb_if.v=-1
|
373 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/start.bat=-1
|
374 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/tb.v=-1
|
375 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wave.do=-1
|
376 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_simple_ram_slave_if.v=-1
|
377 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_slave_if.v=-1
|
378 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/delete.do=-1
|
379 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/setup_sim.do=-1
|
380 |
|
|
wishbone\testbecnh\dev_test_check/SciTE.session=-1
|
381 |
|
|
wishbone\testbecnh\dev_test_check\sim/delete.bat=-1
|
382 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.v=-1
|
383 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.vPreview=-1
|
384 |
|
|
wishbone\testbecnh\dev_test_check\sim/start.bat=-1
|
385 |
|
|
wishbone\testbecnh\dev_test_check\sim/tb.v=-1
|
386 |
|
|
wishbone\testbecnh\dev_test_check\sim/wave.do=-1
|
387 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/delete.do=-1
|
388 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/setup_sim.do=-1
|
389 |
|
|
wishbone\testbecnh\dev_test_gen/SciTE.session=-1
|
390 |
|
|
wishbone\testbecnh\dev_test_gen\sim/delete.bat=-1
|
391 |
|
|
wishbone\testbecnh\dev_test_gen\sim/ds_dma_test_gen_burst_master_if.v=-1
|
392 |
|
|
wishbone\testbecnh\dev_test_gen\sim/start.bat=-1
|
393 |
|
|
wishbone\testbecnh\dev_test_gen\sim/tb.v=-1
|
394 |
|
|
wishbone\testbecnh\dev_test_gen\sim/wave.do=-1
|
395 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/delete.do=-1
|
396 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/setup_sim.do=-1
|
397 |
|
|
wishbone\testbecnh\dev_wb_cross/SciTE.session=-1
|
398 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/delete.bat=-1
|
399 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/start.bat=-1
|
400 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/tb.v=-1
|
401 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wave.do=-1
|
402 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_intf.sv=-1
|
403 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_master.sv=-1
|
404 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_ram_slave.v=-1
|
405 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/delete.do=-1
|
406 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/setup_sim.do=-1
|
407 |
|
|
|
408 |
|
|
[Files.Data]
|
409 |
|
|
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
|
410 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc=External File
|
411 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd=VHDL Source Code
|
412 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.xco=External File
|
413 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.ngc=External File
|
414 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.vhd=VHDL Source Code
|
415 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.xco=External File
|
416 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.ngc=External File
|
417 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.vhd=VHDL Source Code
|
418 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.xco=External File
|
419 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.ngc=External File
|
420 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.vhd=VHDL Source Code
|
421 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.xco=External File
|
422 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.ngc=External File
|
423 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.vhd=VHDL Source Code
|
424 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.xco=External File
|
425 |
|
|
.\src\pcie_src\components\coregen\read.me=External File
|
426 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m2.vhd=VHDL Source Code
|
427 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd=VHDL Source Code
|
428 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd=VHDL Source Code
|
429 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd=VHDL Source Code
|
430 |
|
|
.\src\pcie_src\components\rtl\host_pkg.vhd=VHDL Source Code
|
431 |
|
|
.\src\pcie_src\components\rtl\core64_pb_transaction.vhd=VHDL Source Code
|
432 |
|
|
.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd=VHDL Source Code
|
433 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone.vhd=VHDL Source Code
|
434 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone_ctrl.v=Verilog Source Code
|
435 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_type_pkg.vhd=VHDL Source Code
|
436 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_interrupt.vhd=VHDL Source Code
|
437 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_pb_disp.vhd=VHDL Source Code
|
438 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_reg_access.vhd=VHDL Source Code
|
439 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine.vhd=VHDL Source Code
|
440 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m2.vhd=VHDL Source Code
|
441 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m4.vhd=VHDL Source Code
|
442 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine.vhd=VHDL Source Code
|
443 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m2.vhd=VHDL Source Code
|
444 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m4.vhd=VHDL Source Code
|
445 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_adr.vhd=VHDL Source Code
|
446 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_ext_cmd.vhd=VHDL Source Code
|
447 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_descriptor.vhd=VHDL Source Code
|
448 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_main.vhd=VHDL Source Code
|
449 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd_pb.vhd=VHDL Source Code
|
450 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd.vhd=VHDL Source Code
|
451 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_ram.vhd=VHDL Source Code
|
452 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\block_pe_fifo_ext.vhd=VHDL Source Code
|
453 |
|
|
.\src\pcie_src\pcie_core64_m1\source\bram_common.v=Verilog Source Code
|
454 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cfg_wr_enable.v=Verilog Source Code
|
455 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_decoder.v=Verilog Source Code
|
456 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_en.v=Verilog Source Code
|
457 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_nfl_en.v=Verilog Source Code
|
458 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cor.v=Verilog Source Code
|
459 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cpl.v=Verilog Source Code
|
460 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ftl.v=Verilog Source Code
|
461 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_nfl.v=Verilog Source Code
|
462 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram4x26.v=Verilog Source Code
|
463 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram8x26.v=Verilog Source Code
|
464 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_intr.v=Verilog Source Code
|
465 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.v=Verilog Source Code
|
466 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.xco=External File
|
467 |
|
|
.\src\pcie_src\pcie_core64_m1\source\extend_clk.v=Verilog Source Code
|
468 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf.v=Verilog Source Code
|
469 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_arb.v=Verilog Source Code
|
470 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_err.v=Verilog Source Code
|
471 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_mgmt.v=Verilog Source Code
|
472 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_pwr.v=Verilog Source Code
|
473 |
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|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_if.v=Verilog Source Code
|
474 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll.v=Verilog Source Code
|
475 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_arb.v=Verilog Source Code
|
476 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_credit.v=Verilog Source Code
|
477 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_oqbqfifo.v=Verilog Source Code
|
478 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx.v=Verilog Source Code
|
479 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx_arb.v=Verilog Source Code
|
480 |
|
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_rx.v=Verilog Source Code
|
481 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_tx.v=Verilog Source Code
|
482 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_clocking.v=Verilog Source Code
|
483 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_ep.v=Verilog Source Code
|
484 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gtx_wrapper.v=Verilog Source Code
|
485 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper.v=Verilog Source Code
|
486 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper_top.v=Verilog Source Code
|
487 |
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.\src\pcie_src\pcie_core64_m1\source\pcie_mim_wrapper.v=Verilog Source Code
|
488 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_reset_logic.v=Verilog Source Code
|
489 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_soft_int.v=Verilog Source Code
|
490 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_top.v=Verilog Source Code
|
491 |
|
|
.\src\pcie_src\pcie_core64_m1\source\prod_fixes.v=Verilog Source Code
|
492 |
|
|
.\src\pcie_src\pcie_core64_m1\source\sync_fifo.v=Verilog Source Code
|
493 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk.v=Verilog Source Code
|
494 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_bar.v=Verilog Source Code
|
495 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_mal.v=Verilog Source Code
|
496 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_pwr_mgmt.v=Verilog Source Code
|
497 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtp.v=Verilog Source Code
|
498 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtx.v=Verilog Source Code
|
499 |
|
|
.\src\pcie_src\pcie_core64_m1\source\use_newinterrupt.v=Verilog Source Code
|
500 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\cl_s6pcie_m2.vhd=VHDL Source Code
|
501 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper.vhd=VHDL Source Code
|
502 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper_tile.vhd=VHDL Source Code
|
503 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_brams_s6.vhd=VHDL Source Code
|
504 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_s6.vhd=VHDL Source Code
|
505 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_top_s6.vhd=VHDL Source Code
|
506 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx.vhd=VHDL Source Code
|
507 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_null_gen.vhd=VHDL Source Code
|
508 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_pipeline.vhd=VHDL Source Code
|
509 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_top.vhd=VHDL Source Code
|
510 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx.vhd=VHDL Source Code
|
511 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_pipeline.vhd=VHDL Source Code
|
512 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_thrtl_ctl.vhd=VHDL Source Code
|
513 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_m1.vhd=VHDL Source Code
|
514 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.vhd=VHDL Source Code
|
515 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.xco=External File
|
516 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_drp_chanalign_fix_3752_v6.vhd=VHDL Source Code
|
517 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_rx_valid_filter_v6.vhd=VHDL Source Code
|
518 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_tx_sync_rate_v6.vhd=VHDL Source Code
|
519 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_wrapper_v6.vhd=VHDL Source Code
|
520 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_2_0_v6.vhd=VHDL Source Code
|
521 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_brams_v6.vhd=VHDL Source Code
|
522 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_top_v6.vhd=VHDL Source Code
|
523 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_v6.vhd=VHDL Source Code
|
524 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_clocking_v6.vhd=VHDL Source Code
|
525 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_gtx_v6.vhd=VHDL Source Code
|
526 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_lane_v6.vhd=VHDL Source Code
|
527 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_misc_v6.vhd=VHDL Source Code
|
528 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_v6.vhd=VHDL Source Code
|
529 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_reset_delay_v6.vhd=VHDL Source Code
|
530 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_upconfig_fix_3451_v6.vhd=VHDL Source Code
|
531 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m1.vhd=VHDL Source Code
|
532 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m4.vhd=VHDL Source Code
|
533 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m6.vhd=VHDL Source Code
|
534 |
|
|
.\src\pcie_src\pcie_sim\dsport\glbl.v=Verilog Source Code
|
535 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_rport_v6.vhd=VHDL Source Code
|
536 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_v6_rp.vhd=VHDL Source Code
|
537 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_cfg.vhd=VHDL Source Code
|
538 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_pl.vhd=VHDL Source Code
|
539 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_rx_m2.vhd=VHDL Source Code
|
540 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_tx_m2.vhd=VHDL Source Code
|
541 |
|
|
.\src\pcie_src\pcie_sim\dsport\test_interface.vhd=VHDL Source Code
|
542 |
|
|
.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd=VHDL Source Code
|
543 |
|
|
.\src\pcie_src\pcie_sim\sim\block_pkg.vhd=VHDL Source Code
|
544 |
|
|
.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd=VHDL Source Code
|
545 |
|
|
.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd=VHDL Source Code
|
546 |
|
|
.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd=VHDL Source Code
|
547 |
|
|
.\src\testbench\stend_sp605_wishbone.vhd=VHDL Source Code
|
548 |
|
|
.\src\testbench\test_pkg.vhd=VHDL Source Code
|
549 |
|
|
.\src\testbench\wb_block_pkg.vhd=VHDL Source Code
|
550 |
|
|
.\src\testbench\modelsim\delete.bat=External File
|
551 |
|
|
.\src\testbench\modelsim\start.bat=External File
|
552 |
|
|
.\src\testbench\modelsim\wave.do=Macro
|
553 |
|
|
.\src\testbench\modelsim\zz_do\delete.do=Macro
|
554 |
|
|
.\src\testbench\modelsim\zz_do\setup_sim.do=Macro
|
555 |
|
|
.\src\testbench\modelsim\required_tests\SciTE.session=External File
|
556 |
|
|
.\src\testbench\modelsim\required_tests\test0\block_check_wb_burst_slave_0.v=Verilog Source Code
|
557 |
|
|
.\src\testbench\modelsim\required_tests\test0\delete.bat=External File
|
558 |
|
|
.\src\testbench\modelsim\required_tests\test0\read.me=External File
|
559 |
|
|
.\src\testbench\modelsim\required_tests\test0\start.bat=External File
|
560 |
|
|
.\src\testbench\modelsim\required_tests\test0\wave.do=Macro
|
561 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do=Macro
|
562 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
563 |
|
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
564 |
|
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
565 |
|
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
566 |
|
|
.\test.log=Text File
|
567 |
|
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
568 |
|
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
569 |
|
|
.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd=VHDL Source Code
|
570 |
|
|
.\src\wishbone\block_test_check\cl_test_check.vhd=VHDL Source Code
|
571 |
|
|
.\src\wishbone\block_test_check\block_test_check_wb.vhd=VHDL Source Code
|
572 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_burst_slave.v=Verilog Source Code
|
573 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_config_slave.vhd=VHDL Source Code
|
574 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_pkg.vhd=VHDL Source Code
|
575 |
|
|
.\src\wishbone\block_test_generate\cl_test_generate.vhd=VHDL Source Code
|
576 |
|
|
.\src\wishbone\block_test_generate\block_test_generate_wb.vhd=VHDL Source Code
|
577 |
|
|
.\src\wishbone\cross\read.me=External File
|
578 |
|
|
.\src\wishbone\cross\wb_conmax_arb.v=Verilog Source Code
|
579 |
|
|
.\src\wishbone\cross\wb_conmax_defines.v=Verilog Source Code
|
580 |
|
|
.\src\wishbone\cross\wb_conmax_master_if.v=Verilog Source Code
|
581 |
|
|
.\src\wishbone\cross\wb_conmax_msel.v=Verilog Source Code
|
582 |
|
|
.\src\wishbone\cross\wb_conmax_pri_dec.v=Verilog Source Code
|
583 |
|
|
.\src\wishbone\cross\wb_conmax_pri_enc.v=Verilog Source Code
|
584 |
|
|
.\src\wishbone\cross\wb_conmax_rf.v=Verilog Source Code
|
585 |
|
|
.\src\wishbone\cross\wb_conmax_slave_if.v=Verilog Source Code
|
586 |
|
|
.\src\wishbone\cross\wb_conmax_top.v=Verilog Source Code
|
587 |
|
|
.\src\wishbone\cross\wb_conmax_top_pkg.vhd=VHDL Source Code
|
588 |
|
|
.\src\wishbone\doc\block_test_generate.htm=HTML Document
|
589 |
|
|
.\src\wishbone\doc\style.css=External File
|
590 |
|
|
.\src\wishbone\doc\block_test_check.htm=HTML Document
|
591 |
|
|
.\src\wishbone\doc\wishbonbe_test.htm=HTML Document
|
592 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.ngc=External File
|
593 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd=VHDL Source Code
|
594 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.xco=External File
|
595 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\SciTE.session=External File
|
596 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\delete.bat=External File
|
597 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\ds_dma_pb_if.v=Verilog Source Code
|
598 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\start.bat=External File
|
599 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\tb.v=Verilog Source Code
|
600 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wave.do=Macro
|
601 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_simple_ram_slave_if.v=Verilog Source Code
|
602 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_slave_if.v=Verilog Source Code
|
603 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\delete.do=Macro
|
604 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\setup_sim.do=Macro
|
605 |
|
|
.\src\wishbone\testbecnh\dev_test_check\SciTE.session=External File
|
606 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\delete.bat=External File
|
607 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.v=Verilog Source Code
|
608 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.vPreview=External File
|
609 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\start.bat=External File
|
610 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\tb.v=Verilog Source Code
|
611 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\wave.do=Macro
|
612 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\delete.do=Macro
|
613 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\setup_sim.do=Macro
|
614 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\SciTE.session=External File
|
615 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\delete.bat=External File
|
616 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\ds_dma_test_gen_burst_master_if.v=Verilog Source Code
|
617 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\start.bat=External File
|
618 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\tb.v=Verilog Source Code
|
619 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\wave.do=Macro
|
620 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\delete.do=Macro
|
621 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\setup_sim.do=Macro
|
622 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\SciTE.session=External File
|
623 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\delete.bat=External File
|
624 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\start.bat=External File
|
625 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\tb.v=Verilog Source Code
|
626 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wave.do=Macro
|
627 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
628 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
629 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
630 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
631 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
632 |
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