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[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [src/] [testbench/] [test_pkg.vhd] - Blame information for rev 2

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1 2 dsmv 
---------------------------------------------------------------------------------------------------
2 
--
3 
-- Title       : test_pkg.vhd
4 
-- Author      : Dmitry Smekhov
5 
-- Company     : Instrumental System
6 
--
7 
-- Version     : 1.0
8 
--
9 
---------------------------------------------------------------------------------------------------
10 
--
11 
-- Description : Пакет для тестирования ambpex5.
12 
--
13 
---------------------------------------------------------------------------------------------------
14 
--
15 
--  Version 1.1 (25.10.2011) Kuzmi4
16 
--      Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
17 
--
18 
---------------------------------------------------------------------------------------------------
19 
library ieee;
20 
use ieee.std_logic_1164.all;
21 
use ieee.std_logic_arith.all;
22 
use ieee.std_logic_unsigned.all;
23 
use ieee.std_logic_textio.all;
24 
use std.textio.all;
25 
 
26 
library work;
27 
use work.cmd_sim_pkg.all;
28 
use work.block_pkg.all;
29 
use work.wb_block_pkg.all;
30 
 
31 
package test_pkg is
32 
 
33 
--! Инициализация теста
34 
procedure test_init(
35 
                fname: in string        --! имя файла отчёта
36 
        );
37 
 
38 
--! Завершение теста
39 
procedure test_close;
40 
 
41 
 
42 
 
43 
--! Запуск DMA с неправильным дескриптором
44 
procedure test_dsc_incorrect (
45 
                signal  cmd:    out bh_cmd; --! команда
46 
                signal  ret:    in  bh_ret  --! ответ
47 
                );
48 
 
49 
--! Запуск DMA на приём одного блока 4 кБ
50 
procedure test_read_4kb (
51 
                signal  cmd:    out bh_cmd; --! команда
52 
                signal  ret:    in  bh_ret  --! ответ
53 
                );
54 
 
55 
 
56 
--! Чтение 8 кБ из тетрады DIO_IN
57 
procedure test_adm_read_8kb (
58 
                signal  cmd:    out bh_cmd; --! команда
59 
                signal  ret:    in  bh_ret  --! ответ
60 
                );
61 
 
62 
----! Проверка обращений к блоку MAIN
63 
--procedure test_block_main (
64 
--              signal  cmd:    out bh_cmd; --! команда
65 
--              signal  ret:    in  bh_ret  --! ответ
66 
--              );
67 
--
68 
----! Чтение 16 кБ с использованием двух блоков дескрипторов
69 
--procedure test_adm_read_16kb (
70 
--              signal  cmd:    out bh_cmd; --! команда
71 
--              signal  ret:    in  bh_ret  --! ответ
72 
--              );
73 
--
74 
--! Запись 16 кБ с использованием двух блоков дескрипторов
75 
procedure test_adm_write_16kb (
76 
                signal  cmd:    out bh_cmd; --! команда
77 
                signal  ret:    in  bh_ret  --! ответ
78 
                );
79 
---------------------------------------------------------------------------------------------------
80 
--
81 
--
82 
--
83 
procedure test_num_1(
84 
                            signal  cmd:    out bh_cmd; --! команда
85 
                            signal  ret:    in  bh_ret  --! ответ
86 
                    );
87 
procedure test_num_2(
88 
                            signal  cmd:    out bh_cmd; --! команда
89 
                            signal  ret:    in  bh_ret  --! ответ
90 
                    );
91 
-- ==> TEST_CHECK.WB_CFG_SLAVE
92 
procedure test_wb_1(
93 
                            signal  cmd:    out bh_cmd; --! команда
94 
                            signal  ret:    in  bh_ret  --! ответ
95 
                    );
96 
-- ==> TEST_GEN.WB_CFG_SLAVE
97 
procedure test_wb_2(
98 
                            signal  cmd:    out bh_cmd; --! команда
99 
                            signal  ret:    in  bh_ret  --! ответ
100 
                    );
101 
end package     test_pkg;
102 
---------------------------------------------------------------------------------------------------
103 
package body test_pkg is
104 
 
105 
        FILE   log: text;
106 
 
107 
        shared variable cnt_ok, cnt_error: integer;
108 
 
109 
        -- Инициализация теста
110 
        procedure test_init(
111 
                fname: in string                                        -- имя файла отчёта
112 
                ) is
113 
        begin
114 
 
115 
                file_open( log, fname, WRITE_MODE );
116 
                cnt_ok:=0;
117 
                cnt_error:=0;
118 
 
119 
        end test_init;
120 
 
121 
        -- Завершение теста
122 
        procedure test_close is
123 
                variable str : LINE;            -- pointer to string
124 
        begin
125 
 
126 
                std.textio.write( str, string'(" " ));
127 
                writeline( log, str );
128 
                writeline( log, str );
129 
 
130 
                write( str, string'("Проверка завершена" ));
131 
                writeline( log, str );
132 
                write( str, string'("Число успешных тестов:  " ));
133 
                write( str, cnt_ok );
134 
                writeline( log, str );
135 
                write( str, string'("Число ошибочных тестов: " ));
136 
                write( str, cnt_error );
137 
                writeline( log, str );
138 
 
139 
 
140 
                file_close( log );
141 
 
142 
        end test_close;
143 
 
144 
 
145 
 
146 
--! Запуск DMA с неправильным дескриптором
147 
procedure test_dsc_incorrect (
148 
                signal  cmd:    out bh_cmd; --! команда
149 
                signal  ret:    in  bh_ret  --! ответ
150 
                )
151 
is
152 
 
153 
variable        adr             : std_logic_vector( 31 downto 0 );
154 
variable        data    : std_logic_vector( 31 downto 0 );
155 
variable        str             : line;
156 
begin
157 
 
158 
        write( str, string'("TEST_DSC_INCORRECT" ));
159 
        writeline( log, str );
160 
 
161 
        ---- Формирование блока дескрипторов ---
162 
        for ii in 0 to 127 loop
163 
                adr:= x"00100000";
164 
                adr:=adr + ii*4;
165 
                int_mem_write( cmd, ret, adr,  x"00000000" );
166 
        end loop;
167 
 
168 
        int_mem_write( cmd, ret, x"00100000",  x"03020100" );
169 
        int_mem_write( cmd, ret, x"001001FC",  x"FF00AA00" );
170 
 
171 
        ---- Программирование канала DMA ----
172 
        block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
173 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
174 
 
175 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
176 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
177 
        block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR
178 
 
179 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
180 
 
181 
        wait for 10 us;
182 
 
183 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
184 
 
185 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
186 
        if( data( 15 downto 0 )=x"A021" ) then
187 
                write( str, string'(" - Ok" ));
188 
                cnt_ok := cnt_ok + 1;
189 
        else
190 
                write( str, string'(" - Error" ));
191 
                cnt_error := cnt_error + 1;
192 
        end if;
193 
 
194 
        writeline( log, str );
195 
 
196 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
197 
 
198 
end test_dsc_incorrect;
199 
 
200 
 
201 
--! Запуск DMA приём одного блока 4 кБ
202 
procedure test_read_4kb (
203 
                signal  cmd:    out bh_cmd; --! команда
204 
                signal  ret:    in  bh_ret  --! ответ
205 
                )
206 
is
207 
 
208 
variable        adr                             : std_logic_vector( 31 downto 0 );
209 
variable        data                    : std_logic_vector( 31 downto 0 );
210 
variable        str                             : line;
211 
 
212 
variable        error                   : integer:=0;
213 
variable        dma_complete    : integer;
214 
 
215 
begin
216 
 
217 
        write( str, string'("TEST_READ_4KB" ));
218 
        writeline( log, str );
219 
 
220 
        ---- Формирование блока дескрипторов ---
221 
        for ii in 0 to 127 loop
222 
                adr:= x"00100000";
223 
                adr:=adr + ii*4;
224 
                int_mem_write( cmd, ret, adr,  x"00000000" );
225 
        end loop;
226 
 
227 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
228 
        int_mem_write( cmd, ret, x"00100004",  x"00000100" );
229 
 
230 
 
231 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
232 
        int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );
233 
 
234 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- сброс
235 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
236 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- чтение идентификатора блока
237 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
238 
        hwrite( str, data );
239 
        writeline( log, str );
240 
 
241 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- размер блока - 1 килобайт
242 
 
243 
 
244 
        ---- Программирование канала DMA ----
245 
        block_write( cmd, ret, 4, 8, x"00000025" );             -- DMA_MODE - без запросов DMA
246 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
247 
 
248 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
249 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
250 
        block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
251 
 
252 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- запуск тестовой последовательности
253 
 
254 
        wait for 1 us;
255 
 
256 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
257 
 
258 
 
259 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
260 
 
261 
        wait for 20 us;
262 
 
263 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
264 
 
265 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
266 
        if( data( 8 )='1' ) then
267 
                write( str, string'(" - Дескриптор правильный" ));
268 
        else
269 
                write( str, string'(" - Ошибка чтения дескриптора" ));
270 
                error := error + 1;
271 
        end if;
272 
 
273 
        writeline( log, str );
274 
 
275 
        if( error=0 ) then
276 
 
277 
                ---- Ожидание завершения DMA ----
278 
                dma_complete := 0;
279 
                for ii in 0 to 100 loop
280 
 
281 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
282 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
283 
                        if( data(5)='1' ) then
284 
                                write( str, string'(" - DMA завершён " ));
285 
                                dma_complete := 1;
286 
                        end if;
287 
                        writeline( log, str );
288 
 
289 
                        if( dma_complete=1 ) then
290 
                                exit;
291 
                        end if;
292 
 
293 
                        wait for 1 us;
294 
 
295 
                end loop;
296 
 
297 
                writeline( log, str );
298 
 
299 
                if( dma_complete=0 ) then
300 
                        write( str, string'("Ошибка - DMA не завершён " ));
301 
                        writeline( log, str );
302 
                        error:=error+1;
303 
                end if;
304 
 
305 
        end if;
306 
 
307 
        for ii in 0 to 3 loop
308 
 
309 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
310 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
311 
                writeline( log, str );
312 
                wait for 500 ns;
313 
 
314 
        end loop;
315 
 
316 
 
317 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
318 
 
319 
        write( str, string'(" Прочитано: " ));
320 
        writeline( log, str );
321 
 
322 
        for ii in 0 to 15 loop
323 
 
324 
                adr:= x"00800000";
325 
                adr:=adr + ii*4;
326 
                int_mem_read( cmd, ret, adr,  data );
327 
 
328 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
329 
                writeline( log, str );
330 
 
331 
        end loop;
332 
 
333 
 
334 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
335 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
336 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
337 
 
338 
 
339 
        writeline( log, str );
340 
        if( error=0 ) then
341 
                write( str, string'(" Тест завершён успешно " ));
342 
                cnt_ok := cnt_ok + 1;
343 
        else
344 
                write( str, string'(" Тест не выполнен " ));
345 
                cnt_error := cnt_error + 1;
346 
        end if;
347 
        writeline( log, str );
348 
        writeline( log, str );
349 
 
350 
end test_read_4kb;
351 
 
352 
 
353 
--! Чтение 8 кБ из тетрады DIO_IN
354 
procedure test_adm_read_8kb (
355 
                signal  cmd:    out bh_cmd; --! команда
356 
                signal  ret:    in  bh_ret  --! ответ
357 
                )
358 
is
359 
 
360 
variable        adr                             : std_logic_vector( 31 downto 0 );
361 
variable        data                    : std_logic_vector( 31 downto 0 );
362 
variable        str                             : line;
363 
 
364 
variable        error                   : integer:=0;
365 
variable        dma_complete    : integer;
366 
 
367 
begin
368 
 
369 
        write( str, string'("TEST_ADM_READ_8KB" ));
370 
        writeline( log, str );
371 
 
372 
        ---- Формирование блока дескрипторов ---
373 
        for ii in 0 to 127 loop
374 
                adr:= x"00100000";
375 
                adr:=adr + ii*4;
376 
                int_mem_write( cmd, ret, adr,  x"00000000" );
377 
        end loop;
378 
 
379 
        --- Дескриптор 0 ---
380 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
381 
        int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- переход к следующему
382 
 
383 
        --- Дескриптор 1 ---
384 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
385 
        int_mem_write( cmd, ret, x"0010000C",  x"00000110" );   -- остановка
386 
 
387 
 
388 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
389 
        int_mem_write( cmd, ret, x"001001FC",  x"D6644953" );
390 
 
391 
 
392 
        ---- Программирование канала DMA ----
393 
        block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
394 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
395 
 
396 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
397 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
398 
        block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
399 
 
400 
 
401 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- сброс
402 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
403 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- чтение идентификатора блока
404 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
405 
        hwrite( str, data );
406 
        writeline( log, str );
407 
 
408 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- размер блока - 1 килобайт
409 
 
410 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
411 
 
412 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- запуск тестовой последовательности
413 
 
414 
        wait for 20 us;
415 
 
416 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
417 
 
418 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
419 
        if( data( 8 )='1' ) then
420 
                write( str, string'(" - Дескриптор правильный" ));
421 
        else
422 
                write( str, string'(" - Ошибка чтения дескриптора" ));
423 
                error := error + 1;
424 
        end if;
425 
 
426 
        writeline( log, str );
427 
 
428 
        if( error=0 ) then
429 
 
430 
                ---- Ожидание завершения DMA ----
431 
                dma_complete := 0;
432 
                for ii in 0 to 100 loop
433 
 
434 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
435 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
436 
                        if( data(5)='1' ) then
437 
                                write( str, string'(" - DMA завершён " ));
438 
                                dma_complete := 1;
439 
 
440 
                                block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
441 
 
442 
                        end if;
443 
                        writeline( log, str );
444 
 
445 
                        if( dma_complete=1 ) then
446 
                                exit;
447 
                        end if;
448 
 
449 
                        wait for 1 us;
450 
 
451 
                end loop;
452 
 
453 
                writeline( log, str );
454 
 
455 
                if( dma_complete=0 ) then
456 
                        write( str, string'("Ошибка - DMA не завершён " ));
457 
                        writeline( log, str );
458 
                        error:=error+1;
459 
                end if;
460 
 
461 
        end if;
462 
 
463 
        for ii in 0 to 3 loop
464 
 
465 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
466 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
467 
                writeline( log, str );
468 
                wait for 500 ns;
469 
 
470 
        end loop;
471 
 
472 
 
473 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
474 
 
475 
        write( str, string'(" Блок 0 - прочитано: " ));
476 
        writeline( log, str );
477 
 
478 
        for ii in 0 to 15 loop
479 
 
480 
                adr:= x"00800000";
481 
                adr:=adr + ii*4;
482 
                int_mem_read( cmd, ret, adr,  data );
483 
 
484 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
485 
                writeline( log, str );
486 
 
487 
        end loop;
488 
 
489 
        writeline( log, str );
490 
 
491 
        write( str, string'(" Блок 1 - прочитано: " ));
492 
        writeline( log, str );
493 
 
494 
        for ii in 0 to 15 loop
495 
 
496 
                adr:= x"00801000";
497 
                adr:=adr + ii*4;
498 
                int_mem_read( cmd, ret, adr,  data );
499 
 
500 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
501 
                writeline( log, str );
502 
 
503 
        end loop;
504 
 
505 
 
506 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
507 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
508 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
509 
 
510 
 
511 
        writeline( log, str );
512 
        if( error=0 ) then
513 
                write( str, string'(" Тест завершён успешно " ));
514 
                cnt_ok := cnt_ok + 1;
515 
        else
516 
                write( str, string'(" Тест не выполнен " ));
517 
                cnt_error := cnt_error + 1;
518 
        end if;
519 
        writeline( log, str );
520 
        writeline( log, str );
521 
 
522 
end test_adm_read_8kb;
523 
--
524 
--
525 
----! Проверка обращений к блоку MAIN
526 
--procedure test_block_main (
527 
--              signal  cmd:    out bh_cmd; --! команда
528 
--              signal  ret:    in  bh_ret  --! ответ
529 
--              )
530 
--is
531 
--
532 
--variable      adr                             : std_logic_vector( 31 downto 0 );
533 
--variable      data                    : std_logic_vector( 31 downto 0 );
534 
--variable      str                             : line;
535 
--
536 
--variable      error                   : integer:=0;
537 
--variable      dma_complete    : integer;
538 
--
539 
--begin
540 
--
541 
--      write( str, string'("TEST_BLOCK_MAIN" ));
542 
--      writeline( log, str );
543 
--
544 
--      block_read( cmd, ret, 4, 16#00#, data );
545 
--      write( str,  string'("БЛОК 4: " )); hwrite( str, data ); writeline( log, str );
546 
--
547 
--      wait for 10 us;
548 
--
549 
----    write( str, "Константы:" );
550 
----    writeline( log, str );
551 
----    for ii in 0 to 5 loop
552 
----            write( str, "Блок " );
553 
----            write( str, ii );
554 
----            for jj in 0 to 7 loop
555 
----                    block_read( cmd, ret, ii, jj, data );
556 
----                    write( str, "   " );
557 
----                    hwrite( str, data );
558 
----            end loop;
559 
----            writeline( log, str );
560 
----    end loop;
561 
----
562 
----
563 
----    writeline( log, str );
564 
----
565 
----    block_read( cmd, ret, 0, 16#10#, data );
566 
----    write( str,  "STATUS: " ); hwrite( str, data ); writeline( log, str );
567 
----
568 
----    block_write( cmd, ret, 80, 16#08#, x"00000100" );
569 
----
570 
----    block_read( cmd, ret, 0, 16#10#, data );
571 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
572 
----
573 
----    block_write( cmd, ret, 80, 16#08#, x"00000200" );
574 
----
575 
----    block_read( cmd, ret, 0, 16#10#, data );
576 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
577 
----
578 
----
579 
----    writeline( log, str );
580 
----    if( error=0 ) then
581 
----            write( str, " Тест завершён успешно " );
582 
----            cnt_ok := cnt_ok + 1;
583 
----    else
584 
----            write( str, " Тест не выполнен " );
585 
----            cnt_error := cnt_error + 1;
586 
----    end if;
587 
--
588 
--      for ii in 0 to 127 loop
589 
--
590 
--              block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
591 
--              block_read( cmd, ret, 4, 8, data );
592 
--              write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
593 
--              if( data/=x"0000AA55" ) then
594 
--                      error:=error+1;
595 
--              end if;
596 
--
597 
--      end loop;
598 
--
599 
--
600 
--
601 
--
602 
--      writeline( log, str );
603 
--      writeline( log, str );
604 
--
605 
--end test_block_main;
606 
--
607 
--
608 
--
609 
--
610 
----! Чтение 16 кБ с использованием двух блоков дескрипторов
611 
--procedure test_adm_read_16kb (
612 
--              signal  cmd:    out bh_cmd; --! команда
613 
--              signal  ret:    in  bh_ret  --! ответ
614 
--              )
615 
--is
616 
--
617 
--variable      adr                             : std_logic_vector( 31 downto 0 );
618 
--variable      data                    : std_logic_vector( 31 downto 0 );
619 
--variable      str                             : line;
620 
--
621 
--variable      error                   : integer:=0;
622 
--variable      dma_complete    : integer;
623 
--variable      kk                              : integer;
624 
--variable      status                  : std_logic_vector( 15 downto 0 );
625 
--
626 
--begin
627 
--
628 
--      write( str, string'("TEST_ADM_READ_16KB" ));
629 
--      writeline( log, str );
630 
--
631 
--      ---- Формирование блока дескрипторов ---
632 
--      for ii in 0 to 256 loop
633 
--              adr:= x"00100000";
634 
--              adr:=adr + ii*4;
635 
--              int_mem_write( cmd, ret, adr,  x"00000000" );
636 
--      end loop;
637 
--
638 
--      --- Блок 0 ---
639 
--
640 
--      --- Дескриптор 0 ---
641 
--      int_mem_write( cmd, ret, x"00100000",  x"00008000" );
642 
--      int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- переход к следующему дескриптору
643 
--
644 
--      --- Дескриптор 1 ---
645 
--      int_mem_write( cmd, ret, x"00100008",  x"00008010" );
646 
--      int_mem_write( cmd, ret, x"0010000C",  x"00000112" );   -- переход к следующему блоку
647 
--
648 
--      --- Дескриптор 2 ---
649 
--      int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- адрес следующего дескриптора
650 
--      int_mem_write( cmd, ret, x"00100014",  x"00000000" );
651 
--
652 
--
653 
--      int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
654 
--      int_mem_write( cmd, ret, x"001001FC",  x"14644953" );
655 
--
656 
--
657 
--      --- Блок 1 ---
658 
--
659 
--      --- Дескриптор 0 ---
660 
--      int_mem_write( cmd, ret, x"00100200",  x"00008020" );
661 
--      int_mem_write( cmd, ret, x"00100204",  x"00000111" );   -- переход к следующему дескриптору
662 
--
663 
--      --- Дескриптор 1 ---
664 
--      int_mem_write( cmd, ret, x"00100208",  x"00008030" );
665 
--      int_mem_write( cmd, ret, x"0010020C",  x"00000110" );   -- остановка
666 
--
667 
--
668 
--      int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
669 
--      int_mem_write( cmd, ret, x"001003FC",  x"D67C4953" );
670 
--
671 
--
672 
--
673 
--      ---- Программирование канала DMA ----
674 
--      block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
675 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
676 
--
677 
--      block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
678 
--      block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
679 
--      block_write( cmd, ret, 4, 23, x"00019000" );    -- LOCAL_ADR
680 
--
681 
--
682 
--      ---- Подготовка тетрады ----
683 
--      trd_test_mode( cmd, ret, 0 );   -- переход в рабочий режим --
684 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1600" );               -- DMAR0 - от тетрады 6 --
685 
--
686 
--      trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" );   -- Размер блока = 4 кБ --
687 
--
688 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
689 
--
690 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Подключение выхода генератора к DIO_IN --
691 
--
692 
--      trd_wait_cmd( cmd, ret, 6,      0, x"2038" );           -- запуск тетрады DIO_IN
693 
--
694 
--      trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" );   -- Запуск тестовой последовательности --
695 
--
696 
--      wait for 20 us;
697 
--
698 
--      block_read( cmd, ret, 4, 16, data );                    -- STATUS
699 
--
700 
--      write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
701 
--      if( data( 8 )='1' ) then
702 
--              write( str, string'(" - Дескриптор правильный" ));
703 
--      else
704 
--              write( str, string'(" - Ошибка чтения дескриптора" ));
705 
--              error := error + 1;
706 
--      end if;
707 
--
708 
--      writeline( log, str );
709 
--
710 
--      if( error=0 ) then
711 
--
712 
--              kk:=0;
713 
--              loop
714 
--
715 
--              trd_status( cmd, ret, 6, status );
716 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
717 
--
718 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
719 
--              write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
720 
--
721 
--                      if( data(4)='1' ) then
722 
--                              write( str, string'(" - завершено чтение блока " ));
723 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
724 
--                              kk:=kk+1;
725 
--                              if( kk=4 ) then
726 
--                                      exit;
727 
--                              end if;
728 
--                      end if;
729 
--                      writeline( log, str );
730 
--
731 
--                      wait for 500 ns;
732 
--
733 
--
734 
--              end loop;
735 
--
736 
--              ---- Ожидание завершения DMA ----
737 
--              dma_complete := 0;
738 
--              for ii in 0 to 100 loop
739 
--
740 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
741 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
742 
--                      if( data(5)='1' ) then
743 
--                              write( str, string'(" - DMA завершён " ));
744 
--                              dma_complete := 1;
745 
--
746 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
747 
--
748 
--                      end if;
749 
--                      writeline( log, str );
750 
--
751 
--                      if( dma_complete=1 ) then
752 
--                              exit;
753 
--                      end if;
754 
--
755 
--                      wait for 1 us;
756 
--
757 
--              end loop;
758 
--
759 
--              writeline( log, str );
760 
--
761 
--              if( dma_complete=0 ) then
762 
--                      write( str, string'("Ошибка - DMA не завершён " ));
763 
--                      writeline( log, str );
764 
--                      error:=error+1;
765 
--              end if;
766 
--
767 
--      end if;
768 
--
769 
--      for ii in 0 to 3 loop
770 
--
771 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
772 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
773 
--              writeline( log, str );
774 
--              wait for 500 ns;
775 
--
776 
--      end loop;
777 
--
778 
--
779 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
780 
--
781 
--      write( str, string'(" Блок 0 - прочитано: " ));
782 
--      writeline( log, str );
783 
--
784 
--      for ii in 0 to 15 loop
785 
--
786 
--              adr:= x"00800000";
787 
--              adr:=adr + ii*4;
788 
--              int_mem_read( cmd, ret, adr,  data );
789 
--
790 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
791 
--              writeline( log, str );
792 
--
793 
--      end loop;
794 
--
795 
--      writeline( log, str );
796 
--
797 
--      write( str, string'(" Блок 1 - прочитано: " ));
798 
--      writeline( log, str );
799 
--
800 
--      for ii in 0 to 15 loop
801 
--
802 
--              adr:= x"00801000";
803 
--              adr:=adr + ii*4;
804 
--              int_mem_read( cmd, ret, adr,  data );
805 
--
806 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
807 
--              writeline( log, str );
808 
--
809 
--      end loop;
810 
--
811 
--      write( str, string'(" Блок 2 - прочитано: " ));
812 
--      writeline( log, str );
813 
--
814 
--      for ii in 0 to 15 loop
815 
--
816 
--              adr:= x"00802000";
817 
--              adr:=adr + ii*4;
818 
--              int_mem_read( cmd, ret, adr,  data );
819 
--
820 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
821 
--              writeline( log, str );
822 
--
823 
--      end loop;
824 
--
825 
--
826 
--      write( str, string'(" Блок 3 - прочитано: " ));
827 
--      writeline( log, str );
828 
--
829 
--      for ii in 0 to 15 loop
830 
--
831 
--              adr:= x"00803000";
832 
--              adr:=adr + ii*4;
833 
--              int_mem_read( cmd, ret, adr,  data );
834 
--
835 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
836 
--              writeline( log, str );
837 
--
838 
--      end loop;
839 
--
840 
----    block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
841 
----    block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
842 
----    block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
843 
--
844 
--
845 
--      writeline( log, str );
846 
--      if( error=0 ) then
847 
--              write( str, string'(" Тест завершён успешно " ));
848 
--              cnt_ok := cnt_ok + 1;
849 
--      else
850 
--              write( str, string'(" Тест не выполнен " ));
851 
--              cnt_error := cnt_error + 1;
852 
--      end if;
853 
--      writeline( log, str );
854 
--      writeline( log, str );
855 
--
856 
--end test_adm_read_16kb;
857 
--
858 
--
859 
--
860 
--
861 
--! Запись 16 кБ с использованием двух блоков дескрипторов
862 
procedure test_adm_write_16kb (
863 
                signal  cmd:    out bh_cmd; --! команда
864 
                signal  ret:    in  bh_ret  --! ответ
865 
                )
866 
is
867 
 
868 
variable        adr                             : std_logic_vector( 31 downto 0 );
869 
variable        data                    : std_logic_vector( 31 downto 0 );
870 
variable        str                             : line;
871 
 
872 
variable        error                   : integer:=0;
873 
variable        dma_complete    : integer;
874 
variable        kk                              : integer;
875 
variable        status                  : std_logic_vector( 15 downto 0 );
876 
 
877 
variable        data64                  : std_logic_vector( 63 downto 0 );
878 
variable        data64n                 : std_logic_vector( 63 downto 0 );
879 
 
880 
begin
881 
 
882 
        write( str, string'("TEST_ADM_WRITE_16KB" ));
883 
        writeline( log, str );
884 
 
885 
        ---- Формирование блока дескрипторов ---
886 
        for ii in 0 to 256 loop
887 
                adr:= x"00100000";
888 
                adr:=adr + ii*4;
889 
                int_mem_write( cmd, ret, adr,  x"00000000" );
890 
        end loop;
891 
 
892 
 
893 
        data64 :=x"0000000000000000";
894 
        data64n := not data64;
895 
 
896 
        ---- Заполнение блока 0 ----
897 
        adr:= x"00800000";
898 
    data:=x"A5A50123";
899 
        int_mem_write( cmd, ret, adr,  data );
900 
        adr:=adr + 4;
901 
 
902 
        data:=x"00000000";
903 
        int_mem_write( cmd, ret, adr,  data );
904 
        adr:=adr + 4;
905 
 
906 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
907 
        adr:=adr + 4;
908 
 
909 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
910 
        adr:=adr + 4;
911 
 
912 
        data64:=data64 + 1;
913 
        data64n := not data64;
914 
 
915 
        for ii in 0 to 254 loop
916 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
917 
                adr:=adr + 4;
918 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
919 
                adr:=adr + 4;
920 
 
921 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
922 
                adr:=adr + 4;
923 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
924 
                adr:=adr + 4;
925 
 
926 
                data64:=data64 + 1;
927 
                data64n := not data64;
928 
 
929 
        end loop;
930 
 
931 
        ---- Заполнение блока 1 ----
932 
        adr:= x"00801000";
933 
    data:=x"A5A50123";
934 
        int_mem_write( cmd, ret, adr,  data );
935 
        adr:=adr + 4;
936 
 
937 
        data:=x"00000001";
938 
        int_mem_write( cmd, ret, adr,  data );
939 
        adr:=adr + 4;
940 
 
941 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
942 
        adr:=adr + 4;
943 
 
944 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
945 
        adr:=adr + 4;
946 
 
947 
        data64:=data64 + 1;
948 
        data64n := not data64;
949 
 
950 
        for ii in 0 to 254 loop
951 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
952 
                adr:=adr + 4;
953 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
954 
                adr:=adr + 4;
955 
 
956 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
957 
                adr:=adr + 4;
958 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
959 
                adr:=adr + 4;
960 
 
961 
                data64:=data64 + 1;
962 
                data64n := not data64;
963 
 
964 
        end loop;
965 
 
966 
        ---- Заполнение блока 2 ----
967 
        adr:= x"00802000";
968 
    data:=x"A5A50123";
969 
        int_mem_write( cmd, ret, adr,  data );
970 
        adr:=adr + 4;
971 
 
972 
        data:=x"00000002";
973 
        int_mem_write( cmd, ret, adr,  data );
974 
        adr:=adr + 4;
975 
 
976 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
977 
        adr:=adr + 4;
978 
 
979 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
980 
        adr:=adr + 4;
981 
 
982 
        data64:=data64 + 1;
983 
        data64n := not data64;
984 
 
985 
        for ii in 0 to 254 loop
986 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
987 
                adr:=adr + 4;
988 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
989 
                adr:=adr + 4;
990 
 
991 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
992 
                adr:=adr + 4;
993 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
994 
                adr:=adr + 4;
995 
 
996 
                data64:=data64 + 1;
997 
                data64n := not data64;
998 
 
999 
        end loop;
1000 
 
1001 
        ---- Заполнение блока 3 ----
1002 
        adr:= x"00803000";
1003 
    data:=x"A5A50123";
1004 
        int_mem_write( cmd, ret, adr,  data );
1005 
        adr:=adr + 4;
1006 
 
1007 
        data:=x"00000003";
1008 
        int_mem_write( cmd, ret, adr,  data );
1009 
        adr:=adr + 4;
1010 
 
1011 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1012 
        adr:=adr + 4;
1013 
 
1014 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1015 
        adr:=adr + 4;
1016 
 
1017 
        data64:=data64 + 1;
1018 
        data64n := not data64;
1019 
 
1020 
        for ii in 0 to 254 loop
1021 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1022 
                adr:=adr + 4;
1023 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1024 
                adr:=adr + 4;
1025 
 
1026 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1027 
                adr:=adr + 4;
1028 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1029 
                adr:=adr + 4;
1030 
 
1031 
                data64:=data64 + 1;
1032 
                data64n := not data64;
1033 
 
1034 
        end loop;
1035 
--      for ii in 0 to 256 loop
1036 
--              adr:= x"00802000";
1037 
--              adr:=adr + ii*4;
1038 
--              data:=x"00A20000";
1039 
--              data:=data + ii;
1040 
--              int_mem_write( cmd, ret, adr,  data );
1041 
--      end loop;
1042 
--
1043 
--      for ii in 0 to 256 loop
1044 
--              adr:= x"00803000";
1045 
--              adr:=adr + ii*4;
1046 
--              data:=x"00A30000";
1047 
--              data:=data + ii;
1048 
--              int_mem_write( cmd, ret, adr,  data );
1049 
--      end loop;
1050 
 
1051 
        --- Блок 0 ---
1052 
 
1053 
        --- Дескриптор 0 ---
1054 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
1055 
        int_mem_write( cmd, ret, x"00100004",  x"00000011" );   -- переход к следующему дескриптору
1056 
 
1057 
        --- Дескриптор 1 ---
1058 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
1059 
        int_mem_write( cmd, ret, x"0010000C",  x"00000012" );   -- переход к следующему блоку
1060 
 
1061 
        --- Дескриптор 2 ---
1062 
        int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- адрес следующего дескриптора
1063 
        int_mem_write( cmd, ret, x"00100014",  x"00000000" );
1064 
 
1065 
 
1066 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
1067 
        int_mem_write( cmd, ret, x"001001FC",  x"14A44953" );
1068 
 
1069 
 
1070 
        --- Блок 1 ---
1071 
 
1072 
        --- Дескриптор 0 ---
1073 
        int_mem_write( cmd, ret, x"00100200",  x"00008020" );
1074 
        int_mem_write( cmd, ret, x"00100204",  x"00000011" );   -- переход к следующему дескриптору
1075 
 
1076 
        --- Дескриптор 1 ---
1077 
        int_mem_write( cmd, ret, x"00100208",  x"00008030" );
1078 
        int_mem_write( cmd, ret, x"0010020C",  x"00000010" );   -- остановка
1079 
 
1080 
 
1081 
        int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
1082 
        int_mem_write( cmd, ret, x"001003FC",  x"D6BC4953" );
1083 
 
1084 
 
1085 
 
1086 
        ---- Программирование канала DMA ----
1087 
        block_write( cmd, ret, 5, 8, x"00000023" );             -- DMA_MODE  - с запросами
1088 
        --block_write( cmd, ret, 5, 8, x"00000021" );           -- DMA_MODE - без запросов
1089 
        block_write( cmd, ret, 5, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1090 
 
1091 
        block_write( cmd, ret, 5, 20, x"00100000" );    -- PCI_ADRL
1092 
        block_write( cmd, ret, 5, 21, x"00100000" );    -- PCI_ADRH
1093 
        block_write( cmd, ret, 5, 23, x"00001000" );    -- LOCAL_ADR
1094 
 
1095 
 
1096 
        ---- Подготовка тетрады ----
1097 
--      trd_test_mode( cmd, ret, 0 );   -- переход в рабочий режим --
1098 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1700" );               -- DMAR0 - от тетрады 7 --
1099 
--
1100 
--      trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" );   -- Размер блока = 4 кБ --
1101 
 
1102 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000001" ); -- сброс
1103 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
1104 
        wb_block_check_read( cmd, ret, REG_BLOCK_ID, data ); -- чтение идентификатора блока
1105 
        write( str, string'("BLOCK TEST_CHECK  ID: " ));
1106 
        hwrite( str, data );
1107 
        writeline( log, str );
1108 
 
1109 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_SIZE, x"00000001" ); -- размер блока - 1 килобайт
1110 
 
1111 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"000006A0" ); -- запуск тестовой последовательности
1112 
        --
1113 
        --
1114 
        --
1115 
        data:=wb_block_check_burst_ctrl_build('1', 40, 473);
1116 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
1117 
        --
1118 
        --
1119 
        --
1120 
        block_write( cmd, ret, 5, 9, x"00000001" );             -- DMA_CTRL - START
1121 
 
1122 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Подключение выхода генератора к DIO_IN --
1123 
--
1124 
--      trd_wait_cmd( cmd, ret, 7,      0, x"2038" );           -- запуск тетрады DIO_OUT
1125 
--
1126 
--      trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" );   -- Запуск тестовой последовательности --
1127 
 
1128 
        wait for 20 us;
1129 
 
1130 
 
1131 
        for ii in 0 to 20 loop
1132 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1133 
 
1134 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1135 
                if( data( 8 )='1' ) then
1136 
                        write( str, string'(" - Дескриптор правильный" ));
1137 
                        error := 0;
1138 
                        exit;
1139 
                else
1140 
                        write( str, string'(" - Ошибка чтения дескриптора" ));
1141 
                        error := error + 1;
1142 
                        wait for 10 us;
1143 
                end if;
1144 
 
1145 
                writeline( log, str );
1146 
        end loop;
1147 
 
1148 
 
1149 
        if( error=0 ) then
1150 
 
1151 
                kk:=0;
1152 
                loop
1153 
 
1154 
--              trd_status( cmd, ret, 6, status );
1155 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
1156 
 
1157 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1158 
                write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1159 
 
1160 
                        if( data(4)='1' ) then
1161 
                                write( str, string'(" - завершена передача блока " ));
1162 
                                block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
1163 
                                kk:=kk+1;
1164 
                                if( kk=4 ) then
1165 
                                        exit;
1166 
                                end if;
1167 
                        end if;
1168 
                        writeline( log, str );
1169 
 
1170 
                        wait for 500 ns;
1171 
 
1172 
 
1173 
                end loop;
1174 
 
1175 
                ---- Ожидание завершения DMA ----
1176 
                dma_complete := 0;
1177 
                for ii in 0 to 100 loop
1178 
 
1179 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1180 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1181 
 
1182 
                        if( data(4)='1' ) then
1183 
                                write( str, string'(" - завершёна передача блока " ));
1184 
 
1185 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
1186 
 
1187 
                        end if;
1188 
                        writeline( log, str );
1189 
 
1190 
 
1191 
                        if( data(5)='1' ) then
1192 
                                write( str, string'(" - DMA завершён " ));
1193 
                                dma_complete := 1;
1194 
 
1195 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - сброс EOT
1196 
 
1197 
                        end if;
1198 
                        writeline( log, str );
1199 
 
1200 
                        if( dma_complete=1 ) then
1201 
                                exit;
1202 
                        end if;
1203 
 
1204 
                        wait for 1 us;
1205 
 
1206 
                end loop;
1207 
 
1208 
                writeline( log, str );
1209 
 
1210 
                if( dma_complete=0 ) then
1211 
                        write( str, string'("Ошибка - DMA не завершён " ));
1212 
                        writeline( log, str );
1213 
                        error:=error+1;
1214 
                end if;
1215 
 
1216 
        end if;
1217 
 
1218 
        for ii in 0 to 3 loop
1219 
 
1220 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1221 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1222 
                writeline( log, str );
1223 
                wait for 500 ns;
1224 
 
1225 
        end loop;
1226 
 
1227 
        wait for 10 us;
1228 
 
1229 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
1230 
        write( str, string'( "Принято блоков: " ) );
1231 
        hwrite( str, data );
1232 
        kk := conv_integer( data );
1233 
        if( 4/=kk ) then
1234 
                write( str, string'( " - Ошибка" ) );
1235 
                error := error + 1;
1236 
        else
1237 
                write( str, string'( " - Ok" ) );
1238 
        end if;
1239 
        writeline( log, str );
1240 
 
1241 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
1242 
        write( str, string'( "TEST_CHECK_BL_OK: " ) );
1243 
        hwrite( str, data );
1244 
        kk := conv_integer( data );
1245 
        if( 3/=kk ) then
1246 
                write( str, string'( " - Ошибка" ) );
1247 
                error := error + 1;
1248 
        else
1249 
                write( str, string'( " - Ok" ) );
1250 
        end if;
1251 
        writeline( log, str );
1252 
 
1253 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
1254 
        write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
1255 
        hwrite( str, data );
1256 
        kk := conv_integer( data );
1257 
        if( 0/=kk ) then
1258 
                write( str, string'( " - Ошибка" ) );
1259 
                error := error + 1;
1260 
        else
1261 
                write( str, string'( " - Ok" ) );
1262 
        end if;
1263 
        writeline( log, str );
1264 
 
1265 
 
1266 
 
1267 
        block_write( cmd, ret, 5, 9, x"00000000" );             -- DMA_CTRL - STOP
1268 
 
1269 
 
1270 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1271 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
1272 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
1273 
 
1274 
 
1275 
        writeline( log, str );
1276 
        if( error=0 ) then
1277 
                write( str, string'(" Тест завершён успешно " ));
1278 
                cnt_ok := cnt_ok + 1;
1279 
        else
1280 
                write( str, string'(" Тест не выполнен " ));
1281 
                cnt_error := cnt_error + 1;
1282 
        end if;
1283 
        writeline( log, str );
1284 
        writeline( log, str );
1285 
 
1286 
end test_adm_write_16kb;
1287 
---------------------------------------------------------------------------------------------------
1288 
--
1289 
-- My procedure for test Updated Design (test_read_4kb like refenernce)
1290 
--
1291 
procedure test_num_1 (
1292 
                            signal  cmd:    out bh_cmd; --! команда
1293 
                            signal  ret:    in  bh_ret  --! ответ
1294 
                        ) is
1295 
 
1296 
    variable    adr             : std_logic_vector( 31 downto 0 );
1297 
    variable    data            : std_logic_vector( 31 downto 0 );
1298 
    variable    str             : line;
1299 
 
1300 
    variable    error           : integer:=0;
1301 
    variable    dma_complete    : integer:=0;
1302 
 
1303 
begin
1304 
    -- Init Header
1305 
    write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
1306 
    writeline( log, str );
1307 
    --
1308 
    ---- Формирование блока дескрипторов ---
1309 
    for ii in 0 to 127 loop
1310 
        adr:= x"00100000";
1311 
        adr:=adr + ii*4;
1312 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1313 
    end loop;
1314 
    -- HOST MEM Writes:
1315 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1316 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1317 
 
1318 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1319 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1320 
    --
1321 
    ---- Программирование канала DMA ---- PE_EXT_FIFO module: have bug in PE_EXT_FIFO, for check WB we will make a trick:
1322 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1323 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1324 
 
1325 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1326 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1327 
    block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
1328 
 
1329 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1330 
    --
1331 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Ошибка #24
1332 
    wait for 1 us;
1333 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1334 
    --
1335 
    -- Delay for design
1336 
    wait for 20 us;
1337 
    --
1338 
    -- Read STATUS
1339 
    block_read( cmd, ret, 4, 16, data );
1340 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1341 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1342 
    if( data( 8 )='1' ) then
1343 
        write( str, string'(" - Descriptor==OK" ));
1344 
    else
1345 
        write( str, string'(" - Descriptor RD ERR" ));
1346 
        error := error + 1;
1347 
    end if;
1348 
    writeline( log, str );  -- upd LOGFILE
1349 
    --
1350 
    -- Deal with STATUS Results:
1351 
    if( error=0 ) then  -- w8ing for DMA final
1352 
        dma_complete := 0;
1353 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1354 
            -- Read STATUS
1355 
            block_read( cmd, ret, 4, 16, data );
1356 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1357 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1358 
            if( data(5)='1' ) then
1359 
                write( str, string'(" - DMA finished" ));
1360 
                dma_complete := 1;
1361 
            end if;
1362 
            writeline( log, str );
1363 
            -- Check "dma_complete"
1364 
            if( dma_complete=1 ) then
1365 
                exit;           -- EXIT Loop on FINAL
1366 
            else
1367 
                wait for 1 us;  -- DELAY in other case
1368 
            end if;
1369 
        end loop;
1370 
        writeline( log, str );  -- upd LOGFILE
1371 
 
1372 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1373 
            write( str, string'("ERR - DMA not finished " ));
1374 
            writeline( log, str );
1375 
            error:=error+1;
1376 
        end if;
1377 
 
1378 
    end if;
1379 
    --
1380 
    -- Print STATUS now
1381 
    for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1382 
        -- Read STATUS
1383 
        block_read( cmd, ret, 4, 16, data );
1384 
        -- Construct LOG MSG in accordance to STATUS value
1385 
        write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1386 
        -- upd LOGFILE
1387 
        writeline( log, str );
1388 
        wait for 500 ns;
1389 
    end loop;
1390 
    --
1391 
    -- Now STOP Design
1392 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1393 
    --
1394 
    -- Now print RX values:
1395 
    --
1396 
    -- Construct Header:
1397 
    writeline( log, str );
1398 
    write( str, string'("PRINT 1st 15 RX values: " ));
1399 
    writeline( log, str );
1400 
    -- Get first 15 DATA values and print it:
1401 
    for ii in 0 to 15 loop
1402 
        adr:= x"00800000";                      -- init ADDR value
1403 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1404 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1405 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1406 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1407 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1408 
        writeline( log, str );  -- upd LOGFILE
1409 
    end loop;
1410 
    writeline( log, str );      -- upd LOGFILE
1411 
    --
1412 
    -- Final CHECK errors:
1413 
    if( error=0 ) then
1414 
        write( str, string'("SUCCSESSFULL FINAL " ));
1415 
        cnt_ok := cnt_ok + 1;
1416 
    else
1417 
        write( str, string'("FAILED FINAL " ));
1418 
        cnt_error := cnt_error + 1;
1419 
    end if;
1420 
    writeline( log, str );  -- upd LOGFILE
1421 
    writeline( log, str );  -- upd LOGFILE
1422 
    --
1423 
    -- END
1424 
end test_num_1;
1425 
--
1426 
--
1427 
--
1428 
procedure test_num_2 (
1429 
                            signal  cmd:    out bh_cmd; --! команда
1430 
                            signal  ret:    in  bh_ret  --! ответ
1431 
                        ) is
1432 
 
1433 
    variable    adr             : std_logic_vector( 31 downto 0 );
1434 
    variable    data            : std_logic_vector( 31 downto 0 );
1435 
    variable    data64          : std_logic_vector( 63 downto 0 );
1436 
    variable    str             : line;
1437 
 
1438 
    variable    error           : integer:=0;
1439 
    variable    dma_complete    : integer:=0;
1440 
 
1441 
begin
1442 
    -- Init Header
1443 
    write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
1444 
    writeline( log, str );
1445 
    --
1446 
    ---- Формирование блока дескрипторов ---
1447 
    for ii in 0 to 127 loop
1448 
        adr:= x"00100000";
1449 
        adr:=adr + ii*4;
1450 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1451 
    end loop;
1452 
    -- HOST MEM Writes:
1453 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1454 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1455 
 
1456 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1457 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1458 
    --
1459 
    -- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
1460 
    adr     :=x"20002048";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
1461 
    data64  :=x"0000000000000001";      --  TEST_GEN_SIZE=x01
1462 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1463 
 
1464 
    adr     :=x"20002040";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
1465 
    data64  :=x"0000000000000022";      --  TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
1466 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1467 
 
1468 
    -- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
1469 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1470 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1471 
 
1472 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1473 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1474 
    block_write( cmd, ret, 4, 23, x"00003000" );    -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
1475 
 
1476 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1477 
    --
1478 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Ошибка #24
1479 
    wait for 1 us;
1480 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1481 
    --
1482 
    -- Delay for design
1483 
    wait for 20 us;
1484 
    --
1485 
    -- Read STATUS (check RD DESCR status):
1486 
    block_read( cmd, ret, 4, 16, data );
1487 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1488 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1489 
    if( data( 8 )='1' ) then
1490 
        write( str, string'(" - Descriptor==OK" ));
1491 
    else
1492 
        write( str, string'(" - Descriptor RD ERR" ));
1493 
        error := error + 1;
1494 
    end if;
1495 
    writeline( log, str );  -- upd LOGFILE
1496 
    --
1497 
    -- W8ing for DMA finish:
1498 
    if( error=0 ) then  -- w8ing for DMA final
1499 
        dma_complete := 0;
1500 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1501 
            -- Read STATUS
1502 
            block_read( cmd, ret, 4, 16, data );
1503 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1504 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1505 
            if( data(5)='1' ) then
1506 
                write( str, string'(" - DMA finished" ));
1507 
                dma_complete := 1;
1508 
            end if;
1509 
            writeline( log, str );
1510 
            -- Check "dma_complete"
1511 
            if( dma_complete=1 ) then
1512 
                exit;           -- EXIT Loop on FINAL
1513 
            else
1514 
                wait for 1 us;  -- DELAY in other case
1515 
            end if;
1516 
        end loop;
1517 
        writeline( log, str );  -- upd LOGFILE
1518 
 
1519 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1520 
            write( str, string'("ERR - DMA not finished " ));
1521 
            writeline( log, str );
1522 
            error:=error+1;
1523 
        end if;
1524 
 
1525 
    end if;
1526 
    --
1527 
    -- Print STATUS in ERR
1528 
    if (error /= 0 ) then
1529 
        for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1530 
            -- Read STATUS
1531 
            block_read( cmd, ret, 4, 16, data );
1532 
            -- Construct LOG MSG in accordance to STATUS value
1533 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1534 
            -- upd LOGFILE
1535 
            writeline( log, str );
1536 
            wait for 500 ns;
1537 
        end loop;
1538 
    end if;
1539 
    --
1540 
    -- Now STOP Design
1541 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1542 
    --
1543 
    -- Now print RX values:
1544 
    --
1545 
    -- Construct Header:
1546 
    writeline( log, str );
1547 
    write( str, string'("PRINT 1st 15 RX values: " ));
1548 
    writeline( log, str );
1549 
    -- Get first 15 DATA values and print it:
1550 
    for ii in 0 to 15 loop
1551 
        adr:= x"00800000";                      -- init ADDR value
1552 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1553 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1554 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1555 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1556 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1557 
        writeline( log, str );  -- upd LOGFILE
1558 
    end loop;
1559 
    writeline( log, str );      -- upd LOGFILE
1560 
    --
1561 
    -- Final CHECK errors:
1562 
    if( error=0 ) then
1563 
        write( str, string'(" stb SUCCSESSFULL FINAL " ));
1564 
        cnt_ok := cnt_ok + 1;
1565 
    else
1566 
        write( str, string'(" stb FAILED FINAL " ));
1567 
        cnt_error := cnt_error + 1;
1568 
    end if;
1569 
    writeline( log, str );  -- upd LOGFILE
1570 
    writeline( log, str );  -- upd LOGFILE
1571 
    --
1572 
    -- END
1573 
end test_num_2;
1574 
---------------------------------------------------------------------------------------------------
1575 
--
1576 
-- My procedure for test WB stuff in Design:
1577 
--  ==> TEST_CHECK.WB_CFG_SLAVE
1578 
--
1579 
procedure test_wb_1 (
1580 
                            signal  cmd:    out bh_cmd; --! команда
1581 
                            signal  ret:    in  bh_ret  --! ответ
1582 
                    ) is
1583 
 
1584 
    variable    adr             : std_logic_vector( 31 downto 0 );
1585 
    variable    data32          : std_logic_vector( 31 downto 0 );
1586 
    variable    data64          : std_logic_vector( 63 downto 0 );
1587 
    variable    str             : line;
1588 
 
1589 
    variable    error           : integer:=0;
1590 
    variable    dma_complete    : integer:=0;
1591 
 
1592 
    --
1593 
    --
1594 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1595 
    type wb_cfg_slave_data is record
1596 
        const   :   wb_cfg_slave_value(7 downto 0);
1597 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1598 
        sts     :   wb_cfg_slave_value(7 downto 0);
1599 
    end record;
1600 
    --
1601 
    --
1602 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1603 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1604 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1605 
 
1606 
 
1607 
begin
1608 
    -- Init Header
1609 
    write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
1610 
    writeline( log, str );
1611 
    --
1612 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1613 
    write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1614 
    writeline( log, str );
1615 
    adr     := x"20000000";
1616 
 
1617 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1618 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1619 
            -- PCIE RD
1620 
            data_read64(cmd, ret, adr, data64);
1621 
            -- Put RD_Value to apropriate holder
1622 
            if (i=0) then       -- const
1623 
                st_wb_cfg_slave_data_0.const(j) := data64;
1624 
            elsif (i=1) then    -- cmd
1625 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1626 
            else                -- sts
1627 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1628 
            end if;
1629 
            -- Incr ADDR
1630 
            adr := adr + x"00000008";
1631 
            -- Print RD_Value
1632 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1633 
            writeline( log, str );
1634 
 
1635 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1636 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1637 
 
1638 
    --
1639 
    -- Write
1640 
    write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
1641 
    writeline( log, str );
1642 
    adr     := x"20000000";
1643 
 
1644 
    TEST_CHECK_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1645 
        TEST_CHECK_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1646 
            -- Prepare WR_Value
1647 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1648 
            -- PCIE WR
1649 
            data_write64(cmd, ret, adr, data64);
1650 
            -- Put WR_Value to apropriate holder
1651 
            if (i=0) then       -- const
1652 
                st_wb_cfg_slave_data_1.const(j) := data64;
1653 
            elsif (i=1) then    -- cmd
1654 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1655 
            else                -- sts
1656 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1657 
            end if;
1658 
            -- Incr ADDR
1659 
            adr := adr + x"00000008";
1660 
            -- Print WR_Value
1661 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1662 
            writeline( log, str );
1663 
 
1664 
        end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
1665 
    end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
1666 
 
1667 
    --
1668 
    -- Read
1669 
    write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1670 
    writeline( log, str );
1671 
    adr     := x"20000000";
1672 
 
1673 
    TEST_CHECK_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1674 
        TEST_CHECK_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1675 
            -- PCIE RD
1676 
            data_read64(cmd, ret, adr, data64);
1677 
            -- Put RD_Value to apropriate holder
1678 
            if (i=0) then       -- const
1679 
                st_wb_cfg_slave_data_2.const(j) := data64;
1680 
            elsif (i=1) then    -- cmd
1681 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1682 
            else                -- sts
1683 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1684 
            end if;
1685 
            -- Incr ADDR
1686 
            adr := adr + x"00000008";
1687 
            -- Print RD_Value
1688 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1689 
            writeline( log, str );
1690 
 
1691 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
1692 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
1693 
 
1694 
    --
1695 
    -- Compare results
1696 
    write( str, string'("4) Process Results:"));
1697 
    writeline( log, str );
1698 
    --  cmp#0 - constants
1699 
    CMP_CONST   :   for i in 0 to 7 loop
1700 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1701 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1702 
            writeline( log, str );
1703 
            error := error + 1;
1704 
        end if;
1705 
    end loop CMP_CONST;
1706 
    --  cmp#1 - commands
1707 
    CMP_CMD     :   for i in 0 to 7 loop
1708 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1709 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1710 
            writeline( log, str );
1711 
            error := error + 1;
1712 
        end if;
1713 
    end loop CMP_CMD;
1714 
    --  cmp#2 - status
1715 
    CMP_STATUS  :   for i in 0 to 7 loop
1716 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
1717 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1718 
            writeline( log, str );
1719 
            error := error + 1;
1720 
        end if;
1721 
    end loop CMP_STATUS;
1722 
    --  print OK
1723 
    if (error = 0) then
1724 
        write( str, string'("   Results==OK"));
1725 
        writeline( log, str );
1726 
        cnt_ok := cnt_ok + 1;
1727 
    else
1728 
        cnt_error := cnt_error + 1;
1729 
    end if;
1730 
 
1731 
    -- Final Header
1732 
    write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
1733 
    writeline( log, str );  -- upd LOGFILE
1734 
    --
1735 
    -- END
1736 
end test_wb_1;
1737 
---------------------------------------------------------------------------------------------------
1738 
--
1739 
-- My procedure for test WB stuff in Design:
1740 
--  ==> TEST_GEN.WB_CFG_SLAVE
1741 
--
1742 
procedure test_wb_2 (
1743 
                            signal  cmd:    out bh_cmd; --! команда
1744 
                            signal  ret:    in  bh_ret  --! ответ
1745 
                    ) is
1746 
 
1747 
    variable    adr             : std_logic_vector( 31 downto 0 );
1748 
    variable    data32          : std_logic_vector( 31 downto 0 );
1749 
    variable    data64          : std_logic_vector( 63 downto 0 );
1750 
    variable    str             : line;
1751 
 
1752 
    variable    error           : integer:=0;
1753 
    variable    dma_complete    : integer:=0;
1754 
 
1755 
    --
1756 
    --
1757 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1758 
    type wb_cfg_slave_data is record
1759 
        const   :   wb_cfg_slave_value(7 downto 0);
1760 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1761 
        sts     :   wb_cfg_slave_value(7 downto 0);
1762 
    end record;
1763 
    --
1764 
    --
1765 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1766 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1767 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1768 
 
1769 
 
1770 
begin
1771 
    -- Init Header
1772 
    write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
1773 
    writeline( log, str );
1774 
    --
1775 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1776 
    write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1777 
    writeline( log, str );
1778 
    adr     := x"20002000";
1779 
 
1780 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1781 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1782 
            -- PCIE RD
1783 
            data_read64(cmd, ret, adr, data64);
1784 
            -- Put RD_Value to apropriate holder
1785 
            if (i=0) then       -- const
1786 
                st_wb_cfg_slave_data_0.const(j) := data64;
1787 
            elsif (i=1) then    -- cmd
1788 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1789 
            else                -- sts
1790 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1791 
            end if;
1792 
            -- Incr ADDR
1793 
            adr := adr + x"00000008";
1794 
            -- Print RD_Value
1795 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1796 
            writeline( log, str );
1797 
 
1798 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1799 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1800 
 
1801 
    --
1802 
    -- Write
1803 
    write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
1804 
    writeline( log, str );
1805 
    adr     := x"20002000";
1806 
 
1807 
    TEST_GEN_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1808 
        TEST_GEN_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1809 
            -- Prepare WR_Value
1810 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1811 
            -- PCIE WR
1812 
            data_write64(cmd, ret, adr, data64);
1813 
            -- Put WR_Value to apropriate holder
1814 
            if (i=0) then       -- const
1815 
                st_wb_cfg_slave_data_1.const(j) := data64;
1816 
            elsif (i=1) then    -- cmd
1817 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1818 
            else                -- sts
1819 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1820 
            end if;
1821 
            -- Incr ADDR
1822 
            adr := adr + x"00000008";
1823 
            -- Print WR_Value
1824 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1825 
            writeline( log, str );
1826 
 
1827 
        end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
1828 
    end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
1829 
 
1830 
    --
1831 
    -- Read
1832 
    write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1833 
    writeline( log, str );
1834 
    adr     := x"20002000";
1835 
 
1836 
    TEST_GEN_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1837 
        TEST_GEN_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1838 
            -- PCIE RD
1839 
            data_read64(cmd, ret, adr, data64);
1840 
            -- Put RD_Value to apropriate holder
1841 
            if (i=0) then       -- const
1842 
                st_wb_cfg_slave_data_2.const(j) := data64;
1843 
            elsif (i=1) then    -- cmd
1844 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1845 
            else                -- sts
1846 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1847 
            end if;
1848 
            -- Incr ADDR
1849 
            adr := adr + x"00000008";
1850 
            -- Print RD_Value
1851 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1852 
            writeline( log, str );
1853 
 
1854 
        end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
1855 
    end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
1856 
 
1857 
    --
1858 
    -- Compare results
1859 
    write( str, string'("4) Process Results:"));
1860 
    writeline( log, str );
1861 
    --  cmp#0 - constants
1862 
    CMP_CONST   :   for i in 0 to 7 loop
1863 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1864 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1865 
            writeline( log, str );
1866 
            error := error + 1;
1867 
        end if;
1868 
    end loop CMP_CONST;
1869 
    --  cmp#1 - commands
1870 
    CMP_CMD     :   for i in 0 to 7 loop
1871 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1872 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1873 
            writeline( log, str );
1874 
            error := error + 1;
1875 
        end if;
1876 
    end loop CMP_CMD;
1877 
    --  cmp#2 - status
1878 
    CMP_STATUS  :   for i in 0 to 7 loop
1879 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
1880 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1881 
            writeline( log, str );
1882 
            error := error + 1;
1883 
        end if;
1884 
    end loop CMP_STATUS;
1885 
    --  print OK
1886 
    if (error = 0) then
1887 
        write( str, string'("   Results==OK"));
1888 
        writeline( log, str );
1889 
        cnt_ok := cnt_ok + 1;
1890 
    else
1891 
        cnt_error := cnt_error + 1;
1892 
    end if;
1893 
 
1894 
    -- Final Header
1895 
    write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
1896 
    writeline( log, str );  -- upd LOGFILE
1897 
    --
1898 
    -- END
1899 
end test_wb_2;
1900 
---------------------------------------------------------------------------------------------------
1901 
end package     body test_pkg;

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