1 |
2 |
dsmv |
---------------------------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- Title : wb_block_pkg.vhd
|
4 |
|
|
-- Author : Dmitry Smekhov
|
5 |
|
|
-- Company : Instrumental Systems
|
6 |
|
|
-- E-mail : dsmv@insys.ru
|
7 |
|
|
--
|
8 |
|
|
-- Version : 1.0
|
9 |
|
|
---------------------------------------------------------------------------------------------------
|
10 |
|
|
--
|
11 |
|
|
-- Description : Набор функций для доступа к блокам управления на шине WISHBONE
|
12 |
|
|
--
|
13 |
|
|
---------------------------------------------------------------------------------------------------
|
14 |
|
|
--
|
15 |
|
|
-- Version 1.0 01.11.2011
|
16 |
|
|
-- Создан из trd_pkg.vhd v1.0
|
17 |
|
|
--
|
18 |
|
|
---------------------------------------------------------------------------------------------------
|
19 |
|
|
|
20 |
|
|
library ieee;
|
21 |
|
|
use ieee.std_logic_1164.all;
|
22 |
|
|
use ieee.std_logic_arith.all;
|
23 |
|
|
use ieee.std_logic_textio.all;
|
24 |
|
|
use ieee.std_logic_unsigned.all;
|
25 |
|
|
|
26 |
|
|
library work;
|
27 |
|
|
use work.cmd_sim_pkg.all;
|
28 |
|
|
|
29 |
|
|
use std.textio.all;
|
30 |
|
|
use std.textio;
|
31 |
|
|
|
32 |
|
|
---------------------------------------------------------------------------------------------------
|
33 |
|
|
package wb_block_pkg is
|
34 |
|
|
|
35 |
|
|
--
|
36 |
|
|
-- Define TEST_CHECK reg id (addr in 64b cells)
|
37 |
|
|
--
|
38 |
|
|
constant REG_BLOCK_ID : integer:=0;
|
39 |
|
|
constant REG_BLOCK_VER : integer:=1;
|
40 |
|
|
|
41 |
|
|
constant REG_TEST_CHECK_CTRL : integer:=8;
|
42 |
|
|
constant REG_TEST_CHECK_SIZE : integer:=9;
|
43 |
|
|
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#;
|
44 |
|
|
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#;
|
45 |
|
|
|
46 |
|
|
constant REG_TEST_CHECK_BL_RD : integer:=16#10#;
|
47 |
|
|
constant REG_TEST_CHECK_BL_OK : integer:=16#11#;
|
48 |
|
|
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#;
|
49 |
|
|
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#;
|
50 |
|
|
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#;
|
51 |
|
|
--
|
52 |
|
|
-- Define TEST_GEN reg id (addr in 64b cells)
|
53 |
|
|
--
|
54 |
|
|
constant REG_TEST_GEN_CTRL : integer:=8;
|
55 |
|
|
constant REG_TEST_GEN_SIZE : integer:=9;
|
56 |
|
|
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
|
57 |
|
|
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
|
58 |
|
|
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
|
59 |
|
|
--
|
60 |
|
|
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
|
61 |
|
|
--
|
62 |
|
|
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
|
63 |
|
|
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
|
64 |
|
|
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
|
65 |
|
|
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
|
69 |
|
|
procedure wb_block_check_write (
|
70 |
|
|
signal cmd: out bh_cmd; -- команда
|
71 |
|
|
signal ret: in bh_ret; -- ответ
|
72 |
|
|
reg: in integer; -- номер регистра
|
73 |
|
|
data: in std_logic_vector( 31 downto 0 ) -- данные
|
74 |
|
|
);
|
75 |
|
|
|
76 |
|
|
|
77 |
|
|
---- Чтение из регистра блока TEST_CHECK.WB_CFG_SLAVE ----
|
78 |
|
|
procedure wb_block_check_read (
|
79 |
|
|
signal cmd: out bh_cmd; -- команда для ADSP
|
80 |
|
|
signal ret: in bh_ret; -- ответ ADSP
|
81 |
|
|
reg: in integer; -- номер регистра
|
82 |
|
|
data: out std_logic_vector( 31 downto 0 ) -- данные
|
83 |
|
|
);
|
84 |
|
|
|
85 |
|
|
---- Запись в регистр блока TEST_GEN.WB_CFG_SLAVE ----
|
86 |
|
|
procedure wb_block_gen_write (
|
87 |
|
|
signal cmd: out bh_cmd; -- команда
|
88 |
|
|
signal ret: in bh_ret; -- ответ
|
89 |
|
|
reg: in integer; -- номер регистра
|
90 |
|
|
data: in std_logic_vector( 31 downto 0 ) -- данные
|
91 |
|
|
);
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
---- Чтение из регистра блока TEST_GEN.WB_CFG_SLAVE ----
|
95 |
|
|
procedure wb_block_gen_read (
|
96 |
|
|
signal cmd: out bh_cmd; -- команда для ADSP
|
97 |
|
|
signal ret: in bh_ret; -- ответ ADSP
|
98 |
|
|
reg: in integer; -- номер регистра
|
99 |
|
|
data: out std_logic_vector( 31 downto 0 ) -- данные
|
100 |
|
|
);
|
101 |
|
|
|
102 |
|
|
|
103 |
|
|
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
|
104 |
|
|
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector;
|
105 |
|
|
|
106 |
|
|
end package wb_block_pkg;
|
107 |
|
|
---------------------------------------------------------------------------------------------------
|
108 |
|
|
package body wb_block_pkg is
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
---- Запись в регистр блока TEST_CHECK.WB_CFG_SLAVE ----
|
112 |
|
|
procedure wb_block_check_write (
|
113 |
|
|
signal cmd: out bh_cmd; -- команда
|
114 |
|
|
signal ret: in bh_ret; -- ответ
|
115 |
|
|
reg: in integer; -- номер регистра
|
116 |
|
|
data: in std_logic_vector( 31 downto 0 ) -- данные
|
117 |
|
|
) is
|
118 |
|
|
begin
|
119 |
|
|
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
|
120 |
|
|
end;
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
---- Чтение из регистра блока TEST_CHECK ----
|
124 |
|
|
procedure wb_block_check_read (
|
125 |
|
|
signal cmd: out bh_cmd; -- команда для ADSP
|
126 |
|
|
signal ret: in bh_ret; -- ответ ADSP
|
127 |
|
|
reg: in integer; -- номер регистра
|
128 |
|
|
data: out std_logic_vector( 31 downto 0 ) -- данные
|
129 |
|
|
) is
|
130 |
|
|
begin
|
131 |
|
|
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
|
132 |
|
|
end;
|
133 |
|
|
|
134 |
|
|
---- Запись в регистр блока TEST_GEN.WB_CFG_SLAVE ----
|
135 |
|
|
procedure wb_block_gen_write (
|
136 |
|
|
signal cmd: out bh_cmd; -- команда
|
137 |
|
|
signal ret: in bh_ret; -- ответ
|
138 |
|
|
reg: in integer; -- номер регистра
|
139 |
|
|
data: in std_logic_vector( 31 downto 0 ) -- данные
|
140 |
|
|
) is
|
141 |
|
|
begin
|
142 |
|
|
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
|
143 |
|
|
end;
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
---- Чтение из регистра блока TEST_GEN.WB_CFG_SLAVE ----
|
147 |
|
|
procedure wb_block_gen_read (
|
148 |
|
|
signal cmd: out bh_cmd; -- команда для ADSP
|
149 |
|
|
signal ret: in bh_ret; -- ответ ADSP
|
150 |
|
|
reg: in integer; -- номер регистра
|
151 |
|
|
data: out std_logic_vector( 31 downto 0 ) -- данные
|
152 |
|
|
) is
|
153 |
|
|
begin
|
154 |
|
|
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
|
155 |
|
|
end;
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
|
159 |
|
|
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is
|
160 |
|
|
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0');
|
161 |
|
|
begin
|
162 |
|
|
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9);
|
163 |
|
|
return iv_ret;
|
164 |
|
|
end wb_block_check_burst_ctrl_build;
|
165 |
|
|
|
166 |
|
|
|
167 |
|
|
end package body wb_block_pkg;
|
168 |
|
|
|