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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [soft/] [linux/] [common/] [pex/] [pex_board.h] - Blame information for rev 2

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#ifndef __PEX_BOARD_H__
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#define __PEX_BOARD_H__
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#ifndef __BOARD__H__
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    #include "board.h"
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#endif
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#ifndef _STREAMLL_H_
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    #include "streamll.h"
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#endif
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#ifndef _PEXIOCTL_H_
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    #include "pexioctl.h"
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#endif
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#ifndef _AMBPEXREGS_H_
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    #include "ambpexregs.h"
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#endif
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#include <vector>
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#include <string>
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#include <stdint.h>
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//-----------------------------------------------------------------------------
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class dma_memory;
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//-----------------------------------------------------------------------------
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#define MAX_NUMBER_OF_DMACHANNELS 4
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//-----------------------------------------------------------------------------
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class pex_board : public board {
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private:
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    int fd;
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    u32 *bar0;
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    u32 *bar1;
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    struct board_info bi;
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    void core_pause(int ms);
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    dma_memory *m_dma;
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    AMB_MEM_DMA_CHANNEL *m_Descr[MAX_NUMBER_OF_DMACHANNELS];
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    u32                  m_DescrSize[MAX_NUMBER_OF_DMACHANNELS];
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public:
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    pex_board();
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    virtual ~pex_board();
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    int core_open(const char *name);
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    int core_init();
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    int core_reset();
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    int core_close();
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    int core_load_dsp();
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    int core_load_pld();
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    int core_board_info();
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    int core_pld_info();
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    int core_resource();
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    u32 core_alloc(int DmaChan, BRDctrl_StreamCBufAlloc* sSCA);
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    u32 core_allocate_memory(int DmaChan, void** pBuf, u32 blkSize, u32 blkNum, u32 isSysMem, u32 dir, u32 addr);
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    u32 core_free_memory(int DmaChan);
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    u32 core_start_dma(int DmaChan, int IsCycling);
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    u32 core_stop_dma(int DmaChan);
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    u32 core_state_dma(int DmaChan, u32 msTimeout, int& state, u32& blkNum);
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    u32 core_wait_buffer(int DmaChan, u32 msTimeout);
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    u32 core_wait_block(int DmaChan, u32 msTimeout);
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    u32 core_reset_fifo(int DmaChan);
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    u32 core_set_local_addr(int DmaChan, u32 addr);
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    u32 core_adjust(int DmaChan, u32 mode);
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    u32 core_done(int DmaChan, u32 blockNumber);
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    u32 core_reg_peek_dir( u32 trd, u32 reg );
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    u32 core_reg_peek_ind( u32 trd, u32 reg );
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    void core_reg_poke_dir( u32 trd, u32 reg, u32 val );
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    void core_reg_poke_ind( u32 trd, u32 reg, u32 val );
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    u32  core_bar0_read( u32 offset );
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    void core_bar0_write( u32 offset, u32 val );
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    u32  core_bar1_read( u32 offset );
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    void core_bar1_write( u32 offset, u32 val );
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    void core_block_write( u32 nb, u32 reg, u32 val );
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    u32  core_block_read( u32 nb, u32 reg );
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};
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#endif //__PEX_BOARD_H__

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