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[/] [pcie_ds_dma/] [trunk/] [soft/] [linux/] [driver/] [pexdrv/] [ambpexregs.h] - Blame information for rev 2

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//****************** File AmbpexRegs.h *********************************
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// AMBPEX card definitions
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//
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//      Copyright (c) 2007, Instrumental Systems,Corp.
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//  Written by Dorokhin Andrey
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//
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//  History:
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//  19-03-07 - builded
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//
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//*******************************************************************
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#ifndef _AMBPEXREGS_H_
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#define _AMBPEXREGS_H_
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#ifndef __KERNEL__
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#include <stdint.h>
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t  u8;
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#endif
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#define PCI_EXPROM_SIZE 512
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#define PE_MAIN_ADDR 0x000
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#define PE_FIFO_ADDR 0x100
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#define PE_EXT_FIFO_ADDR 0x400
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#define PE_MAIN_ID              0x0013
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#define PE_FIFO_ID              0x0014
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#define PE_EXT_FIFO_ID  0x0018
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// PCI-Express Main block Registers Layout
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typedef volatile struct _PE_MAIN_REGISTERS {
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    u32   BlockId;      // 0 (0x00) Control MAIN block identification register (only read)
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    u32   BlockVer;     // 1 (0x04) Control MAIN block version register (only read)
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    u32   DeviceId;     // 2 (0x08) Device identification register (only read)
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    u32   DeviceRev;    // 3 (0x0C) Device revision register (only read)
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    u32   PldVersion;   // 4 (0x10) PLD version register (only read)
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    u32   BlockNum;     // 5 (0x14) Number of control blocks (only read)
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    u32   DpramOffset;// 6 (0x18) (only read)
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    u32   DpramSize;    // 7 (0x1C) (only read)
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    u32   BrdMode;      // 8 (0x20) Board control register
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    u32   IrqMask;      // 9 (0x24) Interrupt mask register
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    u32   IrqInv;               // 10(0x0A) (0x28) Interrupt inversion register
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    u32   Leds;         // 11(0x0B) (0x2C) LEDs control register
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    u32   Reg12;                // 12(0x0C) (0x30) REG12 - Reserved space
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    u32   PSynx;                // 13(0x0D) (0x34) not use
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    u32   Reg14;                // 14(0x0E) (0x38) REG14 - Reserved space
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    u32   Reg15;                // 15(0x0F) (0x3C) REG15 - Reserved space
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    u32   BrdStatus;    // 16(0x10) (0x40) Board status register
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    u32   Reg17;                // 17(0x11) (0x44) REG17 - Reserved space
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    u32   Reg18;                // 18(0x12) (0x48) REG18 - Reserved space
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    u32   Sem0;         // 19(0x13) (0x4C) not use
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    u32   PldConf;      // 20(0x14) (0x50) not use
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    u32   Reg21;                // 21(0x15) (0x54) REG21 - Reserved space
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    u32   SpdCtrl;      // 22(0x16) (0x58) SPD&ADM_ROM Access Control register
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    u32   SpdAddr;      // 23(0x17) (0x5C) Memory address register
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    u32   SpdDataLo;    // 24(0x18) (0x60) Memory low data register
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    u32   SpdDataHi;    // 25(0x19) (0x64) Memory high address register
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    u32   LbData;               // 26(0x1A) (0x68) Loopback mode data register
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    u32   Reg27;                // 27(0x1B) (0x6C) REG27 - Reserved space
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    u32   JtagCnt;      // 28(0x1C) (0x70) number of shift bit register
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    u32   JtagTms;      // 29(0x1D) (0x74) signal TMS register
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    u32   JtagTdi;      // 30(0x1E) (0x78) signal TDI register
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    u32   JtagTdo;      // 31(0x1F) (0x7C) signal TDO register
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} PE_MAIN_REGISTERS, *PPE_MAIN_REGISTERS;
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// Numbers of PCI-Express Main block Registers
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typedef enum _PE_MAIN_ADDR_REG {
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    PEMAINadr_BLOCK_ID          = 0x00, // 0x00
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    PEMAINadr_BLOCK_VER         = 0x08, // 0x01
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    PEMAINadr_DEVICE_ID         = 0x10, // 0x02
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    PEMAINadr_DEVICE_REV        = 0x18, // 0x03
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    PEMAINadr_PLD_VER           = 0x20, // 0x04
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    PEMAINadr_BLOCK_CNT         = 0x28, // 0x05
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    PEMAINadr_DPRAM_OFFSET      = 0x30, // 0x06
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    PEMAINadr_DPRAM_SIZE        = 0x38, // 0x07
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    PEMAINadr_BRD_MODE          = 0x40, // 0x08
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    PEMAINadr_IRQ_MASK          = 0x48, // 0x09
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    PEMAINadr_IRQ_INV           = 0x50, // 0x0A
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    PEMAINadr_LEDS                      = 0x58, // 0x0B
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    PEMAINadr_BRD_STATUS        = 0x80, // 0x10
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    PEMAINadr_SPD_CTRL          = 0xB0, // 0x16
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    PEMAINadr_SPD_ADDR          = 0xB8, // 0x17
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    PEMAINadr_SPD_DATAL         = 0xC0, // 0x18
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    PEMAINadr_SPD_DATAH         = 0xC8, // 0x19
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    PEMAINadr_LB_DATA           = 0xD0, // 0x1A
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    PEMAINadr_JTAG_CNT          = 0xE0, // 0x1C
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    PEMAINadr_JTAG_TMS          = 0xE8, // 0x1D
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    PEMAINadr_JTAG_TDI          = 0xF0, // 0x1E
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    PEMAINadr_JTAG_TDO          = 0xF8, // 0x1F
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} PE_MAIN_ADDR_REG;
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// PCI-Express FIFO block Registers Layout
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typedef volatile struct _PE_FIFO_REGISTERS {
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    u32   BlockId;      // 0 (0x00) Control FIFO block identification register (only read)
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    u32   BlockVer;     // 1 (0x04) Control FIFO block version register (only read)
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    u32   FifoId;               // 2 (0x08) FIFO identification register (only read)
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    u32   FifoNumber;   // 3 (0x0C) FIFO number register (only read)
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    u32   DmaSize;      // 4 (0x10) DMA size register (only read) - NOT use by EXT
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    u32   Reg5;         // 5 (0x14) REG5 - Reserved space
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    u32   Reg6;         // 6 (0x18) REG6 - Reserved space
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    u32   Reg7;         // 7 (0x1C) REG7 - Reserved space
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    u32   FifoCtlr;     // 8 (0x20) FIFO control register - NOT use by EXT
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    u32   DmaCtlr;      // 9 (0x24) DMA control register
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    u32   Reg10;                // 10(0x0A) (0x28) REG10 - Reserved space
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    u32   Reg11;                // 11(0x0B) (0x2C) REG11 - Reserved space
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    u32   Reg12;                // 12(0x0C) (0x30) REG12 - Reserved space
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    u32   Reg13;                // 13(0x0D) (0x34) REG13 - Reserved space
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    u32   Reg14;                // 14(0x0E) (0x38) REG14 - Reserved space
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    u32   Reg15;                // 15(0x0F) (0x3C) REG15 - Reserved space
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    u32   FifoStatus;   // 16(0x10) (0x40) FIFO status register
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    u32   FlagClr;      // 17(0x11) (0x44) Flags clear register
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    u32   Reg18;                // 18(0x12) (0x48) REG18 - Reserved space
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    u32   Reg19;                // 19(0x13) (0x4C) REG19 - Reserved space
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    u32   PciAddrLo;    // 20(0x14) (0x50) PCI address (low part) register
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    u32   PciAddrHi;    // 21(0x15) (0x54) PCI address (high part) register
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    u32   PciSize;      // 22(0x16) (0x58) block size register - NOT use by EXT
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    u32   LocalAddr;    // 23(0x17) (0x5C) Local address register
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    u32   Reg24;                // 24(0x18) (0x60) REG24 - Reserved space
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    u32   Reg25;                // 25(0x19) (0x64) REG25 - Reserved space
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    u32   Reg26;                // 26(0x1A) (0x68) REG26 - Reserved space
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    u32   Reg27;                // 27(0x1B) (0x6C) REG27 - Reserved space
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    u32   Reg28;                // 28(0x1C) (0x70) REG28 - Reserved space
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    u32   Reg29;                // 29(0x1D) (0x74) REG29 - Reserved space
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    u32   Reg30;                // 30(0x1E) (0x78) REG30 - Reserved space
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    u32   Reg31;                // 31(0x1F) (0x7C) REG31 - Reserved space
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} PE_FIFO_REGISTERS, *PPE_FIFO_REGISTERS;
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// Numbers of PCI-Express FIFO block Registers
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typedef enum _PE_FIFO_ADDR_REG {
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    PEFIFOadr_BLOCK_ID          = 0x00, // 0x00
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    PEFIFOadr_BLOCK_VER         = 0x08, // 0x01
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    PEFIFOadr_FIFO_ID           = 0x10, // 0x02
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    PEFIFOadr_FIFO_NUM          = 0x18, // 0x03
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    PEFIFOadr_DMA_SIZE          = 0x20, // 0x04 - RESOURCE by EXT
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    PEFIFOadr_FIFO_CTRL         = 0x40, // 0x08 - DMA_MODE by EXT
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    PEFIFOadr_DMA_CTRL          = 0x48, // 0x09
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    PEFIFOadr_FIFO_STATUS       = 0x80, // 0x10
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    PEFIFOadr_FLAG_CLR          = 0x88, // 0x11
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    PEFIFOadr_PCI_ADDRL         = 0xA0, // 0x14
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    PEFIFOadr_PCI_ADDRH         = 0xA8, // 0x15
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    PEFIFOadr_PCI_SIZE          = 0xB0, // 0x16 - NOT use by EXT
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    PEFIFOadr_LOCAL_ADR         = 0xB8, // 0x17
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} PE_FIFO_ADDR_REG;
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// Board Control register 0x40 (PE_MAIN)
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typedef union _BRD_MODE {
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    u16 AsWhole; // Board Control Register as a Whole Word
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    struct { // Board Control Register as Bit Pattern
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        u16     RstClkOut       : 1, // Output Clock Reset for ADMPLD
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        Sleep           : 1, // Sleep mode for ADMPLD
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        RstClkIn        : 1, // Input Clock Reset for ADMPLD
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        Reset           : 1, // Reset for ADMPLD
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        RegLoop         : 1, // Register operation loopback mode
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        Res                     : 3, // Reserved
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        OutFlags        : 8; // Output Flags
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    } ByBits;
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} BRD_MODE, *PBRD_MODE;
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// Board Status register 0x80 (PE_MAIN)
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typedef union _BRD_STATUS {
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    u16 AsWhole; // Board Status Register as a Whole Word
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    struct { // Board Status Register as Bit Pattern
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        u16     SlvDcm          : 1, // Capture Input Clock from ADMPLD
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        NotUse          : 7, //
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        InFlags         : 8; // Input Flags
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    } ByBits;
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} BRD_STATUS, *PBRD_STATUS;
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// SPD Control register 0xB0 (PE_MAIN)
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typedef union _SPD_CTRL {
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    u16 AsWhole; // SPD Control Register as a Whole Word
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    struct { // SPD Control Register as Bit Pattern
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        u16     ReadOp          : 1, // Read Operation
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        WriteOp         : 1, // Write Operation
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        Res                     : 2, // Reserved
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        WriteEn         : 1, // Write Enable
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        WriteDis        : 1, // Read Disable
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        Res1            : 2, // Reserved
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        SpdId           : 3, // SPD Identification
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        Res2            : 3, // Reserved
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        Sema            : 1, // Semaphor
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        Ready           : 1; // Data Ready
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    } ByBits;
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} SPD_CTRL, *PSPD_CTRL;
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// FIFO ID register 0x10 (PE_FIFO)
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typedef union _FIFO_ID {
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    u16 AsWhole; // FIFO ID Register as a Whole Word
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    struct { // FIFO ID Register as Bit Pattern
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        u16     Size            : 12, // FIFO size (32-bit words)
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        Dir                     : 4; // DMA direction
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    } ByBits;
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} FIFO_ID, *PFIFO_ID;
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// FIFO Control register 0x40 (PE_FIFO)
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typedef union _FIFO_CTRL {
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    u16 AsWhole; // FIFO Control Register as a Whole Word
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    struct { // FIFO Control Register as Bit Pattern
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        u16     Reset           : 1, // FIFO Reset
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        DrqEn           : 1, // DMA Request enable
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        Loopback        : 1, // Not use
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        TstCnt          : 1, // 32-bit Test Counter enable
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        Res                     : 12; // Reserved
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    } ByBits;
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} FIFO_CTRL, *PFIFO_CTRL;
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// DMA Mode register 0x40 (PE_EXT_FIFO)
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typedef union _DMA_MODE_EXT {
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    u16 AsWhole; // DMA Mode Register as a Whole Word
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    struct { // FIFO Control Register as Bit Pattern
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        u16     SGModeEnbl      : 1, // 1 - Scatter/Gather mode enable
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        DemandMode      : 1, // 1 - always
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        Dir                     : 1, // DMA direction
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        Res0            : 2, // Reserved
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        IntEnbl         : 1, // Interrrupt enable (End of DMA)
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        Res                     : 10; // Reserved
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    } ByBits;
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} DMA_MODE_EXT, *PDMA_MODE_EXT;
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// DMA Control register 0x48 (PE_FIFO)
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typedef union _DMA_CTRL {
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    u16 AsWhole; // DMA Control Register as a Whole Word
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    struct { // DMA Control Register as Bit Pattern
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        u16     Start           : 1, // DMA start
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        Stop            : 1, // DMA stop
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        SGEnbl          : 1, // Scatter/Gather mode enable
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        Res0            : 1, // Reserved
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        DemandMode      : 1, // 1 - always
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        IntEnbl         : 1, // Interrrupt enable (End of DMA)
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        Res                     : 10; // Reserved
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    } ByBits;
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} DMA_CTRL, *PDMA_CTRL;
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// DMA Control register 0x48 (PE_EXT_FIFO)
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typedef union _DMA_CTRL_EXT {
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    u16 AsWhole; // DMA Control Register as a Whole Word
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    struct { // DMA Control Register as Bit Pattern
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        u16     Start           : 1, // DMA start/stop
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        Res0            : 2, // Reserved
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        Pause           : 1, // DMA pause
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        ResetFIFO       : 1, // FIFO Reset
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        Res                     : 11; // Reserved
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    } ByBits;
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} DMA_CTRL_EXT, *PDMA_CTRL_EXT;
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// FIFO Status register 0x80 (PE_FIFO)
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typedef union _FIFO_STATUS {
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    u16 AsWhole; // FIFO Status Register as a Whole Word
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    struct { // FIFO Status Register as Bit Pattern
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        u16     DmaStat : 4, // DMA Status
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        DmaEot          : 1, // DMA block Complete (End of Transfer)
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        SGEot           : 1, // Scatter/Gather End of Transfer (all blocks complete)
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        IntErr          : 1, // not serviced of interrrupt - ERROR!!! block leave out!!!
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        IntRql          : 1, // Interrrupt request
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        //                              DmaErr          : 1, // DMA channel error
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        DscrErr         : 1, // Descriptor error
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        NotUse          : 3, // Not Use
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        Sign            : 4; // Signature (0x0A)
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    } ByBits;
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} FIFO_STATUS, *PFIFO_STATUS;
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// Numbers of Tetrad Registers
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typedef enum _TETRAD_REG {
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    TRDadr_STATUS,
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    TRDadr_DATA,
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    TRDadr_CMD_ADR,
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    TRDadr_CMD_DATA
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} TETRAD_REG, *PTETRAD_REG;
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typedef enum _AmbStatusRegBits {
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    AMB_statCMDRDY = 1
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                 } AmbStatusRegBits;
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// Main Select of Interrupts & DMA channels Register (MODE0 +16)
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typedef union _MAIN_SELX {
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    u32 AsWhole; // Board Mode Register as a Whole Word
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    struct { // Mode Register as Bit Pattern
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        u32     IrqNum  : 4, // Interrupt number
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        Res1    : 4, // Reserved
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        DmaTetr : 4, // Tetrad number for DMA channel X
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        DrqEnbl : 1, // DMA request enable
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        DmaMode : 3; // DMA mode
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    } ByBits;
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} MAIN_SELX, *PMAIN_SELX;
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#define REG_SIZE        0x00001000              // register size
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#define TETRAD_SIZE     0x00004000              // tetrad size
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#define ADM_SIZE        0x00020000              // ADM interface size
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// Numbers of Registers
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typedef enum _AMB_AUX_NUM_REG {
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    AUXnr_ADM_PLD_DATA                  = 0,
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    AUXnr_ADM_PLD_MODE_STATUS   = 1,
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    AUXnr_SUBMOD_ID_ROM                 = 2,
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    AUXnr_DSP_PLD_DATA                  = 3,
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    AUXnr_DSP_PLD_MODE_STATUS   = 4,
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} AMB_AUX_NUM_REG;
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#endif //_AMBPEXREGS_H_

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