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[/] [pcie_ds_dma/] [trunk/] [soft/] [linux/] [driver/] [pexdrv/] [ambpexregs.h] - Blame information for rev 41

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//****************** File AmbpexRegs.h *********************************
// AMBPEX card definitions
//
//      Copyright (c) 2007, Instrumental Systems,Corp.
//  Written by Dorokhin Andrey
//
//  History:
//  19-03-07 - builded
//
//*******************************************************************
 
#ifndef _AMBPEXREGS_H_
#define _AMBPEXREGS_H_
 
#ifndef __KERNEL__
#include <stdint.h>
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t  u8;
#endif
 
#define PCI_EXPROM_SIZE 512
 
#define PE_MAIN_ADDR 0x000
#define PE_FIFO_ADDR 0x100
#define PE_EXT_FIFO_ADDR 0x400
 
#define PE_MAIN_ID              0x0013
#define PE_FIFO_ID              0x0014
#define PE_EXT_FIFO_ID  0x0018
 
// PCI-Express Main block Registers Layout
typedef volatile struct _PE_MAIN_REGISTERS {
    u32   BlockId;      // 0 (0x00) Control MAIN block identification register (only read)
    u32   BlockVer;     // 1 (0x04) Control MAIN block version register (only read)
    u32   DeviceId;     // 2 (0x08) Device identification register (only read)
    u32   DeviceRev;    // 3 (0x0C) Device revision register (only read)
    u32   PldVersion;   // 4 (0x10) PLD version register (only read)
    u32   BlockNum;     // 5 (0x14) Number of control blocks (only read)
    u32   DpramOffset;// 6 (0x18) (only read)
    u32   DpramSize;    // 7 (0x1C) (only read)
    u32   BrdMode;      // 8 (0x20) Board control register
    u32   IrqMask;      // 9 (0x24) Interrupt mask register
    u32   IrqInv;               // 10(0x0A) (0x28) Interrupt inversion register
    u32   Leds;         // 11(0x0B) (0x2C) LEDs control register
    u32   Reg12;                // 12(0x0C) (0x30) REG12 - Reserved space
    u32   PSynx;                // 13(0x0D) (0x34) not use
    u32   Reg14;                // 14(0x0E) (0x38) REG14 - Reserved space
    u32   Reg15;                // 15(0x0F) (0x3C) REG15 - Reserved space
    u32   BrdStatus;    // 16(0x10) (0x40) Board status register
    u32   Reg17;                // 17(0x11) (0x44) REG17 - Reserved space
    u32   Reg18;                // 18(0x12) (0x48) REG18 - Reserved space
    u32   Sem0;         // 19(0x13) (0x4C) not use
    u32   PldConf;      // 20(0x14) (0x50) not use
    u32   Reg21;                // 21(0x15) (0x54) REG21 - Reserved space
    u32   SpdCtrl;      // 22(0x16) (0x58) SPD&ADM_ROM Access Control register
    u32   SpdAddr;      // 23(0x17) (0x5C) Memory address register
    u32   SpdDataLo;    // 24(0x18) (0x60) Memory low data register
    u32   SpdDataHi;    // 25(0x19) (0x64) Memory high address register
    u32   LbData;               // 26(0x1A) (0x68) Loopback mode data register
    u32   Reg27;                // 27(0x1B) (0x6C) REG27 - Reserved space
    u32   JtagCnt;      // 28(0x1C) (0x70) number of shift bit register
    u32   JtagTms;      // 29(0x1D) (0x74) signal TMS register
    u32   JtagTdi;      // 30(0x1E) (0x78) signal TDI register
    u32   JtagTdo;      // 31(0x1F) (0x7C) signal TDO register
} PE_MAIN_REGISTERS, *PPE_MAIN_REGISTERS;
 
// Numbers of PCI-Express Main block Registers
typedef enum _PE_MAIN_ADDR_REG {
    PEMAINadr_BLOCK_ID          = 0x00, // 0x00
    PEMAINadr_BLOCK_VER         = 0x08, // 0x01
    PEMAINadr_DEVICE_ID         = 0x10, // 0x02
    PEMAINadr_DEVICE_REV        = 0x18, // 0x03
    PEMAINadr_PLD_VER           = 0x20, // 0x04
    PEMAINadr_BLOCK_CNT         = 0x28, // 0x05
    PEMAINadr_DPRAM_OFFSET      = 0x30, // 0x06
    PEMAINadr_DPRAM_SIZE        = 0x38, // 0x07
    PEMAINadr_BRD_MODE          = 0x40, // 0x08
    PEMAINadr_IRQ_MASK          = 0x48, // 0x09
    PEMAINadr_IRQ_INV           = 0x50, // 0x0A
    PEMAINadr_LEDS                      = 0x58, // 0x0B
    PEMAINadr_BRD_STATUS        = 0x80, // 0x10
    PEMAINadr_SPD_CTRL          = 0xB0, // 0x16
    PEMAINadr_SPD_ADDR          = 0xB8, // 0x17
    PEMAINadr_SPD_DATAL         = 0xC0, // 0x18
    PEMAINadr_SPD_DATAH         = 0xC8, // 0x19
    PEMAINadr_LB_DATA           = 0xD0, // 0x1A
    PEMAINadr_JTAG_CNT          = 0xE0, // 0x1C
    PEMAINadr_JTAG_TMS          = 0xE8, // 0x1D
    PEMAINadr_JTAG_TDI          = 0xF0, // 0x1E
    PEMAINadr_JTAG_TDO          = 0xF8, // 0x1F
} PE_MAIN_ADDR_REG;
 
// PCI-Express FIFO block Registers Layout
typedef volatile struct _PE_FIFO_REGISTERS {
    u32   BlockId;      // 0 (0x00) Control FIFO block identification register (only read)
    u32   BlockVer;     // 1 (0x04) Control FIFO block version register (only read)
    u32   FifoId;               // 2 (0x08) FIFO identification register (only read)
    u32   FifoNumber;   // 3 (0x0C) FIFO number register (only read)
    u32   DmaSize;      // 4 (0x10) DMA size register (only read) - NOT use by EXT
    u32   Reg5;         // 5 (0x14) REG5 - Reserved space
    u32   Reg6;         // 6 (0x18) REG6 - Reserved space
    u32   Reg7;         // 7 (0x1C) REG7 - Reserved space
    u32   FifoCtlr;     // 8 (0x20) FIFO control register - NOT use by EXT
    u32   DmaCtlr;      // 9 (0x24) DMA control register
    u32   Reg10;                // 10(0x0A) (0x28) REG10 - Reserved space
    u32   Reg11;                // 11(0x0B) (0x2C) REG11 - Reserved space
    u32   Reg12;                // 12(0x0C) (0x30) REG12 - Reserved space
    u32   Reg13;                // 13(0x0D) (0x34) REG13 - Reserved space
    u32   Reg14;                // 14(0x0E) (0x38) REG14 - Reserved space
    u32   Reg15;                // 15(0x0F) (0x3C) REG15 - Reserved space
    u32   FifoStatus;   // 16(0x10) (0x40) FIFO status register
    u32   FlagClr;      // 17(0x11) (0x44) Flags clear register
    u32   Reg18;                // 18(0x12) (0x48) REG18 - Reserved space
    u32   Reg19;                // 19(0x13) (0x4C) REG19 - Reserved space
    u32   PciAddrLo;    // 20(0x14) (0x50) PCI address (low part) register
    u32   PciAddrHi;    // 21(0x15) (0x54) PCI address (high part) register
    u32   PciSize;      // 22(0x16) (0x58) block size register - NOT use by EXT
    u32   LocalAddr;    // 23(0x17) (0x5C) Local address register
    u32   Reg24;                // 24(0x18) (0x60) REG24 - Reserved space
    u32   Reg25;                // 25(0x19) (0x64) REG25 - Reserved space
    u32   Reg26;                // 26(0x1A) (0x68) REG26 - Reserved space
    u32   Reg27;                // 27(0x1B) (0x6C) REG27 - Reserved space
    u32   Reg28;                // 28(0x1C) (0x70) REG28 - Reserved space
    u32   Reg29;                // 29(0x1D) (0x74) REG29 - Reserved space
    u32   Reg30;                // 30(0x1E) (0x78) REG30 - Reserved space
    u32   Reg31;                // 31(0x1F) (0x7C) REG31 - Reserved space
} PE_FIFO_REGISTERS, *PPE_FIFO_REGISTERS;
 
// Numbers of PCI-Express FIFO block Registers
typedef enum _PE_FIFO_ADDR_REG {
    PEFIFOadr_BLOCK_ID          = 0x00, // 0x00
    PEFIFOadr_BLOCK_VER         = 0x08, // 0x01
    PEFIFOadr_FIFO_ID           = 0x10, // 0x02
    PEFIFOadr_FIFO_NUM          = 0x18, // 0x03
    PEFIFOadr_DMA_SIZE          = 0x20, // 0x04 - RESOURCE by EXT
    PEFIFOadr_FIFO_CTRL         = 0x40, // 0x08 - DMA_MODE by EXT
    PEFIFOadr_DMA_CTRL          = 0x48, // 0x09
    PEFIFOadr_FIFO_STATUS       = 0x80, // 0x10
    PEFIFOadr_FLAG_CLR          = 0x88, // 0x11
    PEFIFOadr_PCI_ADDRL         = 0xA0, // 0x14
    PEFIFOadr_PCI_ADDRH         = 0xA8, // 0x15
    PEFIFOadr_PCI_SIZE          = 0xB0, // 0x16 - NOT use by EXT
    PEFIFOadr_LOCAL_ADR         = 0xB8, // 0x17
} PE_FIFO_ADDR_REG;
 
// Board Control register 0x40 (PE_MAIN)
typedef union _BRD_MODE {
    u16 AsWhole; // Board Control Register as a Whole Word
    struct { // Board Control Register as Bit Pattern
        u16     RstClkOut       : 1, // Output Clock Reset for ADMPLD
        Sleep           : 1, // Sleep mode for ADMPLD
        RstClkIn        : 1, // Input Clock Reset for ADMPLD
        Reset           : 1, // Reset for ADMPLD
        RegLoop         : 1, // Register operation loopback mode
        Res                     : 3, // Reserved
        OutFlags        : 8; // Output Flags
    } ByBits;
} BRD_MODE, *PBRD_MODE;
 
// Board Status register 0x80 (PE_MAIN)
typedef union _BRD_STATUS {
    u16 AsWhole; // Board Status Register as a Whole Word
    struct { // Board Status Register as Bit Pattern
        u16     SlvDcm          : 1, // Capture Input Clock from ADMPLD
        NotUse          : 7, //
        InFlags         : 8; // Input Flags
    } ByBits;
} BRD_STATUS, *PBRD_STATUS;
 
// SPD Control register 0xB0 (PE_MAIN)
typedef union _SPD_CTRL {
    u16 AsWhole; // SPD Control Register as a Whole Word
    struct { // SPD Control Register as Bit Pattern
        u16     ReadOp          : 1, // Read Operation
        WriteOp         : 1, // Write Operation
        Res                     : 2, // Reserved
        WriteEn         : 1, // Write Enable
        WriteDis        : 1, // Read Disable
        Res1            : 2, // Reserved
        SpdId           : 3, // SPD Identification
        Res2            : 3, // Reserved
        Sema            : 1, // Semaphor
        Ready           : 1; // Data Ready
    } ByBits;
} SPD_CTRL, *PSPD_CTRL;
 
// FIFO ID register 0x10 (PE_FIFO)
typedef union _FIFO_ID {
    u16 AsWhole; // FIFO ID Register as a Whole Word
    struct { // FIFO ID Register as Bit Pattern
        u16     Size            : 12, // FIFO size (32-bit words)
        Dir                     : 4; // DMA direction
    } ByBits;
} FIFO_ID, *PFIFO_ID;
 
// FIFO Control register 0x40 (PE_FIFO)
typedef union _FIFO_CTRL {
    u16 AsWhole; // FIFO Control Register as a Whole Word
    struct { // FIFO Control Register as Bit Pattern
        u16     Reset           : 1, // FIFO Reset
        DrqEn           : 1, // DMA Request enable
        Loopback        : 1, // Not use
        TstCnt          : 1, // 32-bit Test Counter enable
        Res                     : 12; // Reserved
    } ByBits;
} FIFO_CTRL, *PFIFO_CTRL;
 
// DMA Mode register 0x40 (PE_EXT_FIFO)
typedef union _DMA_MODE_EXT {
    u16 AsWhole; // DMA Mode Register as a Whole Word
    struct { // FIFO Control Register as Bit Pattern
        u16     SGModeEnbl      : 1, // 1 - Scatter/Gather mode enable
        DemandMode      : 1, // 1 - always
        Dir                     : 1, // DMA direction
        Res0            : 2, // Reserved
        IntEnbl         : 1, // Interrrupt enable (End of DMA)
        Res                     : 10; // Reserved
    } ByBits;
} DMA_MODE_EXT, *PDMA_MODE_EXT;
 
// DMA Control register 0x48 (PE_FIFO)
typedef union _DMA_CTRL {
    u16 AsWhole; // DMA Control Register as a Whole Word
    struct { // DMA Control Register as Bit Pattern
        u16     Start           : 1, // DMA start
        Stop            : 1, // DMA stop
        SGEnbl          : 1, // Scatter/Gather mode enable
        Res0            : 1, // Reserved
        DemandMode      : 1, // 1 - always
        IntEnbl         : 1, // Interrrupt enable (End of DMA)
        Res                     : 10; // Reserved
    } ByBits;
} DMA_CTRL, *PDMA_CTRL;
 
// DMA Control register 0x48 (PE_EXT_FIFO)
typedef union _DMA_CTRL_EXT {
    u16 AsWhole; // DMA Control Register as a Whole Word
    struct { // DMA Control Register as Bit Pattern
        u16     Start           : 1, // DMA start/stop
        Res0            : 2, // Reserved
        Pause           : 1, // DMA pause
        ResetFIFO       : 1, // FIFO Reset
        Res                     : 11; // Reserved
    } ByBits;
} DMA_CTRL_EXT, *PDMA_CTRL_EXT;
 
// FIFO Status register 0x80 (PE_FIFO)
typedef union _FIFO_STATUS {
    u16 AsWhole; // FIFO Status Register as a Whole Word
    struct { // FIFO Status Register as Bit Pattern
        u16     DmaStat : 4, // DMA Status
        DmaEot          : 1, // DMA block Complete (End of Transfer)
        SGEot           : 1, // Scatter/Gather End of Transfer (all blocks complete)
        IntErr          : 1, // not serviced of interrrupt - ERROR!!! block leave out!!!
        IntRql          : 1, // Interrrupt request
        //                              DmaErr          : 1, // DMA channel error
        DscrErr         : 1, // Descriptor error
        NotUse          : 3, // Not Use
        Sign            : 4; // Signature (0x0A)
    } ByBits;
} FIFO_STATUS, *PFIFO_STATUS;
 
// Numbers of Tetrad Registers
typedef enum _TETRAD_REG {
    TRDadr_STATUS,
    TRDadr_DATA,
    TRDadr_CMD_ADR,
    TRDadr_CMD_DATA
} TETRAD_REG, *PTETRAD_REG;
 
typedef enum _AmbStatusRegBits {
    AMB_statCMDRDY = 1
                 } AmbStatusRegBits;
 
// Main Select of Interrupts & DMA channels Register (MODE0 +16)
typedef union _MAIN_SELX {
    u32 AsWhole; // Board Mode Register as a Whole Word
    struct { // Mode Register as Bit Pattern
        u32     IrqNum  : 4, // Interrupt number
        Res1    : 4, // Reserved
        DmaTetr : 4, // Tetrad number for DMA channel X
        DrqEnbl : 1, // DMA request enable
        DmaMode : 3; // DMA mode
    } ByBits;
} MAIN_SELX, *PMAIN_SELX;
 
#define REG_SIZE        0x00001000              // register size
#define TETRAD_SIZE     0x00004000              // tetrad size
#define ADM_SIZE        0x00020000              // ADM interface size
 
// Numbers of Registers
typedef enum _AMB_AUX_NUM_REG {
    AUXnr_ADM_PLD_DATA                  = 0,
    AUXnr_ADM_PLD_MODE_STATUS   = 1,
    AUXnr_SUBMOD_ID_ROM                 = 2,
    AUXnr_DSP_PLD_DATA                  = 3,
    AUXnr_DSP_PLD_MODE_STATUS   = 4,
} AMB_AUX_NUM_REG;
 
#endif //_AMBPEXREGS_H_

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [soft/] [linux/] [driver/] [pexdrv/] [ambpexregs.h] - Blame information for rev 41

Line No.	Rev	Author	Line
1	2	dsmv	`//**************** File AmbpexRegs.h *******************************`
2			`// AMBPEX card definitions`
3			`//`
4			`// Copyright (c) 2007, Instrumental Systems,Corp.`
5			`// Written by Dorokhin Andrey`
6			`//`
7			`// History:`
8			`// 19-03-07 - builded`
9			`//`
10			`//*******************************************************************`
11
12			`#ifndef _AMBPEXREGS_H_`
13			`#define _AMBPEXREGS_H_`
14
15			`#ifndef __KERNEL__`
16			`#include <stdint.h>`
17			`typedef uint64_t u64;`
18			`typedef uint32_t u32;`
19			`typedef uint16_t u16;`
20			`typedef uint8_t u8;`
21			`#endif`
22
23			`#define PCI_EXPROM_SIZE 512`
24
25			`#define PE_MAIN_ADDR 0x000`
26			`#define PE_FIFO_ADDR 0x100`
27			`#define PE_EXT_FIFO_ADDR 0x400`
28
29			`#define PE_MAIN_ID 0x0013`
30			`#define PE_FIFO_ID 0x0014`
31			`#define PE_EXT_FIFO_ID 0x0018`
32
33			`// PCI-Express Main block Registers Layout`
34			`typedef volatile struct _PE_MAIN_REGISTERS {`
35			`u32 BlockId; // 0 (0x00) Control MAIN block identification register (only read)`
36			`u32 BlockVer; // 1 (0x04) Control MAIN block version register (only read)`
37			`u32 DeviceId; // 2 (0x08) Device identification register (only read)`
38			`u32 DeviceRev; // 3 (0x0C) Device revision register (only read)`
39			`u32 PldVersion; // 4 (0x10) PLD version register (only read)`
40			`u32 BlockNum; // 5 (0x14) Number of control blocks (only read)`
41			`u32 DpramOffset;// 6 (0x18) (only read)`
42			`u32 DpramSize; // 7 (0x1C) (only read)`
43			`u32 BrdMode; // 8 (0x20) Board control register`
44			`u32 IrqMask; // 9 (0x24) Interrupt mask register`
45			`u32 IrqInv; // 10(0x0A) (0x28) Interrupt inversion register`
46			`u32 Leds; // 11(0x0B) (0x2C) LEDs control register`
47			`u32 Reg12; // 12(0x0C) (0x30) REG12 - Reserved space`
48			`u32 PSynx; // 13(0x0D) (0x34) not use`
49			`u32 Reg14; // 14(0x0E) (0x38) REG14 - Reserved space`
50			`u32 Reg15; // 15(0x0F) (0x3C) REG15 - Reserved space`
51			`u32 BrdStatus; // 16(0x10) (0x40) Board status register`
52			`u32 Reg17; // 17(0x11) (0x44) REG17 - Reserved space`
53			`u32 Reg18; // 18(0x12) (0x48) REG18 - Reserved space`
54			`u32 Sem0; // 19(0x13) (0x4C) not use`
55			`u32 PldConf; // 20(0x14) (0x50) not use`
56			`u32 Reg21; // 21(0x15) (0x54) REG21 - Reserved space`
57			`u32 SpdCtrl; // 22(0x16) (0x58) SPD&ADM_ROM Access Control register`
58			`u32 SpdAddr; // 23(0x17) (0x5C) Memory address register`
59			`u32 SpdDataLo; // 24(0x18) (0x60) Memory low data register`
60			`u32 SpdDataHi; // 25(0x19) (0x64) Memory high address register`
61			`u32 LbData; // 26(0x1A) (0x68) Loopback mode data register`
62			`u32 Reg27; // 27(0x1B) (0x6C) REG27 - Reserved space`
63			`u32 JtagCnt; // 28(0x1C) (0x70) number of shift bit register`
64			`u32 JtagTms; // 29(0x1D) (0x74) signal TMS register`
65			`u32 JtagTdi; // 30(0x1E) (0x78) signal TDI register`
66			`u32 JtagTdo; // 31(0x1F) (0x7C) signal TDO register`
67			`} PE_MAIN_REGISTERS, *PPE_MAIN_REGISTERS;`
68
69			`// Numbers of PCI-Express Main block Registers`
70			`typedef enum _PE_MAIN_ADDR_REG {`
71			`PEMAINadr_BLOCK_ID = 0x00, // 0x00`
72			`PEMAINadr_BLOCK_VER = 0x08, // 0x01`
73			`PEMAINadr_DEVICE_ID = 0x10, // 0x02`
74			`PEMAINadr_DEVICE_REV = 0x18, // 0x03`
75			`PEMAINadr_PLD_VER = 0x20, // 0x04`
76			`PEMAINadr_BLOCK_CNT = 0x28, // 0x05`
77			`PEMAINadr_DPRAM_OFFSET = 0x30, // 0x06`
78			`PEMAINadr_DPRAM_SIZE = 0x38, // 0x07`
79			`PEMAINadr_BRD_MODE = 0x40, // 0x08`
80			`PEMAINadr_IRQ_MASK = 0x48, // 0x09`
81			`PEMAINadr_IRQ_INV = 0x50, // 0x0A`
82			`PEMAINadr_LEDS = 0x58, // 0x0B`
83			`PEMAINadr_BRD_STATUS = 0x80, // 0x10`
84			`PEMAINadr_SPD_CTRL = 0xB0, // 0x16`
85			`PEMAINadr_SPD_ADDR = 0xB8, // 0x17`
86			`PEMAINadr_SPD_DATAL = 0xC0, // 0x18`
87			`PEMAINadr_SPD_DATAH = 0xC8, // 0x19`
88			`PEMAINadr_LB_DATA = 0xD0, // 0x1A`
89			`PEMAINadr_JTAG_CNT = 0xE0, // 0x1C`
90			`PEMAINadr_JTAG_TMS = 0xE8, // 0x1D`
91			`PEMAINadr_JTAG_TDI = 0xF0, // 0x1E`
92			`PEMAINadr_JTAG_TDO = 0xF8, // 0x1F`
93			`} PE_MAIN_ADDR_REG;`
94
95			`// PCI-Express FIFO block Registers Layout`
96			`typedef volatile struct _PE_FIFO_REGISTERS {`
97			`u32 BlockId; // 0 (0x00) Control FIFO block identification register (only read)`
98			`u32 BlockVer; // 1 (0x04) Control FIFO block version register (only read)`
99			`u32 FifoId; // 2 (0x08) FIFO identification register (only read)`
100			`u32 FifoNumber; // 3 (0x0C) FIFO number register (only read)`
101			`u32 DmaSize; // 4 (0x10) DMA size register (only read) - NOT use by EXT`
102			`u32 Reg5; // 5 (0x14) REG5 - Reserved space`
103			`u32 Reg6; // 6 (0x18) REG6 - Reserved space`
104			`u32 Reg7; // 7 (0x1C) REG7 - Reserved space`
105			`u32 FifoCtlr; // 8 (0x20) FIFO control register - NOT use by EXT`
106			`u32 DmaCtlr; // 9 (0x24) DMA control register`
107			`u32 Reg10; // 10(0x0A) (0x28) REG10 - Reserved space`
108			`u32 Reg11; // 11(0x0B) (0x2C) REG11 - Reserved space`
109			`u32 Reg12; // 12(0x0C) (0x30) REG12 - Reserved space`
110			`u32 Reg13; // 13(0x0D) (0x34) REG13 - Reserved space`
111			`u32 Reg14; // 14(0x0E) (0x38) REG14 - Reserved space`
112			`u32 Reg15; // 15(0x0F) (0x3C) REG15 - Reserved space`
113			`u32 FifoStatus; // 16(0x10) (0x40) FIFO status register`
114			`u32 FlagClr; // 17(0x11) (0x44) Flags clear register`
115			`u32 Reg18; // 18(0x12) (0x48) REG18 - Reserved space`
116			`u32 Reg19; // 19(0x13) (0x4C) REG19 - Reserved space`
117			`u32 PciAddrLo; // 20(0x14) (0x50) PCI address (low part) register`
118			`u32 PciAddrHi; // 21(0x15) (0x54) PCI address (high part) register`
119			`u32 PciSize; // 22(0x16) (0x58) block size register - NOT use by EXT`
120			`u32 LocalAddr; // 23(0x17) (0x5C) Local address register`
121			`u32 Reg24; // 24(0x18) (0x60) REG24 - Reserved space`
122			`u32 Reg25; // 25(0x19) (0x64) REG25 - Reserved space`
123			`u32 Reg26; // 26(0x1A) (0x68) REG26 - Reserved space`
124			`u32 Reg27; // 27(0x1B) (0x6C) REG27 - Reserved space`
125			`u32 Reg28; // 28(0x1C) (0x70) REG28 - Reserved space`
126			`u32 Reg29; // 29(0x1D) (0x74) REG29 - Reserved space`
127			`u32 Reg30; // 30(0x1E) (0x78) REG30 - Reserved space`
128			`u32 Reg31; // 31(0x1F) (0x7C) REG31 - Reserved space`
129			`} PE_FIFO_REGISTERS, *PPE_FIFO_REGISTERS;`
130
131			`// Numbers of PCI-Express FIFO block Registers`
132			`typedef enum _PE_FIFO_ADDR_REG {`
133			`PEFIFOadr_BLOCK_ID = 0x00, // 0x00`
134			`PEFIFOadr_BLOCK_VER = 0x08, // 0x01`
135			`PEFIFOadr_FIFO_ID = 0x10, // 0x02`
136			`PEFIFOadr_FIFO_NUM = 0x18, // 0x03`
137			`PEFIFOadr_DMA_SIZE = 0x20, // 0x04 - RESOURCE by EXT`
138			`PEFIFOadr_FIFO_CTRL = 0x40, // 0x08 - DMA_MODE by EXT`
139			`PEFIFOadr_DMA_CTRL = 0x48, // 0x09`
140			`PEFIFOadr_FIFO_STATUS = 0x80, // 0x10`
141			`PEFIFOadr_FLAG_CLR = 0x88, // 0x11`
142			`PEFIFOadr_PCI_ADDRL = 0xA0, // 0x14`
143			`PEFIFOadr_PCI_ADDRH = 0xA8, // 0x15`
144			`PEFIFOadr_PCI_SIZE = 0xB0, // 0x16 - NOT use by EXT`
145			`PEFIFOadr_LOCAL_ADR = 0xB8, // 0x17`
146			`} PE_FIFO_ADDR_REG;`
147
148			`// Board Control register 0x40 (PE_MAIN)`
149			`typedef union _BRD_MODE {`
150			`u16 AsWhole; // Board Control Register as a Whole Word`
151			`struct { // Board Control Register as Bit Pattern`
152			`u16 RstClkOut : 1, // Output Clock Reset for ADMPLD`
153			`Sleep : 1, // Sleep mode for ADMPLD`
154			`RstClkIn : 1, // Input Clock Reset for ADMPLD`
155			`Reset : 1, // Reset for ADMPLD`
156			`RegLoop : 1, // Register operation loopback mode`
157			`Res : 3, // Reserved`
158			`OutFlags : 8; // Output Flags`
159			`} ByBits;`
160			`} BRD_MODE, *PBRD_MODE;`
161
162			`// Board Status register 0x80 (PE_MAIN)`
163			`typedef union _BRD_STATUS {`
164			`u16 AsWhole; // Board Status Register as a Whole Word`
165			`struct { // Board Status Register as Bit Pattern`
166			`u16 SlvDcm : 1, // Capture Input Clock from ADMPLD`
167			`NotUse : 7, //`
168			`InFlags : 8; // Input Flags`
169			`} ByBits;`
170			`} BRD_STATUS, *PBRD_STATUS;`
171
172			`// SPD Control register 0xB0 (PE_MAIN)`
173			`typedef union _SPD_CTRL {`
174			`u16 AsWhole; // SPD Control Register as a Whole Word`
175			`struct { // SPD Control Register as Bit Pattern`
176			`u16 ReadOp : 1, // Read Operation`
177			`WriteOp : 1, // Write Operation`
178			`Res : 2, // Reserved`
179			`WriteEn : 1, // Write Enable`
180			`WriteDis : 1, // Read Disable`
181			`Res1 : 2, // Reserved`
182			`SpdId : 3, // SPD Identification`
183			`Res2 : 3, // Reserved`
184			`Sema : 1, // Semaphor`
185			`Ready : 1; // Data Ready`
186			`} ByBits;`
187			`} SPD_CTRL, *PSPD_CTRL;`
188
189			`// FIFO ID register 0x10 (PE_FIFO)`
190			`typedef union _FIFO_ID {`
191			`u16 AsWhole; // FIFO ID Register as a Whole Word`
192			`struct { // FIFO ID Register as Bit Pattern`
193			`u16 Size : 12, // FIFO size (32-bit words)`
194			`Dir : 4; // DMA direction`
195			`} ByBits;`
196			`} FIFO_ID, *PFIFO_ID;`
197
198			`// FIFO Control register 0x40 (PE_FIFO)`
199			`typedef union _FIFO_CTRL {`
200			`u16 AsWhole; // FIFO Control Register as a Whole Word`
201			`struct { // FIFO Control Register as Bit Pattern`
202			`u16 Reset : 1, // FIFO Reset`
203			`DrqEn : 1, // DMA Request enable`
204			`Loopback : 1, // Not use`
205			`TstCnt : 1, // 32-bit Test Counter enable`
206			`Res : 12; // Reserved`
207			`} ByBits;`
208			`} FIFO_CTRL, *PFIFO_CTRL;`
209
210			`// DMA Mode register 0x40 (PE_EXT_FIFO)`
211			`typedef union _DMA_MODE_EXT {`
212			`u16 AsWhole; // DMA Mode Register as a Whole Word`
213			`struct { // FIFO Control Register as Bit Pattern`
214			`u16 SGModeEnbl : 1, // 1 - Scatter/Gather mode enable`
215			`DemandMode : 1, // 1 - always`
216			`Dir : 1, // DMA direction`
217			`Res0 : 2, // Reserved`
218			`IntEnbl : 1, // Interrrupt enable (End of DMA)`
219			`Res : 10; // Reserved`
220			`} ByBits;`
221			`} DMA_MODE_EXT, *PDMA_MODE_EXT;`
222
223			`// DMA Control register 0x48 (PE_FIFO)`
224			`typedef union _DMA_CTRL {`
225			`u16 AsWhole; // DMA Control Register as a Whole Word`
226			`struct { // DMA Control Register as Bit Pattern`
227			`u16 Start : 1, // DMA start`
228			`Stop : 1, // DMA stop`
229			`SGEnbl : 1, // Scatter/Gather mode enable`
230			`Res0 : 1, // Reserved`
231			`DemandMode : 1, // 1 - always`
232			`IntEnbl : 1, // Interrrupt enable (End of DMA)`
233			`Res : 10; // Reserved`
234			`} ByBits;`
235			`} DMA_CTRL, *PDMA_CTRL;`
236
237			`// DMA Control register 0x48 (PE_EXT_FIFO)`
238			`typedef union _DMA_CTRL_EXT {`
239			`u16 AsWhole; // DMA Control Register as a Whole Word`
240			`struct { // DMA Control Register as Bit Pattern`
241			`u16 Start : 1, // DMA start/stop`
242			`Res0 : 2, // Reserved`
243			`Pause : 1, // DMA pause`
244			`ResetFIFO : 1, // FIFO Reset`
245			`Res : 11; // Reserved`
246			`} ByBits;`
247			`} DMA_CTRL_EXT, *PDMA_CTRL_EXT;`
248
249			`// FIFO Status register 0x80 (PE_FIFO)`
250			`typedef union _FIFO_STATUS {`
251			`u16 AsWhole; // FIFO Status Register as a Whole Word`
252			`struct { // FIFO Status Register as Bit Pattern`
253			`u16 DmaStat : 4, // DMA Status`
254			`DmaEot : 1, // DMA block Complete (End of Transfer)`
255			`SGEot : 1, // Scatter/Gather End of Transfer (all blocks complete)`
256			`IntErr : 1, // not serviced of interrrupt - ERROR!!! block leave out!!!`
257			`IntRql : 1, // Interrrupt request`
258			`// DmaErr : 1, // DMA channel error`
259			`DscrErr : 1, // Descriptor error`
260			`NotUse : 3, // Not Use`
261			`Sign : 4; // Signature (0x0A)`
262			`} ByBits;`
263			`} FIFO_STATUS, *PFIFO_STATUS;`
264
265			`// Numbers of Tetrad Registers`
266			`typedef enum _TETRAD_REG {`
267			`TRDadr_STATUS,`
268			`TRDadr_DATA,`
269			`TRDadr_CMD_ADR,`
270			`TRDadr_CMD_DATA`
271			`} TETRAD_REG, *PTETRAD_REG;`
272
273			`typedef enum _AmbStatusRegBits {`
274			`AMB_statCMDRDY = 1`
275			`} AmbStatusRegBits;`
276
277			`// Main Select of Interrupts & DMA channels Register (MODE0 +16)`
278			`typedef union _MAIN_SELX {`
279			`u32 AsWhole; // Board Mode Register as a Whole Word`
280			`struct { // Mode Register as Bit Pattern`
281			`u32 IrqNum : 4, // Interrupt number`
282			`Res1 : 4, // Reserved`
283			`DmaTetr : 4, // Tetrad number for DMA channel X`
284			`DrqEnbl : 1, // DMA request enable`
285			`DmaMode : 3; // DMA mode`
286			`} ByBits;`
287			`} MAIN_SELX, *PMAIN_SELX;`
288
289			`#define REG_SIZE 0x00001000 // register size`
290			`#define TETRAD_SIZE 0x00004000 // tetrad size`
291			`#define ADM_SIZE 0x00020000 // ADM interface size`
292
293			`// Numbers of Registers`
294			`typedef enum _AMB_AUX_NUM_REG {`
295			`AUXnr_ADM_PLD_DATA = 0,`
296			`AUXnr_ADM_PLD_MODE_STATUS = 1,`
297			`AUXnr_SUBMOD_ID_ROM = 2,`
298			`AUXnr_DSP_PLD_DATA = 3,`
299			`AUXnr_DSP_PLD_MODE_STATUS = 4,`
300			`} AMB_AUX_NUM_REG;`
301
302			`#endif //_AMBPEXREGS_H_`