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dsmv |
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#include <linux/kernel.h>
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#define __NO_VERSION__
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/pagemap.h>
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "pexmodule.h"
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#include "hardware.h"
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#include "ambpexregs.h"
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//--------------------------------------------------------------------
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int set_device_name(struct pex_device *brd, u16 dev_id, int index)
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{
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if(!brd)
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return -1;
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switch(dev_id) {
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case AMBPEX5_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX5", index); break;
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case AMBPEX8_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX8", index); break;
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case ADP201X1AMB_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1AMB", index); break;
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case ADP201X1DSP_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1DSP", index); break;
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case AMBPEXARM_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEXARM_DEVID", index); break;
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case AMBFMC106P_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBFMC106P_DEVID", index); break;
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default:
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snprintf(brd->m_name, sizeof(brd->m_name), "%s%d", "Unknown", index); break;
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}
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return 0;
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}
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//--------------------------------------------------------------------
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int lock_pages( void *va, u32 size )
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{
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struct page *start_page_addr = virt_to_page(va);
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int i = 0;
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for (i=0; i < (size >> PAGE_CACHE_SHIFT); i++) {
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SetPageReserved(start_page_addr+i);
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//dbg_msg(dbg_trace, "%s(): page_addr[%d] = 0x%x\n", __FUNCTION__, i, (int)(start_page_addr+i));
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}
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return i;
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}
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//--------------------------------------------------------------------
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int unlock_pages( void *va, u32 size )
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{
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struct page *start_page_addr = virt_to_page(va);
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int i = 0;
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for (i=0; i < (size >> PAGE_CACHE_SHIFT); i++) {
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ClearPageReserved(start_page_addr+i);
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//dbg_msg(dbg_trace, "%s(): page_addr[%d] = 0x%x\n", __FUNCTION__, i, (int)(start_page_addr+i));
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}
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return i;
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}
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//--------------------------------------------------------------------
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void read_memory32(u32 *src, u32 *dst, u32 cnt)
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{
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int i=0;
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for(i=0; i<cnt; i++) {
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dst[i] = readl(src);
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}
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}
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//--------------------------------------------------------------------
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void write_memory32(u32 *src, u32 *dst, u32 cnt)
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{
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int i=0;
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for(i=0; i<cnt; i++) {
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writel(src[i], dst);
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}
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}
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//--------------------------------------------------------------------
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int InitializeBoard(struct pex_device *brd)
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{
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u16 temp = 0; // holds registers while we are modifying bits
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u16 blockId = 0;
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u16 blockVer = 0;
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u16 deviceID = 0;
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u16 deviceRev = 0;
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int iChan = 0;
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int iBlock = 0;
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int i = 0;
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FIFO_ID FifoId;
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blockId = ReadOperationWordReg(brd, PEMAINadr_BLOCK_ID);
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blockVer = ReadOperationWordReg(brd, PEMAINadr_BLOCK_VER);
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dbg_msg(dbg_trace, "%s(): BlockID = 0x%X, BlockVER = 0x%X.\n", __FUNCTION__, blockId, blockVer);
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deviceID = ReadOperationWordReg(brd, PEMAINadr_DEVICE_ID);
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deviceRev = ReadOperationWordReg(brd, PEMAINadr_DEVICE_REV);
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dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
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if((AMBPEX8_DEVID != deviceID) &&
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(ADP201X1AMB_DEVID != deviceID) &&
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(AMBPEX5_DEVID != deviceID) &&
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(AMBPEXARM_DEVID != deviceID))
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return -ENODEV;
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temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
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dbg_msg(dbg_trace, "%s(): PldVER = 0x%X.\n", __FUNCTION__, temp);
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brd->m_BlockCnt = ReadOperationWordReg(brd, PEMAINadr_BLOCK_CNT);
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dbg_msg(dbg_trace, "%s(): Block count = %d.\n", __FUNCTION__, brd->m_BlockCnt);
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// начальное обнуление информации о каналах ПДП
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brd->m_DmaChanMask = 0;
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for(iChan = 0; iChan < MAX_NUMBER_OF_DMACHANNELS; iChan++)
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{
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brd->m_BlockFifoId[iChan] = 0;
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brd->m_DmaFifoSize[iChan] = 0;
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brd->m_DmaDir[iChan] = 0;
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brd->m_MaxDmaSize[iChan] = 0;
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}
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// определим какие каналы ПДП присутствуют и их характеристики:
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// направление передачи данных, размер FIFO, максимальный размер блока ПДП
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for(iBlock = 0; iBlock < brd->m_BlockCnt; iBlock++)
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{
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u32 FifoAddr = 0;
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u16 block_id = 0;
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FifoAddr = (iBlock + 1) * PE_FIFO_ADDR;
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temp = ReadOperationWordReg(brd, PEFIFOadr_BLOCK_ID + FifoAddr);
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block_id = (temp & 0x0FFF);
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if(block_id == PE_EXT_FIFO_ID)
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{
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u32 resource_id = 0;
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u16 iChan = ReadOperationWordReg(brd, PEFIFOadr_FIFO_NUM + FifoAddr);
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brd->m_FifoAddr[iChan] = FifoAddr;
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brd->m_BlockFifoId[iChan] = block_id;
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brd->m_DmaChanMask |= (1 << iChan);
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FifoId.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_FIFO_ID + FifoAddr);
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brd->m_DmaFifoSize[iChan] = FifoId.ByBits.Size;
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brd->m_DmaDir[iChan] = FifoId.ByBits.Dir;
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brd->m_MaxDmaSize[iChan] = 0x40000000; // макс. размер ПДП пусть будет 1 Гбайт
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resource_id = ReadOperationWordReg(brd, PEFIFOadr_DMA_SIZE + FifoAddr); // RESOURCE
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dbg_msg(dbg_trace, "%s(): Channel(ID) = %d(0x%x), FIFO size = %d Bytes, DMA Dir = %d, Max DMA size = %d MBytes, resource = 0x%x.\n", __FUNCTION__,
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iChan, block_id, brd->m_DmaFifoSize[iChan] * 4, brd->m_DmaDir[iChan], brd->m_MaxDmaSize[iChan] / 1024 / 1024, resource_id);
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}
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}
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dbg_msg(dbg_trace, "%s(): m_DmaChanMask = 0x%X\n", __FUNCTION__, brd->m_DmaChanMask);
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// подготовим к работе ПЛИС ADM
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dbg_msg(dbg_trace, "%s(): Prepare ADM PLD.\n", __FUNCTION__);
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WriteOperationWordReg(brd,PEMAINadr_BRD_MODE, 0);
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ToPause(100); // pause ~ 100 msec
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for(i = 0; i < 10; i++)
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{
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, 1);
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ToPause(100); // pause ~ 100 msec
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, 3);
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ToPause(100); // pause ~ 100 msec
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, 7);
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ToPause(100); // pause ~ 100 msec
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temp = ReadOperationWordReg(brd, PEMAINadr_BRD_STATUS) & 0x01;
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if(temp)
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break;
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}
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, 0x0F);
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ToPause(100); // pause ~ 100 msec
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if(temp)
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{
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u32 idx = 0;
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BRD_STATUS brd_status;
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dbg_msg(dbg_trace, "%s(): ADM PLD is captured.\n", __FUNCTION__);
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brd_status.AsWhole = ReadOperationWordReg(brd, PEMAINadr_BRD_STATUS);
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if(AMBPEX8_DEVID == deviceID)
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brd_status.ByBits.InFlags &= 0x80; // 1 - ADM PLD in test mode
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else
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brd_status.ByBits.InFlags = 0x80; // 1 - ADM PLD in test mode
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if(brd_status.ByBits.InFlags)
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{
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BRD_MODE brd_mode;
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dbg_msg(dbg_trace, "%s(): ADM PLD in test mode.\n", __FUNCTION__);
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// проверка линий передачи флагов
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brd_mode.AsWhole = ReadOperationWordReg(brd, PEMAINadr_BRD_MODE);
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for(idx = 0; idx < 4; idx++)
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{
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brd_mode.ByBits.OutFlags = idx;
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, brd_mode.AsWhole);
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ToPause(10);
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brd_status.AsWhole = ReadOperationWordReg(brd, PEMAINadr_BRD_STATUS);
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brd_status.ByBits.InFlags &= 0x03;
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if(brd_mode.ByBits.OutFlags != brd_status.ByBits.InFlags)
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{
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temp = 0;
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dbg_msg(dbg_trace, "%s(): FLG_IN (%d) NOT equ FLG_OUT (%d).\n", __FUNCTION__,
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brd_status.ByBits.InFlags, brd_mode.ByBits.OutFlags);
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break;
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}
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}
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if(temp)
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dbg_msg(dbg_trace, "%s(): FLG_IN equ FLG_OUT.\n", __FUNCTION__);
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}
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else
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temp = 0;
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}
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if(!temp)
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{
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, 0);
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ToPause(100); // pause ~ 100 msec
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}
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brd->m_PldStatus[0] = temp; // состояние ПЛИС ADM: 0 - не готова
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dbg_msg(dbg_trace, "%s(): ADM PLD[%d] status = 0x%X.\n", __FUNCTION__, i, temp);
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{
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BRD_MODE brd_mode;
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brd_mode.AsWhole = ReadOperationWordReg(brd, PEMAINadr_BRD_MODE);
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brd_mode.ByBits.OutFlags = 0;
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WriteOperationWordReg(brd, PEMAINadr_BRD_MODE, brd_mode.AsWhole);
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dbg_msg(dbg_trace, "%s(): BRD_MODE = 0x%X.\n", __FUNCTION__, brd_mode.AsWhole);
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}
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WriteOperationWordReg(brd, PEMAINadr_IRQ_MASK, 0x4000);
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//WriteAmbMainReg(brd, 0x0, 0x1);
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//WriteAmbMainReg(brd, 0x0, 0x1);
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return 0;
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}
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249 |
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//--------------------------------------------------------------------
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u32 ReadOperationReg(struct pex_device *brd, u32 RelativePort)
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{
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return readl((u32*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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}
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//--------------------------------------------------------------------
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258 |
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259 |
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void WriteOperationReg(struct pex_device *brd, u32 RelativePort, u32 Value)
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260 |
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{
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writel( Value, (u32*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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}
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//--------------------------------------------------------------------
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265 |
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266 |
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u16 ReadOperationWordReg(struct pex_device *brd, u32 RelativePort)
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267 |
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{
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268 |
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return readw((u16*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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269 |
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}
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270 |
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271 |
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//--------------------------------------------------------------------
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272 |
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273 |
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void WriteOperationWordReg(struct pex_device *brd, u32 RelativePort, u16 Value)
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274 |
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{
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275 |
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writew( Value, (u16*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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276 |
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}
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277 |
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278 |
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//--------------------------------------------------------------------
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279 |
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280 |
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u8 ReadOperationByteReg(struct pex_device *brd, u32 RelativePort)
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281 |
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{
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282 |
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return readb((u8*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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283 |
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}
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284 |
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285 |
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//--------------------------------------------------------------------
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286 |
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287 |
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void WriteOperationByteReg(struct pex_device *brd, u32 RelativePort, u8 Value)
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288 |
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{
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289 |
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writeb( Value, (u8*)((u8*)brd->m_BAR0.virtual_address + RelativePort));
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290 |
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}
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291 |
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//--------------------------------------------------------------------
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293 |
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294 |
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u32 ReadAmbReg(struct pex_device *brd, u32 AdmNumber, u32 RelativePort)
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295 |
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{
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296 |
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u8* pBaseAddress = (u8*)brd->m_BAR1.virtual_address + AdmNumber * ADM_SIZE;
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return readl((u32*)(pBaseAddress + RelativePort));
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}
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299 |
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300 |
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//--------------------------------------------------------------------
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301 |
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302 |
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u32 ReadAmbMainReg(struct pex_device *brd, u32 RelativePort)
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303 |
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{
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304 |
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return readl((u32*)((u8*)brd->m_BAR1.virtual_address + RelativePort));
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305 |
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}
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306 |
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307 |
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//--------------------------------------------------------------------
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308 |
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309 |
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void WriteAmbReg(struct pex_device *brd, u32 AdmNumber, u32 RelativePort, u32 Value)
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310 |
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{
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311 |
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u8* pBaseAddress = (u8*)brd->m_BAR1.virtual_address + AdmNumber * ADM_SIZE;
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312 |
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writel( Value, (u32*)(pBaseAddress + RelativePort) );
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313 |
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}
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314 |
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315 |
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//--------------------------------------------------------------------
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316 |
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317 |
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void WriteAmbMainReg(struct pex_device *brd, u32 RelativePort, u32 Value)
|
318 |
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{
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319 |
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writel( Value, (u32*)((u8*)brd->m_BAR1.virtual_address + RelativePort));
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320 |
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}
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321 |
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322 |
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//--------------------------------------------------------------------
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323 |
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324 |
|
|
void ReadBufAmbReg(struct pex_device *brd, u32 AdmNumber, u32 RelativePort, u32* VirtualAddress, u32 DwordsCount)
|
325 |
|
|
{
|
326 |
|
|
u8* pBaseAddress = (u8*)brd->m_BAR1.virtual_address + AdmNumber * ADM_SIZE;
|
327 |
|
|
read_memory32((u32*)(pBaseAddress + RelativePort),VirtualAddress,DwordsCount);
|
328 |
|
|
}
|
329 |
|
|
|
330 |
|
|
//--------------------------------------------------------------------
|
331 |
|
|
|
332 |
|
|
void WriteBufAmbReg(struct pex_device *brd, u32 AdmNumber, u32 RelativePort, u32* VirtualAddress, u32 DwordsCount)
|
333 |
|
|
{
|
334 |
|
|
u8* pBaseAddress = (u8*)brd->m_BAR1.virtual_address + AdmNumber * ADM_SIZE;
|
335 |
|
|
write_memory32((u32*)(pBaseAddress + RelativePort), VirtualAddress, DwordsCount);
|
336 |
|
|
}
|
337 |
|
|
|
338 |
|
|
//--------------------------------------------------------------------
|
339 |
|
|
|
340 |
|
|
void WriteBufAmbMainReg(struct pex_device *brd, u32 RelativePort, u32* VirtualAddress, u32 DwordsCount)
|
341 |
|
|
{
|
342 |
|
|
write_memory32( (u32*)((u8*)brd->m_BAR1.virtual_address + RelativePort), VirtualAddress, DwordsCount);
|
343 |
|
|
}
|
344 |
|
|
|
345 |
|
|
//--------------------------------------------------------------------
|
346 |
|
|
|
347 |
|
|
void TimeoutTimerCallback(unsigned long arg )
|
348 |
|
|
{
|
349 |
|
|
struct pex_device *pDevice = (struct pex_device*) arg;
|
350 |
|
|
atomic_set(&pDevice->m_IsTimeout, 1);
|
351 |
|
|
}
|
352 |
|
|
|
353 |
|
|
//--------------------------------------------------------------------
|
354 |
|
|
|
355 |
|
|
void SetRelativeTimer ( struct timer_list *timer, int timeout, void *data )
|
356 |
|
|
{
|
357 |
|
|
struct pex_device *dev = (struct pex_device*)data;
|
358 |
|
|
|
359 |
|
|
if (!dev)
|
360 |
|
|
return;
|
361 |
|
|
|
362 |
|
|
atomic_set( &dev->m_IsTimeout, 0 );
|
363 |
|
|
|
364 |
|
|
timer->data = ( unsigned long ) data;
|
365 |
|
|
timer->function = TimeoutTimerCallback;
|
366 |
|
|
timer->expires = ( jiffies + timeout * HZ / 1000);
|
367 |
|
|
|
368 |
|
|
add_timer ( timer );
|
369 |
|
|
}
|
370 |
|
|
|
371 |
|
|
//--------------------------------------------------------------------
|
372 |
|
|
|
373 |
|
|
void CancelTimer ( struct timer_list *timer )
|
374 |
|
|
{
|
375 |
|
|
del_timer( timer );
|
376 |
|
|
}
|
377 |
|
|
|
378 |
|
|
//--------------------------------------------------------------------
|
379 |
|
|
|
380 |
|
|
int WaitCmdReady(struct pex_device *brd, u32 AdmNumber, u32 StatusAddress)
|
381 |
|
|
{
|
382 |
|
|
u32 cmd_rdy;
|
383 |
|
|
|
384 |
|
|
atomic_set(&brd->m_IsTimeout, 0);
|
385 |
|
|
|
386 |
|
|
SetRelativeTimer(&brd->m_TimeoutTimer, 1000, (void*)brd); // wait 1 sec
|
387 |
|
|
|
388 |
|
|
do {
|
389 |
|
|
cmd_rdy = ReadAmbReg(brd, AdmNumber, StatusAddress);
|
390 |
|
|
cmd_rdy &= AMB_statCMDRDY; //HOST_statCMDRDY;
|
391 |
|
|
} while(!atomic_read(&brd->m_IsTimeout) && !cmd_rdy);
|
392 |
|
|
|
393 |
|
|
CancelTimer(&brd->m_TimeoutTimer);
|
394 |
|
|
|
395 |
|
|
if (atomic_read(&brd->m_IsTimeout))
|
396 |
|
|
return -1;
|
397 |
|
|
|
398 |
|
|
return 0;
|
399 |
|
|
}
|
400 |
|
|
|
401 |
|
|
//--------------------------------------------------------------------
|
402 |
|
|
|
403 |
|
|
int WriteRegData(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber, u32 RegNumber, u32 Value)
|
404 |
|
|
{
|
405 |
|
|
int Status = 0;
|
406 |
|
|
u32 Address = TetrNumber * TETRAD_SIZE;
|
407 |
|
|
u32 CmdAddress = Address + TRDadr_CMD_ADR * REG_SIZE;
|
408 |
|
|
u32 DataAddress = Address + TRDadr_CMD_DATA * REG_SIZE;
|
409 |
|
|
u32 StatusAddress = Address + TRDadr_STATUS * REG_SIZE;
|
410 |
|
|
|
411 |
|
|
WriteAmbReg(brd, AdmNumber, CmdAddress, RegNumber);
|
412 |
|
|
Status = WaitCmdReady(brd, AdmNumber, StatusAddress); // wait CMD_RDY
|
413 |
|
|
if(Status != 0) {
|
414 |
|
|
err_msg(err_trace, "%s(): ERROR wait cmd ready.\n", __FUNCTION__);
|
415 |
|
|
return Status;
|
416 |
|
|
}
|
417 |
|
|
WriteAmbReg(brd, AdmNumber, DataAddress, Value);
|
418 |
|
|
|
419 |
|
|
return Status;
|
420 |
|
|
}
|
421 |
|
|
|
422 |
|
|
//--------------------------------------------------------------------
|
423 |
|
|
|
424 |
|
|
void ToPause(int time_out)
|
425 |
|
|
{
|
426 |
|
|
msleep(time_out);
|
427 |
|
|
}
|
428 |
|
|
|
429 |
|
|
//--------------------------------------------------------------------
|
430 |
|
|
|
431 |
|
|
void ToTimeOut(int mctime_out)
|
432 |
|
|
{
|
433 |
|
|
udelay ( mctime_out );
|
434 |
|
|
}
|
435 |
|
|
|
436 |
|
|
//--------------------------------------------------------------------
|
437 |
|
|
|
438 |
|
|
int ReadRegData(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber, u32 RegNumber, u32 *Value)
|
439 |
|
|
{
|
440 |
|
|
int Status = 0;
|
441 |
|
|
u32 Address = TetrNumber * TETRAD_SIZE;
|
442 |
|
|
u32 CmdAddress = Address + TRDadr_CMD_ADR * REG_SIZE;
|
443 |
|
|
u32 StatusAddress = Address + TRDadr_STATUS * REG_SIZE;
|
444 |
|
|
u32 DataAddress = Address + TRDadr_CMD_DATA * REG_SIZE;
|
445 |
|
|
|
446 |
|
|
WriteAmbReg(brd, AdmNumber, CmdAddress, RegNumber);
|
447 |
|
|
Status = WaitCmdReady(brd, AdmNumber, StatusAddress); // wait CMD_RDY
|
448 |
|
|
if(Status != 0) {
|
449 |
|
|
err_msg(err_trace,"%s(): ERROR wait cmd ready.\n", __FUNCTION__);
|
450 |
|
|
return Status;
|
451 |
|
|
}
|
452 |
|
|
|
453 |
|
|
*Value = ReadAmbReg(brd, AdmNumber, DataAddress);
|
454 |
|
|
|
455 |
|
|
dbg_msg(dbg_trace, "%s(): Adm = %d, Tetr = %d, Reg = %d, Val = %x\n",
|
456 |
|
|
__FUNCTION__, AdmNumber, TetrNumber, RegNumber, (int)*Value);
|
457 |
|
|
|
458 |
|
|
return Status;
|
459 |
|
|
}
|
460 |
|
|
|
461 |
|
|
//--------------------------------------------------------------------
|
462 |
|
|
|
463 |
|
|
int SetDmaMode(struct pex_device *brd, u32 NumberOfChannel, u32 AdmNumber, u32 TetrNumber)
|
464 |
|
|
{
|
465 |
|
|
int Status = -EINVAL;
|
466 |
|
|
MAIN_SELX sel_reg = {0};
|
467 |
|
|
Status = ReadRegData(brd, AdmNumber, 0, 16 + NumberOfChannel, &sel_reg.AsWhole);
|
468 |
|
|
sel_reg.ByBits.DmaTetr = TetrNumber;
|
469 |
|
|
sel_reg.ByBits.DrqEnbl = 1;
|
470 |
|
|
Status = WriteRegData(brd, AdmNumber, 0, 16 + NumberOfChannel, sel_reg.AsWhole);
|
471 |
|
|
//err_msg(err_trace,"%s(): MAIN_SELX = 0x%X\n", __FUNCTION__, sel_reg.AsWhole);
|
472 |
|
|
return Status;
|
473 |
|
|
}
|
474 |
|
|
|
475 |
|
|
//--------------------------------------------------------------------
|
476 |
|
|
|
477 |
|
|
int SetDrqFlag(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber, u32 DrqFlag)
|
478 |
|
|
{
|
479 |
|
|
int Status = 0;
|
480 |
|
|
u32 Value = 0;
|
481 |
|
|
Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
|
482 |
|
|
if(Status != 0) return Status;
|
483 |
|
|
Value |= (DrqFlag << 12);
|
484 |
|
|
Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
|
485 |
|
|
return Status;
|
486 |
|
|
}
|
487 |
|
|
|
488 |
|
|
//--------------------------------------------------------------------
|
489 |
|
|
|
490 |
|
|
int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
|
491 |
|
|
{
|
492 |
|
|
int Status = 0;
|
493 |
|
|
u32 Value = 0;
|
494 |
|
|
Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
|
495 |
|
|
if(Status != 0) return Status;
|
496 |
|
|
Value |= 0x8; // DRQ enable
|
497 |
|
|
Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
|
498 |
|
|
//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
|
499 |
|
|
return Status;
|
500 |
|
|
}
|
501 |
|
|
|
502 |
|
|
//--------------------------------------------------------------------
|
503 |
|
|
|
504 |
|
|
int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
|
505 |
|
|
{
|
506 |
|
|
int Status = 0;
|
507 |
|
|
u32 Value = 0;
|
508 |
|
|
Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
|
509 |
|
|
if(Status != 0) return Status;
|
510 |
|
|
Value &= 0xfff7; // DRQ disable
|
511 |
|
|
Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
|
512 |
|
|
return Status;
|
513 |
|
|
}
|
514 |
|
|
|
515 |
|
|
//--------------------------------------------------------------------
|
516 |
|
|
|
517 |
|
|
int ResetFifo(struct pex_device *brd, u32 NumberOfChannel)
|
518 |
|
|
{
|
519 |
|
|
int Status = 0;
|
520 |
|
|
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
|
521 |
|
|
|
522 |
|
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
523 |
|
|
{
|
524 |
|
|
DMA_CTRL_EXT CtrlExt;
|
525 |
|
|
CtrlExt.AsWhole = 0;//ReadOperationWordReg(PEFIFOadr_DMA_CTRL + FifoAddr);
|
526 |
|
|
WriteOperationWordReg(brd,PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
527 |
|
|
ToPause(1);
|
528 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
|
529 |
|
|
CtrlExt.ByBits.ResetFIFO = 1;
|
530 |
|
|
WriteOperationWordReg(brd,PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
531 |
|
|
ToPause(1);
|
532 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
|
533 |
|
|
CtrlExt.ByBits.ResetFIFO = 0;
|
534 |
|
|
WriteOperationWordReg(brd,PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
535 |
|
|
//ToPause(200);
|
536 |
|
|
ToPause(10);
|
537 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
|
538 |
|
|
}
|
539 |
|
|
return Status;
|
540 |
|
|
}
|
541 |
|
|
|
542 |
|
|
//--------------------------------------------------------------------
|
543 |
|
|
|
544 |
|
|
int Done(struct pex_device *brd, u32 NumberOfChannel)
|
545 |
|
|
{
|
546 |
|
|
DMA_CTRL_EXT CtrlExt;
|
547 |
|
|
int Status = 0;
|
548 |
|
|
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
|
549 |
|
|
CtrlExt.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr);
|
550 |
|
|
CtrlExt.ByBits.Pause = 0;
|
551 |
|
|
|
552 |
|
|
//printk("<0>%s(): CtrlExt.AsWhole = 0x%x\n", __FUNCTION__, CtrlExt.AsWhole);
|
553 |
|
|
|
554 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
555 |
|
|
|
556 |
|
|
return Status;
|
557 |
|
|
}
|
558 |
|
|
|
559 |
|
|
//--------------------------------------------------------------------
|
560 |
|
|
int HwStartDmaTransfer(struct pex_device *brd, u32 NumberOfChannel)
|
561 |
|
|
{
|
562 |
|
|
int Status = 0;
|
563 |
|
|
DMA_CTRL DmaCtrl;
|
564 |
|
|
u64 SGTableAddress;
|
565 |
|
|
u32 LocalAddress, DmaDirection;
|
566 |
|
|
u32 adm_num, tetr_num;
|
567 |
|
|
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
|
568 |
|
|
|
569 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, FifoAddr = 0x%04X.\n",__FUNCTION__, NumberOfChannel, FifoAddr);
|
570 |
|
|
|
571 |
|
|
DmaCtrl.AsWhole = 0;
|
572 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, DmaCtrl.AsWhole);
|
573 |
|
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
574 |
|
|
{
|
575 |
|
|
DMA_MODE_EXT ModeExt;
|
576 |
|
|
ModeExt.AsWhole = 0;
|
577 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr, ModeExt.AsWhole);
|
578 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_FLAG_CLR + FifoAddr, 0x10);
|
579 |
|
|
}
|
580 |
|
|
GetSGStartParams(brd->m_DmaChannel[NumberOfChannel], &SGTableAddress, &LocalAddress, &DmaDirection); // SG
|
581 |
|
|
|
582 |
|
|
WriteOperationReg(brd, PEFIFOadr_PCI_ADDRL + FifoAddr, SGTableAddress); // SG
|
583 |
|
|
WriteOperationReg(brd, PEFIFOadr_PCI_ADDRH + FifoAddr, 0);
|
584 |
|
|
|
585 |
|
|
WriteOperationReg(brd, PEFIFOadr_PCI_SIZE + FifoAddr, 0); // SG
|
586 |
|
|
dbg_msg(dbg_trace, "%s(): SG Table Address = 0x%llX, Local Address = 0x%X.\n", __FUNCTION__, SGTableAddress, LocalAddress);
|
587 |
|
|
|
588 |
|
|
WriteOperationReg(brd, PEFIFOadr_LOCAL_ADR + FifoAddr, LocalAddress);
|
589 |
|
|
|
590 |
|
|
brd->m_DmaChanEnbl[NumberOfChannel] = 1;
|
591 |
|
|
brd->m_DmaIrqEnbl = 1;
|
592 |
|
|
|
593 |
|
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
594 |
|
|
{
|
595 |
|
|
DMA_MODE_EXT ModeExt;
|
596 |
|
|
DMA_CTRL_EXT CtrlExt;
|
597 |
|
|
|
598 |
|
|
ModeExt.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr);
|
599 |
|
|
ModeExt.ByBits.SGModeEnbl = 1;
|
600 |
|
|
ModeExt.ByBits.DemandMode = 1;
|
601 |
|
|
ModeExt.ByBits.IntEnbl = 1;
|
602 |
|
|
ModeExt.ByBits.Dir = DmaDirection;
|
603 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr, ModeExt.AsWhole);
|
604 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_MODE_EXT = 0x%X.\n", __FUNCTION__, NumberOfChannel, ModeExt.AsWhole);
|
605 |
|
|
|
606 |
|
|
CtrlExt.AsWhole = 0;
|
607 |
|
|
CtrlExt.ByBits.Start = 1;
|
608 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
609 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_CTRL_EXT = 0x%04X.\n", __FUNCTION__, NumberOfChannel, CtrlExt.AsWhole);
|
610 |
|
|
}
|
611 |
|
|
|
612 |
|
|
adm_num = GetAdmNum(brd->m_DmaChannel[NumberOfChannel]);
|
613 |
|
|
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
|
614 |
|
|
Status = DmaEnable(brd, adm_num, tetr_num);
|
615 |
|
|
|
616 |
|
|
return Status;
|
617 |
|
|
}
|
618 |
|
|
|
619 |
|
|
//--------------------------------------------------------------------
|
620 |
|
|
|
621 |
|
|
int HwCompleteDmaTransfer(struct pex_device *brd, u32 NumberOfChannel)
|
622 |
|
|
{
|
623 |
|
|
int Status = 0;
|
624 |
|
|
u32 FifoAddr = brd->m_FifoAddr[NumberOfChannel];
|
625 |
|
|
int enbl = 0;
|
626 |
|
|
int i = 0;
|
627 |
|
|
u32 tetr_num;
|
628 |
|
|
|
629 |
|
|
if(brd->m_BlockFifoId[NumberOfChannel] == PE_EXT_FIFO_ID)
|
630 |
|
|
{
|
631 |
|
|
DMA_CTRL_EXT CtrlExt;
|
632 |
|
|
DMA_MODE_EXT ModeExt;
|
633 |
|
|
|
634 |
|
|
CtrlExt.AsWhole = 0;
|
635 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
636 |
|
|
dbg_msg(dbg_trace, "%s(): DMA_CTRL_EXT = 0x%04X.\n", __FUNCTION__, CtrlExt.AsWhole);
|
637 |
|
|
|
638 |
|
|
ModeExt.AsWhole = 0;
|
639 |
|
|
WriteOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr, ModeExt.AsWhole);
|
640 |
|
|
dbg_msg(dbg_trace, "%s(): channel = %d, DMA_MODE_EXT = 0x%X.\n", __FUNCTION__, NumberOfChannel, ModeExt.AsWhole);
|
641 |
|
|
}
|
642 |
|
|
|
643 |
|
|
brd->m_DmaChanEnbl[NumberOfChannel] = 0;
|
644 |
|
|
for(i = 0; i < MAX_NUMBER_OF_DMACHANNELS; i++)
|
645 |
|
|
if(brd->m_DmaChanEnbl[i])
|
646 |
|
|
enbl = 1;
|
647 |
|
|
brd->m_DmaIrqEnbl = enbl;
|
648 |
|
|
|
649 |
|
|
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
|
650 |
|
|
Status = DmaDisable(brd, 0, tetr_num);
|
651 |
|
|
CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
|
652 |
|
|
|
653 |
|
|
return Status;
|
654 |
|
|
}
|
655 |
|
|
|
656 |
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//--------------------------------------------------------------------
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657 |
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#if 0
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658 |
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static irqreturn_t pex_device_isr( int irq, void *pContext )
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659 |
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{
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660 |
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FIFO_STATUS FifoStatus; //
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661 |
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662 |
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struct pex_device* pDevice = (struct pex_device*)pContext; // our device
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663 |
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664 |
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if(!pDevice->m_DmaIrqEnbl && !pDevice->m_FlgIrqEnbl)
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665 |
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return IRQ_NONE; // we did not interrupt
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666 |
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if(pDevice->m_FlgIrqEnbl)
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667 |
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{ // прерывание от флагов состояния
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668 |
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/*
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669 |
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u32 status = ReadOperationWordReg(pDevice, PEMAINadr_BRD_STATUS);
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670 |
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err_msg(err_trace, "%s(): BRD_STATUS = 0x%X.\n", __FUNCTION__, status);
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671 |
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if(status & 0x4000)
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672 |
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{
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673 |
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for(int i = 0; i < NUM_TETR_IRQ; i++)
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674 |
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if(pDevice->m_TetrIrq[i] != 0)
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675 |
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{
|
676 |
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u32 status = ReadAmbMainReg(pDevice, pDevice->m_TetrIrq[i].Address);
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677 |
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KdPrint(("CWambpex::WambpexIsr: TetrIrq = %d, Address = 0x%X, IrqInv = 0x%X, IrqMask = 0x%X, Status = 0x%X.\n",
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678 |
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i, pDevice->m_TetrIrq[i].Address, pDevice->m_TetrIrq[i].IrqInv, pDevice->m_TetrIrq[i].IrqMask, status));
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679 |
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status ^= pDevice->m_TetrIrq[i].IrqInv;
|
680 |
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status &= pDevice->m_TetrIrq[i].IrqMask;
|
681 |
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KdPrint(("CWambpex::WambpexIsr: TetrIrq = %d, Address = 0x%X, IrqInv = 0x%X, IrqMask = 0x%X, Status = 0x%X.\n",
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682 |
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i, pDevice->m_TetrIrq[i].Address, pDevice->m_TetrIrq[i].IrqInv, pDevice->m_TetrIrq[i].IrqMask, status));
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683 |
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if(status)
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684 |
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{
|
685 |
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KeInsertQueueDpc(&pDevice->m_TetrIrq[i].Dpc, NULL, NULL);
|
686 |
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KdPrint(("CWambpex::WambpexIsr - Tetrad IRQ address = %d\n", pDevice->m_TetrIrq[i].Address));
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687 |
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// сброс статусного бита, вызвавшего прерывание
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688 |
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//pDevice->WriteAmbMainReg(pDevice->m_TetrIrq[i].Address + 0x200);
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689 |
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ULONG CmdAddress = pDevice->m_TetrIrq[i].Address + TRDadr_CMD_ADR * REG_SIZE;
|
690 |
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pDevice->WriteAmbMainReg(CmdAddress, 0);
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691 |
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ULONG DataAddress = pDevice->m_TetrIrq[i].Address + TRDadr_CMD_DATA * REG_SIZE;
|
692 |
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ULONG Mode0Value = pDevice->ReadAmbMainReg(DataAddress);
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693 |
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Mode0Value &= 0xFFFB;
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694 |
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//pDevice->WriteAmbMainReg(CmdAddress, 0);
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695 |
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pDevice->WriteAmbMainReg(DataAddress, Mode0Value);
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696 |
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break;
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697 |
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}
|
698 |
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}
|
699 |
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return IRQ_HANDLED;
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700 |
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}
|
701 |
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else // вообще не наше прерывание !!!
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702 |
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return IRQ_NONE; // we did not interrupt
|
703 |
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*/
|
704 |
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}
|
705 |
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|
706 |
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if(pDevice->m_DmaIrqEnbl)
|
707 |
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{ // прерывание от каналов ПДП
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708 |
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long NumberOfChannel = -1;
|
709 |
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u32 FifoAddr;
|
710 |
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long iChan = pDevice->m_primChan;
|
711 |
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for(LONG i = 0; i < MAX_NUMBER_OF_DMACHANNELS; i++)
|
712 |
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{
|
713 |
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if(pDevice->m_DmaChanMask & (1 << iChan))
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714 |
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{
|
715 |
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FifoAddr = pDevice->m_FifoAddr[iChan];
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716 |
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FifoStatus.AsWhole = ReadOperationWordReg(pDevice, PEFIFOadr_FIFO_STATUS + FifoAddr);
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717 |
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if(FifoStatus.ByBits.IntRql)
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718 |
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{
|
719 |
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err_msg(err_trace, "%s(): - Channel = %d, Fifo Status = 0x%X\n", __FUNCTION__, iChan, FifoStatus.AsWhole);
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720 |
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NumberOfChannel = iChan;
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721 |
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pDevice->m_primChan = ((pDevice->m_primChan+1) >= MAX_NUMBER_OF_DMACHANNELS) ? 0 : pDevice->m_primChan+1;
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722 |
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break;
|
723 |
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}
|
724 |
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}
|
725 |
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iChan = ((iChan+1) >= MAX_NUMBER_OF_DMACHANNELS) ? 0 : iChan+1;
|
726 |
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}
|
727 |
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|
728 |
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if(NumberOfChannel != -1)
|
729 |
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{
|
730 |
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u32 flag = NextDmaTransfer(pDevice->m_DmaChannel[NumberOfChannel]);
|
731 |
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|
732 |
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if(!flag)
|
733 |
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{
|
734 |
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DMA_CTRL_EXT CtrlExt;
|
735 |
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CtrlExt.AsWhole = 0;
|
736 |
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CtrlExt.ByBits.Pause = 1;
|
737 |
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CtrlExt.ByBits.Start = 1;
|
738 |
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WriteOperationWordReg(pDevice, PEFIFOadr_DMA_CTRL + FifoAddr, CtrlExt.AsWhole);
|
739 |
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err_msg(err_trace, "%s(): - Pause\n", __FUNCTION__);
|
740 |
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}
|
741 |
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|
742 |
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err_msg(err_trace, "%s(): - Flag Clear\n", __FUNCTION__);
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743 |
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WriteOperationWordReg(pDevice, PEFIFOadr_FLAG_CLR + FifoAddr, 0x10);
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744 |
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WriteOperationWordReg(pDevice, PEFIFOadr_FLAG_CLR + FifoAddr, 0x00);
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745 |
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err_msg(err_trace, "%s(): - Complete\n", __FUNCTION__);
|
746 |
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|
747 |
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return IRQ_HANDLED;
|
748 |
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}
|
749 |
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}
|
750 |
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return IRQ_NONE; // we did not interrupt
|
751 |
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}
|
752 |
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#endif
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