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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 1.3
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-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
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-- / / Filename : gtpa1_dual_wrapper_tile.vhd
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-- /___/ /\ Timestamp :
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-- \ \ / \
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-- \___\/\___\
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--
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--
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-- Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper)
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-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
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--
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--
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of,
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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--***************************** Entity Declaration ****************************
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entity GTPA1_DUAL_WRAPPER_TILE is
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generic
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(
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-- Simulation attributes
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TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
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--
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TILE_CLKINDC_B_0 : boolean := FALSE;
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TIlE_CLKINDC_B_1 : boolean := FALSE;
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--
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TILE_PLL_SOURCE_0 : string := "PLL0";
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TILE_PLL_SOURCE_1 : string := "PLL1"
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);
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port
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(
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------------------------ Loopback and Powerdown Ports ----------------------
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RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
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RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
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TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
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TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
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--------------------------------- PLL Ports --------------------------------
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CLK00_IN : in std_logic;
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CLK01_IN : in std_logic;
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GTPRESET0_IN : in std_logic;
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GTPRESET1_IN : in std_logic;
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PLLLKDET0_OUT : out std_logic;
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PLLLKDET1_OUT : out std_logic;
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RESETDONE0_OUT : out std_logic;
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RESETDONE1_OUT : out std_logic;
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----------------------- Receive Ports - 8b10b Decoder ----------------------
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RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
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RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
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RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
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RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
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RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
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RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
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---------------------- Receive Ports - Clock Correction --------------------
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RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
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RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
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--------------- Receive Ports - Comma Detection and Alignment --------------
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RXENMCOMMAALIGN0_IN : in std_logic;
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RXENMCOMMAALIGN1_IN : in std_logic;
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RXENPCOMMAALIGN0_IN : in std_logic;
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RXENPCOMMAALIGN1_IN : in std_logic;
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------------------- Receive Ports - RX Data Path interface -----------------
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RXDATA0_OUT : out std_logic_vector(15 downto 0);
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RXDATA1_OUT : out std_logic_vector(15 downto 0);
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RXRESET0_IN : in std_logic;
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RXRESET1_IN : in std_logic;
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RXUSRCLK0_IN : in std_logic;
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RXUSRCLK1_IN : in std_logic;
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RXUSRCLK20_IN : in std_logic;
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RXUSRCLK21_IN : in std_logic;
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------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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GATERXELECIDLE0_IN : in std_logic;
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GATERXELECIDLE1_IN : in std_logic;
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IGNORESIGDET0_IN : in std_logic;
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IGNORESIGDET1_IN : in std_logic;
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RXELECIDLE0_OUT : out std_logic;
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RXELECIDLE1_OUT : out std_logic;
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RXN0_IN : in std_logic;
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RXN1_IN : in std_logic;
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RXP0_IN : in std_logic;
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RXP1_IN : in std_logic;
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----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
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RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
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RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
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-------------- Receive Ports - RX Pipe Control for PCI Express -------------
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PHYSTATUS0_OUT : out std_logic;
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PHYSTATUS1_OUT : out std_logic;
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RXVALID0_OUT : out std_logic;
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RXVALID1_OUT : out std_logic;
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-------------------- Receive Ports - RX Polarity Control -------------------
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RXPOLARITY0_IN : in std_logic;
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RXPOLARITY1_IN : in std_logic;
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---------------------------- TX/RX Datapath Ports --------------------------
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GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
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GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
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------------------- Transmit Ports - 8b10b Encoder Control -----------------
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TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
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TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
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TXCHARISK0_IN : in std_logic_vector(1 downto 0);
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TXCHARISK1_IN : in std_logic_vector(1 downto 0);
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------------------ Transmit Ports - TX Data Path interface -----------------
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TXDATA0_IN : in std_logic_vector(15 downto 0);
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TXDATA1_IN : in std_logic_vector(15 downto 0);
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TXUSRCLK0_IN : in std_logic;
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TXUSRCLK1_IN : in std_logic;
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TXUSRCLK20_IN : in std_logic;
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TXUSRCLK21_IN : in std_logic;
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--------------- Transmit Ports - TX Driver and OOB signalling --------------
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TXN0_OUT : out std_logic;
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TXN1_OUT : out std_logic;
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TXP0_OUT : out std_logic;
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TXP1_OUT : out std_logic;
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----------------- Transmit Ports - TX Ports for PCI Express ----------------
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TXDETECTRX0_IN : in std_logic;
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TXDETECTRX1_IN : in std_logic;
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TXELECIDLE0_IN : in std_logic;
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TXELECIDLE1_IN : in std_logic
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);
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end GTPA1_DUAL_WRAPPER_TILE;
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architecture RTL of GTPA1_DUAL_WRAPPER_TILE is
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--**************************** Signal Declarations ****************************
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-- ground and tied_to_vcc_i signals
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signal tied_to_ground_i : std_logic;
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signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
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signal tied_to_vcc_i : std_logic;
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-- RX Datapath signals
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signal rxdata0_i : std_logic_vector(31 downto 0);
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signal rxchariscomma0_float_i : std_logic_vector(1 downto 0);
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signal rxcharisk0_float_i : std_logic_vector(1 downto 0);
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signal rxdisperr0_float_i : std_logic_vector(1 downto 0);
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signal rxnotintable0_float_i : std_logic_vector(1 downto 0);
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signal rxrundisp0_float_i : std_logic_vector(1 downto 0);
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-- TX Datapath signals
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signal txdata0_i : std_logic_vector(31 downto 0);
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signal txkerr0_float_i : std_logic_vector(1 downto 0);
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signal txrundisp0_float_i : std_logic_vector(1 downto 0);
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-- RX Datapath signals
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signal rxdata1_i : std_logic_vector(31 downto 0);
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signal rxchariscomma1_float_i : std_logic_vector(1 downto 0);
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signal rxcharisk1_float_i : std_logic_vector(1 downto 0);
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signal rxdisperr1_float_i : std_logic_vector(1 downto 0);
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signal rxnotintable1_float_i : std_logic_vector(1 downto 0);
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signal rxrundisp1_float_i : std_logic_vector(1 downto 0);
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-- TX Datapath signals
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signal txdata1_i : std_logic_vector(31 downto 0);
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signal txkerr1_float_i : std_logic_vector(1 downto 0);
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signal txrundisp1_float_i : std_logic_vector(1 downto 0);
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--******************************** Main Body of Code***************************
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begin
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--------------------------- Static signal Assignments ---------------------
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tied_to_ground_i <= '0';
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tied_to_ground_vec_i(63 downto 0) <= (others => '0');
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tied_to_vcc_i <= '1';
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------------------- GTP Datapath byte mapping -----------------
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-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
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RXDATA0_OUT <= rxdata0_i(15 downto 0);
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txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN);
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-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
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RXDATA1_OUT <= rxdata1_i(15 downto 0);
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txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN);
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----------------------------- GTPA1_DUAL Instance --------------------------
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gtpa1_dual_i:GTPA1_DUAL
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generic map
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(
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--_______________________ Simulation-Only Attributes ___________________
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SIM_RECEIVER_DETECT_PASS => (TRUE),
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SIM_TX_ELEC_IDLE_LEVEL => ("X"),
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SIM_VERSION => ("1.0"),
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SIM_REFCLK0_SOURCE => ("000"),
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SIM_REFCLK1_SOURCE => ("000"),
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SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
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--PLL Attributes
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CLK25_DIVIDER_0 => (4),
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CLKINDC_B_0 => (TILE_CLKINDC_B_0),
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CLKRCV_TRST_0 => (TRUE),
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OOB_CLK_DIVIDER_0 => (4),
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PLL_COM_CFG_0 => (x"21680a"),
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PLL_CP_CFG_0 => (x"00"),
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PLL_DIVSEL_FB_0 => (5),
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PLL_DIVSEL_REF_0 => (2),
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PLL_RXDIVSEL_OUT_0 => (1),
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PLL_SATA_0 => (FALSE),
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PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
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PLL_TXDIVSEL_OUT_0 => (1),
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PLLLKDET_CFG_0 => ("111"),
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CLK25_DIVIDER_1 => (5),
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--
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CLKINDC_B_1 => (TILE_CLKINDC_B_1),
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CLKRCV_TRST_1 => (TRUE),
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OOB_CLK_DIVIDER_1 => (4),
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PLL_COM_CFG_1 => (x"21680a"),
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PLL_CP_CFG_1 => (x"00"),
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PLL_DIVSEL_FB_1 => (2),
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PLL_DIVSEL_REF_1 => (1),
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PLL_RXDIVSEL_OUT_1 => (1),
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PLL_SATA_1 => (FALSE),
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PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
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PLL_TXDIVSEL_OUT_1 => (1),
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PLLLKDET_CFG_1 => ("111"),
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PMA_COM_CFG_EAST => (x"000000000"),
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PMA_COM_CFG_WEST => (x"000000000"),
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TST_ATTR_0 => (x"00000000"),
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TST_ATTR_1 => (x"00000000"),
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--TX Interface Attributes
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CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
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TX_TDCC_CFG_0 => ("11"),
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CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
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TX_TDCC_CFG_1 => ("11"),
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--TX Buffer and Phase Alignment Attributes
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PMA_TX_CFG_0 => (x"00082"),
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TX_BUFFER_USE_0 => (TRUE),
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TX_XCLK_SEL_0 => ("TXOUT"),
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TXRX_INVERT_0 => ("011"),
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PMA_TX_CFG_1 => (x"00082"),
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TX_BUFFER_USE_1 => (TRUE),
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TX_XCLK_SEL_1 => ("TXOUT"),
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TXRX_INVERT_1 => ("011"),
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--TX Driver and OOB signalling Attributes
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CM_TRIM_0 => ("00"),
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TX_IDLE_DELAY_0 => ("011"),
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CM_TRIM_1 => ("00"),
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TX_IDLE_DELAY_1 => ("011"),
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--TX PIPE/SATA Attributes
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COM_BURST_VAL_0 => ("1111"),
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|
|
COM_BURST_VAL_1 => ("1111"),
|
318 |
|
|
|
319 |
|
|
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
|
320 |
|
|
AC_CAP_DIS_0 => (FALSE),
|
321 |
|
|
OOBDETECT_THRESHOLD_0 => ("111"),
|
322 |
|
|
PMA_CDR_SCAN_0 => (x"6404040"),
|
323 |
|
|
PMA_RX_CFG_0 => (x"05ce048"),
|
324 |
|
|
PMA_RXSYNC_CFG_0 => (x"00"),
|
325 |
|
|
RCV_TERM_GND_0 => (TRUE),
|
326 |
|
|
RCV_TERM_VTTRX_0 => (FALSE),
|
327 |
|
|
RXEQ_CFG_0 => ("01111011"),
|
328 |
|
|
TERMINATION_CTRL_0 => ("10100"),
|
329 |
|
|
TERMINATION_OVRD_0 => (FALSE),
|
330 |
|
|
TX_DETECT_RX_CFG_0 => (x"1832"),
|
331 |
|
|
AC_CAP_DIS_1 => (FALSE),
|
332 |
|
|
OOBDETECT_THRESHOLD_1 => ("111"),
|
333 |
|
|
PMA_CDR_SCAN_1 => (x"6404040"),
|
334 |
|
|
PMA_RX_CFG_1 => (x"05ce048"),
|
335 |
|
|
PMA_RXSYNC_CFG_1 => (x"00"),
|
336 |
|
|
RCV_TERM_GND_1 => (TRUE),
|
337 |
|
|
RCV_TERM_VTTRX_1 => (FALSE),
|
338 |
|
|
RXEQ_CFG_1 => ("01111011"),
|
339 |
|
|
TERMINATION_CTRL_1 => ("10100"),
|
340 |
|
|
TERMINATION_OVRD_1 => (FALSE),
|
341 |
|
|
TX_DETECT_RX_CFG_1 => (x"1832"),
|
342 |
|
|
|
343 |
|
|
--Comma Detection and Alignment Attributes
|
344 |
|
|
ALIGN_COMMA_WORD_0 => (1),
|
345 |
|
|
COMMA_10B_ENABLE_0 => ("1111111111"),
|
346 |
|
|
DEC_MCOMMA_DETECT_0 => (TRUE),
|
347 |
|
|
DEC_PCOMMA_DETECT_0 => (TRUE),
|
348 |
|
|
DEC_VALID_COMMA_ONLY_0 => (TRUE),
|
349 |
|
|
MCOMMA_10B_VALUE_0 => ("1010000011"),
|
350 |
|
|
MCOMMA_DETECT_0 => (TRUE),
|
351 |
|
|
PCOMMA_10B_VALUE_0 => ("0101111100"),
|
352 |
|
|
PCOMMA_DETECT_0 => (TRUE),
|
353 |
|
|
RX_SLIDE_MODE_0 => ("PCS"),
|
354 |
|
|
ALIGN_COMMA_WORD_1 => (1),
|
355 |
|
|
COMMA_10B_ENABLE_1 => ("1111111111"),
|
356 |
|
|
DEC_MCOMMA_DETECT_1 => (TRUE),
|
357 |
|
|
DEC_PCOMMA_DETECT_1 => (TRUE),
|
358 |
|
|
DEC_VALID_COMMA_ONLY_1 => (TRUE),
|
359 |
|
|
MCOMMA_10B_VALUE_1 => ("1010000011"),
|
360 |
|
|
MCOMMA_DETECT_1 => (TRUE),
|
361 |
|
|
PCOMMA_10B_VALUE_1 => ("0101111100"),
|
362 |
|
|
PCOMMA_DETECT_1 => (TRUE),
|
363 |
|
|
RX_SLIDE_MODE_1 => ("PCS"),
|
364 |
|
|
|
365 |
|
|
--RX Loss-of-sync State Machine Attributes
|
366 |
|
|
RX_LOS_INVALID_INCR_0 => (8),
|
367 |
|
|
RX_LOS_THRESHOLD_0 => (128),
|
368 |
|
|
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
|
369 |
|
|
RX_LOS_INVALID_INCR_1 => (8),
|
370 |
|
|
RX_LOS_THRESHOLD_1 => (128),
|
371 |
|
|
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
|
372 |
|
|
|
373 |
|
|
--RX Elastic Buffer and Phase alignment Attributes
|
374 |
|
|
RX_BUFFER_USE_0 => (TRUE),
|
375 |
|
|
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
|
376 |
|
|
RX_IDLE_HI_CNT_0 => ("1000"),
|
377 |
|
|
RX_IDLE_LO_CNT_0 => ("0000"),
|
378 |
|
|
RX_XCLK_SEL_0 => ("RXREC"),
|
379 |
|
|
RX_BUFFER_USE_1 => (TRUE),
|
380 |
|
|
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
|
381 |
|
|
RX_IDLE_HI_CNT_1 => ("1000"),
|
382 |
|
|
RX_IDLE_LO_CNT_1 => ("0000"),
|
383 |
|
|
RX_XCLK_SEL_1 => ("RXREC"),
|
384 |
|
|
|
385 |
|
|
--Clock Correction Attributes
|
386 |
|
|
CLK_COR_ADJ_LEN_0 => (1),
|
387 |
|
|
CLK_COR_DET_LEN_0 => (1),
|
388 |
|
|
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
|
389 |
|
|
CLK_COR_KEEP_IDLE_0 => (FALSE),
|
390 |
|
|
CLK_COR_MAX_LAT_0 => (20),
|
391 |
|
|
CLK_COR_MIN_LAT_0 => (18),
|
392 |
|
|
CLK_COR_PRECEDENCE_0 => (TRUE),
|
393 |
|
|
CLK_COR_REPEAT_WAIT_0 => (0),
|
394 |
|
|
CLK_COR_SEQ_1_1_0 => ("0100011100"),
|
395 |
|
|
CLK_COR_SEQ_1_2_0 => ("0000000000"),
|
396 |
|
|
CLK_COR_SEQ_1_3_0 => ("0000000000"),
|
397 |
|
|
CLK_COR_SEQ_1_4_0 => ("0000000000"),
|
398 |
|
|
CLK_COR_SEQ_1_ENABLE_0 => ("0001"),
|
399 |
|
|
CLK_COR_SEQ_2_1_0 => ("0000000000"),
|
400 |
|
|
CLK_COR_SEQ_2_2_0 => ("0000000000"),
|
401 |
|
|
CLK_COR_SEQ_2_3_0 => ("0000000000"),
|
402 |
|
|
CLK_COR_SEQ_2_4_0 => ("0000000000"),
|
403 |
|
|
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
|
404 |
|
|
CLK_COR_SEQ_2_USE_0 => (FALSE),
|
405 |
|
|
CLK_CORRECT_USE_0 => (TRUE),
|
406 |
|
|
RX_DECODE_SEQ_MATCH_0 => (TRUE),
|
407 |
|
|
CLK_COR_ADJ_LEN_1 => (1),
|
408 |
|
|
CLK_COR_DET_LEN_1 => (1),
|
409 |
|
|
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
|
410 |
|
|
CLK_COR_KEEP_IDLE_1 => (FALSE),
|
411 |
|
|
CLK_COR_MAX_LAT_1 => (20),
|
412 |
|
|
CLK_COR_MIN_LAT_1 => (18),
|
413 |
|
|
CLK_COR_PRECEDENCE_1 => (TRUE),
|
414 |
|
|
CLK_COR_REPEAT_WAIT_1 => (0),
|
415 |
|
|
CLK_COR_SEQ_1_1_1 => ("0100011100"),
|
416 |
|
|
CLK_COR_SEQ_1_2_1 => ("0000000000"),
|
417 |
|
|
CLK_COR_SEQ_1_3_1 => ("0000000000"),
|
418 |
|
|
CLK_COR_SEQ_1_4_1 => ("0000000000"),
|
419 |
|
|
CLK_COR_SEQ_1_ENABLE_1 => ("0001"),
|
420 |
|
|
CLK_COR_SEQ_2_1_1 => ("0000000000"),
|
421 |
|
|
CLK_COR_SEQ_2_2_1 => ("0000000000"),
|
422 |
|
|
CLK_COR_SEQ_2_3_1 => ("0000000000"),
|
423 |
|
|
CLK_COR_SEQ_2_4_1 => ("0000000000"),
|
424 |
|
|
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
|
425 |
|
|
CLK_COR_SEQ_2_USE_1 => (FALSE),
|
426 |
|
|
CLK_CORRECT_USE_1 => (TRUE),
|
427 |
|
|
RX_DECODE_SEQ_MATCH_1 => (TRUE),
|
428 |
|
|
|
429 |
|
|
--Channel Bonding Attributes
|
430 |
|
|
CHAN_BOND_1_MAX_SKEW_0 => (1),
|
431 |
|
|
CHAN_BOND_2_MAX_SKEW_0 => (1),
|
432 |
|
|
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
|
433 |
|
|
CHAN_BOND_SEQ_1_1_0 => ("0001001010"),
|
434 |
|
|
CHAN_BOND_SEQ_1_2_0 => ("0001001010"),
|
435 |
|
|
CHAN_BOND_SEQ_1_3_0 => ("0001001010"),
|
436 |
|
|
CHAN_BOND_SEQ_1_4_0 => ("0110111100"),
|
437 |
|
|
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
|
438 |
|
|
CHAN_BOND_SEQ_2_1_0 => ("0100111100"),
|
439 |
|
|
CHAN_BOND_SEQ_2_2_0 => ("0100111100"),
|
440 |
|
|
CHAN_BOND_SEQ_2_3_0 => ("0110111100"),
|
441 |
|
|
CHAN_BOND_SEQ_2_4_0 => ("0100011100"),
|
442 |
|
|
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
|
443 |
|
|
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
|
444 |
|
|
CHAN_BOND_SEQ_LEN_0 => (1),
|
445 |
|
|
RX_EN_MODE_RESET_BUF_0 => (FALSE),
|
446 |
|
|
CHAN_BOND_1_MAX_SKEW_1 => (1),
|
447 |
|
|
CHAN_BOND_2_MAX_SKEW_1 => (1),
|
448 |
|
|
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
|
449 |
|
|
CHAN_BOND_SEQ_1_1_1 => ("0001001010"),
|
450 |
|
|
CHAN_BOND_SEQ_1_2_1 => ("0001001010"),
|
451 |
|
|
CHAN_BOND_SEQ_1_3_1 => ("0001001010"),
|
452 |
|
|
CHAN_BOND_SEQ_1_4_1 => ("0110111100"),
|
453 |
|
|
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
|
454 |
|
|
CHAN_BOND_SEQ_2_1_1 => ("0100111100"),
|
455 |
|
|
CHAN_BOND_SEQ_2_2_1 => ("0100111100"),
|
456 |
|
|
CHAN_BOND_SEQ_2_3_1 => ("0110111100"),
|
457 |
|
|
CHAN_BOND_SEQ_2_4_1 => ("0100011100"),
|
458 |
|
|
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
|
459 |
|
|
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
|
460 |
|
|
CHAN_BOND_SEQ_LEN_1 => (1),
|
461 |
|
|
RX_EN_MODE_RESET_BUF_1 => (FALSE),
|
462 |
|
|
|
463 |
|
|
--RX PCI Express Attributes
|
464 |
|
|
CB2_INH_CC_PERIOD_0 => (8),
|
465 |
|
|
CDR_PH_ADJ_TIME_0 => ("01010"),
|
466 |
|
|
PCI_EXPRESS_MODE_0 => (TRUE),
|
467 |
|
|
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
|
468 |
|
|
RX_EN_IDLE_RESET_FR_0 => (TRUE),
|
469 |
|
|
RX_EN_IDLE_RESET_PH_0 => (TRUE),
|
470 |
|
|
RX_STATUS_FMT_0 => ("PCIE"),
|
471 |
|
|
TRANS_TIME_FROM_P2_0 => (x"03c"),
|
472 |
|
|
TRANS_TIME_NON_P2_0 => (x"19"),
|
473 |
|
|
TRANS_TIME_TO_P2_0 => (x"064"),
|
474 |
|
|
CB2_INH_CC_PERIOD_1 => (8),
|
475 |
|
|
CDR_PH_ADJ_TIME_1 => ("01010"),
|
476 |
|
|
PCI_EXPRESS_MODE_1 => (TRUE),
|
477 |
|
|
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
|
478 |
|
|
RX_EN_IDLE_RESET_FR_1 => (TRUE),
|
479 |
|
|
RX_EN_IDLE_RESET_PH_1 => (TRUE),
|
480 |
|
|
RX_STATUS_FMT_1 => ("PCIE"),
|
481 |
|
|
TRANS_TIME_FROM_P2_1 => (x"03c"),
|
482 |
|
|
TRANS_TIME_NON_P2_1 => (x"19"),
|
483 |
|
|
TRANS_TIME_TO_P2_1 => (x"064"),
|
484 |
|
|
|
485 |
|
|
--RX SATA Attributes
|
486 |
|
|
SATA_BURST_VAL_0 => ("100"),
|
487 |
|
|
SATA_IDLE_VAL_0 => ("100"),
|
488 |
|
|
SATA_MAX_BURST_0 => (9),
|
489 |
|
|
SATA_MAX_INIT_0 => (27),
|
490 |
|
|
SATA_MAX_WAKE_0 => (9),
|
491 |
|
|
SATA_MIN_BURST_0 => (5),
|
492 |
|
|
SATA_MIN_INIT_0 => (15),
|
493 |
|
|
SATA_MIN_WAKE_0 => (5),
|
494 |
|
|
SATA_BURST_VAL_1 => ("100"),
|
495 |
|
|
SATA_IDLE_VAL_1 => ("100"),
|
496 |
|
|
SATA_MAX_BURST_1 => (9),
|
497 |
|
|
SATA_MAX_INIT_1 => (27),
|
498 |
|
|
SATA_MAX_WAKE_1 => (9),
|
499 |
|
|
SATA_MIN_BURST_1 => (5),
|
500 |
|
|
SATA_MIN_INIT_1 => (15),
|
501 |
|
|
SATA_MIN_WAKE_1 => (5)
|
502 |
|
|
|
503 |
|
|
|
504 |
|
|
)
|
505 |
|
|
port map
|
506 |
|
|
(
|
507 |
|
|
------------------------ Loopback and Powerdown Ports ----------------------
|
508 |
|
|
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
|
509 |
|
|
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
|
510 |
|
|
RXPOWERDOWN0 => RXPOWERDOWN0_IN,
|
511 |
|
|
RXPOWERDOWN1 => RXPOWERDOWN1_IN,
|
512 |
|
|
TXPOWERDOWN0 => TXPOWERDOWN0_IN,
|
513 |
|
|
TXPOWERDOWN1 => TXPOWERDOWN1_IN,
|
514 |
|
|
--------------------------------- PLL Ports --------------------------------
|
515 |
|
|
CLK00 => CLK00_IN,
|
516 |
|
|
CLK01 => CLK01_IN,
|
517 |
|
|
CLK10 => tied_to_ground_i,
|
518 |
|
|
CLK11 => tied_to_ground_i,
|
519 |
|
|
CLKINEAST0 => tied_to_ground_i,
|
520 |
|
|
CLKINEAST1 => tied_to_ground_i,
|
521 |
|
|
CLKINWEST0 => tied_to_ground_i,
|
522 |
|
|
CLKINWEST1 => tied_to_ground_i,
|
523 |
|
|
GCLK00 => tied_to_ground_i,
|
524 |
|
|
GCLK01 => tied_to_ground_i,
|
525 |
|
|
GCLK10 => tied_to_ground_i,
|
526 |
|
|
GCLK11 => tied_to_ground_i,
|
527 |
|
|
GTPRESET0 => GTPRESET0_IN,
|
528 |
|
|
GTPRESET1 => GTPRESET1_IN,
|
529 |
|
|
GTPTEST0 => "00010000",
|
530 |
|
|
GTPTEST1 => "00010000",
|
531 |
|
|
INTDATAWIDTH0 => tied_to_vcc_i,
|
532 |
|
|
INTDATAWIDTH1 => tied_to_vcc_i,
|
533 |
|
|
PLLCLK00 => tied_to_ground_i,
|
534 |
|
|
PLLCLK01 => tied_to_ground_i,
|
535 |
|
|
PLLCLK10 => tied_to_ground_i,
|
536 |
|
|
PLLCLK11 => tied_to_ground_i,
|
537 |
|
|
PLLLKDET0 => PLLLKDET0_OUT,
|
538 |
|
|
PLLLKDET1 => PLLLKDET1_OUT,
|
539 |
|
|
PLLLKDETEN0 => tied_to_vcc_i,
|
540 |
|
|
PLLLKDETEN1 => tied_to_vcc_i,
|
541 |
|
|
PLLPOWERDOWN0 => tied_to_ground_i,
|
542 |
|
|
PLLPOWERDOWN1 => tied_to_ground_i,
|
543 |
|
|
REFCLKOUT0 => open,
|
544 |
|
|
REFCLKOUT1 => open,
|
545 |
|
|
REFCLKPLL0 => open,
|
546 |
|
|
REFCLKPLL1 => open,
|
547 |
|
|
REFCLKPWRDNB0 => tied_to_vcc_i,
|
548 |
|
|
REFCLKPWRDNB1 => tied_to_vcc_i,
|
549 |
|
|
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
|
550 |
|
|
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
|
551 |
|
|
RESETDONE0 => RESETDONE0_OUT,
|
552 |
|
|
RESETDONE1 => RESETDONE1_OUT,
|
553 |
|
|
TSTCLK0 => tied_to_ground_i,
|
554 |
|
|
TSTCLK1 => tied_to_ground_i,
|
555 |
|
|
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
|
556 |
|
|
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
|
557 |
|
|
TSTOUT0 => open,
|
558 |
|
|
TSTOUT1 => open,
|
559 |
|
|
----------------------- Receive Ports - 8b10b Decoder ----------------------
|
560 |
|
|
RXCHARISCOMMA0 => open,
|
561 |
|
|
RXCHARISCOMMA1 => open,
|
562 |
|
|
RXCHARISK0(3 downto 2) => rxcharisk0_float_i,
|
563 |
|
|
RXCHARISK0(1 downto 0) => RXCHARISK0_OUT,
|
564 |
|
|
RXCHARISK1(3 downto 2) => rxcharisk1_float_i,
|
565 |
|
|
RXCHARISK1(1 downto 0) => RXCHARISK1_OUT,
|
566 |
|
|
RXDEC8B10BUSE0 => tied_to_vcc_i,
|
567 |
|
|
RXDEC8B10BUSE1 => tied_to_vcc_i,
|
568 |
|
|
RXDISPERR0(3 downto 2) => rxdisperr0_float_i,
|
569 |
|
|
RXDISPERR0(1 downto 0) => RXDISPERR0_OUT,
|
570 |
|
|
RXDISPERR1(3 downto 2) => rxdisperr1_float_i,
|
571 |
|
|
RXDISPERR1(1 downto 0) => RXDISPERR1_OUT,
|
572 |
|
|
RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i,
|
573 |
|
|
RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT,
|
574 |
|
|
RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i,
|
575 |
|
|
RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT,
|
576 |
|
|
RXRUNDISP0 => open,
|
577 |
|
|
RXRUNDISP1 => open,
|
578 |
|
|
USRCODEERR0 => tied_to_ground_i,
|
579 |
|
|
USRCODEERR1 => tied_to_ground_i,
|
580 |
|
|
---------------------- Receive Ports - Channel Bonding ---------------------
|
581 |
|
|
RXCHANBONDSEQ0 => open,
|
582 |
|
|
RXCHANBONDSEQ1 => open,
|
583 |
|
|
RXCHANISALIGNED0 => open,
|
584 |
|
|
RXCHANISALIGNED1 => open,
|
585 |
|
|
RXCHANREALIGN0 => open,
|
586 |
|
|
RXCHANREALIGN1 => open,
|
587 |
|
|
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
|
588 |
|
|
RXCHBONDMASTER0 => tied_to_ground_i,
|
589 |
|
|
RXCHBONDMASTER1 => tied_to_ground_i,
|
590 |
|
|
RXCHBONDO => open,
|
591 |
|
|
RXCHBONDSLAVE0 => tied_to_ground_i,
|
592 |
|
|
RXCHBONDSLAVE1 => tied_to_ground_i,
|
593 |
|
|
RXENCHANSYNC0 => tied_to_ground_i,
|
594 |
|
|
RXENCHANSYNC1 => tied_to_ground_i,
|
595 |
|
|
---------------------- Receive Ports - Clock Correction --------------------
|
596 |
|
|
RXCLKCORCNT0 => RXCLKCORCNT0_OUT,
|
597 |
|
|
RXCLKCORCNT1 => RXCLKCORCNT1_OUT,
|
598 |
|
|
--------------- Receive Ports - Comma Detection and Alignment --------------
|
599 |
|
|
RXBYTEISALIGNED0 => open,
|
600 |
|
|
RXBYTEISALIGNED1 => open,
|
601 |
|
|
RXBYTEREALIGN0 => open,
|
602 |
|
|
RXBYTEREALIGN1 => open,
|
603 |
|
|
RXCOMMADET0 => open,
|
604 |
|
|
RXCOMMADET1 => open,
|
605 |
|
|
RXCOMMADETUSE0 => tied_to_vcc_i,
|
606 |
|
|
RXCOMMADETUSE1 => tied_to_vcc_i,
|
607 |
|
|
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
|
608 |
|
|
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
|
609 |
|
|
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
|
610 |
|
|
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
|
611 |
|
|
RXSLIDE0 => tied_to_ground_i,
|
612 |
|
|
RXSLIDE1 => tied_to_ground_i,
|
613 |
|
|
----------------------- Receive Ports - PRBS Detection ---------------------
|
614 |
|
|
PRBSCNTRESET0 => tied_to_ground_i,
|
615 |
|
|
PRBSCNTRESET1 => tied_to_ground_i,
|
616 |
|
|
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
|
617 |
|
|
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
|
618 |
|
|
RXPRBSERR0 => open,
|
619 |
|
|
RXPRBSERR1 => open,
|
620 |
|
|
------------------- Receive Ports - RX Data Path interface -----------------
|
621 |
|
|
RXDATA0 => rxdata0_i,
|
622 |
|
|
RXDATA1 => rxdata1_i,
|
623 |
|
|
RXDATAWIDTH0 => "01",
|
624 |
|
|
RXDATAWIDTH1 => "01",
|
625 |
|
|
RXRECCLK0 => open,
|
626 |
|
|
RXRECCLK1 => open,
|
627 |
|
|
RXRESET0 => RXRESET0_IN,
|
628 |
|
|
RXRESET1 => RXRESET1_IN,
|
629 |
|
|
RXUSRCLK0 => RXUSRCLK0_IN,
|
630 |
|
|
RXUSRCLK1 => RXUSRCLK1_IN,
|
631 |
|
|
RXUSRCLK20 => RXUSRCLK20_IN,
|
632 |
|
|
RXUSRCLK21 => RXUSRCLK21_IN,
|
633 |
|
|
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
634 |
|
|
GATERXELECIDLE0 => GATERXELECIDLE0_IN,
|
635 |
|
|
GATERXELECIDLE1 => GATERXELECIDLE1_IN,
|
636 |
|
|
IGNORESIGDET0 => IGNORESIGDET0_IN,
|
637 |
|
|
IGNORESIGDET1 => IGNORESIGDET1_IN,
|
638 |
|
|
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
|
639 |
|
|
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
|
640 |
|
|
RCALOUTEAST => open,
|
641 |
|
|
RCALOUTWEST => open,
|
642 |
|
|
RXCDRRESET0 => tied_to_ground_i,
|
643 |
|
|
RXCDRRESET1 => tied_to_ground_i,
|
644 |
|
|
RXELECIDLE0 => RXELECIDLE0_OUT,
|
645 |
|
|
RXELECIDLE1 => RXELECIDLE1_OUT,
|
646 |
|
|
RXEQMIX0 => "11",
|
647 |
|
|
RXEQMIX1 => "11",
|
648 |
|
|
RXN0 => RXN0_IN,
|
649 |
|
|
RXN1 => RXN1_IN,
|
650 |
|
|
RXP0 => RXP0_IN,
|
651 |
|
|
RXP1 => RXP1_IN,
|
652 |
|
|
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
653 |
|
|
RXBUFRESET0 => tied_to_ground_i,
|
654 |
|
|
RXBUFRESET1 => tied_to_ground_i,
|
655 |
|
|
RXBUFSTATUS0 => open,
|
656 |
|
|
RXBUFSTATUS1 => open,
|
657 |
|
|
RXENPMAPHASEALIGN0 => tied_to_ground_i,
|
658 |
|
|
RXENPMAPHASEALIGN1 => tied_to_ground_i,
|
659 |
|
|
RXPMASETPHASE0 => tied_to_ground_i,
|
660 |
|
|
RXPMASETPHASE1 => tied_to_ground_i,
|
661 |
|
|
RXSTATUS0 => RXSTATUS0_OUT,
|
662 |
|
|
RXSTATUS1 => RXSTATUS1_OUT,
|
663 |
|
|
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
|
664 |
|
|
RXLOSSOFSYNC0 => open,
|
665 |
|
|
RXLOSSOFSYNC1 => open,
|
666 |
|
|
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
|
667 |
|
|
PHYSTATUS0 => PHYSTATUS0_OUT,
|
668 |
|
|
PHYSTATUS1 => PHYSTATUS1_OUT,
|
669 |
|
|
RXVALID0 => RXVALID0_OUT,
|
670 |
|
|
RXVALID1 => RXVALID1_OUT,
|
671 |
|
|
-------------------- Receive Ports - RX Polarity Control -------------------
|
672 |
|
|
RXPOLARITY0 => RXPOLARITY0_IN,
|
673 |
|
|
RXPOLARITY1 => RXPOLARITY1_IN,
|
674 |
|
|
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
|
675 |
|
|
DADDR => tied_to_ground_vec_i(7 downto 0),
|
676 |
|
|
DCLK => tied_to_ground_i,
|
677 |
|
|
DEN => tied_to_ground_i,
|
678 |
|
|
DI => tied_to_ground_vec_i(15 downto 0),
|
679 |
|
|
DRDY => open,
|
680 |
|
|
DRPDO => open,
|
681 |
|
|
DWE => tied_to_ground_i,
|
682 |
|
|
---------------------------- TX/RX Datapath Ports --------------------------
|
683 |
|
|
GTPCLKFBEAST => open,
|
684 |
|
|
GTPCLKFBSEL0EAST => "10",
|
685 |
|
|
GTPCLKFBSEL0WEST => "00",
|
686 |
|
|
GTPCLKFBSEL1EAST => "11",
|
687 |
|
|
GTPCLKFBSEL1WEST => "01",
|
688 |
|
|
GTPCLKFBWEST => open,
|
689 |
|
|
GTPCLKOUT0 => GTPCLKOUT0_OUT,
|
690 |
|
|
GTPCLKOUT1 => GTPCLKOUT1_OUT,
|
691 |
|
|
------------------- Transmit Ports - 8b10b Encoder Control -----------------
|
692 |
|
|
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
|
693 |
|
|
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
|
694 |
|
|
TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
695 |
|
|
TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN,
|
696 |
|
|
TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
697 |
|
|
TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN,
|
698 |
|
|
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
|
699 |
|
|
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
|
700 |
|
|
TXCHARISK0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
701 |
|
|
TXCHARISK0(1 downto 0) => TXCHARISK0_IN,
|
702 |
|
|
TXCHARISK1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
703 |
|
|
TXCHARISK1(1 downto 0) => TXCHARISK1_IN,
|
704 |
|
|
TXENC8B10BUSE0 => tied_to_vcc_i,
|
705 |
|
|
TXENC8B10BUSE1 => tied_to_vcc_i,
|
706 |
|
|
TXKERR0 => open,
|
707 |
|
|
TXKERR1 => open,
|
708 |
|
|
TXRUNDISP0 => open,
|
709 |
|
|
TXRUNDISP1 => open,
|
710 |
|
|
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
|
711 |
|
|
TXBUFSTATUS0 => open,
|
712 |
|
|
TXBUFSTATUS1 => open,
|
713 |
|
|
TXENPMAPHASEALIGN0 => tied_to_ground_i,
|
714 |
|
|
TXENPMAPHASEALIGN1 => tied_to_ground_i,
|
715 |
|
|
TXPMASETPHASE0 => tied_to_ground_i,
|
716 |
|
|
TXPMASETPHASE1 => tied_to_ground_i,
|
717 |
|
|
------------------ Transmit Ports - TX Data Path interface -----------------
|
718 |
|
|
TXDATA0 => txdata0_i,
|
719 |
|
|
TXDATA1 => txdata1_i,
|
720 |
|
|
TXDATAWIDTH0 => "01",
|
721 |
|
|
TXDATAWIDTH1 => "01",
|
722 |
|
|
TXOUTCLK0 => open,
|
723 |
|
|
TXOUTCLK1 => open,
|
724 |
|
|
TXRESET0 => tied_to_ground_i,
|
725 |
|
|
TXRESET1 => tied_to_ground_i,
|
726 |
|
|
TXUSRCLK0 => TXUSRCLK0_IN,
|
727 |
|
|
TXUSRCLK1 => TXUSRCLK1_IN,
|
728 |
|
|
TXUSRCLK20 => TXUSRCLK20_IN,
|
729 |
|
|
TXUSRCLK21 => TXUSRCLK21_IN,
|
730 |
|
|
--------------- Transmit Ports - TX Driver and OOB signalling --------------
|
731 |
|
|
TXBUFDIFFCTRL0 => "101",
|
732 |
|
|
TXBUFDIFFCTRL1 => "101",
|
733 |
|
|
TXDIFFCTRL0 => "0111",
|
734 |
|
|
TXDIFFCTRL1 => "0111",
|
735 |
|
|
TXINHIBIT0 => tied_to_ground_i,
|
736 |
|
|
TXINHIBIT1 => tied_to_ground_i,
|
737 |
|
|
TXN0 => TXN0_OUT,
|
738 |
|
|
TXN1 => TXN1_OUT,
|
739 |
|
|
TXP0 => TXP0_OUT,
|
740 |
|
|
TXP1 => TXP1_OUT,
|
741 |
|
|
TXPREEMPHASIS0 => "100",
|
742 |
|
|
TXPREEMPHASIS1 => "100",
|
743 |
|
|
--------------------- Transmit Ports - TX PRBS Generator -------------------
|
744 |
|
|
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
|
745 |
|
|
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
|
746 |
|
|
TXPRBSFORCEERR0 => tied_to_ground_i,
|
747 |
|
|
TXPRBSFORCEERR1 => tied_to_ground_i,
|
748 |
|
|
-------------------- Transmit Ports - TX Polarity Control ------------------
|
749 |
|
|
TXPOLARITY0 => tied_to_ground_i,
|
750 |
|
|
TXPOLARITY1 => tied_to_ground_i,
|
751 |
|
|
----------------- Transmit Ports - TX Ports for PCI Express ----------------
|
752 |
|
|
TXDETECTRX0 => TXDETECTRX0_IN,
|
753 |
|
|
TXDETECTRX1 => TXDETECTRX1_IN,
|
754 |
|
|
TXELECIDLE0 => TXELECIDLE0_IN,
|
755 |
|
|
TXELECIDLE1 => TXELECIDLE1_IN,
|
756 |
|
|
TXPDOWNASYNCH0 => tied_to_ground_i,
|
757 |
|
|
TXPDOWNASYNCH1 => tied_to_ground_i,
|
758 |
|
|
--------------------- Transmit Ports - TX Ports for SATA -------------------
|
759 |
|
|
TXCOMSTART0 => tied_to_ground_i,
|
760 |
|
|
TXCOMSTART1 => tied_to_ground_i,
|
761 |
|
|
TXCOMTYPE0 => tied_to_ground_i,
|
762 |
|
|
TXCOMTYPE1 => tied_to_ground_i
|
763 |
|
|
|
764 |
|
|
);
|
765 |
|
|
|
766 |
|
|
end RTL;
|
767 |
|
|
|
768 |
|
|
|
769 |
|
|
|