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[/] [pcie_mini/] [trunk/] [example_design/] [pcie_bram_s6.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information of Xilinx, Inc.
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-- and is protected under U.S. and international copyright and other
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-- intellectual property laws.
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--
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-- DISCLAIMER
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--
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-- This disclaimer is not a license and does not grant any rights to the
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-- materials distributed herewith. Except as otherwise provided in a valid
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-- license issued to you by Xilinx, and to the maximum extent permitted by
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-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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-- and (2) Xilinx shall not be liable (whether in contract or tort, including
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-- negligence, or under any other theory of liability) for any loss or damage
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-- of any kind or nature related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect, special, incidental,
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-- or consequential loss or damage (including loss of data, profits, goodwill,
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-- or any type of loss or damage suffered as a result of any action brought by
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-- a third party) even if such damage or loss was reasonably foreseeable or
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-- Xilinx had been advised of the possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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--
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-- Xilinx products are not designed or intended to be fail-safe, or for use in
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-- any application requiring fail-safe performance, such as life-support or
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-- safety devices or systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any other
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-- applications that could lead to death, personal injury, or severe property
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-- or environmental damage (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and liability of any use of
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-- Xilinx products in Critical Applications, subject only to applicable laws
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-- and regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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-- AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project    : Spartan-6 Integrated Block for PCI Express
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-- File       : pcie_bram_s6.vhd
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-- Description: BlockRAM module for Spartan-6 PCIe Block
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--              The BRAM A port is the write port.
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--              The BRAM B port is the read port.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_bram_s6 is
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  generic (
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    DOB_REG   : integer := 0; --  1 use output register, 0 don't use output register
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    WIDTH     : integer := 0  --  supported WIDTH values are: 4, 9, 18, 36
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  );
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  port (
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    user_clk_i   : in  std_logic; --  user clock
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    reset_i      : in  std_logic; --  bram reset
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    wen_i        : in  std_logic; --  write enable
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    waddr_i      : in  std_logic_vector(11 downto 0); --  write address
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    wdata_i      : in  std_logic_vector(WIDTH-1 downto 0); --  write data
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    ren_i        : in  std_logic; --  read enable
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    rce_i        : in  std_logic; --  output register clock enable
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    raddr_i      : in  std_logic_vector(11 downto 0); --  read address
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    rdata_o      : out std_logic_vector(WIDTH-1 downto 0) --  read data
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  );
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end pcie_bram_s6;
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architecture rtl of pcie_bram_s6 is
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  function CALC_ADDR(constant WIDTH : in integer;
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                     constant addr_in : in std_logic_vector(11 downto 0)
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                    ) return std_logic_vector is
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    variable ADDR : std_logic_vector(13 downto 0);
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  begin
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    if    WIDTH = 4 then  ADDR := addr_in(11 downto 0) & "00";
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    elsif WIDTH = 9 then  ADDR := addr_in(10 downto 0) & "000";
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    elsif WIDTH = 18 then ADDR := addr_in(9  downto 0) & "0000";
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    else                  ADDR := addr_in(8  downto 0) & "00000"; -- WIDTH=36
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    end if;
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    return ADDR;
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  end function CALC_ADDR;
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  signal di_int     : std_logic_vector(31 downto 0);
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  signal dip_int    : std_logic_vector(3 downto 0);
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  signal do_int     : std_logic_vector(31 downto 0);
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  signal dop_int    : std_logic_vector(3 downto 0);
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  signal waddr_int  : std_logic_vector(13 downto 0);
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  signal raddr_int  : std_logic_vector(13 downto 0);
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  signal wen_int    : std_logic_vector(3 downto 0);
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begin
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  --synthesis translate_off
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  process
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  begin
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    case WIDTH is
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      when 4 | 9 | 18 | 36 =>
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        null;
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      when others =>
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        report "ERROR: WIDTH size " & integer'image(WIDTH) & " is not supported."
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          severity failure;
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    end case;
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    wait;
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  end process;
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  --synthesis translate_on
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  -- Wire up BRAM I/Os to module I/Os - map data & parity bits appropriately
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  width_36 : if (WIDTH = 36) generate
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    di_int                <= wdata_i(31 downto 0);
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    dip_int               <= wdata_i(35 downto 32);
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    rdata_o(35 downto 32) <= dop_int;
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    rdata_o(31 downto 0)  <= do_int;
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  end generate width_36;
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  width_18 : if (WIDTH = 18) generate
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    di_int(31 downto 16)  <= (OTHERS => '0');
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    di_int(15 downto 0)   <= wdata_i(15 downto 0);
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    dip_int(3 downto 2)   <= (OTHERS => '0');
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    dip_int(1 downto 0)   <= wdata_i(17 downto 16);
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    rdata_o(17 downto 16) <= dop_int(1 downto 0);
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    rdata_o(15 downto 0)  <= do_int(15 downto 0);
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  end generate width_18;
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  width_9 : if (WIDTH = 9) generate
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    di_int(31 downto 8)   <= (OTHERS => '0');
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    di_int(7 downto 0)    <= wdata_i(7 downto 0);
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    dip_int(3 downto 1)   <= (OTHERS => '0');
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    dip_int(0)            <= wdata_i(8);
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    rdata_o(8)            <= dop_int(0);
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    rdata_o(7 downto 0)   <= do_int(7 downto 0);
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  end generate width_9;
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  width_4 : if (WIDTH = 4) generate
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    di_int(31 downto 4)   <= (OTHERS => '0');
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    di_int(3 downto 0)    <= wdata_i(3 downto 0);
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    dip_int               <= (OTHERS => '0');
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    rdata_o               <= do_int(3 downto 0);
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  end generate width_4;
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  waddr_int <= CALC_ADDR(WIDTH, waddr_i);
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  raddr_int <= CALC_ADDR(WIDTH, raddr_i);
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  wen_int   <= wen_i & wen_i & wen_i & wen_i;
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  ramb16 : RAMB16BWER
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  generic map (
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    DATA_WIDTH_A  => WIDTH,
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    DATA_WIDTH_B  => WIDTH,
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    DOA_REG       => 0,
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    DOB_REG       => DOB_REG,
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    WRITE_MODE_A  => "NO_CHANGE",
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    WRITE_MODE_B  => "NO_CHANGE"
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  )
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  port map (
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    CLKA           => user_clk_i,
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    RSTA           => reset_i,
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    DOA            => open,
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    DOPA           => open,
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    ADDRA          => waddr_int,
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    DIA            => di_int,
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    DIPA           => dip_int,
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    ENA            => wen_i,
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    WEA            => wen_int,
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    REGCEA         => '0',
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    CLKB           => user_clk_i,
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    RSTB           => reset_i,
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    WEB            => "0000",
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    DIB            => x"00000000",
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    DIPB           => "0000",
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    ADDRB          => raddr_int,
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    DOB            => do_int,
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    DOPB           => dop_int,
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    ENB            => ren_i,
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    REGCEB         => rce_i
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  );
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end rtl;
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