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[/] [pcie_mini/] [trunk/] [main_sources/] [oldversions/] [xilinx_pcie2wb_v1.2.vhd] - Blame information for rev 11

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1 11 buenos
----------------------------------------------------------------------------------
2
-- Company:
3
-- Engineer: Istvan Nagy, buenos@freemail.hu
4
-- 
5
-- Create Date:    05/30/2010
6
-- Modify date:    08/10/2012
7
-- Design Name:    pcie_mini
8
-- Module Name:    xilinx_pcie2wb - Behavioral 
9
-- Version:        1.2
10
-- Project Name: 
11
-- Target Devices: Xilinx Series-5/6/7 FPGAs
12
-- Tool versions: ISE-DS 12.1
13
-- Description: 
14
--  PCI-express endpoint block, transaction layer logic and back-end logic. The main 
15
--  purpose of this file is to make a useable back-end interface and handle flow control
16
--  for the xilinx auto-generated PCIe endpoint IP.
17
--  The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
18
--  This 256MBytes size is set up in the core config, and also hardcoded in this 
19
--  file (search for: "256MBytes").
20
--  This 1 BAR is implemented as a Wishbone master interface with byte addressing,
21
--  where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
22
--  ADDRESSES ARE BYTE ADDRESSES. 
23
--  The lower address bits are usually zero, so the slave (MCB) has to select bytes based 
24
--  on the byte select signals: sel[3:0]. The output address of the core contails the 2 
25
--  LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
26
--  The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a 
27
--  single PCIe transaction, and can handle only one request at a time. If a new request 
28
--  is arriving while processing the previous one (e.g. getting the data from a wishbone 
29
--  read), then the state machine will not process it immediately, or it will hang. So 
30
--  the user software has to wait for the previous read completion before issueing a new 
31
--  request. The multiple DWORDs are handled separately by the WB statemachine.
32
--  Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum 
33
--  data throughput can be achieved when using the maximum data payload (block).
34
--  The core uses INTA wirtual wire to signal interrupts.
35
--  
36
-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. The generated core had to
37
-- be edited manually to support 100MHz, as per Xilinx AR#33761.
38
--
39
-- Dependencies: The CoreGenerator's configured PCIe core is included.
40
--  If we generate a new pcie endpoint, then copy the new files from the source
41
--  directory into the project's directory, and copy the generic section of the "pcie" 
42
--  from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
43
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
44
--
45
-- Revision: 
46
-- Revision 1.0 - File Created by Istvan Nagy
47
-- Revision 1.1 - some fixes by Istvan Nagy
48
-- Revision 1.2 - interrupt fix by Stephen Battazzo
49
--
50
----------------------------------------------------------------------------------
51
 
52
library IEEE;
53
use IEEE.STD_LOGIC_1164.ALL;
54
use IEEE.STD_LOGIC_ARITH.ALL;
55
use IEEE.STD_LOGIC_UNSIGNED.ALL;
56
 
57
-- Uncomment the following library declaration if instantiating
58
-- any Xilinx primitives in this code.
59
library UNISIM;
60
use UNISIM.VComponents.all;
61
 
62
 
63
 
64
entity xilinx_pcie2wb is
65
    Port ( --FPGA PINS(EXTERNAL):
66
                         pci_exp_txp             : out std_logic;
67
                         pci_exp_txn             : out std_logic;
68
                         pci_exp_rxp             : in  std_logic;
69
                         pci_exp_rxn             : in  std_logic;
70
                         sys_clk_n                 : in  std_logic;
71
                         sys_clk_p                 : in  std_logic;
72
                         sys_reset_n             : in  std_logic;
73
                         --ON CHIP PORTS:
74
                         --DATA BUS for BAR0 (wishbone):
75
                         pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
76
                         pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
77
                         pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
78
                         pcie_bar0_wb_cyc_o : out std_logic;
79
                         pcie_bar0_wb_stb_o : out std_logic;
80
                         pcie_bar0_wb_wr_o : out std_logic;
81
                         pcie_bar0_wb_ack_i : in std_logic;
82
                         pcie_bar0_wb_clk_o : out std_logic; --62.5MHz          
83
                         pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
84
                         --OTHER:
85
                         pcie_irq : in std_logic;
86
                         pcie_resetout  : out std_logic --active high
87
                        );
88
end xilinx_pcie2wb;
89
 
90
 
91
 
92
 
93
architecture Behavioral of xilinx_pcie2wb is
94
 
95
 
96
 
97
 
98
   -- Internal Signals ------------------------------------------------------------
99
        --SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
100
        SIGNAL          cfg_do  :               std_logic_vector(31     downto  0);
101
        SIGNAL          cfg_rd_wr_done_n        :               std_logic;
102
        SIGNAL          cfg_dwaddr      :               std_logic_vector(9      downto  0);
103
        SIGNAL          cfg_rd_en_n     :               std_logic;
104
        SIGNAL          cfg_err_ur_n    :               std_logic;
105
        SIGNAL          cfg_err_cor_n   :               std_logic;
106
        SIGNAL          cfg_err_ecrc_n  :               std_logic;
107
        SIGNAL          cfg_err_cpl_timeout_n   :               std_logic;
108
        SIGNAL          cfg_err_cpl_abort_n     :               std_logic;
109
        SIGNAL          cfg_err_posted_n        :               std_logic;
110
        SIGNAL          cfg_err_locked_n        :               std_logic;
111
        SIGNAL          cfg_err_tlp_cpl_header  :               std_logic_vector(47     downto  0);
112
        SIGNAL          cfg_err_cpl_rdy_n       :               std_logic;
113
        SIGNAL          cfg_interrupt_n :               std_logic;
114
        SIGNAL          cfg_interrupt_rdy_n     :               std_logic;
115
        SIGNAL          cfg_interrupt_assert_n  :               std_logic;
116
        SIGNAL          cfg_interrupt_do        :               std_logic_vector(7      downto  0);
117
        SIGNAL          cfg_interrupt_di        :               std_logic_vector(7      downto  0);
118
        SIGNAL          cfg_interrupt_mmenable  :               std_logic_vector(2      downto  0);
119
        SIGNAL          cfg_interrupt_msienable :               std_logic;
120
        SIGNAL          cfg_turnoff_ok_n        :               std_logic;
121
        SIGNAL          cfg_to_turnoff_n        :               std_logic;
122
        SIGNAL          cfg_pm_wake_n   :               std_logic;
123
        SIGNAL          cfg_pcie_link_state_n   :               std_logic_vector(2      downto  0);
124
        SIGNAL          cfg_trn_pending_n       :               std_logic;
125
        SIGNAL          cfg_dsn :               std_logic_vector(63     downto  0);
126
        SIGNAL          cfg_bus_number  :               std_logic_vector(7      downto  0);
127
        SIGNAL          cfg_device_number       :               std_logic_vector(4      downto  0);
128
        SIGNAL          cfg_function_number     :               std_logic_vector(2      downto  0);
129
        SIGNAL          cfg_status      :               std_logic_vector(15     downto  0);
130
        SIGNAL          cfg_command     :               std_logic_vector(15     downto  0);
131
        SIGNAL          cfg_dstatus     :               std_logic_vector(15     downto  0);
132
        SIGNAL          cfg_dcommand    :               std_logic_vector(15     downto  0);
133
        SIGNAL          cfg_lstatus     :               std_logic_vector(15     downto  0);
134
        SIGNAL          cfg_lcommand    :               std_logic_vector(15     downto  0);
135
    -- System Interface
136
        SIGNAL      sys_clk                 :   std_logic;
137
        SIGNAL      trn_clk                 :  std_logic;
138
        SIGNAL      trn_reset_n             :  std_logic;
139
        SIGNAL      received_hot_reset      :  std_logic;
140
    -- Transaction (TRN) Interface
141
        SIGNAL      trn_lnk_up_n            :  std_logic;
142
        --      data interface Tx                                       
143
        SIGNAL          trn_td  :               std_logic_vector(31     downto  0);
144
        SIGNAL          trn_tsof_n      :               std_logic;
145
        SIGNAL          trn_teof_n      :               std_logic;
146
        SIGNAL          trn_tsrc_rdy_n  :               std_logic;
147
        SIGNAL          trn_tdst_rdy_n  :               std_logic;
148
        SIGNAL          trn_terr_drop_n :               std_logic;
149
        SIGNAL          trn_tsrc_dsc_n  :               std_logic;
150
        SIGNAL          trn_terrfwd_n   :               std_logic;
151
        SIGNAL          trn_tbuf_av     :               std_logic_vector(5      downto  0);
152
        SIGNAL          trn_tstr_n      :               std_logic;
153
        SIGNAL          trn_tcfg_req_n  :               std_logic;
154
        SIGNAL          trn_tcfg_gnt_n  :               std_logic;
155
        --      data interface Rx                                       
156
        SIGNAL          trn_rd  :               std_logic_vector(31     downto  0);
157
        SIGNAL          trn_rsof_n      :               std_logic;
158
        SIGNAL          trn_reof_n      :               std_logic;
159
        SIGNAL          trn_rsrc_rdy_n  :               std_logic;
160
        SIGNAL          trn_rsrc_dsc_n  :               std_logic;
161
        SIGNAL          trn_rdst_rdy_n  :               std_logic;
162
        SIGNAL          trn_rerrfwd_n   :               std_logic;
163
        SIGNAL          trn_rnp_ok_n    :               std_logic;
164
        SIGNAL          trn_rbar_hit_n  :               std_logic_vector(6      downto  0);
165
        -- flow control
166
        SIGNAL          trn_fc_sel      :               std_logic_vector(2      downto  0);
167
        SIGNAL          trn_fc_nph      :               std_logic_vector(7      downto  0);
168
        SIGNAL          trn_fc_npd      :               std_logic_vector(11     downto  0);
169
        SIGNAL          trn_fc_ph       :               std_logic_vector(7      downto  0);
170
        SIGNAL          trn_fc_pd       :               std_logic_vector(11     downto  0);
171
        SIGNAL          trn_fc_cplh     :               std_logic_vector(7      downto  0);
172
        SIGNAL          trn_fc_cpld     :               std_logic_vector(11     downto  0);
173
 
174
        SIGNAL   start_read_wb0 :               std_logic;
175
        SIGNAL   start_write_wb0        :               std_logic;
176
        SIGNAL   wb_transaction_complete        :               std_logic;
177
        SIGNAL   pcie_bar0_wb_data_i_latched    :               std_logic_vector(31     downto  0);
178
        SIGNAL   pcie_bar0_wb_data_o_feed       :               std_logic_vector(31     downto  0);
179
        SIGNAL   pcie_bar0_wb_addr_o_feed       :               std_logic_vector(27     downto  0);
180
        SIGNAL   pcie_bar0_wb_sel_o_feed        :               std_logic_vector(3      downto  0);
181
        SIGNAL   start_read_wb1 :               std_logic;
182
        SIGNAL   start_write_wb1        :               std_logic;
183
        SIGNAL   rd_data_ready_wb1      :               std_logic;
184
 
185
    SIGNAL   pcie_just_received_a_new_tlp      :  std_logic  ;
186
    SIGNAL   pcie_start_reading_rx_tlp      :  std_logic  ;
187
    SIGNAL   pcie_there_is_a_new_tlp_to_transmit      :  std_logic  ;
188
    SIGNAL   rxtlp_decodedaddress      :  std_logic_vector(31 downto 0);
189
    SIGNAL   tlp_payloadsize_dwords      :  std_logic_vector(7 downto 0);
190
    SIGNAL   rxtlp_firstdw_be      :  std_logic_vector(3 downto 0);
191
    SIGNAL   rxtlp_lastdw_be      :  std_logic_vector(3 downto 0);
192
    SIGNAL   rxtlp_requesterid      :  std_logic_vector(15 downto 0);
193
    SIGNAL   tlp_state      :  std_logic_vector(7 downto 0);
194
    SIGNAL   tlp_state_copy      :  std_logic_vector(7 downto 0);
195
    SIGNAL   rxtlp_data_0      :  std_logic_vector(31 downto 0);
196
    SIGNAL   rxtlp_data_1      :  std_logic_vector(31 downto 0);
197
    SIGNAL   rxtlp_data_2      :  std_logic_vector(31 downto 0);
198
    SIGNAL   rxtlp_data_3      :  std_logic_vector(31 downto 0);
199
    SIGNAL   rxtlp_data_4      :  std_logic_vector(31 downto 0);
200
    SIGNAL   rxtlp_data_5      :  std_logic_vector(31 downto 0);
201
    SIGNAL   rxtlp_data_6      :  std_logic_vector(31 downto 0);
202
    SIGNAL   rxtlp_data_7      :  std_logic_vector(31 downto 0);
203
    SIGNAL   txtlp_data_0      :  std_logic_vector(31 downto 0);
204
    SIGNAL   txtlp_data_1      :  std_logic_vector(31 downto 0);
205
    SIGNAL   txtlp_data_2      :  std_logic_vector(31 downto 0);
206
    SIGNAL   txtlp_data_3      :  std_logic_vector(31 downto 0);
207
    SIGNAL   txtlp_data_4      :  std_logic_vector(31 downto 0);
208
    SIGNAL   txtlp_data_5      :  std_logic_vector(31 downto 0);
209
    SIGNAL   txtlp_data_6      :  std_logic_vector(31 downto 0);
210
    SIGNAL   txtlp_data_7      :  std_logic_vector(31 downto 0);
211
    SIGNAL   pcie_tlp_tx_complete       :  std_logic;
212
 
213
         --this signal added by StBa, AAC Microtec
214
         SIGNAL  irq_prohibit    :   std_logic;
215
 
216
         SIGNAL  pcieirq_state    :  std_logic_vector(7 downto 0);
217
         SIGNAL  txtrn_counter   :  std_logic_vector(7 downto 0);
218
         SIGNAL  trn_rx_counter   :  std_logic_vector(7 downto 0);
219
         SIGNAL cfg_completer_id  :  std_logic_vector(15 downto 0);
220
         SIGNAL wb0_state :   std_logic_vector(7 downto 0);
221
         SIGNAL epif_tx_state :   std_logic_vector(7 downto 0);
222
         SIGNAL epif_rx_state :   std_logic_vector(7 downto 0);
223
         SIGNAL bit10 :   std_logic_vector(1 downto 0);
224
 
225
  SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
226
  SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
227
  SIGNAL bram_rxtlp_writedata : std_logic_vector(31 downto 0);
228
  SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
229
  SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
230
  SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
231
  SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
232
  SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
233
  SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
234
  SIGNAL bram_txtlp_readdata : std_logic_vector(31 downto 0);
235
 
236
  SIGNAL tlp_datacount :   std_logic_vector(7 downto 0);
237
  --SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
238
  SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
239
  SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
240
  SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
241
  SIGNAL rxtlp_header_dw4 : std_logic_vector(31 downto 0);
242
  SIGNAL flag1 :      std_logic;
243
  SIGNAL rxdw1_23_0  : std_logic_vector(23 downto 0);
244
  SIGNAL pcie_rxtlp_tag  : std_logic_vector(7 downto 0);
245
  SIGNAL pciewb_localreset_n :      std_logic;
246
  SIGNAL cfg_interrupt_assert_n_1 :      std_logic;
247
  SIGNAL trn_tsrc_rdy_n_1 :      std_logic;
248
  SIGNAL trn_tsof_n1 :      std_logic;
249
  SIGNAL rcompl_bytecount_field  : std_logic_vector(9 downto 0);
250
  SIGNAL rxstm_readytoroll :      std_logic;
251
  SIGNAL tlpstm_isin_idle :      std_logic;
252
 
253
 
254
 
255
 
256
 
257
        -- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
258
 
259
  --this is the pcie endpoint core from coregenerator.
260
        --Core name: Xilinx Spartan-6 Integrated
261
        --Block for PCI Express
262
        --Version: 1.2
263
        --Release Date: September 16, 2009. ISE DS 11.4
264
  component pcie is
265
  generic (
266
    TL_TX_RAM_RADDR_LATENCY           : integer    := 0;
267
    TL_TX_RAM_RDATA_LATENCY           : integer    := 2;
268
    TL_RX_RAM_RADDR_LATENCY           : integer    := 0;
269
    TL_RX_RAM_RDATA_LATENCY           : integer    := 2;
270
    TL_RX_RAM_WRITE_LATENCY           : integer    := 0;
271
    VC0_TX_LASTPACKET                 : integer    := 14;
272
    VC0_RX_RAM_LIMIT                  : bit_vector := x"7FF";
273
    VC0_TOTAL_CREDITS_PH              : integer    := 32;
274
    VC0_TOTAL_CREDITS_PD              : integer    := 211;
275
    VC0_TOTAL_CREDITS_NPH             : integer    := 8;
276
    VC0_TOTAL_CREDITS_CH              : integer    := 40;
277
    VC0_TOTAL_CREDITS_CD              : integer    := 211;
278
    VC0_CPL_INFINITE                  : boolean    := TRUE;
279
    BAR0                              : bit_vector := x"F0000000";
280
    BAR1                              : bit_vector := x"00000000";
281
    BAR2                              : bit_vector := x"00000000";
282
    BAR3                              : bit_vector := x"00000000";
283
    BAR4                              : bit_vector := x"00000000";
284
    BAR5                              : bit_vector := x"00000000";
285
    EXPANSION_ROM                     : bit_vector := "0000000000000000000000";
286
    DISABLE_BAR_FILTERING             : boolean    := FALSE;
287
    DISABLE_ID_CHECK                  : boolean    := FALSE;
288
    TL_TFC_DISABLE                    : boolean    := FALSE;
289
    TL_TX_CHECKS_DISABLE              : boolean    := FALSE;
290
    USR_CFG                           : boolean    := FALSE;
291
    USR_EXT_CFG                       : boolean    := FALSE;
292
    DEV_CAP_MAX_PAYLOAD_SUPPORTED     : integer    := 2;
293
    CLASS_CODE                        : bit_vector := x"068000";
294
    CARDBUS_CIS_POINTER               : bit_vector := x"00000000";
295
    PCIE_CAP_CAPABILITY_VERSION       : bit_vector := x"1";
296
    PCIE_CAP_DEVICE_PORT_TYPE         : bit_vector := x"1";
297
    PCIE_CAP_SLOT_IMPLEMENTED         : boolean    := FALSE;
298
    PCIE_CAP_INT_MSG_NUM              : bit_vector := "00000";
299
    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer    := 0;
300
    DEV_CAP_EXT_TAG_SUPPORTED         : boolean    := FALSE;
301
    DEV_CAP_ENDPOINT_L0S_LATENCY      : integer    := 7;
302
    DEV_CAP_ENDPOINT_L1_LATENCY       : integer    := 7;
303
    SLOT_CAP_ATT_BUTTON_PRESENT       : boolean    := FALSE;
304
    SLOT_CAP_ATT_INDICATOR_PRESENT    : boolean    := FALSE;
305
    SLOT_CAP_POWER_INDICATOR_PRESENT  : boolean    := FALSE;
306
    DEV_CAP_ROLE_BASED_ERROR          : boolean    := TRUE;
307
    LINK_CAP_ASPM_SUPPORT             : integer    := 1;
308
    --LINK_CAP_L0S_EXIT_LATENCY         : integer    := 7;
309
    --LINK_CAP_L1_EXIT_LATENCY          : integer    := 7;
310
    LL_ACK_TIMEOUT                    : bit_vector := x"0000";
311
    LL_ACK_TIMEOUT_EN                 : boolean    := FALSE;
312
    --LL_REPLAY_TIMEOUT                 : bit_vector := x"0204";
313
         LL_REPLAY_TIMEOUT                 : bit_vector := x"0000";
314
    LL_REPLAY_TIMEOUT_EN              : boolean    := FALSE;
315
    MSI_CAP_MULTIMSGCAP               : integer    := 0;
316
    MSI_CAP_MULTIMSG_EXTENSION        : integer    := 0;
317
    LINK_STATUS_SLOT_CLOCK_CONFIG     : boolean    := FALSE;
318
    PLM_AUTO_CONFIG                   : boolean    := FALSE;
319
    FAST_TRAIN                        : boolean    := FALSE;
320
    ENABLE_RX_TD_ECRC_TRIM            : boolean    := FALSE;
321
    DISABLE_SCRAMBLING                : boolean    := FALSE;
322
    PM_CAP_VERSION                    : integer    := 3;
323
    PM_CAP_PME_CLOCK                  : boolean    := FALSE;
324
    PM_CAP_DSI                        : boolean    := FALSE;
325
    PM_CAP_AUXCURRENT                 : integer    := 0;
326
    PM_CAP_D1SUPPORT                  : boolean    := TRUE;
327
    PM_CAP_D2SUPPORT                  : boolean    := TRUE;
328
    PM_CAP_PMESUPPORT                 : bit_vector := x"0F";
329
    PM_DATA0                          : bit_vector := x"04";
330
    PM_DATA_SCALE0                    : bit_vector := x"0";
331
    PM_DATA1                          : bit_vector := x"00";
332
    PM_DATA_SCALE1                    : bit_vector := x"0";
333
    PM_DATA2                          : bit_vector := x"00";
334
    PM_DATA_SCALE2                    : bit_vector := x"0";
335
    PM_DATA3                          : bit_vector := x"00";
336
    PM_DATA_SCALE3                    : bit_vector := x"0";
337
    PM_DATA4                          : bit_vector := x"04";
338
    PM_DATA_SCALE4                    : bit_vector := x"0";
339
    PM_DATA5                          : bit_vector := x"00";
340
    PM_DATA_SCALE5                    : bit_vector := x"0";
341
    PM_DATA6                          : bit_vector := x"00";
342
    PM_DATA_SCALE6                    : bit_vector := x"0";
343
    PM_DATA7                          : bit_vector := x"00";
344
    PM_DATA_SCALE7                    : bit_vector := x"0";
345
    PCIE_GENERIC                      : bit_vector := "000011101111";
346
    GTP_SEL                           : integer    := 0;
347
    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"10EE";
348
    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"BADD";
349
    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"00";
350
    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"10EE";
351
    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"1234";
352
    REF_CLK_FREQ                      : integer    := 0
353
  );
354
  port (
355
    -- PCI Express Fabric Interface
356
    pci_exp_txp             : out std_logic;
357
    pci_exp_txn             : out std_logic;
358
    pci_exp_rxp             : in  std_logic;
359
    pci_exp_rxn             : in  std_logic;
360
 
361
    -- Transaction (TRN) Interface
362
    trn_lnk_up_n            : out std_logic;
363
 
364
    -- Tx
365
    trn_td                  : in  std_logic_vector(31 downto 0);
366
    trn_tsof_n              : in  std_logic;
367
    trn_teof_n              : in  std_logic;
368
    trn_tsrc_rdy_n          : in  std_logic;
369
    trn_tdst_rdy_n          : out std_logic;
370
    trn_terr_drop_n         : out std_logic;
371
    trn_tsrc_dsc_n          : in  std_logic;
372
    trn_terrfwd_n           : in  std_logic;
373
    trn_tbuf_av             : out std_logic_vector(5 downto 0);
374
    trn_tstr_n              : in  std_logic;
375
    trn_tcfg_req_n          : out std_logic;
376
    trn_tcfg_gnt_n          : in  std_logic;
377
 
378
    -- Rx
379
    trn_rd                  : out std_logic_vector(31 downto 0);
380
    trn_rsof_n              : out std_logic;
381
    trn_reof_n              : out std_logic;
382
    trn_rsrc_rdy_n          : out std_logic;
383
    trn_rsrc_dsc_n          : out std_logic;
384
    trn_rdst_rdy_n          : in  std_logic;
385
    trn_rerrfwd_n           : out std_logic;
386
    trn_rnp_ok_n            : in  std_logic;
387
    trn_rbar_hit_n          : out std_logic_vector(6 downto 0);
388
    trn_fc_sel              : in  std_logic_vector(2 downto 0);
389
    trn_fc_nph              : out std_logic_vector(7 downto 0);
390
    trn_fc_npd              : out std_logic_vector(11 downto 0);
391
    trn_fc_ph               : out std_logic_vector(7 downto 0);
392
    trn_fc_pd               : out std_logic_vector(11 downto 0);
393
    trn_fc_cplh             : out std_logic_vector(7 downto 0);
394
    trn_fc_cpld             : out std_logic_vector(11 downto 0);
395
 
396
    -- Host (CFG) Interface
397
    cfg_do                  : out std_logic_vector(31 downto 0);
398
    cfg_rd_wr_done_n        : out std_logic;
399
    cfg_dwaddr              : in  std_logic_vector(9 downto 0);
400
    cfg_rd_en_n             : in  std_logic;
401
    cfg_err_ur_n            : in  std_logic;
402
    cfg_err_cor_n           : in  std_logic;
403
    cfg_err_ecrc_n          : in  std_logic;
404
    cfg_err_cpl_timeout_n   : in  std_logic;
405
    cfg_err_cpl_abort_n     : in  std_logic;
406
    cfg_err_posted_n        : in  std_logic;
407
    cfg_err_locked_n        : in  std_logic;
408
    cfg_err_tlp_cpl_header  : in  std_logic_vector(47 downto 0);
409
    cfg_err_cpl_rdy_n       : out std_logic;
410
    cfg_interrupt_n         : in  std_logic;
411
    cfg_interrupt_rdy_n     : out std_logic;
412
    cfg_interrupt_assert_n  : in  std_logic;
413
    cfg_interrupt_do        : out std_logic_vector(7 downto 0);
414
    cfg_interrupt_di        : in  std_logic_vector(7 downto 0);
415
    cfg_interrupt_mmenable  : out std_logic_vector(2 downto 0);
416
    cfg_interrupt_msienable : out std_logic;
417
    cfg_turnoff_ok_n        : in  std_logic;
418
    cfg_to_turnoff_n        : out std_logic;
419
    cfg_pm_wake_n           : in  std_logic;
420
    cfg_pcie_link_state_n   : out std_logic_vector(2 downto 0);
421
    cfg_trn_pending_n       : in  std_logic;
422
    cfg_dsn                 : in  std_logic_vector(63 downto 0);
423
    cfg_bus_number          : out std_logic_vector(7 downto 0);
424
    cfg_device_number       : out std_logic_vector(4 downto 0);
425
    cfg_function_number     : out std_logic_vector(2 downto 0);
426
    cfg_status              : out std_logic_vector(15 downto 0);
427
    cfg_command             : out std_logic_vector(15 downto 0);
428
    cfg_dstatus             : out std_logic_vector(15 downto 0);
429
    cfg_dcommand            : out std_logic_vector(15 downto 0);
430
    cfg_lstatus             : out std_logic_vector(15 downto 0);
431
    cfg_lcommand            : out std_logic_vector(15 downto 0);
432
 
433
    -- System Interface
434
    sys_clk                 : in  std_logic;
435
    sys_reset_n             : in  std_logic;
436
    trn_clk                 : out std_logic;
437
    trn_reset_n             : out std_logic;
438
    received_hot_reset      : out std_logic
439
    );
440
  end component pcie;
441
 
442
        COMPONENT blk_mem_gen_v4_1
443
        PORT(
444
                clka : IN std_logic;
445
                wea : IN std_logic_vector(0 to 0);
446
                addra : IN std_logic_vector(8 downto 0);
447
                dina : IN std_logic_vector(31 downto 0);
448
                clkb : IN std_logic;
449
                addrb : IN std_logic_vector(8 downto 0);
450
                doutb : OUT std_logic_vector(31 downto 0)
451
                );
452
        END COMPONENT;
453
 
454
 
455
 
456
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
457
--attribute keep_hierarchy : string; 
458
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes"; 
459
attribute keep : string;
460
attribute keep of cfg_dstatus : signal is "true";
461
attribute keep of tlp_state : signal is "true";
462
 
463
 
464
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
465
begin
466
 
467
 
468
cfg_turnoff_ok_n <= '1';
469
 
470
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
471
 
472
 
473
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
474
 
475
  inst_pcie : pcie
476
  port map (
477
    pci_exp_txp             => pci_exp_txp,
478
    pci_exp_txn             => pci_exp_txn,
479
    pci_exp_rxp             => pci_exp_rxp,
480
    pci_exp_rxn             => pci_exp_rxn,
481
    trn_lnk_up_n            => trn_lnk_up_n,
482
    trn_td                  => trn_td,                   -- Bus [31 : 0]
483
    trn_tsof_n              => trn_tsof_n,
484
    trn_teof_n              => trn_teof_n,
485
    trn_tsrc_rdy_n          => trn_tsrc_rdy_n,
486
    trn_tdst_rdy_n          => trn_tdst_rdy_n,
487
    trn_terr_drop_n         => trn_terr_drop_n,
488
    trn_tsrc_dsc_n          => trn_tsrc_dsc_n,
489
    trn_terrfwd_n           => trn_terrfwd_n,
490
    trn_tbuf_av             => trn_tbuf_av,              -- Bus [31 : 0]
491
    trn_tstr_n              => trn_tstr_n,
492
    trn_tcfg_req_n          => trn_tcfg_req_n,
493
    trn_tcfg_gnt_n          => trn_tcfg_gnt_n,
494
    trn_rd                  => trn_rd,                   -- Bus [31 : 0]
495
    trn_rsof_n              => trn_rsof_n,
496
    trn_reof_n              => trn_reof_n,
497
    trn_rsrc_rdy_n          => trn_rsrc_rdy_n,
498
    trn_rsrc_dsc_n          => trn_rsrc_dsc_n,
499
    trn_rdst_rdy_n          => trn_rdst_rdy_n,
500
    trn_rerrfwd_n           => trn_rerrfwd_n,
501
    trn_rnp_ok_n            => trn_rnp_ok_n,
502
    trn_rbar_hit_n          => trn_rbar_hit_n,           -- Bus [31 : 0]
503
    trn_fc_sel              => trn_fc_sel,               -- Bus [31 : 0]
504
    trn_fc_nph              => trn_fc_nph,               -- Bus [31 : 0]
505
    trn_fc_npd              => trn_fc_npd,               -- Bus [31 : 0]
506
    trn_fc_ph               => trn_fc_ph,                -- Bus [31 : 0]
507
    trn_fc_pd               => trn_fc_pd,                -- Bus [31 : 0]
508
    trn_fc_cplh             => trn_fc_cplh,              -- Bus [31 : 0]
509
    trn_fc_cpld             => trn_fc_cpld,              -- Bus [31 : 0]
510
    cfg_do                  => cfg_do,                   -- Bus [31 : 0]
511
    cfg_rd_wr_done_n        => cfg_rd_wr_done_n,
512
    cfg_dwaddr              => cfg_dwaddr,               -- Bus [31 : 0]
513
    cfg_rd_en_n             => cfg_rd_en_n,
514
    cfg_err_ur_n            => cfg_err_ur_n,
515
    cfg_err_cor_n           => cfg_err_cor_n,
516
    cfg_err_ecrc_n          => cfg_err_ecrc_n,
517
    cfg_err_cpl_timeout_n   => cfg_err_cpl_timeout_n,
518
    cfg_err_cpl_abort_n     => cfg_err_cpl_abort_n,
519
    cfg_err_posted_n        => cfg_err_posted_n,
520
    cfg_err_locked_n        => cfg_err_locked_n,
521
    cfg_err_tlp_cpl_header  => cfg_err_tlp_cpl_header,   -- Bus [31 : 0]
522
    cfg_err_cpl_rdy_n       => cfg_err_cpl_rdy_n,
523
    cfg_interrupt_n         => cfg_interrupt_n,
524
    cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n,
525
    cfg_interrupt_assert_n  => cfg_interrupt_assert_n,
526
    cfg_interrupt_do        => cfg_interrupt_do,         -- Bus [31 : 0]
527
    cfg_interrupt_di        => cfg_interrupt_di,         -- Bus [31 : 0]
528
    cfg_interrupt_mmenable  => cfg_interrupt_mmenable,   -- Bus [31 : 0]
529
    cfg_interrupt_msienable => cfg_interrupt_msienable,
530
    cfg_turnoff_ok_n        => cfg_turnoff_ok_n,
531
    cfg_to_turnoff_n        => cfg_to_turnoff_n,
532
    cfg_pm_wake_n           => cfg_pm_wake_n,
533
    cfg_pcie_link_state_n   => cfg_pcie_link_state_n,    -- Bus [31 : 0]
534
    cfg_trn_pending_n       => cfg_trn_pending_n,
535
    cfg_dsn                 => cfg_dsn,                  -- Bus [31 : 0]
536
    cfg_bus_number          => cfg_bus_number,           -- Bus [31 : 0]
537
    cfg_device_number       => cfg_device_number,        -- Bus [31 : 0]
538
    cfg_function_number     => cfg_function_number,      -- Bus [31 : 0]
539
    cfg_status              => cfg_status,               -- Bus [31 : 0]
540
    cfg_command             => cfg_command,              -- Bus [31 : 0]
541
    cfg_dstatus             => cfg_dstatus,              -- Bus [31 : 0]
542
    cfg_dcommand            => cfg_dcommand,             -- Bus [31 : 0]
543
    cfg_lstatus             => cfg_lstatus,              -- Bus [31 : 0]
544
    cfg_lcommand            => cfg_lcommand,             -- Bus [31 : 0]
545
    sys_clk                 => sys_clk,
546
    sys_reset_n             => sys_reset_n,
547
    trn_clk                 => trn_clk,
548
    trn_reset_n             => trn_reset_n,
549
    received_hot_reset      => received_hot_reset
550
  );
551
 
552
        --block ram for RX TLP:
553
        Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
554
                clka => trn_clk,
555
                wea => bram_rxtlp_we,
556
                addra => bram_rxtlp_writeaddress(8 downto 0),
557
                dina => bram_rxtlp_writedata,
558
                clkb => trn_clk,
559
                addrb => bram_rxtlp_readaddress(8 downto 0),
560
                doutb => bram_rxtlp_readdata
561
        );
562
 
563
        --block ram for TX TLP:
564
        Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
565
                clka => trn_clk,
566
                wea => bram_txtlp_we,
567
                addra => bram_txtlp_writeaddress(8 downto 0),
568
                dina => bram_txtlp_writedata,
569
                clkb => trn_clk,
570
                addrb => bram_txtlp_readaddress(8 downto 0),
571
                doutb => bram_txtlp_readdata
572
        );
573
 
574
 
575
 
576
 
577
 
578
        -- MAIN LOGIC: ---------------------------------------------------------------------------------------------
579
 
580
 
581
 
582
        --System Signals:--------------------------------
583
 
584
  --Clock Input Buffer for differential system clock
585
   IBUFDS_inst : IBUFDS
586
   generic map (
587
      DIFF_TERM => TRUE, -- Differential Termination 
588
      IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
589
      IOSTANDARD => "DEFAULT")
590
   port map (
591
      O => sys_clk,  -- Buffer output
592
      I => sys_clk_p,  -- Diff_p buffer input (connect directly to top-level port)
593
      IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
594
   );
595
 
596
  --wishbone clock output:
597
  pcie_bar0_wb_clk_o <= trn_clk;
598
  --pcie_bar1_wb_clk_o <= trn_clk; 
599
 
600
 
601
  --use one of these for resetting logic in this file:
602
    pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
603
    --pciewb_localreset_n <= trn_reset_n;
604
         --pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
605
  --reset to the core:
606
  --sys_reset_n comes from toplevel directly to the core. same name
607
  --reset output to other cores:
608
  pcie_resetout <= not pciewb_localreset_n;
609
 
610
  --trn_lnk_up_n    --not used.
611
 
612
 
613
  --pcie ep ip config port: ----------------------------------------------------------
614
 
615
   --trn_fc_sel             <= "000";
616
 
617
  trn_rnp_ok_n           <= '0';
618
  --trn_terrfwd_n          <= '1';
619
 
620
  --trn_tcfg_gnt_n         <= '0';
621
 
622
  cfg_err_cor_n          <= '1';
623
  cfg_err_ur_n           <= '1';
624
  cfg_err_ecrc_n         <= '1';
625
  cfg_err_cpl_timeout_n  <= '1';
626
  cfg_err_cpl_abort_n    <= '1';
627
  cfg_err_posted_n       <= '0';
628
  cfg_err_locked_n       <= '1';
629
  cfg_pm_wake_n          <= '1';
630
  cfg_trn_pending_n      <= '1';
631
 
632
  --trn_tstr_n             <= '0'; 
633
  --cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
634
  --cfg_interrupt_n        <= '1';
635
  --cfg_interrupt_di       <= x"00"; --intA used
636
 
637
  cfg_err_tlp_cpl_header <= (OTHERS => '0');
638
  cfg_dwaddr             <= (OTHERS => '0');
639
  cfg_rd_en_n            <= '1';
640
  --serial number:
641
  cfg_dsn                <= (OTHERS => '0');
642
 
643
 -- AT THE BOTTOM OF THIS FILE:
644
 --      --some fix values:
645
 --      trn_tsrc_dsc_n <= '1'; --no errors on trn bus
646
 --      trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
647
 --      trn_tcfg_gnt_n <= '0'; --no tlp priorities
648
 --      trn_terrfwd_n <= '1'; --no errors on trn
649
 --      --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
650
 
651
 
652
 
653
  --use this in read completion packets:
654
  cfg_completer_id       <= cfg_bus_number & cfg_device_number & cfg_function_number;
655
 
656
 
657
 
658
 
659
 
660
 
661
        -- WISBONE BACK-end INTERFACE ----------------------------------------------------
662
 
663
    --main state machine: set states, capture inputs, set addr/data outputs
664
         --minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
665
    process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
666
                                pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
667
    begin
668
    if (pciewb_localreset_n='0') then
669
       wb0_state <= "00000000";
670
       wb_transaction_complete <= '0';
671
                 pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
672
                 pcie_bar0_wb_sel_o <= "0000";
673
                 pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
674
                 wb_transaction_complete <='0';
675
    else
676
      if (trn_clk'event and trn_clk = '1') then
677
                case ( wb0_state ) is
678
 
679
                --********** IDLE STATE  **********
680
                when "00000000" =>   --state 0        
681
                    wb_transaction_complete <='0';
682
                                                  pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
683
                                                  pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
684
                                                  if (start_read_wb0 ='1') then --go to read
685
                                                    wb0_state <= "00000001";
686
                                                  elsif (start_write_wb0 ='1') then --go to write
687
                                                    wb0_state <= "00000010";
688
                                                         --no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
689
                                                    pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
690
                                                    pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
691
                                                    pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
692
                                                    pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism                                                           
693
                                                  end if;
694
 
695
                --********** READ STATE ********** 
696
                                         --set the outputs, 
697
                                         --if ACK asserted, sample the data input
698
                                         --The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
699
                when "00000001" =>   --state 1
700
                    if (pcie_bar0_wb_ack_i='1') then
701
                                                    --no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
702
                                                    pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
703
                                                    pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
704
                                                    pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
705
                                                    pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism                                                      
706
                                                         wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
707
                                                         wb0_state <= "00000000"; --go to state 0
708
                                                  else
709
                                                         wb_transaction_complete <='0';
710
                                                  end if;
711
 
712
                --********** WRITE STATE **********     
713
                                         --if ACK asserted, go back to idle
714
                                         --The hold requirements are oversatisfyed by waiting for ACK to remove write data                                       
715
                when "00000010" =>   --state 2
716
                    if (pcie_bar0_wb_ack_i='1') then
717
                                                         wb0_state <= "00000000"; --go to state 0
718
                                                         wb_transaction_complete <='1';
719
                                                  else
720
                                                     wb_transaction_complete <='0';
721
                                                  end if;
722
 
723
                when others => --error
724
                      wb0_state <= "00000000"; --go to state 0
725
                end case;
726
       end if;
727
    end if;
728
    end process;
729
    --sync control on wb-control signals:
730
    process (pciewb_localreset_n, wb0_state)
731
    begin
732
    if (pciewb_localreset_n='0') then
733
                pcie_bar0_wb_cyc_o  <= '0';
734
                pcie_bar0_wb_stb_o  <= '0';
735
                pcie_bar0_wb_wr_o  <= '0';
736
    else
737
      if (wb0_state = "00000000") then --idle
738
                        pcie_bar0_wb_cyc_o  <= '0';
739
                        pcie_bar0_wb_stb_o  <= '0';
740
                        pcie_bar0_wb_wr_o  <= '0';
741
      elsif (wb0_state = "00000001") then --read 
742
                        pcie_bar0_wb_cyc_o  <= '1';
743
                        pcie_bar0_wb_stb_o  <= '1';
744
                        pcie_bar0_wb_wr_o  <= '0';
745
      elsif (wb0_state = "00000010") then --write 
746
                        pcie_bar0_wb_cyc_o  <= '1';
747
                        pcie_bar0_wb_stb_o  <= '1';
748
                        pcie_bar0_wb_wr_o  <= '1';
749
                else
750
                        pcie_bar0_wb_cyc_o  <= '0';
751
                        pcie_bar0_wb_stb_o  <= '0';
752
                        pcie_bar0_wb_wr_o  <= '0';
753
                end if;
754
    end if;
755
    end process;
756
 
757
 
758
 
759
 
760
 
761
 
762
 
763
 
764
        -- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
765
        --trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
766
        --so it is not a clock domain crossing.
767
 
768
 
769
        -- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
770
        --Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
771
    process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
772
                                pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
773
    begin
774
    if (pciewb_localreset_n='0') then
775
      epif_tx_state <= "00000000";
776
      trn_tsrc_rdy_n_1 <='1';
777
                trn_tsof_n1 <= '1';
778
                trn_teof_n <= '1';
779
                trn_td <= (OTHERS => '0');
780
                pcie_tlp_tx_complete <= '0';
781
                txtrn_counter <= "00000001";
782
                bram_txtlp_readaddress <= (OTHERS => '0');
783
    else
784
      if (trn_clk'event and trn_clk = '1') then
785
                case ( epif_tx_state ) is
786
 
787
                --********** idle STATE  **********
788
                when "00000000" =>   --state 0        
789
                    --if there is a new TLP assembled and the EP is ready, 
790
                                                  --start the tx-trn bus transaction.
791
                                                  if (pcie_there_is_a_new_tlp_to_transmit='1') then
792
                                                    epif_tx_state <= "00000001"; --next state
793
                                                  end if;
794
                    trn_tsrc_rdy_n_1 <='1';
795
                                                  trn_tsof_n1 <= '1';
796
                                                  trn_teof_n <= '1';
797
                                                  trn_td <= (OTHERS => '0');
798
                                                  pcie_tlp_tx_complete <= '0';
799
                                                  txtrn_counter <= "00000001";
800
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
801
 
802
                --********** ready-wait STATE  **********
803
                when "00000001" =>   --state 1        
804
                    --if there is a new TLP assembled and the EP is ready, 
805
                                                  --start the tx-trn bus transaction.
806
                                                  if (trn_tdst_rdy_n='0') then
807
                                                    epif_tx_state <= "00000010"; --next state
808
                                                  end if;
809
                    trn_tsrc_rdy_n_1 <='1';
810
                                                  trn_tsof_n1 <= '1';
811
                                                  trn_teof_n <= '1';
812
                                                  trn_td <= (OTHERS => '0');
813
                                                  pcie_tlp_tx_complete <= '0';
814
                                                  txtrn_counter <= "00000001";
815
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
816
 
817
                --********** transfer STATE **********                                   
818
                when "00000010" =>   --state 2
819
                    trn_tsrc_rdy_n_1 <='0';
820
                                                  trn_td <= bram_txtlp_readdata;
821
                                                  if (trn_tdst_rdy_n='0') then
822
                                                    txtrn_counter <= txtrn_counter +1;
823
                                                         bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
824
                                                  end if;
825
                                                  if (txtrn_counter = "00000010") then
826
                                                    trn_tsof_n1 <= '0'; --start
827
                                                  else
828
                                                    trn_tsof_n1 <= '1';
829
                                                  end if;
830
                                                  --test number of dwords:
831
                                                  if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
832
                                                  --this is the last dword, next clk is next state
833
                                                         epif_tx_state <= "00000000"; --back to idle, since finished
834
                                                    trn_teof_n <= '0'; --end
835
                                                    pcie_tlp_tx_complete <= '1'; --assert for 1 clk
836
                                                  else
837
                                                    trn_teof_n <= '1'; --not end yet
838
                                                    pcie_tlp_tx_complete <= '0'; --not complete yet
839
                                                  end if;
840
 
841
                when others => --error
842
                    epif_tx_state <= "00000000"; --back to idle
843
                    trn_tsrc_rdy_n_1 <='1';
844
                                                  trn_tsof_n1 <= '1';
845
                                                  trn_teof_n <= '1';
846
                                                  trn_td <= (OTHERS => '0');
847
                                                  pcie_tlp_tx_complete <= '0';
848
                                                  txtrn_counter <= "00000001";
849
 
850
                end case;
851
       end if;
852
    end if;
853
    end process;
854
 
855
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
856
        trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
857
        trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
858
 
859
 
860
 
861
         --some fix values:
862
         trn_tsrc_dsc_n <= '1'; --no errors on trn bus
863
         trn_tstr_n <= '0'; --pipelining 
864
         trn_tcfg_gnt_n <= '0'; --no tlp priorities 
865
         trn_terrfwd_n <= '1'; --no errors on trn
866
         --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
867
 
868
 
869
 
870
 
871
 
872
        -- RX: INTERFACE TO THE PCIE-EP: GET thereceived TLP PACKETS:- ----
873
    process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter,
874
                                bram_rxtlp_writeaddress, rxstm_readytoroll, trn_rsof_n, tlpstm_isin_idle, trn_rdst_rdy_n)
875
    begin
876
    if (pciewb_localreset_n='0') then
877
                 pcie_just_received_a_new_tlp <= '0';
878
                 epif_rx_state  <= "00000000";
879
                 trn_rdst_rdy_n <= '1';
880
                 trn_rx_counter <= (OTHERS => '0');
881
                 bram_rxtlp_we <= "0";
882
                 bram_rxtlp_writeaddress <= (OTHERS => '0');
883
                 bram_rxtlp_writedata  <= (OTHERS => '0');
884
                 rxstm_readytoroll <= '0';
885
    else
886
      if (trn_clk'event and trn_clk = '1') then
887
 
888
                case ( epif_rx_state ) is
889
 
890
                --********** idle STATE  **********
891
                when "00000000" =>   --state 0
892
                                                  pcie_just_received_a_new_tlp <= '0';
893
                                                  bram_rxtlp_writedata  <= trn_rd;
894
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1' and trn_rdst_rdy_n='0') then
895
                                                    trn_rx_counter <= trn_rx_counter +1;
896
                                                         bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
897
                                                         epif_rx_state <= "00000001";
898
                                                  else
899
                                                    trn_rx_counter <= (OTHERS => '0');
900
                                                         bram_rxtlp_writeaddress  <= (OTHERS => '0');
901
                                                  end if;
902
                                                  --destination ready:
903
                                                  if (tlpstm_isin_idle = '1')then
904
                                                          trn_rdst_rdy_n <= '0';
905
                                                  else
906
                                                          trn_rdst_rdy_n <= '1';
907
                                                  end if;
908
                                                  --write into buffer:
909
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1') then
910
                                                         bram_rxtlp_we <= "1";
911
                                                         rxstm_readytoroll <= '1';
912
                                                  else
913
                                                         bram_rxtlp_we <= "0";
914
                                                         rxstm_readytoroll <= '0';
915
                                                  end if;
916
 
917
                --********** read STATE ********** 
918
                when "00000001" =>   --state 1
919
                                                  rxstm_readytoroll <= '0';
920
                                                  if (trn_reof_n ='0') then --last dw
921
                                                    epif_rx_state <= "00000010"; --for the next clk cycle
922
                                                         trn_rdst_rdy_n <= '1'; --ok, dont send more yet
923
                                                  end if;
924
                                                  if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
925
                                                          trn_rx_counter <= trn_rx_counter +1;
926
                                                          bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
927
                                                          bram_rxtlp_writedata  <= trn_rd;
928
                                                  end if;
929
                                                  --in an early stage of this transfer, the scheduler can already
930
                                                  --start working on the data, this way its pipelined, so the latency is lower.
931
                                                  if (trn_rx_counter = "00000010") then
932
                                                   pcie_just_received_a_new_tlp <= '1';--assert for one clk only
933
                                                  else
934
                                                   pcie_just_received_a_new_tlp <= '0';
935
                                                  end if;
936
 
937
                --********** finished filling up RX TLP STATE **********                                 
938
                when "00000010" =>   --state 2
939
                                                  epif_rx_state <= "00000000";
940
                                                  trn_rx_counter <= (OTHERS => '0');
941
 
942
                when others => --error
943
                      epif_rx_state <= "00000000"; --go to state 0
944
                end case;
945
       end if;
946
    end if;
947
    end process;
948
 
949
         --fixed connections:
950
         --trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
951
         --not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
952
 
953
 
954
 
955
 
956
 
957
        -- flow control: INTERFACE TO THE PCIE-EP: - ----
958
        --not used. pcie-ep provides information about credit status.
959
        --unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
960
        trn_fc_sel <= "000";
961
 
962
 
963
 
964
 
965
 
966
        -- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
967
        -- --- ALSO TLP PACKET PROCESSING.
968
        --Theory of operation:
969
        --RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle), 
970
        --then store it (pcie_received_tlp), decode it (to figure out if its read request, 
971
        --posted write or non-supported request), then assert a flag (start_write_wb0 or 
972
        --start_read_wb0)to initiate a wishbone cycle.
973
        --TX: At the completion of a wishbone read, the wishbone statemachine asserts the 
974
        --wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp) 
975
        --and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be 
976
        --a read completion packet on the PCIe link.
977
        --
978
        --This core can handle 1...8 DWORD accesses in one request (max 256bit payload ), 
979
        --and can handle only one request at a time. If a new request is arriving while
980
        --processing the previous one (e.g. getting the data from a wishbone read), then 
981
        --the state machine will not process it immediately, or it will hang. So the user 
982
        --software has to wait for the previous read completion before issueing a new request.
983
        --The multiple DWORDs are handled separately by the WB statemachine.
984
   --Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
985
        --
986
        --TLP decoding: 
987
        --Header+Payload_data+TLP_DIGEST(ECRC). 
988
        --received Header:
989
        --First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data, 
990
        --10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory 
991
        --read requests, 00000 or 00001 are memory write request if type=1x. read request 
992
        --completion is 01010 and type=10. bit.9:0 is payload size [DW]. 
993
        --Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is 
994
        --byte enable for last dword data. intermediate dwords have all bytes enabled.
995
        --Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
996
        --uses 3rd-dword for addre63:32, 4th dword for addr31:0.
997
        --
998
        --The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
999
        --
1000
        --Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
1001
        --The core has to store the requester ID and feed it back in the completion packet.
1002
        --Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
1003
        --count is N.of bytes left. lower_address is the first enabled byte of data returned 
1004
        --with the Completion.
1005
        --
1006
        --  Completion packet header:
1007
        --DW1 >
1008
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1009
        --r FMT type----- r TC--- reserv- T E att r r lenght-------------
1010
        --  x 0                           D P rib
1011
        --DW2 >
1012
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1013
        --COMPLETER_ID------------------- statu B byte_count-------------
1014
        --                                      CM
1015
        --DW3 >
1016
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1017
        --REQUESTER_ID------------------- tag------------ r lower_address
1018
 
1019
 
1020
         --TLP-protocol statemachine:
1021
    process (pciewb_localreset_n, trn_clk, tlp_state,
1022
                                pcie_just_received_a_new_tlp, tlp_datacount,
1023
                                bram_rxtlp_readdata,  bram_txtlp_writeaddress, bram_rxtlp_readaddress,
1024
                                tlp_state_copy, rxtlp_decodedaddress,
1025
                                rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
1026
                                bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
1027
                                tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
1028
                                rxtlp_requesterid)
1029
    begin
1030
    if (pciewb_localreset_n='0') then
1031
                start_read_wb0 <= '0';
1032
                start_write_wb0 <= '0';
1033
                pcie_bar0_wb_data_o_feed         <= (others => '0');
1034
                pcie_bar0_wb_addr_o_feed <= (others => '0');
1035
                pcie_bar0_wb_sel_o_feed  <= (others => '0');
1036
                pcie_there_is_a_new_tlp_to_transmit  <= '0';
1037
                rxtlp_decodedaddress<= (others => '0');
1038
                tlp_payloadsize_dwords <= (others => '0');
1039
                rxtlp_firstdw_be <= (others => '0');
1040
                rxtlp_lastdw_be <= (others => '0');
1041
                rxtlp_requesterid <= (others => '0');
1042
                tlp_state <= (others => '0');
1043
                tlp_state_copy  <= (others => '0');
1044
                bram_txtlp_we <= "0";
1045
                bram_txtlp_writeaddress    <= (others => '0');
1046
                bram_txtlp_writedata     <= (others => '0');
1047
                bram_rxtlp_readaddress   <= (others => '0');
1048
                rxtlp_header_dw1   <= "01111111000000000000000000000000";
1049
                rxtlp_header_dw2   <= (others => '0');
1050
                rxtlp_header_dw3   <= (others => '0');
1051
                rxtlp_header_dw4   <= (others => '0');
1052
                flag1 <= '0';
1053
                rxdw1_23_0 <= (others => '0');
1054
                pcie_rxtlp_tag <= (others => '0');
1055
                rcompl_bytecount_field  <= (others => '0');
1056
                tlpstm_isin_idle <= '1';
1057
    else
1058
      if (trn_clk'event and trn_clk = '1') then
1059
                case ( tlp_state ) is
1060
 
1061
                --********** IDLE STATE  **********
1062
                                         --also re-initialize signals...
1063
                when "00000000" =>   --state 0        
1064
                    if (pcie_just_received_a_new_tlp='1') then
1065
                                                    tlp_state <= "00000001"; --to tlp decoding state
1066
                                                         tlpstm_isin_idle <= '0';
1067
                                                  else
1068
                                                    tlpstm_isin_idle <= '1';
1069
                                                  end if;
1070
                                                  start_write_wb0 <= '0';
1071
                                                  start_read_wb0 <= '0';
1072
                                                  tlp_state_copy <= tlp_state;
1073
                                                        bram_txtlp_we <= "0";
1074
                                                        bram_txtlp_writeaddress   <= (others => '0');
1075
                                                        bram_txtlp_writedata     <= (others => '0');
1076
                                                        bram_rxtlp_readaddress    <= (others => '0');
1077
                                                        tlp_datacount <= "00000001";
1078
                                                        rxtlp_header_dw1   <= "01111111000000000000000000000000"; --this is to prevent false decode
1079
                                                        pcie_bar0_wb_data_o_feed         <= (others => '0');
1080
                                                        pcie_bar0_wb_addr_o_feed <= (others => '0');
1081
                                                        pcie_bar0_wb_sel_o_feed  <= (others => '0');
1082
                                                        rxtlp_header_dw2   <= (others => '0');
1083
                                                        rxtlp_header_dw3   <= (others => '0');
1084
                                                        rxtlp_header_dw4   <= (others => '0');
1085
                                                        rxdw1_23_0 <= (others => '0');
1086
                                                        pcie_rxtlp_tag <= (others => '0');
1087
                                                        pcie_there_is_a_new_tlp_to_transmit  <= '0';
1088
                                                        rxtlp_decodedaddress<= (others => '0');
1089
                                                        tlp_payloadsize_dwords <= (others => '0');
1090
                                                        rxtlp_firstdw_be <= (others => '0');
1091
                                                        rxtlp_lastdw_be <= (others => '0');
1092
                                                        rxtlp_requesterid <= (others => '0');
1093
                                                        rcompl_bytecount_field  <= (others => '0');
1094
 
1095
 
1096
                --********** TLP ARRIVED STATE **********
1097
                                         --read TLP out of EP, decode and decide,
1098
                                         --latch address/sel/wr_data
1099
                                         --All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
1100
                                         --Added an ectra clock delay, based on testing, since the data is one more CLK late.
1101
                when "00000001" =>   --state 1
1102
                    --latch the header:
1103
                                                  bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1104
                                                  if (bram_rxtlp_readaddress = "000000010") then
1105
                                                    rxtlp_header_dw1 <= bram_rxtlp_readdata;
1106
                                                  elsif (bram_rxtlp_readaddress = "000000011") then
1107
                                                    rxtlp_header_dw2 <= bram_rxtlp_readdata;
1108
                                                  elsif (bram_rxtlp_readaddress = "000000100") then
1109
                                                    rxtlp_header_dw3 <= bram_rxtlp_readdata;
1110
                                                  elsif (bram_rxtlp_readaddress = "000000101") then
1111
                                                    rxtlp_header_dw4 <= bram_rxtlp_readdata;
1112
                                                  end if;
1113
                                                  --decode some parameters: 
1114
                                                  tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
1115
                                                  rxtlp_firstdw_be <= rxtlp_header_dw2(3 downto 0);
1116
                                                  rxtlp_lastdw_be <= rxtlp_header_dw2(7 downto 4);
1117
                                                  rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
1118
                                                  flag1 <= rxtlp_header_dw1(31);
1119
                                                  rxdw1_23_0 <= rxtlp_header_dw1(23 downto 0); --various fields pcie_received_tlp (22 downto 0);
1120
                                                  pcie_rxtlp_tag <= rxtlp_header_dw2(15 downto 8) ; --pcie_received_tlp (47 downto 40);--tag
1121
                                                  --decide based on header:
1122
                                                  if (rxtlp_header_dw1(30 downto 24)="0000000") then --32bit read
1123
                                                         if (bram_rxtlp_readaddress = "000000100") then
1124
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1125
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1126
                                                                tlp_state <= "00000011";
1127
                                                         end if;
1128
                                                  elsif (rxtlp_header_dw1(30 downto 24)="0100000") then --64bit read
1129
                                                         if (bram_rxtlp_readaddress = "000000101") then
1130
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1131
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1132
                                                                tlp_state <= "00000011";
1133
                                                         end if;
1134
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1000000") then --32bit write
1135
                                                         if (bram_rxtlp_readaddress = "000000100") then
1136
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1137
                                                                tlp_state <= "00000010";
1138
                                                         end if;
1139
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1100000") then --64bit write
1140
                                                         if (bram_rxtlp_readaddress = "000000101") then
1141
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1142
                                                                tlp_state <= "00000010";
1143
                                                         end if;
1144
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1111111") then --just wait until this gets a real value
1145
                                                    rxtlp_decodedaddress <= bram_rxtlp_readdata;
1146
                                                  else --unsupported request
1147
                                                    if (bram_rxtlp_readaddress = "000000100") then
1148
                                                           tlp_state <= "00000101";
1149
                                                                bram_txtlp_writeaddress <= "111111111";
1150
                                                         end if;
1151
                                                  end if;
1152
 
1153
 
1154
                --********** WRITE STATE **********
1155
                                         --initiate WB write(s) (1...N DWORD accesses)
1156
                when "00000010" =>   --state 2
1157
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
1158
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1159
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1160
                                                pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
1161
                                                tlp_state_copy <= tlp_state;
1162
                                                if (tlp_state_copy = tlp_state) then
1163
                                                  start_write_wb0 <= '0';
1164
                                                else --generate just one pulse, at the first clk cycle in this state
1165
                                                  start_write_wb0 <= '1';
1166
                                                end if;
1167
                                                if (wb_transaction_complete='1') then --one DW transfer completed
1168
 
1169
                                                        if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
1170
                                                          tlp_state <= "00000000"; --to idle
1171
                                                        else
1172
                                                          tlp_state <= "00010100"; --restart wb transaction with new data
1173
                                                          bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1174
                                                          tlp_datacount <= tlp_datacount +1;
1175
                                                        end if;
1176
                                                end if;
1177
                --* Write restart state *
1178
                when "00010100" =>   --state 20
1179
                                                tlp_state <= "00000010";
1180
 
1181
 
1182
                --********** READ STATE **********
1183
                                         --initiate WB read, then go to completion state
1184
                when "00000011" =>   --state 3
1185
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
1186
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1187
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1188
                                                tlp_state_copy <= tlp_state;
1189
                                                if (tlp_state_copy = tlp_state) then
1190
                                                  start_read_wb0 <= '0';
1191
                                                else --generate just one pulse
1192
                                                  start_read_wb0 <= '1';
1193
                                                end if;
1194
                                                if (wb_transaction_complete='1') then
1195
                                                        bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
1196
                                                        bram_txtlp_we <= "1";
1197
                                                        if (tlp_payloadsize_dwords = tlp_datacount)then
1198
                                                          tlp_state <= "01111110"; --read completion
1199
                                                          --bram_txtlp_writeaddress remains the same to capture data in next clock cycle
1200
                                                        else
1201
                                                          tlp_state <= "00011110"; --one more wb read
1202
                                                          bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1203
                                                          tlp_datacount <= tlp_datacount +1;
1204
                                                        end if;
1205
                                                else
1206
                                                  bram_txtlp_we <= "0";
1207
                                                end if;
1208
                --* read restart STATE  *
1209
                when "00011110" =>   --state 30
1210
                                                tlp_state <= "00000011";
1211
                                                bram_txtlp_we <= "0";
1212
                --intermediate state before completion (to ensure data latch at address-4)
1213
                                         when "01111110" =>   --state 126
1214
                                                tlp_state <= "00000100";
1215
                                                bram_txtlp_writeaddress  <=  (OTHERS => '0');
1216
                                                --pre-write header-DW1:
1217
                                                bram_txtlp_writedata (31) <= flag1; --reserved
1218
                                                bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1219
                                                bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1220
                                                --Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
1221
                                                if (rxtlp_lastdw_be="0000") then  --max 1DW
1222
                                                  if (rxtlp_firstdw_be="1111") then --4bytes
1223
                                                    rcompl_bytecount_field <= "0000000100";
1224
                                                  elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
1225
                                                    rcompl_bytecount_field <= "0000000011";
1226
                                                  elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
1227
                                                    rcompl_bytecount_field <= "0000000010";
1228
                                                  else
1229
                                                    rcompl_bytecount_field <= "0000000001";
1230
                                                  end if;
1231
                                                else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
1232
                                                  rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
1233
                                                  rcompl_bytecount_field(1 downto 0) <= "00";
1234
                                                end if;
1235
 
1236
 
1237
                --********** READ COMPLETION STATE **********
1238
                                         --assemble the tx TLP and initiate the transmit
1239
                                         --buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
1240
                when "00000100" =>   --state 4
1241
                    tlp_state_copy <= tlp_state;
1242
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1243
                                                  if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
1244
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1245
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
1246
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1247
                                                          bram_txtlp_writedata (11 downto 10) <= "00";
1248
                                                          bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
1249
                                                          bram_txtlp_we <= "1";
1250
                                                  elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
1251
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1252
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1253
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1254
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1255
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1256
                                                  else --data dwords, disable writes from next clock cycle
1257
                                                    bram_txtlp_we <= "0";
1258
                                                  end if;
1259
                                                  --one pulse to start the ep-if statemachine, upon arriving to this state
1260
                                                        if (tlp_state_copy = tlp_state) then
1261
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1262
                                                        else
1263
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1264
                                                        end if;
1265
                                                        --back to idle when the ep-if tx is finished: (wait to avoid overwrite)
1266
                                                        if (pcie_tlp_tx_complete='1') then
1267
                                                                tlp_state <= "00000000";
1268
                                                        end if;
1269
 
1270
 
1271
                --********** UNSUPPORTED REQUEST STATE **********
1272
                                         --completion response with status=001
1273
                when "00000101" =>   --state 5
1274
                    tlp_state_copy <= tlp_state;
1275
                                                  tlp_payloadsize_dwords <= "00000000";
1276
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1277
                                                  --assembling the TLP packet:           )
1278
                                                  if (bram_txtlp_writeaddress="111111111") then --header 1.dw
1279
                                                    bram_txtlp_we <= "1";
1280
                                                          bram_txtlp_writedata (31) <= flag1; --reserved
1281
                                                          bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1282
                                                          bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1283
                                                  elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
1284
                                                    bram_txtlp_we <= "1";
1285
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1286
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
1287
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1288
                                                          bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
1289
                                                  elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
1290
                                                    bram_txtlp_we <= "1";
1291
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1292
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1293
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1294
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1295
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1296
                                                  else --data dwords 
1297
                                                    bram_txtlp_we <= "0";
1298
                                                  end if;
1299
                                                        --one pulse to start the ep-if statemachine, upon arriving to this state
1300
                                                        if (tlp_state_copy = tlp_state) then
1301
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1302
                                                        else
1303
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1304
                                                        end if;
1305
                                                        --back to idle when finished:
1306
                                                        if (pcie_tlp_tx_complete='1') then
1307
                                                                tlp_state <= "00000000";
1308
                                                        end if;
1309
 
1310
                when others => --error
1311
                      tlp_state <= "00000000"; --go to state 0
1312
                end case;
1313
 
1314
       end if;
1315
    end if;
1316
    end process; --end tlp statemachine
1317
 
1318
 
1319
 
1320
 
1321
        --byte enable encoding to wb_address bit1:0
1322
        --this does not swap the endian, since only the data is swapped in the pcie packets.
1323
         process ( pciewb_localreset_n, rxtlp_firstdw_be )
1324
    begin
1325
       if (pciewb_localreset_n = '0') then
1326
           bit10(1 downto 0) <="00";
1327
       else
1328
         if (rxtlp_firstdw_be ="0001") then
1329
                          bit10(1 downto 0) <= "00";
1330
         elsif (rxtlp_firstdw_be ="0010") then
1331
                          bit10(1 downto 0) <= "01";
1332
         elsif (rxtlp_firstdw_be ="0100") then
1333
                          bit10(1 downto 0) <= "10";
1334
         elsif (rxtlp_firstdw_be ="1000") then
1335
                          bit10(1 downto 0) <= "11";
1336
         elsif (rxtlp_firstdw_be ="0011") then
1337
                          bit10(1 downto 0) <= "00";
1338
         elsif (rxtlp_firstdw_be ="1100") then
1339
                          bit10(1 downto 0) <= "10";
1340
         elsif (rxtlp_firstdw_be ="1111") then
1341
                          bit10(1 downto 0) <= "00";
1342
                        else --this should never happen
1343
                          bit10(1 downto 0) <= "00";
1344
                        end if;
1345
       end if;
1346
    end process;
1347
 
1348
 
1349
 
1350
 
1351
 
1352
        -- INTERRUPTS: -------------------------------------------------------------------------
1353
        --to assert an interrupt, use the cfg_interrupt_assert_n pin.
1354
        --datasheet text:
1355
        --As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
1356
        --cfg_interrupt_assert_n to assert the interrupt. The user application should select a
1357
        --specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
1358
        --in Table 6-19.
1359
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
1360
        --On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
1361
        --Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
1362
        --interrupt message (Assert_INTA, Assert_INTB, and so forth).
1363
        -- After the user application has determined that the interrupt has been serviced, it
1364
        --asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
1365
        --interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
1366
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
1367
        --been accepted. On the following clock cycle, the user application deasserts
1368
        --cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
1369
        --Deassert_INTB, and so forth).
1370
        --cfg_interrupt_di[7:0] value Legacy Interrupt
1371
        --00h INTA
1372
        --01h INTB
1373
        --02h INTC
1374
        --03h INTD 
1375
 
1376
        cfg_interrupt_di    <= "00000000"; --intA used
1377
 
1378
        --prohibit IRQ assert when TLP state machine not idle.
1379
        -- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
1380
        -- added by StBa, AAC Microtec, 2012
1381
        irq_prohibit <= not tlpstm_isin_idle;
1382
 
1383
    process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
1384
                                cfg_interrupt_rdy_n)
1385
    begin
1386
    if (pciewb_localreset_n='0') then
1387
       pcieirq_state <= "00000000";
1388
       cfg_interrupt_n <= '1';
1389
                 cfg_interrupt_assert_n_1 <= '1';
1390
    else
1391
      if (trn_clk'event and trn_clk = '1') then
1392
                case ( pcieirq_state ) is
1393
 
1394
                --********** idle STATE  **********
1395
                when "00000000" =>   --state 0        
1396
                    if (pcie_irq = '1' and irq_prohibit = '0') then
1397
                                                    pcieirq_state <= "00000001";
1398
                                                         cfg_interrupt_n <= '0'; --active
1399
                                                  else
1400
                                                    cfg_interrupt_n <= '1'; --inactive
1401
                                                  end if;
1402
                                                  cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
1403
 
1404
                --********** assert STATE ********** 
1405
                when "00000001" =>   --state 1
1406
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1407
                                                         cfg_interrupt_n <= '1'; --deassert the request 
1408
                                                         pcieirq_state <= "00000010";
1409
                                                 else
1410
                                                         cfg_interrupt_n <= '0'; --request INTA assertion
1411
                                                 end if;
1412
 
1413
                --********** pcie_irq kept asserted STATE **********                                     
1414
                when "00000010" =>   --state 2
1415
                    if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted
1416
                                                    pcieirq_state <= "00000011";
1417
                                                  end if;
1418
                                                 cfg_interrupt_n <= '1'; --inactive     
1419
                                                 cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
1420
 
1421
                --********** DEassert STATE ********** 
1422
                when "00000011" =>   --state 3
1423
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1424
                                                         cfg_interrupt_n <= '1'; --deassert the request 
1425
                                                         pcieirq_state <= "00000000";
1426
                                                 else
1427
                                                         cfg_interrupt_n <= '0'; --request INTA DEassertion
1428
                                                 end if;
1429
 
1430
                                                 when others => --error
1431
                      pcieirq_state <= "00000000"; --go to state 0
1432
                end case;
1433
       end if;
1434
    end if;
1435
    end process;
1436
 
1437
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
1438
        cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
1439
 
1440
 
1441
 
1442
 
1443
 
1444
 
1445
-- -------- END OF FILE -------------------------------------------------------------------------------------
1446
end Behavioral;
1447
 
1448
 

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