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[/] [pcie_mini/] [trunk/] [main_sources/] [xilinx_pcie2wb.vhd] - Blame information for rev 5

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1 2 buenos
----------------------------------------------------------------------------------
2
-- Company:
3
-- Engineer: Istvan Nagy, buenos@freemail.hu
4
-- 
5 3 buenos
-- Create Date:    05/30/2010
6
-- Modify date:    04/26/2011
7 2 buenos
-- Design Name:    pcie_mini
8
-- Module Name:    xilinx_pcie2wb - Behavioral 
9 4 buenos
-- Version:        1.2
10 2 buenos
-- Project Name: 
11 4 buenos
-- Target Devices: Xilinx Series-5/6/7 FPGAs (This code is tested on Spartan-6 XC6SLX45T)
12 2 buenos
-- Tool versions: ISE-DS 12.1
13
-- Description: 
14
--  PCI-express endpoint block, transaction layer logic and back-end logic. The main 
15
--  purpose of this file is to make a useable back-end interface and handle flow control
16
--  for the xilinx auto-generated PCIe endpoint IP.
17
--  The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
18
--  This 256MBytes size is set up in the core config, and also hardcoded in this 
19
--  file (search for: "256MBytes").
20
--  This 1 BAR is implemented as a Wishbone master interface with byte addressing,
21
--  where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
22
--  ADDRESSES ARE BYTE ADDRESSES. 
23
--  The lower address bits are usually zero, so the slave (MCB) has to select bytes based 
24
--  on the byte select signals: sel[3:0]. The output address of the core contails the 2 
25
--  LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
26
--  The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a 
27
--  single PCIe transaction, and can handle only one request at a time. If a new request 
28
--  is arriving while processing the previous one (e.g. getting the data from a wishbone 
29
--  read), then the state machine will not process it immediately, or it will hang. So 
30
--  the user software has to wait for the previous read completion before issueing a new 
31
--  request. The multiple DWORDs are handled separately by the WB statemachine.
32
--  Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum 
33
--  data throughput can be achieved when using the maximum data payload (block).
34
--  The core uses INTA wirtual wire to signal interrupts.
35
--  
36
-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. The generated core had to
37
-- be edited manually to support 100MHz, as per Xilinx AR#33761.
38
--
39
-- Dependencies: The CoreGenerator's configured PCIe core is included.
40
--  If we generate a new pcie endpoint, then copy the new files from the source
41
--  directory into the project's directory, and copy the generic section of the "pcie" 
42
--  from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
43 4 buenos
--
44
-- Device Type Migration:
45 5 buenos
--  This core was tested on Xilinx Spartan-6 FPGAs, specifically on the XC6SLX45T.
46 4 buenos
--  For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
47
--  replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
48
--  in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements 
49
--  will have to be re-specified with the appropriate resources/locations. The coregenerator
50
--  will have to be set up to generate cores with the same parameters and ports as they are
51
--  used here (to be useable as a drop-in replacement). Some resources are instantiated as
52
--  part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
53
--  to adjust their LOC placement constraints in the UCF file.
54 5 buenos
--  Use on 7-series FPGAs:
55
--  Xilinx Series-7 FPGAs have only 64-bit bus support on the PCIe port for x1/x2, 
56
--  and 28bit for x4/x8. Initial compatibility can be maintained with minimal modifications, by 
57
--  replacing the TX and RX block-ram buffers to assymetrically sized port buffers. 64bit on the PCIE-EP side, and 32-bit on the other side. Also the first entry has to be corrected to be at address zero or address-2, since now it is at address-1 which will get misaligned after a port-width conversion. Also the TRN-interfaces have to be modified to work with the AXI4 interface used by the series-7 PCIE-EP blocks.
58
 
59 4 buenos
--
60
-- Coregenerator parameters:
61
--  PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes, 
62
--           ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0, 
63
--           Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off, 
64
--           no_scram =off, Xil_Refboard=None, RefClkFreq=125MHz, TranscLoc/Ch="leave default".
65
--  Blockram: Name=blk_mem_gen_v4_1, Type=SimpleDpRAM, WriteEn=off, Algor=MinArea, 
66
--            WriteWidth=32, WriteDepth=512, Ena=AlwaysEnabled, ReadWidth=32, RegisterPorttB=off
67
--            LoadInitFile=off, Fill=off, UseRSTB=off.
68
--
69 2 buenos
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
70
--
71
-- Revision: 
72
-- Revision 0.01 - File Created
73
 
74
--
75
----------------------------------------------------------------------------------
76
library IEEE;
77
use IEEE.STD_LOGIC_1164.ALL;
78
use IEEE.STD_LOGIC_ARITH.ALL;
79
use IEEE.STD_LOGIC_UNSIGNED.ALL;
80
 
81
-- Uncomment the following library declaration if instantiating
82
-- any Xilinx primitives in this code.
83
library UNISIM;
84
use UNISIM.VComponents.all;
85
 
86
 
87
 
88
entity xilinx_pcie2wb is
89
    Port ( --FPGA PINS(EXTERNAL):
90
                         pci_exp_txp             : out std_logic;
91
                         pci_exp_txn             : out std_logic;
92
                         pci_exp_rxp             : in  std_logic;
93
                         pci_exp_rxn             : in  std_logic;
94
                         sys_clk_n                 : in  std_logic;
95
                         sys_clk_p                 : in  std_logic;
96
                         sys_reset_n             : in  std_logic;
97
                         --ON CHIP PORTS:
98
                         --DATA BUS for BAR0 (wishbone):
99
                         pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
100
                         pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
101
                         pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
102
                         pcie_bar0_wb_cyc_o : out std_logic;
103
                         pcie_bar0_wb_stb_o : out std_logic;
104
                         pcie_bar0_wb_wr_o : out std_logic;
105
                         pcie_bar0_wb_ack_i : in std_logic;
106
                         pcie_bar0_wb_clk_o : out std_logic; --62.5MHz          
107
                         pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
108
                         --OTHER:
109
                         pcie_irq : in std_logic;
110
                         pcie_resetout  : out std_logic --active high
111
                        );
112
end xilinx_pcie2wb;
113
 
114
 
115
 
116
 
117
architecture Behavioral of xilinx_pcie2wb is
118
 
119
 
120
 
121
 
122
   -- Internal Signals ------------------------------------------------------------
123
        --SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
124
        SIGNAL          cfg_do  :               std_logic_vector(31     downto  0);
125
        SIGNAL          cfg_rd_wr_done_n        :               std_logic;
126
        SIGNAL          cfg_dwaddr      :               std_logic_vector(9      downto  0);
127
        SIGNAL          cfg_rd_en_n     :               std_logic;
128
        SIGNAL          cfg_err_ur_n    :               std_logic;
129
        SIGNAL          cfg_err_cor_n   :               std_logic;
130
        SIGNAL          cfg_err_ecrc_n  :               std_logic;
131
        SIGNAL          cfg_err_cpl_timeout_n   :               std_logic;
132
        SIGNAL          cfg_err_cpl_abort_n     :               std_logic;
133
        SIGNAL          cfg_err_posted_n        :               std_logic;
134
        SIGNAL          cfg_err_locked_n        :               std_logic;
135
        SIGNAL          cfg_err_tlp_cpl_header  :               std_logic_vector(47     downto  0);
136
        SIGNAL          cfg_err_cpl_rdy_n       :               std_logic;
137
        SIGNAL          cfg_interrupt_n :               std_logic;
138
        SIGNAL          cfg_interrupt_rdy_n     :               std_logic;
139
        SIGNAL          cfg_interrupt_assert_n  :               std_logic;
140
        SIGNAL          cfg_interrupt_do        :               std_logic_vector(7      downto  0);
141
        SIGNAL          cfg_interrupt_di        :               std_logic_vector(7      downto  0);
142
        SIGNAL          cfg_interrupt_mmenable  :               std_logic_vector(2      downto  0);
143
        SIGNAL          cfg_interrupt_msienable :               std_logic;
144
        SIGNAL          cfg_turnoff_ok_n        :               std_logic;
145
        SIGNAL          cfg_to_turnoff_n        :               std_logic;
146
        SIGNAL          cfg_pm_wake_n   :               std_logic;
147
        SIGNAL          cfg_pcie_link_state_n   :               std_logic_vector(2      downto  0);
148
        SIGNAL          cfg_trn_pending_n       :               std_logic;
149
        SIGNAL          cfg_dsn :               std_logic_vector(63     downto  0);
150
        SIGNAL          cfg_bus_number  :               std_logic_vector(7      downto  0);
151
        SIGNAL          cfg_device_number       :               std_logic_vector(4      downto  0);
152
        SIGNAL          cfg_function_number     :               std_logic_vector(2      downto  0);
153
        SIGNAL          cfg_status      :               std_logic_vector(15     downto  0);
154
        SIGNAL          cfg_command     :               std_logic_vector(15     downto  0);
155
        SIGNAL          cfg_dstatus     :               std_logic_vector(15     downto  0);
156
        SIGNAL          cfg_dcommand    :               std_logic_vector(15     downto  0);
157
        SIGNAL          cfg_lstatus     :               std_logic_vector(15     downto  0);
158
        SIGNAL          cfg_lcommand    :               std_logic_vector(15     downto  0);
159
    -- System Interface
160
        SIGNAL      sys_clk                 :   std_logic;
161
        SIGNAL      trn_clk                 :  std_logic;
162
        SIGNAL      trn_reset_n             :  std_logic;
163
        SIGNAL      received_hot_reset      :  std_logic;
164
    -- Transaction (TRN) Interface
165
        SIGNAL      trn_lnk_up_n            :  std_logic;
166
        --      data interface Tx                                       
167
        SIGNAL          trn_td  :               std_logic_vector(31     downto  0);
168
        SIGNAL          trn_tsof_n      :               std_logic;
169
        SIGNAL          trn_teof_n      :               std_logic;
170
        SIGNAL          trn_tsrc_rdy_n  :               std_logic;
171
        SIGNAL          trn_tdst_rdy_n  :               std_logic;
172
        SIGNAL          trn_terr_drop_n :               std_logic;
173
        SIGNAL          trn_tsrc_dsc_n  :               std_logic;
174
        SIGNAL          trn_terrfwd_n   :               std_logic;
175
        SIGNAL          trn_tbuf_av     :               std_logic_vector(5      downto  0);
176
        SIGNAL          trn_tstr_n      :               std_logic;
177
        SIGNAL          trn_tcfg_req_n  :               std_logic;
178
        SIGNAL          trn_tcfg_gnt_n  :               std_logic;
179
        --      data interface Rx                                       
180
        SIGNAL          trn_rd  :               std_logic_vector(31     downto  0);
181
        SIGNAL          trn_rsof_n      :               std_logic;
182
        SIGNAL          trn_reof_n      :               std_logic;
183
        SIGNAL          trn_rsrc_rdy_n  :               std_logic;
184
        SIGNAL          trn_rsrc_dsc_n  :               std_logic;
185
        SIGNAL          trn_rdst_rdy_n  :               std_logic;
186
        SIGNAL          trn_rerrfwd_n   :               std_logic;
187
        SIGNAL          trn_rnp_ok_n    :               std_logic;
188
        SIGNAL          trn_rbar_hit_n  :               std_logic_vector(6      downto  0);
189
        -- flow control
190
        SIGNAL          trn_fc_sel      :               std_logic_vector(2      downto  0);
191
        SIGNAL          trn_fc_nph      :               std_logic_vector(7      downto  0);
192
        SIGNAL          trn_fc_npd      :               std_logic_vector(11     downto  0);
193
        SIGNAL          trn_fc_ph       :               std_logic_vector(7      downto  0);
194
        SIGNAL          trn_fc_pd       :               std_logic_vector(11     downto  0);
195
        SIGNAL          trn_fc_cplh     :               std_logic_vector(7      downto  0);
196
        SIGNAL          trn_fc_cpld     :               std_logic_vector(11     downto  0);
197
 
198
        SIGNAL   start_read_wb0 :               std_logic;
199
        SIGNAL   start_write_wb0        :               std_logic;
200
        SIGNAL   wb_transaction_complete        :               std_logic;
201
        SIGNAL   pcie_bar0_wb_data_i_latched    :               std_logic_vector(31     downto  0);
202
        SIGNAL   pcie_bar0_wb_data_o_feed       :               std_logic_vector(31     downto  0);
203
        SIGNAL   pcie_bar0_wb_addr_o_feed       :               std_logic_vector(27     downto  0);
204
        SIGNAL   pcie_bar0_wb_sel_o_feed        :               std_logic_vector(3      downto  0);
205
        SIGNAL   start_read_wb1 :               std_logic;
206
        SIGNAL   start_write_wb1        :               std_logic;
207
        SIGNAL   rd_data_ready_wb1      :               std_logic;
208
 
209
    SIGNAL   pcie_just_received_a_new_tlp      :  std_logic  ;
210
    SIGNAL   pcie_start_reading_rx_tlp      :  std_logic  ;
211
    SIGNAL   pcie_there_is_a_new_tlp_to_transmit      :  std_logic  ;
212
    SIGNAL   rxtlp_decodedaddress      :  std_logic_vector(31 downto 0);
213
    SIGNAL   tlp_payloadsize_dwords      :  std_logic_vector(7 downto 0);
214
    SIGNAL   rxtlp_firstdw_be      :  std_logic_vector(3 downto 0);
215
    SIGNAL   rxtlp_lastdw_be      :  std_logic_vector(3 downto 0);
216
    SIGNAL   rxtlp_requesterid      :  std_logic_vector(15 downto 0);
217
    SIGNAL   tlp_state      :  std_logic_vector(7 downto 0);
218
    SIGNAL   tlp_state_copy      :  std_logic_vector(7 downto 0);
219
    SIGNAL   rxtlp_data_0      :  std_logic_vector(31 downto 0);
220
    SIGNAL   rxtlp_data_1      :  std_logic_vector(31 downto 0);
221
    SIGNAL   rxtlp_data_2      :  std_logic_vector(31 downto 0);
222
    SIGNAL   rxtlp_data_3      :  std_logic_vector(31 downto 0);
223
    SIGNAL   rxtlp_data_4      :  std_logic_vector(31 downto 0);
224
    SIGNAL   rxtlp_data_5      :  std_logic_vector(31 downto 0);
225
    SIGNAL   rxtlp_data_6      :  std_logic_vector(31 downto 0);
226
    SIGNAL   rxtlp_data_7      :  std_logic_vector(31 downto 0);
227
    SIGNAL   txtlp_data_0      :  std_logic_vector(31 downto 0);
228
    SIGNAL   txtlp_data_1      :  std_logic_vector(31 downto 0);
229
    SIGNAL   txtlp_data_2      :  std_logic_vector(31 downto 0);
230
    SIGNAL   txtlp_data_3      :  std_logic_vector(31 downto 0);
231
    SIGNAL   txtlp_data_4      :  std_logic_vector(31 downto 0);
232
    SIGNAL   txtlp_data_5      :  std_logic_vector(31 downto 0);
233
    SIGNAL   txtlp_data_6      :  std_logic_vector(31 downto 0);
234
    SIGNAL   txtlp_data_7      :  std_logic_vector(31 downto 0);
235
    SIGNAL   pcie_tlp_tx_complete       :  std_logic;
236
 
237
         SIGNAL  pcieirq_state    :  std_logic_vector(7 downto 0);
238
         SIGNAL  txtrn_counter   :  std_logic_vector(7 downto 0);
239
         SIGNAL  trn_rx_counter   :  std_logic_vector(7 downto 0);
240
         SIGNAL cfg_completer_id  :  std_logic_vector(15 downto 0);
241
         SIGNAL wb0_state :   std_logic_vector(7 downto 0);
242
         SIGNAL epif_tx_state :   std_logic_vector(7 downto 0);
243
         SIGNAL epif_rx_state :   std_logic_vector(7 downto 0);
244
         SIGNAL bit10 :   std_logic_vector(1 downto 0);
245
 
246
  SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
247
  SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
248
  SIGNAL bram_rxtlp_writedata : std_logic_vector(31 downto 0);
249
  SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
250
  SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
251
  SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
252
  SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
253
  SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
254
  SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
255
  SIGNAL bram_txtlp_readdata : std_logic_vector(31 downto 0);
256
 
257
  SIGNAL tlp_datacount :   std_logic_vector(7 downto 0);
258
  --SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
259
  SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
260
  SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
261
  SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
262
  SIGNAL rxtlp_header_dw4 : std_logic_vector(31 downto 0);
263
  SIGNAL flag1 :      std_logic;
264
  SIGNAL rxdw1_23_0  : std_logic_vector(23 downto 0);
265
  SIGNAL pcie_rxtlp_tag  : std_logic_vector(7 downto 0);
266
  SIGNAL pciewb_localreset_n :      std_logic;
267
  SIGNAL cfg_interrupt_assert_n_1 :      std_logic;
268
  SIGNAL trn_tsrc_rdy_n_1 :      std_logic;
269
  SIGNAL trn_tsof_n1 :      std_logic;
270 3 buenos
  SIGNAL rcompl_bytecount_field  : std_logic_vector(9 downto 0);
271
  SIGNAL rxstm_readytoroll :      std_logic;
272
  SIGNAL tlpstm_isin_idle :      std_logic;
273 4 buenos
  SIGNAL pcierx_detected :  std_logic;
274
  SIGNAL pcierx_detect_ff_clear :  std_logic;
275 2 buenos
 
276
 
277
 
278
 
279
        -- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
280
 
281
  --this is the pcie endpoint core from coregenerator.
282
        --Core name: Xilinx Spartan-6 Integrated
283
        --Block for PCI Express
284
        --Version: 1.2
285
        --Release Date: September 16, 2009. ISE DS 11.4
286
  component pcie is
287
  generic (
288
    TL_TX_RAM_RADDR_LATENCY           : integer    := 0;
289
    TL_TX_RAM_RDATA_LATENCY           : integer    := 2;
290
    TL_RX_RAM_RADDR_LATENCY           : integer    := 0;
291
    TL_RX_RAM_RDATA_LATENCY           : integer    := 2;
292
    TL_RX_RAM_WRITE_LATENCY           : integer    := 0;
293
    VC0_TX_LASTPACKET                 : integer    := 14;
294
    VC0_RX_RAM_LIMIT                  : bit_vector := x"7FF";
295
    VC0_TOTAL_CREDITS_PH              : integer    := 32;
296
    VC0_TOTAL_CREDITS_PD              : integer    := 211;
297
    VC0_TOTAL_CREDITS_NPH             : integer    := 8;
298
    VC0_TOTAL_CREDITS_CH              : integer    := 40;
299
    VC0_TOTAL_CREDITS_CD              : integer    := 211;
300
    VC0_CPL_INFINITE                  : boolean    := TRUE;
301
    BAR0                              : bit_vector := x"F0000000";
302
    BAR1                              : bit_vector := x"00000000";
303
    BAR2                              : bit_vector := x"00000000";
304
    BAR3                              : bit_vector := x"00000000";
305
    BAR4                              : bit_vector := x"00000000";
306
    BAR5                              : bit_vector := x"00000000";
307
    EXPANSION_ROM                     : bit_vector := "0000000000000000000000";
308
    DISABLE_BAR_FILTERING             : boolean    := FALSE;
309
    DISABLE_ID_CHECK                  : boolean    := FALSE;
310
    TL_TFC_DISABLE                    : boolean    := FALSE;
311
    TL_TX_CHECKS_DISABLE              : boolean    := FALSE;
312
    USR_CFG                           : boolean    := FALSE;
313
    USR_EXT_CFG                       : boolean    := FALSE;
314
    DEV_CAP_MAX_PAYLOAD_SUPPORTED     : integer    := 2;
315
    CLASS_CODE                        : bit_vector := x"068000";
316
    CARDBUS_CIS_POINTER               : bit_vector := x"00000000";
317
    PCIE_CAP_CAPABILITY_VERSION       : bit_vector := x"1";
318
    PCIE_CAP_DEVICE_PORT_TYPE         : bit_vector := x"1";
319
    PCIE_CAP_SLOT_IMPLEMENTED         : boolean    := FALSE;
320
    PCIE_CAP_INT_MSG_NUM              : bit_vector := "00000";
321
    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer    := 0;
322
    DEV_CAP_EXT_TAG_SUPPORTED         : boolean    := FALSE;
323
    DEV_CAP_ENDPOINT_L0S_LATENCY      : integer    := 7;
324
    DEV_CAP_ENDPOINT_L1_LATENCY       : integer    := 7;
325
    SLOT_CAP_ATT_BUTTON_PRESENT       : boolean    := FALSE;
326
    SLOT_CAP_ATT_INDICATOR_PRESENT    : boolean    := FALSE;
327
    SLOT_CAP_POWER_INDICATOR_PRESENT  : boolean    := FALSE;
328
    DEV_CAP_ROLE_BASED_ERROR          : boolean    := TRUE;
329
    LINK_CAP_ASPM_SUPPORT             : integer    := 1;
330
    LINK_CAP_L0S_EXIT_LATENCY         : integer    := 7;
331
    LINK_CAP_L1_EXIT_LATENCY          : integer    := 7;
332
    LL_ACK_TIMEOUT                    : bit_vector := x"0204";
333
    LL_ACK_TIMEOUT_EN                 : boolean    := FALSE;
334
    LL_REPLAY_TIMEOUT                 : bit_vector := x"0204";
335
    LL_REPLAY_TIMEOUT_EN              : boolean    := FALSE;
336
    MSI_CAP_MULTIMSGCAP               : integer    := 0;
337
    MSI_CAP_MULTIMSG_EXTENSION        : integer    := 0;
338
    LINK_STATUS_SLOT_CLOCK_CONFIG     : boolean    := FALSE;
339
    PLM_AUTO_CONFIG                   : boolean    := FALSE;
340
    FAST_TRAIN                        : boolean    := FALSE;
341
    ENABLE_RX_TD_ECRC_TRIM            : boolean    := FALSE;
342
    DISABLE_SCRAMBLING                : boolean    := FALSE;
343
    PM_CAP_VERSION                    : integer    := 3;
344
    PM_CAP_PME_CLOCK                  : boolean    := FALSE;
345
    PM_CAP_DSI                        : boolean    := FALSE;
346
    PM_CAP_AUXCURRENT                 : integer    := 0;
347
    PM_CAP_D1SUPPORT                  : boolean    := TRUE;
348
    PM_CAP_D2SUPPORT                  : boolean    := TRUE;
349
    PM_CAP_PMESUPPORT                 : bit_vector := x"0F";
350
    PM_DATA0                          : bit_vector := x"04";
351
    PM_DATA_SCALE0                    : bit_vector := x"0";
352
    PM_DATA1                          : bit_vector := x"00";
353
    PM_DATA_SCALE1                    : bit_vector := x"0";
354
    PM_DATA2                          : bit_vector := x"00";
355
    PM_DATA_SCALE2                    : bit_vector := x"0";
356
    PM_DATA3                          : bit_vector := x"00";
357
    PM_DATA_SCALE3                    : bit_vector := x"0";
358
    PM_DATA4                          : bit_vector := x"04";
359
    PM_DATA_SCALE4                    : bit_vector := x"0";
360
    PM_DATA5                          : bit_vector := x"00";
361
    PM_DATA_SCALE5                    : bit_vector := x"0";
362
    PM_DATA6                          : bit_vector := x"00";
363
    PM_DATA_SCALE6                    : bit_vector := x"0";
364
    PM_DATA7                          : bit_vector := x"00";
365
    PM_DATA_SCALE7                    : bit_vector := x"0";
366
    PCIE_GENERIC                      : bit_vector := "000011101111";
367
    GTP_SEL                           : integer    := 0;
368
    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"10EE";
369
    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"ABCD";
370
    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"00";
371
    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"10EE";
372
    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"1234";
373
    REF_CLK_FREQ                      : integer    := 0
374
  );
375
  port (
376
    -- PCI Express Fabric Interface
377
    pci_exp_txp             : out std_logic;
378
    pci_exp_txn             : out std_logic;
379
    pci_exp_rxp             : in  std_logic;
380
    pci_exp_rxn             : in  std_logic;
381
 
382
    -- Transaction (TRN) Interface
383
    trn_lnk_up_n            : out std_logic;
384
 
385
    -- Tx
386
    trn_td                  : in  std_logic_vector(31 downto 0);
387
    trn_tsof_n              : in  std_logic;
388
    trn_teof_n              : in  std_logic;
389
    trn_tsrc_rdy_n          : in  std_logic;
390
    trn_tdst_rdy_n          : out std_logic;
391
    trn_terr_drop_n         : out std_logic;
392
    trn_tsrc_dsc_n          : in  std_logic;
393
    trn_terrfwd_n           : in  std_logic;
394
    trn_tbuf_av             : out std_logic_vector(5 downto 0);
395
    trn_tstr_n              : in  std_logic;
396
    trn_tcfg_req_n          : out std_logic;
397
    trn_tcfg_gnt_n          : in  std_logic;
398
 
399
    -- Rx
400
    trn_rd                  : out std_logic_vector(31 downto 0);
401
    trn_rsof_n              : out std_logic;
402
    trn_reof_n              : out std_logic;
403
    trn_rsrc_rdy_n          : out std_logic;
404
    trn_rsrc_dsc_n          : out std_logic;
405
    trn_rdst_rdy_n          : in  std_logic;
406
    trn_rerrfwd_n           : out std_logic;
407
    trn_rnp_ok_n            : in  std_logic;
408
    trn_rbar_hit_n          : out std_logic_vector(6 downto 0);
409
    trn_fc_sel              : in  std_logic_vector(2 downto 0);
410
    trn_fc_nph              : out std_logic_vector(7 downto 0);
411
    trn_fc_npd              : out std_logic_vector(11 downto 0);
412
    trn_fc_ph               : out std_logic_vector(7 downto 0);
413
    trn_fc_pd               : out std_logic_vector(11 downto 0);
414
    trn_fc_cplh             : out std_logic_vector(7 downto 0);
415
    trn_fc_cpld             : out std_logic_vector(11 downto 0);
416
 
417
    -- Host (CFG) Interface
418
    cfg_do                  : out std_logic_vector(31 downto 0);
419
    cfg_rd_wr_done_n        : out std_logic;
420
    cfg_dwaddr              : in  std_logic_vector(9 downto 0);
421
    cfg_rd_en_n             : in  std_logic;
422
    cfg_err_ur_n            : in  std_logic;
423
    cfg_err_cor_n           : in  std_logic;
424
    cfg_err_ecrc_n          : in  std_logic;
425
    cfg_err_cpl_timeout_n   : in  std_logic;
426
    cfg_err_cpl_abort_n     : in  std_logic;
427
    cfg_err_posted_n        : in  std_logic;
428
    cfg_err_locked_n        : in  std_logic;
429
    cfg_err_tlp_cpl_header  : in  std_logic_vector(47 downto 0);
430
    cfg_err_cpl_rdy_n       : out std_logic;
431
    cfg_interrupt_n         : in  std_logic;
432
    cfg_interrupt_rdy_n     : out std_logic;
433
    cfg_interrupt_assert_n  : in  std_logic;
434
    cfg_interrupt_do        : out std_logic_vector(7 downto 0);
435
    cfg_interrupt_di        : in  std_logic_vector(7 downto 0);
436
    cfg_interrupt_mmenable  : out std_logic_vector(2 downto 0);
437
    cfg_interrupt_msienable : out std_logic;
438
    cfg_turnoff_ok_n        : in  std_logic;
439
    cfg_to_turnoff_n        : out std_logic;
440
    cfg_pm_wake_n           : in  std_logic;
441
    cfg_pcie_link_state_n   : out std_logic_vector(2 downto 0);
442
    cfg_trn_pending_n       : in  std_logic;
443
    cfg_dsn                 : in  std_logic_vector(63 downto 0);
444
    cfg_bus_number          : out std_logic_vector(7 downto 0);
445
    cfg_device_number       : out std_logic_vector(4 downto 0);
446
    cfg_function_number     : out std_logic_vector(2 downto 0);
447
    cfg_status              : out std_logic_vector(15 downto 0);
448
    cfg_command             : out std_logic_vector(15 downto 0);
449
    cfg_dstatus             : out std_logic_vector(15 downto 0);
450
    cfg_dcommand            : out std_logic_vector(15 downto 0);
451
    cfg_lstatus             : out std_logic_vector(15 downto 0);
452
    cfg_lcommand            : out std_logic_vector(15 downto 0);
453
 
454
    -- System Interface
455
    sys_clk                 : in  std_logic;
456
    sys_reset_n             : in  std_logic;
457
    trn_clk                 : out std_logic;
458
    trn_reset_n             : out std_logic;
459
    received_hot_reset      : out std_logic
460
    );
461
  end component pcie;
462
 
463
        COMPONENT blk_mem_gen_v4_1
464
        PORT(
465
                clka : IN std_logic;
466
                wea : IN std_logic_vector(0 to 0);
467
                addra : IN std_logic_vector(8 downto 0);
468
                dina : IN std_logic_vector(31 downto 0);
469
                clkb : IN std_logic;
470
                addrb : IN std_logic_vector(8 downto 0);
471
                doutb : OUT std_logic_vector(31 downto 0)
472
                );
473
        END COMPONENT;
474
 
475
 
476
 
477
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
478
--attribute keep_hierarchy : string; 
479
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes"; 
480
 
481
 
482
 
483
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
484
begin
485
 
486
 
487
cfg_turnoff_ok_n <= '1';
488
 
489
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
490
 
491
 
492
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
493
 
494
  inst_pcie : pcie
495
  port map (
496
    pci_exp_txp             => pci_exp_txp,
497
    pci_exp_txn             => pci_exp_txn,
498
    pci_exp_rxp             => pci_exp_rxp,
499
    pci_exp_rxn             => pci_exp_rxn,
500
    trn_lnk_up_n            => trn_lnk_up_n,
501
    trn_td                  => trn_td,                   -- Bus [31 : 0]
502
    trn_tsof_n              => trn_tsof_n,
503
    trn_teof_n              => trn_teof_n,
504
    trn_tsrc_rdy_n          => trn_tsrc_rdy_n,
505
    trn_tdst_rdy_n          => trn_tdst_rdy_n,
506
    trn_terr_drop_n         => trn_terr_drop_n,
507
    trn_tsrc_dsc_n          => trn_tsrc_dsc_n,
508
    trn_terrfwd_n           => trn_terrfwd_n,
509
    trn_tbuf_av             => trn_tbuf_av,              -- Bus [31 : 0]
510
    trn_tstr_n              => trn_tstr_n,
511
    trn_tcfg_req_n          => trn_tcfg_req_n,
512
    trn_tcfg_gnt_n          => trn_tcfg_gnt_n,
513
    trn_rd                  => trn_rd,                   -- Bus [31 : 0]
514
    trn_rsof_n              => trn_rsof_n,
515
    trn_reof_n              => trn_reof_n,
516
    trn_rsrc_rdy_n          => trn_rsrc_rdy_n,
517
    trn_rsrc_dsc_n          => trn_rsrc_dsc_n,
518
    trn_rdst_rdy_n          => trn_rdst_rdy_n,
519
    trn_rerrfwd_n           => trn_rerrfwd_n,
520
    trn_rnp_ok_n            => trn_rnp_ok_n,
521
    trn_rbar_hit_n          => trn_rbar_hit_n,           -- Bus [31 : 0]
522
    trn_fc_sel              => trn_fc_sel,               -- Bus [31 : 0]
523
    trn_fc_nph              => trn_fc_nph,               -- Bus [31 : 0]
524
    trn_fc_npd              => trn_fc_npd,               -- Bus [31 : 0]
525
    trn_fc_ph               => trn_fc_ph,                -- Bus [31 : 0]
526
    trn_fc_pd               => trn_fc_pd,                -- Bus [31 : 0]
527
    trn_fc_cplh             => trn_fc_cplh,              -- Bus [31 : 0]
528
    trn_fc_cpld             => trn_fc_cpld,              -- Bus [31 : 0]
529
    cfg_do                  => cfg_do,                   -- Bus [31 : 0]
530
    cfg_rd_wr_done_n        => cfg_rd_wr_done_n,
531
    cfg_dwaddr              => cfg_dwaddr,               -- Bus [31 : 0]
532
    cfg_rd_en_n             => cfg_rd_en_n,
533
    cfg_err_ur_n            => cfg_err_ur_n,
534
    cfg_err_cor_n           => cfg_err_cor_n,
535
    cfg_err_ecrc_n          => cfg_err_ecrc_n,
536
    cfg_err_cpl_timeout_n   => cfg_err_cpl_timeout_n,
537
    cfg_err_cpl_abort_n     => cfg_err_cpl_abort_n,
538
    cfg_err_posted_n        => cfg_err_posted_n,
539
    cfg_err_locked_n        => cfg_err_locked_n,
540
    cfg_err_tlp_cpl_header  => cfg_err_tlp_cpl_header,   -- Bus [31 : 0]
541
    cfg_err_cpl_rdy_n       => cfg_err_cpl_rdy_n,
542
    cfg_interrupt_n         => cfg_interrupt_n,
543
    cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n,
544
    cfg_interrupt_assert_n  => cfg_interrupt_assert_n,
545
    cfg_interrupt_do        => cfg_interrupt_do,         -- Bus [31 : 0]
546
    cfg_interrupt_di        => cfg_interrupt_di,         -- Bus [31 : 0]
547
    cfg_interrupt_mmenable  => cfg_interrupt_mmenable,   -- Bus [31 : 0]
548
    cfg_interrupt_msienable => cfg_interrupt_msienable,
549
    cfg_turnoff_ok_n        => cfg_turnoff_ok_n,
550
    cfg_to_turnoff_n        => cfg_to_turnoff_n,
551
    cfg_pm_wake_n           => cfg_pm_wake_n,
552
    cfg_pcie_link_state_n   => cfg_pcie_link_state_n,    -- Bus [31 : 0]
553
    cfg_trn_pending_n       => cfg_trn_pending_n,
554
    cfg_dsn                 => cfg_dsn,                  -- Bus [31 : 0]
555
    cfg_bus_number          => cfg_bus_number,           -- Bus [31 : 0]
556
    cfg_device_number       => cfg_device_number,        -- Bus [31 : 0]
557
    cfg_function_number     => cfg_function_number,      -- Bus [31 : 0]
558
    cfg_status              => cfg_status,               -- Bus [31 : 0]
559
    cfg_command             => cfg_command,              -- Bus [31 : 0]
560
    cfg_dstatus             => cfg_dstatus,              -- Bus [31 : 0]
561
    cfg_dcommand            => cfg_dcommand,             -- Bus [31 : 0]
562
    cfg_lstatus             => cfg_lstatus,              -- Bus [31 : 0]
563
    cfg_lcommand            => cfg_lcommand,             -- Bus [31 : 0]
564
    sys_clk                 => sys_clk,
565
    sys_reset_n             => sys_reset_n,
566
    trn_clk                 => trn_clk,
567
    trn_reset_n             => trn_reset_n,
568
    received_hot_reset      => received_hot_reset
569
  );
570
 
571
        --block ram for RX TLP:
572
        Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
573
                clka => trn_clk,
574
                wea => bram_rxtlp_we,
575
                addra => bram_rxtlp_writeaddress(8 downto 0),
576
                dina => bram_rxtlp_writedata,
577
                clkb => trn_clk,
578
                addrb => bram_rxtlp_readaddress(8 downto 0),
579
                doutb => bram_rxtlp_readdata
580
        );
581
 
582
        --block ram for TX TLP:
583
        Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
584
                clka => trn_clk,
585
                wea => bram_txtlp_we,
586
                addra => bram_txtlp_writeaddress(8 downto 0),
587
                dina => bram_txtlp_writedata,
588
                clkb => trn_clk,
589
                addrb => bram_txtlp_readaddress(8 downto 0),
590
                doutb => bram_txtlp_readdata
591
        );
592
 
593
 
594
 
595
 
596
 
597
        -- MAIN LOGIC: ---------------------------------------------------------------------------------------------
598
 
599
 
600
 
601
        --System Signals:--------------------------------
602
 
603
  --Clock Input Buffer for differential system clock
604
   IBUFDS_inst : IBUFDS
605
   generic map (
606
      DIFF_TERM => TRUE, -- Differential Termination 
607
      IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
608
      IOSTANDARD => "DEFAULT")
609
   port map (
610
      O => sys_clk,  -- Buffer output
611
      I => sys_clk_p,  -- Diff_p buffer input (connect directly to top-level port)
612
      IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
613
   );
614
 
615
  --wishbone clock output:
616
  pcie_bar0_wb_clk_o <= trn_clk;
617
  --pcie_bar1_wb_clk_o <= trn_clk; 
618
 
619
 
620
  --use one of these for resetting logic in this file:
621
    pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
622
    --pciewb_localreset_n <= trn_reset_n;
623
         --pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
624
  --reset to the core:
625
  --sys_reset_n comes from toplevel directly to the core. same name
626
  --reset output to other cores:
627
  pcie_resetout <= not pciewb_localreset_n;
628
 
629
  --trn_lnk_up_n    --not used.
630
 
631
 
632
  --pcie ep ip config port: ----------------------------------------------------------
633
 
634
   --trn_fc_sel             <= "000";
635
 
636
  trn_rnp_ok_n           <= '0';
637
  --trn_terrfwd_n          <= '1';
638
 
639
  --trn_tcfg_gnt_n         <= '0';
640
 
641
  cfg_err_cor_n          <= '1';
642
  cfg_err_ur_n           <= '1';
643
  cfg_err_ecrc_n         <= '1';
644
  cfg_err_cpl_timeout_n  <= '1';
645
  cfg_err_cpl_abort_n    <= '1';
646
  cfg_err_posted_n       <= '0';
647
  cfg_err_locked_n       <= '1';
648
  cfg_pm_wake_n          <= '1';
649
  cfg_trn_pending_n      <= '1';
650
 
651
  --trn_tstr_n             <= '0'; 
652
  --cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
653
  --cfg_interrupt_n        <= '1';
654
  --cfg_interrupt_di       <= x"00"; --intA used
655
 
656
  cfg_err_tlp_cpl_header <= (OTHERS => '0');
657
  cfg_dwaddr             <= (OTHERS => '0');
658
  cfg_rd_en_n            <= '1';
659
  --serial number:
660
  cfg_dsn                <= (OTHERS => '0');
661
 
662
 -- AT THE BOTTOM OF THIS FILE:
663
 --      --some fix values:
664
 --      trn_tsrc_dsc_n <= '1'; --no errors on trn bus
665
 --      trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
666
 --      trn_tcfg_gnt_n <= '0'; --no tlp priorities
667
 --      trn_terrfwd_n <= '1'; --no errors on trn
668
 --      --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
669
 
670
 
671
 
672
  --use this in read completion packets:
673
  cfg_completer_id       <= cfg_bus_number & cfg_device_number & cfg_function_number;
674
 
675
 
676
 
677
 
678
 
679
 
680
        -- WISBONE BACK-end INTERFACE ----------------------------------------------------
681
 
682
    --main state machine: set states, capture inputs, set addr/data outputs
683
         --minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
684
    process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
685
                                pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
686
    begin
687
    if (pciewb_localreset_n='0') then
688
       wb0_state <= "00000000";
689
       wb_transaction_complete <= '0';
690
                 pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
691
                 pcie_bar0_wb_sel_o <= "0000";
692
                 pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
693
                 wb_transaction_complete <='0';
694
    else
695
      if (trn_clk'event and trn_clk = '1') then
696
                case ( wb0_state ) is
697
 
698
                --********** IDLE STATE  **********
699
                when "00000000" =>   --state 0        
700
                    wb_transaction_complete <='0';
701 3 buenos
                                                  pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
702 2 buenos
                                                  pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
703
                                                  if (start_read_wb0 ='1') then --go to read
704
                                                    wb0_state <= "00000001";
705
                                                  elsif (start_write_wb0 ='1') then --go to write
706
                                                    wb0_state <= "00000010";
707
                                                         --no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
708
                                                    pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
709
                                                    pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
710
                                                    pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
711
                                                    pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism                                                           
712
                                                  end if;
713
 
714
                --********** READ STATE ********** 
715
                                         --set the outputs, 
716
                                         --if ACK asserted, sample the data input
717
                                         --The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
718
                when "00000001" =>   --state 1
719
                    if (pcie_bar0_wb_ack_i='1') then
720
                                                    --no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
721
                                                    pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
722
                                                    pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
723
                                                    pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
724
                                                    pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism                                                      
725
                                                         wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
726
                                                         wb0_state <= "00000000"; --go to state 0
727
                                                  else
728
                                                         wb_transaction_complete <='0';
729
                                                  end if;
730
 
731
                --********** WRITE STATE **********     
732
                                         --if ACK asserted, go back to idle
733
                                         --The hold requirements are oversatisfyed by waiting for ACK to remove write data                                       
734
                when "00000010" =>   --state 2
735
                    if (pcie_bar0_wb_ack_i='1') then
736
                                                         wb0_state <= "00000000"; --go to state 0
737
                                                         wb_transaction_complete <='1';
738
                                                  else
739
                                                     wb_transaction_complete <='0';
740
                                                  end if;
741
 
742
                when others => --error
743
                      wb0_state <= "00000000"; --go to state 0
744
                end case;
745
       end if;
746
    end if;
747
    end process;
748
    --sync control on wb-control signals:
749
    process (pciewb_localreset_n, wb0_state)
750
    begin
751
    if (pciewb_localreset_n='0') then
752
                pcie_bar0_wb_cyc_o  <= '0';
753
                pcie_bar0_wb_stb_o  <= '0';
754
                pcie_bar0_wb_wr_o  <= '0';
755
    else
756
      if (wb0_state = "00000000") then --idle
757
                        pcie_bar0_wb_cyc_o  <= '0';
758
                        pcie_bar0_wb_stb_o  <= '0';
759
                        pcie_bar0_wb_wr_o  <= '0';
760
      elsif (wb0_state = "00000001") then --read 
761
                        pcie_bar0_wb_cyc_o  <= '1';
762
                        pcie_bar0_wb_stb_o  <= '1';
763
                        pcie_bar0_wb_wr_o  <= '0';
764
      elsif (wb0_state = "00000010") then --write 
765
                        pcie_bar0_wb_cyc_o  <= '1';
766
                        pcie_bar0_wb_stb_o  <= '1';
767
                        pcie_bar0_wb_wr_o  <= '1';
768
                else
769
                        pcie_bar0_wb_cyc_o  <= '0';
770
                        pcie_bar0_wb_stb_o  <= '0';
771
                        pcie_bar0_wb_wr_o  <= '0';
772
                end if;
773
    end if;
774
    end process;
775
 
776
 
777
 
778
 
779
 
780
 
781
 
782
 
783
        -- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
784
        --trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
785
        --so it is not a clock domain crossing.
786
 
787
 
788
        -- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
789
        --Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
790
    process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
791
                                pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
792
    begin
793
    if (pciewb_localreset_n='0') then
794
      epif_tx_state <= "00000000";
795
      trn_tsrc_rdy_n_1 <='1';
796
                trn_tsof_n1 <= '1';
797
                trn_teof_n <= '1';
798
                trn_td <= (OTHERS => '0');
799
                pcie_tlp_tx_complete <= '0';
800
                txtrn_counter <= "00000001";
801
                bram_txtlp_readaddress <= (OTHERS => '0');
802
    else
803
      if (trn_clk'event and trn_clk = '1') then
804
                case ( epif_tx_state ) is
805
 
806
                --********** idle STATE  **********
807
                when "00000000" =>   --state 0        
808
                    --if there is a new TLP assembled and the EP is ready, 
809
                                                  --start the tx-trn bus transaction.
810
                                                  if (pcie_there_is_a_new_tlp_to_transmit='1') then
811
                                                    epif_tx_state <= "00000001"; --next state
812
                                                  end if;
813
                    trn_tsrc_rdy_n_1 <='1';
814
                                                  trn_tsof_n1 <= '1';
815
                                                  trn_teof_n <= '1';
816
                                                  trn_td <= (OTHERS => '0');
817
                                                  pcie_tlp_tx_complete <= '0';
818
                                                  txtrn_counter <= "00000001";
819
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
820
 
821
                --********** ready-wait STATE  **********
822
                when "00000001" =>   --state 1        
823
                    --if there is a new TLP assembled and the EP is ready, 
824
                                                  --start the tx-trn bus transaction.
825
                                                  if (trn_tdst_rdy_n='0') then
826
                                                    epif_tx_state <= "00000010"; --next state
827
                                                  end if;
828
                    trn_tsrc_rdy_n_1 <='1';
829
                                                  trn_tsof_n1 <= '1';
830
                                                  trn_teof_n <= '1';
831
                                                  trn_td <= (OTHERS => '0');
832
                                                  pcie_tlp_tx_complete <= '0';
833
                                                  txtrn_counter <= "00000001";
834
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
835
 
836
                --********** transfer STATE **********                                   
837
                when "00000010" =>   --state 2
838
                    trn_tsrc_rdy_n_1 <='0';
839
                                                  trn_td <= bram_txtlp_readdata;
840
                                                  if (trn_tdst_rdy_n='0') then
841
                                                    txtrn_counter <= txtrn_counter +1;
842
                                                         bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
843
                                                  end if;
844
                                                  if (txtrn_counter = "00000010") then
845
                                                    trn_tsof_n1 <= '0'; --start
846
                                                  else
847
                                                    trn_tsof_n1 <= '1';
848
                                                  end if;
849
                                                  --test number of dwords:
850
                                                  if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
851
                                                  --this is the last dword, next clk is next state
852
                                                         epif_tx_state <= "00000000"; --back to idle, since finished
853
                                                    trn_teof_n <= '0'; --end
854
                                                    pcie_tlp_tx_complete <= '1'; --assert for 1 clk
855
                                                  else
856
                                                    trn_teof_n <= '1'; --not end yet
857
                                                    pcie_tlp_tx_complete <= '0'; --not complete yet
858
                                                  end if;
859
 
860
                when others => --error
861
                    epif_tx_state <= "00000000"; --back to idle
862
                    trn_tsrc_rdy_n_1 <='1';
863
                                                  trn_tsof_n1 <= '1';
864
                                                  trn_teof_n <= '1';
865
                                                  trn_td <= (OTHERS => '0');
866
                                                  pcie_tlp_tx_complete <= '0';
867
                                                  txtrn_counter <= "00000001";
868
 
869
                end case;
870
       end if;
871
    end if;
872
    end process;
873
 
874
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
875
        trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
876
        trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
877
 
878
 
879
 
880
         --some fix values:
881
         trn_tsrc_dsc_n <= '1'; --no errors on trn bus
882
         trn_tstr_n <= '0'; --pipelining 
883
         trn_tcfg_gnt_n <= '0'; --no tlp priorities 
884
         trn_terrfwd_n <= '1'; --no errors on trn
885
         --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
886
 
887
 
888
 
889
 
890
 
891
        -- RX: INTERFACE TO THE PCIE-EP: GET thereceived TLP PACKETS:- ----
892 3 buenos
    process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter,
893
                                bram_rxtlp_writeaddress, rxstm_readytoroll, trn_rsof_n, tlpstm_isin_idle, trn_rdst_rdy_n)
894 2 buenos
    begin
895
    if (pciewb_localreset_n='0') then
896
                 pcie_just_received_a_new_tlp <= '0';
897
                 epif_rx_state  <= "00000000";
898
                 trn_rdst_rdy_n <= '1';
899
                 trn_rx_counter <= (OTHERS => '0');
900
                 bram_rxtlp_we <= "0";
901
                 bram_rxtlp_writeaddress <= (OTHERS => '0');
902
                 bram_rxtlp_writedata  <= (OTHERS => '0');
903 3 buenos
                 rxstm_readytoroll <= '0';
904 2 buenos
    else
905
      if (trn_clk'event and trn_clk = '1') then
906
 
907
                case ( epif_rx_state ) is
908
 
909
                --********** idle STATE  **********
910
                when "00000000" =>   --state 0
911
                                                  pcie_just_received_a_new_tlp <= '0';
912 3 buenos
                                                  bram_rxtlp_writedata  <= trn_rd;
913
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1' and trn_rdst_rdy_n='0') then
914 2 buenos
                                                    trn_rx_counter <= trn_rx_counter +1;
915
                                                         bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
916
                                                         epif_rx_state <= "00000001";
917
                                                  else
918
                                                    trn_rx_counter <= (OTHERS => '0');
919
                                                         bram_rxtlp_writeaddress  <= (OTHERS => '0');
920 3 buenos
                                                  end if;
921
                                                  --destination ready:
922
                                                  if (tlpstm_isin_idle = '1')then
923
                                                          trn_rdst_rdy_n <= '0';
924
                                                  else
925
                                                          trn_rdst_rdy_n <= '1';
926
                                                  end if;
927
                                                  --write into buffer:
928
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1') then
929
                                                         bram_rxtlp_we <= "1";
930
                                                         rxstm_readytoroll <= '1';
931
                                                  else
932 2 buenos
                                                         bram_rxtlp_we <= "0";
933 3 buenos
                                                         rxstm_readytoroll <= '0';
934 2 buenos
                                                  end if;
935
 
936
                --********** read STATE ********** 
937
                when "00000001" =>   --state 1
938 3 buenos
                                                  rxstm_readytoroll <= '0';
939 2 buenos
                                                  if (trn_reof_n ='0') then --last dw
940
                                                    epif_rx_state <= "00000010"; --for the next clk cycle
941 3 buenos
                                                         trn_rdst_rdy_n <= '1'; --ok, dont send more yet
942 2 buenos
                                                  end if;
943
                                                  if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
944
                                                          trn_rx_counter <= trn_rx_counter +1;
945
                                                          bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
946
                                                          bram_rxtlp_writedata  <= trn_rd;
947
                                                  end if;
948
                                                  --in an early stage of this transfer, the scheduler can already
949
                                                  --start working on the data, this way its pipelined, so the latency is lower.
950
                                                  if (trn_rx_counter = "00000010") then
951
                                                   pcie_just_received_a_new_tlp <= '1';--assert for one clk only
952
                                                  else
953
                                                   pcie_just_received_a_new_tlp <= '0';
954
                                                  end if;
955
 
956
                --********** finished filling up RX TLP STATE **********                                 
957
                when "00000010" =>   --state 2
958
                                                  epif_rx_state <= "00000000";
959
                                                  trn_rx_counter <= (OTHERS => '0');
960
 
961
                when others => --error
962
                      epif_rx_state <= "00000000"; --go to state 0
963
                end case;
964
       end if;
965
    end if;
966
    end process;
967
 
968
         --fixed connections:
969
         --trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
970
         --not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
971
 
972 4 buenos
        --RX detection flip-flop
973
        process (pciewb_localreset_n, trn_clk)
974
        begin
975
        if (pciewb_localreset_n='0') then
976
                pcierx_detected <= '0';
977
        else
978
                if (trn_clk'event and trn_clk = '1') then
979
                        if (pcie_just_received_a_new_tlp ='1') then
980
                          pcierx_detected <= '1';
981
                        elsif (pcierx_detect_ff_clear ='1') then
982
                          pcierx_detected <= '0';
983
                        end if;
984
                end if;
985
        end if;
986
        end process;
987
 
988 2 buenos
 
989
 
990
 
991
        -- flow control: INTERFACE TO THE PCIE-EP: - ----
992
        --not used. pcie-ep provides information about credit status.
993
        --unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
994
        trn_fc_sel <= "000";
995
 
996
 
997
 
998
 
999
 
1000 4 buenos
 
1001 2 buenos
        -- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
1002
        -- --- ALSO TLP PACKET PROCESSING.
1003
        --Theory of operation:
1004
        --RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle), 
1005
        --then store it (pcie_received_tlp), decode it (to figure out if its read request, 
1006
        --posted write or non-supported request), then assert a flag (start_write_wb0 or 
1007
        --start_read_wb0)to initiate a wishbone cycle.
1008
        --TX: At the completion of a wishbone read, the wishbone statemachine asserts the 
1009
        --wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp) 
1010
        --and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be 
1011
        --a read completion packet on the PCIe link.
1012
        --
1013
        --This core can handle 1...8 DWORD accesses in one request (max 256bit payload ), 
1014
        --and can handle only one request at a time. If a new request is arriving while
1015
        --processing the previous one (e.g. getting the data from a wishbone read), then 
1016
        --the state machine will not process it immediately, or it will hang. So the user 
1017
        --software has to wait for the previous read completion before issueing a new request.
1018
        --The multiple DWORDs are handled separately by the WB statemachine.
1019
   --Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
1020
        --
1021
        --TLP decoding: 
1022
        --Header+Payload_data+TLP_DIGEST(ECRC). 
1023
        --received Header:
1024
        --First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data, 
1025
        --10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory 
1026
        --read requests, 00000 or 00001 are memory write request if type=1x. read request 
1027
        --completion is 01010 and type=10. bit.9:0 is payload size [DW]. 
1028
        --Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is 
1029
        --byte enable for last dword data. intermediate dwords have all bytes enabled.
1030
        --Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
1031
        --uses 3rd-dword for addre63:32, 4th dword for addr31:0.
1032
        --
1033
        --The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
1034
        --
1035
        --Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
1036
        --The core has to store the requester ID and feed it back in the completion packet.
1037
        --Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
1038
        --count is N.of bytes left. lower_address is the first enabled byte of data returned 
1039
        --with the Completion.
1040
        --
1041
        --  Completion packet header:
1042
        --DW1 >
1043
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1044
        --r FMT type----- r TC--- reserv- T E att r r lenght-------------
1045
        --  x 0                           D P rib
1046
        --DW2 >
1047
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1048
        --COMPLETER_ID------------------- statu B byte_count-------------
1049
        --                                      CM
1050
        --DW3 >
1051
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1052
        --REQUESTER_ID------------------- tag------------ r lower_address
1053
 
1054
 
1055
         --TLP-protocol statemachine:
1056
    process (pciewb_localreset_n, trn_clk, tlp_state,
1057 4 buenos
                                pcierx_detected, tlp_datacount,
1058 2 buenos
                                bram_rxtlp_readdata,  bram_txtlp_writeaddress, bram_rxtlp_readaddress,
1059
                                tlp_state_copy, rxtlp_decodedaddress,
1060
                                rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
1061
                                bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
1062
                                tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
1063
                                rxtlp_requesterid)
1064
    begin
1065
    if (pciewb_localreset_n='0') then
1066
                start_read_wb0 <= '0';
1067
                start_write_wb0 <= '0';
1068
                pcie_bar0_wb_data_o_feed         <= (others => '0');
1069
                pcie_bar0_wb_addr_o_feed <= (others => '0');
1070
                pcie_bar0_wb_sel_o_feed  <= (others => '0');
1071
                pcie_there_is_a_new_tlp_to_transmit  <= '0';
1072
                rxtlp_decodedaddress<= (others => '0');
1073
                tlp_payloadsize_dwords <= (others => '0');
1074
                rxtlp_firstdw_be <= (others => '0');
1075
                rxtlp_lastdw_be <= (others => '0');
1076
                rxtlp_requesterid <= (others => '0');
1077
                tlp_state <= (others => '0');
1078
                tlp_state_copy  <= (others => '0');
1079
                bram_txtlp_we <= "0";
1080
                bram_txtlp_writeaddress    <= (others => '0');
1081
                bram_txtlp_writedata     <= (others => '0');
1082
                bram_rxtlp_readaddress   <= (others => '0');
1083
                rxtlp_header_dw1   <= "01111111000000000000000000000000";
1084
                rxtlp_header_dw2   <= (others => '0');
1085
                rxtlp_header_dw3   <= (others => '0');
1086
                rxtlp_header_dw4   <= (others => '0');
1087
                flag1 <= '0';
1088
                rxdw1_23_0 <= (others => '0');
1089
                pcie_rxtlp_tag <= (others => '0');
1090
                rcompl_bytecount_field  <= (others => '0');
1091 3 buenos
                tlpstm_isin_idle <= '1';
1092 4 buenos
                pcierx_detect_ff_clear <= '0';
1093 2 buenos
    else
1094
      if (trn_clk'event and trn_clk = '1') then
1095
                case ( tlp_state ) is
1096
 
1097
                --********** IDLE STATE  **********
1098
                                         --also re-initialize signals...
1099
                when "00000000" =>   --state 0        
1100 4 buenos
                    if (pcierx_detected='1') then
1101 2 buenos
                                                    tlp_state <= "00000001"; --to tlp decoding state
1102 3 buenos
                                                         tlpstm_isin_idle <= '0';
1103
                                                  else
1104
                                                    tlpstm_isin_idle <= '1';
1105 2 buenos
                                                  end if;
1106
                                                  start_write_wb0 <= '0';
1107
                                                  start_read_wb0 <= '0';
1108
                                                  tlp_state_copy <= tlp_state;
1109
                                                        bram_txtlp_we <= "0";
1110
                                                        bram_txtlp_writeaddress   <= (others => '0');
1111
                                                        bram_txtlp_writedata     <= (others => '0');
1112
                                                        bram_rxtlp_readaddress    <= (others => '0');
1113
                                                        tlp_datacount <= "00000001";
1114
                                                        rxtlp_header_dw1   <= "01111111000000000000000000000000"; --this is to prevent false decode
1115
                                                        pcie_bar0_wb_data_o_feed         <= (others => '0');
1116
                                                        pcie_bar0_wb_addr_o_feed <= (others => '0');
1117
                                                        pcie_bar0_wb_sel_o_feed  <= (others => '0');
1118
                                                        rxtlp_header_dw2   <= (others => '0');
1119
                                                        rxtlp_header_dw3   <= (others => '0');
1120
                                                        rxtlp_header_dw4   <= (others => '0');
1121
                                                        rxdw1_23_0 <= (others => '0');
1122
                                                        pcie_rxtlp_tag <= (others => '0');
1123
                                                        pcie_there_is_a_new_tlp_to_transmit  <= '0';
1124
                                                        rxtlp_decodedaddress<= (others => '0');
1125
                                                        tlp_payloadsize_dwords <= (others => '0');
1126
                                                        rxtlp_firstdw_be <= (others => '0');
1127
                                                        rxtlp_lastdw_be <= (others => '0');
1128
                                                        rxtlp_requesterid <= (others => '0');
1129
                                                        rcompl_bytecount_field  <= (others => '0');
1130 4 buenos
                                                        pcierx_detect_ff_clear <= '0';
1131 2 buenos
 
1132
 
1133
                --********** TLP ARRIVED STATE **********
1134
                                         --read TLP out of EP, decode and decide,
1135
                                         --latch address/sel/wr_data
1136
                                         --All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
1137
                                         --Added an ectra clock delay, based on testing, since the data is one more CLK late.
1138
                when "00000001" =>   --state 1
1139
                    --latch the header:
1140
                                                  bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1141
                                                  if (bram_rxtlp_readaddress = "000000010") then
1142
                                                    rxtlp_header_dw1 <= bram_rxtlp_readdata;
1143 4 buenos
                                                         pcierx_detect_ff_clear <= '1';
1144 2 buenos
                                                  elsif (bram_rxtlp_readaddress = "000000011") then
1145
                                                    rxtlp_header_dw2 <= bram_rxtlp_readdata;
1146
                                                  elsif (bram_rxtlp_readaddress = "000000100") then
1147
                                                    rxtlp_header_dw3 <= bram_rxtlp_readdata;
1148 4 buenos
                                                         pcierx_detect_ff_clear <= '0';
1149 2 buenos
                                                  elsif (bram_rxtlp_readaddress = "000000101") then
1150
                                                    rxtlp_header_dw4 <= bram_rxtlp_readdata;
1151
                                                  end if;
1152
                                                  --decode some parameters: 
1153
                                                  tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
1154
                                                  rxtlp_firstdw_be <= rxtlp_header_dw2(3 downto 0);
1155
                                                  rxtlp_lastdw_be <= rxtlp_header_dw2(7 downto 4);
1156
                                                  rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
1157
                                                  flag1 <= rxtlp_header_dw1(31);
1158
                                                  rxdw1_23_0 <= rxtlp_header_dw1(23 downto 0); --various fields pcie_received_tlp (22 downto 0);
1159
                                                  pcie_rxtlp_tag <= rxtlp_header_dw2(15 downto 8) ; --pcie_received_tlp (47 downto 40);--tag
1160
                                                  --decide based on header:
1161
                                                  if (rxtlp_header_dw1(30 downto 24)="0000000") then --32bit read
1162
                                                         if (bram_rxtlp_readaddress = "000000100") then
1163
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1164
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1165
                                                                tlp_state <= "00000011";
1166
                                                         end if;
1167
                                                  elsif (rxtlp_header_dw1(30 downto 24)="0100000") then --64bit read
1168
                                                         if (bram_rxtlp_readaddress = "000000101") then
1169
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1170
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1171
                                                                tlp_state <= "00000011";
1172
                                                         end if;
1173
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1000000") then --32bit write
1174
                                                         if (bram_rxtlp_readaddress = "000000100") then
1175
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1176
                                                                tlp_state <= "00000010";
1177
                                                         end if;
1178
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1100000") then --64bit write
1179
                                                         if (bram_rxtlp_readaddress = "000000101") then
1180
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1181
                                                                tlp_state <= "00000010";
1182
                                                         end if;
1183
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1111111") then --just wait until this gets a real value
1184
                                                    rxtlp_decodedaddress <= bram_rxtlp_readdata;
1185
                                                  else --unsupported request
1186
                                                    if (bram_rxtlp_readaddress = "000000100") then
1187
                                                           tlp_state <= "00000101";
1188
                                                                bram_txtlp_writeaddress <= "111111111";
1189
                                                         end if;
1190
                                                  end if;
1191
 
1192
 
1193
                --********** WRITE STATE **********
1194
                                         --initiate WB write(s) (1...N DWORD accesses)
1195
                when "00000010" =>   --state 2
1196
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
1197
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1198
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1199
                                                pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
1200
                                                tlp_state_copy <= tlp_state;
1201
                                                if (tlp_state_copy = tlp_state) then
1202
                                                  start_write_wb0 <= '0';
1203
                                                else --generate just one pulse, at the first clk cycle in this state
1204
                                                  start_write_wb0 <= '1';
1205
                                                end if;
1206
                                                if (wb_transaction_complete='1') then --one DW transfer completed
1207
 
1208
                                                        if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
1209
                                                          tlp_state <= "00000000"; --to idle
1210
                                                        else
1211
                                                          tlp_state <= "00010100"; --restart wb transaction with new data
1212
                                                          bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1213
                                                          tlp_datacount <= tlp_datacount +1;
1214
                                                        end if;
1215
                                                end if;
1216
                --* Write restart state *
1217
                when "00010100" =>   --state 20
1218
                                                tlp_state <= "00000010";
1219 4 buenos
                                                tlp_state_copy <= tlp_state;
1220 2 buenos
 
1221
 
1222
                --********** READ STATE **********
1223
                                         --initiate WB read, then go to completion state
1224
                when "00000011" =>   --state 3
1225
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
1226
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1227
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1228
                                                tlp_state_copy <= tlp_state;
1229
                                                if (tlp_state_copy = tlp_state) then
1230
                                                  start_read_wb0 <= '0';
1231
                                                else --generate just one pulse
1232
                                                  start_read_wb0 <= '1';
1233
                                                end if;
1234
                                                if (wb_transaction_complete='1') then
1235
                                                        bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
1236
                                                        bram_txtlp_we <= "1";
1237
                                                        if (tlp_payloadsize_dwords = tlp_datacount)then
1238
                                                          tlp_state <= "01111110"; --read completion
1239
                                                          --bram_txtlp_writeaddress remains the same to capture data in next clock cycle
1240
                                                        else
1241
                                                          tlp_state <= "00011110"; --one more wb read
1242
                                                          bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1243
                                                          tlp_datacount <= tlp_datacount +1;
1244
                                                        end if;
1245
                                                else
1246
                                                  bram_txtlp_we <= "0";
1247
                                                end if;
1248
                --* read restart STATE  *
1249
                when "00011110" =>   --state 30
1250
                                                tlp_state <= "00000011";
1251
                                                bram_txtlp_we <= "0";
1252 4 buenos
                                                tlp_state_copy <= tlp_state;
1253 2 buenos
                --intermediate state before completion (to ensure data latch at address-4)
1254
                                         when "01111110" =>   --state 126
1255
                                                tlp_state <= "00000100";
1256 4 buenos
                                                tlp_state_copy <= tlp_state;
1257 2 buenos
                                                bram_txtlp_writeaddress  <=  (OTHERS => '0');
1258
                                                --pre-write header-DW1:
1259
                                                bram_txtlp_writedata (31) <= flag1; --reserved
1260
                                                bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1261
                                                bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1262
                                                --Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
1263
                                                if (rxtlp_lastdw_be="0000") then  --max 1DW
1264
                                                  if (rxtlp_firstdw_be="1111") then --4bytes
1265
                                                    rcompl_bytecount_field <= "0000000100";
1266
                                                  elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
1267
                                                    rcompl_bytecount_field <= "0000000011";
1268
                                                  elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
1269
                                                    rcompl_bytecount_field <= "0000000010";
1270
                                                  else
1271
                                                    rcompl_bytecount_field <= "0000000001";
1272
                                                  end if;
1273
                                                else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
1274
                                                  rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
1275
                                                  rcompl_bytecount_field(1 downto 0) <= "00";
1276
                                                end if;
1277
 
1278
 
1279
                --********** READ COMPLETION STATE **********
1280
                                         --assemble the tx TLP and initiate the transmit
1281
                                         --buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
1282
                when "00000100" =>   --state 4
1283
                    tlp_state_copy <= tlp_state;
1284
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1285
                                                  if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
1286
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1287
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
1288
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1289
                                                          bram_txtlp_writedata (11 downto 10) <= "00";
1290
                                                          bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
1291
                                                          bram_txtlp_we <= "1";
1292
                                                  elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
1293
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1294
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1295
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1296
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1297
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1298
                                                  else --data dwords, disable writes from next clock cycle
1299
                                                    bram_txtlp_we <= "0";
1300
                                                  end if;
1301
                                                  --one pulse to start the ep-if statemachine, upon arriving to this state
1302
                                                        if (tlp_state_copy = tlp_state) then
1303
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1304
                                                        else
1305
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1306
                                                        end if;
1307
                                                        --back to idle when the ep-if tx is finished: (wait to avoid overwrite)
1308
                                                        if (pcie_tlp_tx_complete='1') then
1309
                                                                tlp_state <= "00000000";
1310
                                                        end if;
1311
 
1312
 
1313
                --********** UNSUPPORTED REQUEST STATE **********
1314
                                         --completion response with status=001
1315
                when "00000101" =>   --state 5
1316
                    tlp_state_copy <= tlp_state;
1317
                                                  tlp_payloadsize_dwords <= "00000000";
1318 3 buenos
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1319 2 buenos
                                                  --assembling the TLP packet:           )
1320
                                                  if (bram_txtlp_writeaddress="111111111") then --header 1.dw
1321
                                                    bram_txtlp_we <= "1";
1322
                                                          bram_txtlp_writedata (31) <= flag1; --reserved
1323
                                                          bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1324
                                                          bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1325
                                                  elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
1326
                                                    bram_txtlp_we <= "1";
1327
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1328
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
1329
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1330
                                                          bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
1331
                                                  elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
1332
                                                    bram_txtlp_we <= "1";
1333
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1334
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1335
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1336
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1337
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1338
                                                  else --data dwords 
1339
                                                    bram_txtlp_we <= "0";
1340
                                                  end if;
1341
                                                        --one pulse to start the ep-if statemachine, upon arriving to this state
1342
                                                        if (tlp_state_copy = tlp_state) then
1343
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1344
                                                        else
1345
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1346
                                                        end if;
1347
                                                        --back to idle when finished:
1348
                                                        if (pcie_tlp_tx_complete='1') then
1349
                                                                tlp_state <= "00000000";
1350
                                                        end if;
1351
 
1352
                when others => --error
1353
                      tlp_state <= "00000000"; --go to state 0
1354
                end case;
1355
 
1356
       end if;
1357
    end if;
1358
    end process; --end tlp statemachine
1359
 
1360
 
1361
 
1362
 
1363
        --byte enable encoding to wb_address bit1:0
1364 3 buenos
        --this does not swap the endian, since only the data is swapped in the pcie packets.
1365
         process ( pciewb_localreset_n, rxtlp_firstdw_be )
1366
    begin
1367
       if (pciewb_localreset_n = '0') then
1368
           bit10(1 downto 0) <="00";
1369
       else
1370
         if (rxtlp_firstdw_be ="0001") then
1371
                          bit10(1 downto 0) <= "00";
1372
         elsif (rxtlp_firstdw_be ="0010") then
1373
                          bit10(1 downto 0) <= "01";
1374
         elsif (rxtlp_firstdw_be ="0100") then
1375
                          bit10(1 downto 0) <= "10";
1376
         elsif (rxtlp_firstdw_be ="1000") then
1377
                          bit10(1 downto 0) <= "11";
1378
         elsif (rxtlp_firstdw_be ="0011") then
1379
                          bit10(1 downto 0) <= "00";
1380
         elsif (rxtlp_firstdw_be ="1100") then
1381
                          bit10(1 downto 0) <= "10";
1382
         elsif (rxtlp_firstdw_be ="1111") then
1383
                          bit10(1 downto 0) <= "00";
1384
                        else --this should never happen
1385
                          bit10(1 downto 0) <= "00";
1386
                        end if;
1387
       end if;
1388 2 buenos
    end process;
1389
 
1390
 
1391
 
1392
 
1393
 
1394
        -- INTERRUPTS: -------------------------------------------------------------------------
1395
        --to assert an interrupt, use the cfg_interrupt_assert_n pin.
1396
        --datasheet text:
1397
        --As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
1398
        --cfg_interrupt_assert_n to assert the interrupt. The user application should select a
1399
        --specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
1400
        --in Table 6-19.
1401
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
1402
        --On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
1403
        --Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
1404
        --interrupt message (Assert_INTA, Assert_INTB, and so forth).
1405
        -- After the user application has determined that the interrupt has been serviced, it
1406
        --asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
1407
        --interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
1408
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
1409
        --been accepted. On the following clock cycle, the user application deasserts
1410
        --cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
1411
        --Deassert_INTB, and so forth).
1412
        --cfg_interrupt_di[7:0] value Legacy Interrupt
1413
        --00h INTA
1414
        --01h INTB
1415
        --02h INTC
1416
        --03h INTD 
1417
 
1418
        cfg_interrupt_di    <= "00000000"; --intA used
1419
 
1420
    process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
1421
                                cfg_interrupt_rdy_n)
1422
    begin
1423
    if (pciewb_localreset_n='0') then
1424
       pcieirq_state <= "00000000";
1425
       cfg_interrupt_n <= '1';
1426
                 cfg_interrupt_assert_n_1 <= '1';
1427
    else
1428
      if (trn_clk'event and trn_clk = '1') then
1429
                case ( pcieirq_state ) is
1430
 
1431
                --********** idle STATE  **********
1432
                when "00000000" =>   --state 0        
1433
                    if (pcie_irq = '1') then
1434
                                                    pcieirq_state <= "00000001";
1435
                                                         cfg_interrupt_n <= '0'; --active
1436
                                                  else
1437
                                                    cfg_interrupt_n <= '1'; --inactive
1438
                                                  end if;
1439
                                                  cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
1440
 
1441
                --********** assert STATE ********** 
1442
                when "00000001" =>   --state 1
1443
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1444
                                                         cfg_interrupt_n <= '1'; --deassert the request 
1445
                                                         pcieirq_state <= "00000010";
1446
                                                 else
1447
                                                         cfg_interrupt_n <= '0'; --request INTA assertion
1448
                                                 end if;
1449
 
1450
                --********** pcie_irq kept asserted STATE **********                                     
1451
                when "00000010" =>   --state 2
1452
                    if (pcie_irq = '0') then --pcie_irq gets deasserted
1453
                                                    pcieirq_state <= "00000011";
1454
                                                  end if;
1455
                                                 cfg_interrupt_n <= '1'; --inactive     
1456
                                                 cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
1457
 
1458
                --********** DEassert STATE ********** 
1459
                when "00000011" =>   --state 3
1460
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1461
                                                         cfg_interrupt_n <= '1'; --deassert the request 
1462
                                                         pcieirq_state <= "00000000";
1463
                                                 else
1464
                                                         cfg_interrupt_n <= '0'; --request INTA DEassertion
1465
                                                 end if;
1466
 
1467
                                                 when others => --error
1468
                      pcieirq_state <= "00000000"; --go to state 0
1469
                end case;
1470
       end if;
1471
    end if;
1472
    end process;
1473
 
1474
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
1475
        cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
1476
 
1477
 
1478
 
1479
 
1480
 
1481
 
1482
-- -------- END OF FILE -------------------------------------------------------------------------------------
1483
end Behavioral;
1484
 
1485
 

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