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barabba |
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-- Company: ziti
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-- Engineer: wgao
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--
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-- Create Date: 17:01:32 19 Jun 2009
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-- Design Name:
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-- Module Name: class_daq - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity class_daq is
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-- Generic (
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-- C_PRO_DAQ_WIDTH : integer := 16 ;
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-- C_PRO_DLM_WIDTH : integer := 4 ;
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-- C_PRO_CTL_WIDTH : integer := 16
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-- );
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Port (
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-- DAQ Tx
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data2send_start : OUT std_logic;
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data2send_end : OUT std_logic;
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data2send : OUT std_logic_vector(64-1 downto 0);
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crc_error_send : OUT std_logic;
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data2send_stop : IN std_logic;
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-- DAQ Rx
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data_rec_start : IN std_logic;
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data_rec_end : IN std_logic;
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data_rec : IN std_logic_vector(64-1 downto 0);
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crc_error_rec : IN std_logic;
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data_rec_stop : OUT std_logic;
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-- Common signals
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link_tx_clk : IN std_logic;
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link_rx_clk : IN std_logic;
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-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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-- Fabric side: DAQ Rx
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daq_rv : IN std_logic;
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daq_rsof : IN std_logic;
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daq_reof : IN std_logic;
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daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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daq_rstop : OUT std_logic;
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-- Fabric side: DAQ Tx
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daq_tv : OUT std_logic;
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daq_tsof : OUT std_logic;
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daq_teof : OUT std_logic;
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daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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daq_tstop : IN std_logic;
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-- Interrupter trigger
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DAQ_irq : OUT std_logic;
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-- Fabric side: Common signals
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trn_clk : IN std_logic;
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protocol_rst : IN std_logic
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);
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end entity class_daq;
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architecture Behavioral of class_daq is
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-- Standard synchronous FIFO
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component sfifo_1024x72
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port (
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(72-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(72-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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clk : IN std_logic;
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rst : IN std_logic
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);
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end component;
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-- Standard asynchronous FIFO
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component v6_afifo_1024x72
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port (
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wr_clk : IN std_logic;
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(72-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_clk : IN std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(72-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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rst : IN std_logic
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);
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end component;
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-- Standard synchronous FIFO
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component sfifo_256x18
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port (
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(18-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(18-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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clk : IN std_logic;
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rst : IN std_logic
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);
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end component;
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-- Interrupter trigger
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signal DAQ_irq_i : std_logic;
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-- Fabric side: DAQ Tx
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signal daq_tv_i : std_logic;
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signal daq_tsof_i : std_logic;
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signal daq_tsof_vector : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);
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signal daq_teof_i : std_logic;
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signal daq_teof_vector : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);
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signal daq_td_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal daq_rstop_i : std_logic;
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signal daq_up_is_writing : std_logic;
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signal daq_up_is_writing_r1 : std_logic;
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signal Tout_Cnt_daq_up_wr : std_logic_vector(8-1 downto 0);
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-- protocol side: DAQ Send
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signal data2send_start_i : std_logic;
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signal data2send_end_i : std_logic;
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signal data2send_i : std_logic_vector(64-1 downto 0);
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signal crc_error_send_i : std_logic;
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signal data_rec_start_r1 : std_logic;
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signal data_rec_end_r1 : std_logic;
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signal data_rec_end_r2 : std_logic;
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signal data_rec_r1 : std_logic_vector(64-1 downto 0);
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signal data_rec_stop_i : std_logic;
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signal data_rec_stop_r1 : std_logic;
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signal data_rec_stop_r2 : std_logic;
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signal data_rec_stop_r3 : std_logic;
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signal data_rec_stop_r4 : std_logic;
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signal daq_rd_padded : std_logic_vector(72-1 downto 0);
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signal daq_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- DAQ packet number counting up
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signal pkt_number_DAQ_down : std_logic_vector(8-1 downto 0);
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signal daq_down_buf_rden : std_logic;
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signal daq_down_buf_eop : std_logic;
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signal daq_down_buf_sop : std_logic;
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signal daq_down_buf_eop_r1 : std_logic;
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signal daq_down_split_rden : std_logic;
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signal daq_down_buf_read_gap : std_logic;
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signal daq_down_buf_stop_read: std_logic;
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signal daq_down_buf_dout : std_logic_vector(72-1 downto 0);
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signal daq_down_buf_empty : std_logic;
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signal daq_down_buf_rd_valid : std_logic;
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signal noPkt_in_daq_down_buf : std_logic;
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signal daq_up_buf_we : std_logic;
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signal daq_up_buf_din : std_logic_vector(72-1 downto 0);
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signal daq_up_buf_afull : std_logic;
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signal daq_up_buf_afull_r1 : std_logic;
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signal daq_up_buf_re : std_logic;
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signal daq_up_buf_rd_valid : std_logic;
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signal daq_up_buf_dout : std_logic_vector(72-1 downto 0);
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signal daq_up_buf_pempty : std_logic;
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signal daq_up_buf_empty : std_logic;
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signal daq_up_eop : std_logic;
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signal daq_up_eop_r1 : std_logic;
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begin
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-- Fabric side: DAQ Tx
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daq_tv <= daq_tv_i;
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daq_tsof <= daq_tsof_i and daq_tv_i;
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daq_teof <= daq_teof_i and daq_tv_i;
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daq_td <= daq_td_i when daq_tv_i='1' else (OTHERS=>'0');
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daq_rstop <= daq_rstop_i ;
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DAQ_irq <= DAQ_irq_i ;
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DAQ_irq_i <= '0'; -- ?
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-- protocol side: DAQ Send
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data2send_start <= data2send_start_i ;
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data2send_end <= data2send_end_i ;
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data2send <= data2send_i ;
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crc_error_send <= crc_error_send_i ;
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data_rec_stop <= data_rec_stop_i ;
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data_rec_stop_i <= daq_up_buf_afull_r1 ;
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daq_up_eop <= daq_up_buf_dout(16) ;
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--
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DAQ_upstream_Read_Gap:
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process (trn_clk)
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begin
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if trn_clk'event and trn_clk = '1' then
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daq_up_eop_r1 <= daq_up_eop;
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end if;
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end process;
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Syn_delay_daq_up_buf_afull:
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process (link_rx_clk)
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begin
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if link_rx_clk'event and link_rx_clk = '1' then
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daq_up_buf_afull_r1 <= daq_up_buf_afull;
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data_rec_stop_r1 <= data_rec_stop_i;
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data_rec_stop_r2 <= data_rec_stop_r1;
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data_rec_stop_r3 <= data_rec_stop_r2;
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data_rec_stop_r4 <= data_rec_stop_r3;
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end if;
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end process;
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-- DAQ direction: upstream
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-- protocol side
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--
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Transfer_DAQ_upstream_protocol:
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process (link_rx_clk, protocol_rst )
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begin
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if protocol_rst = '1' then
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daq_up_is_writing <= '0';
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Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
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elsif link_rx_clk'event and link_rx_clk = '1' then
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if daq_up_is_writing='0' then
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if data_rec_start='1' and data_rec_start_r1='0' then
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daq_up_is_writing <= '1';
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Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
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else
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daq_up_is_writing <= '0';
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Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
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end if;
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else
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if data_rec_end_r1='1' and data_rec_end_r2='0' then
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daq_up_is_writing <= '0';
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Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
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elsif Tout_Cnt_daq_up_wr(6)='1' then
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daq_up_is_writing <= '0';
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Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr;
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else
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daq_up_is_writing <= '1';
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Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr + '1';
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end if;
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end if;
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end if;
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end process;
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-- Transfer_DAQ_upstream_protocol:
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-- process (link_rx_clk, protocol_rst )
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-- begin
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-- if protocol_rst = '1' then
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-- daq_up_is_writing <= '0';
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-- daq_up_is_writing_r1 <= '0';
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--
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-- elsif link_rx_clk'event and link_rx_clk = '1' then
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-- if data_rec_start='1' and data_rec_end='1' then
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-- daq_up_is_writing <= '0';
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-- daq_up_is_writing_r1 <= not data_rec_stop_i or not data_rec_stop_r1
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-- or not data_rec_stop_r2 or not data_rec_stop_r3
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-- or not data_rec_stop_r4
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-- ;
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-- elsif data_rec_start='1' then
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-- daq_up_is_writing <= not data_rec_stop_i or not data_rec_stop_r1
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-- or not data_rec_stop_r2 or not data_rec_stop_r3
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-- or not data_rec_stop_r4
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-- ;
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-- daq_up_is_writing_r1 <= daq_up_is_writing;
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-- elsif data_rec_end='1' then
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-- daq_up_is_writing <= '0';
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-- daq_up_is_writing_r1 <= daq_up_is_writing;
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-- else
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-- daq_up_is_writing <= daq_up_is_writing;
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-- daq_up_is_writing_r1 <= daq_up_is_writing;
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-- end if;
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--
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-- end if;
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-- end process;
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-- direction: upstream
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Transfer_DAQ_upstream_link:
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process (link_rx_clk, protocol_rst )
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begin
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if protocol_rst = '1' then
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data_rec_start_r1 <= '0';
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data_rec_end_r1 <= '0';
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data_rec_end_r2 <= '0';
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data_rec_r1 <= (OTHERS=>'0');
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daq_up_buf_we <= '0';
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daq_up_buf_din <= (OTHERS=>'0');
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elsif link_rx_clk'event and link_rx_clk = '1' then
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data_rec_start_r1 <= data_rec_start;
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data_rec_end_r1 <= data_rec_end;
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data_rec_end_r2 <= data_rec_end_r1;
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data_rec_r1 <= data_rec;
|
337 |
|
|
daq_up_buf_we <= daq_up_is_writing; --(daq_up_is_writing or daq_up_is_writing_r1);
|
338 |
|
|
daq_up_buf_din <= "000000" & data_rec_start_r1 & data_rec_end_r1 & data_rec_r1;
|
339 |
|
|
|
340 |
|
|
end if;
|
341 |
|
|
end process;
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
-- ------------------------------------------------------------------------------
|
345 |
|
|
-- DAQ buffer to the host
|
346 |
|
|
-- ------------------------------------------------------------------------------
|
347 |
|
|
daq_buf_upstream:
|
348 |
|
|
v6_afifo_1024x72
|
349 |
|
|
port map (
|
350 |
|
|
wr_clk => link_rx_clk , -- IN std_logic;
|
351 |
|
|
wr_en => daq_up_buf_we , -- IN std_logic;
|
352 |
|
|
din => daq_up_buf_din , -- IN std_logic_VECTOR(17 downto 0);
|
353 |
|
|
prog_full => daq_up_buf_afull , -- OUT std_logic;
|
354 |
|
|
full => open , -- OUT std_logic;
|
355 |
|
|
|
356 |
|
|
rd_clk => trn_clk , -- IN std_logic;
|
357 |
|
|
rd_en => daq_up_buf_re , -- IN std_logic;
|
358 |
|
|
dout => daq_up_buf_dout , -- OUT std_logic_VECTOR(17 downto 0);
|
359 |
|
|
prog_empty => daq_up_buf_pempty , -- OUT std_logic;
|
360 |
|
|
empty => daq_up_buf_empty , -- OUT std_logic;
|
361 |
|
|
|
362 |
|
|
rst => protocol_rst -- IN std_logic
|
363 |
|
|
);
|
364 |
|
|
|
365 |
|
|
-- upstream: merging ...
|
366 |
|
|
Transfer_DAQ_upstream_merge:
|
367 |
|
|
process (trn_clk, protocol_rst )
|
368 |
|
|
begin
|
369 |
|
|
if protocol_rst = '1' then
|
370 |
|
|
daq_up_buf_re <= '0';
|
371 |
|
|
daq_up_buf_rd_valid <= '0';
|
372 |
|
|
daq_tv_i <= '0';
|
373 |
|
|
daq_tsof_i <= '0';
|
374 |
|
|
daq_teof_i <= '0';
|
375 |
|
|
daq_td_i <= (OTHERS=>'0');
|
376 |
|
|
|
377 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
378 |
|
|
daq_up_buf_re <= not daq_tstop;
|
379 |
|
|
daq_up_buf_rd_valid <= daq_up_buf_re and not daq_up_buf_empty;
|
380 |
|
|
daq_tv_i <= daq_up_buf_rd_valid;
|
381 |
|
|
daq_tsof_i <= daq_up_buf_dout(65);
|
382 |
|
|
daq_teof_i <= daq_up_buf_dout(64);
|
383 |
|
|
daq_td_i <= daq_up_buf_dout(64-1 downto 0);
|
384 |
|
|
|
385 |
|
|
end if;
|
386 |
|
|
end process;
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
-- ------------------------------------------------------------------------------
|
390 |
|
|
-- DAQ buffer from the host
|
391 |
|
|
-- ------------------------------------------------------------------------------
|
392 |
|
|
daq_buf_downstream:
|
393 |
|
|
v6_afifo_1024x72
|
394 |
|
|
port map (
|
395 |
|
|
wr_clk => trn_clk , -- IN std_logic;
|
396 |
|
|
wr_en => daq_rv , -- IN std_logic;
|
397 |
|
|
din => daq_rd_padded , -- IN std_logic_VECTOR(71 downto 0);
|
398 |
|
|
prog_full => daq_rstop_i , -- OUT std_logic;
|
399 |
|
|
full => open , -- OUT std_logic;
|
400 |
|
|
|
401 |
|
|
rd_clk => link_tx_clk , -- IN std_logic;
|
402 |
|
|
rd_en => daq_down_buf_rden , -- IN std_logic;
|
403 |
|
|
dout => daq_down_buf_dout , -- OUT std_logic_VECTOR(71 downto 0);
|
404 |
|
|
prog_empty => open , -- OUT std_logic;
|
405 |
|
|
empty => daq_down_buf_empty , -- OUT std_logic;
|
406 |
|
|
|
407 |
|
|
rst => protocol_rst -- IN std_logic
|
408 |
|
|
);
|
409 |
|
|
|
410 |
|
|
daq_down_buf_sop <= daq_down_buf_dout(65);
|
411 |
|
|
daq_down_buf_eop <= daq_down_buf_dout(64);
|
412 |
|
|
daq_down_buf_read_gap <= daq_down_buf_eop and not daq_down_buf_eop_r1;
|
413 |
|
|
daq_down_buf_rden <= daq_down_split_rden and not daq_down_buf_read_gap;
|
414 |
|
|
daq_rd_padded <= "000000" & daq_rsof & daq_reof & daq_rd;
|
415 |
|
|
|
416 |
|
|
-- ------------------------------------------------
|
417 |
|
|
Syn_Delay_daq_down_buf_eop:
|
418 |
|
|
process (link_tx_clk)
|
419 |
|
|
begin
|
420 |
|
|
if link_tx_clk'event and link_tx_clk = '1' then
|
421 |
|
|
daq_down_buf_eop_r1 <= daq_down_buf_eop;
|
422 |
|
|
end if;
|
423 |
|
|
end process;
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
---------------------------------------------------
|
427 |
|
|
-- Downstream DAQ buffer read and packets number
|
428 |
|
|
-- bit[71] : mask[3]
|
429 |
|
|
-- bit[70] : mask[2]
|
430 |
|
|
-- bit[69] : mask[1]
|
431 |
|
|
-- bit[68] : mask[0]
|
432 |
|
|
-- bit[67] : (reserved)
|
433 |
|
|
-- bit[66] : crc_error
|
434 |
|
|
-- bit[65] : sof
|
435 |
|
|
-- bit[64] : eof
|
436 |
|
|
--
|
437 |
|
|
Syn_rden_DAQ_downstream_buf:
|
438 |
|
|
process (link_tx_clk, protocol_rst )
|
439 |
|
|
begin
|
440 |
|
|
if protocol_rst = '1' then
|
441 |
|
|
pkt_number_DAQ_down <= (OTHERS=>'0');
|
442 |
|
|
daq_down_split_rden <= '0';
|
443 |
|
|
daq_down_buf_rd_valid <= '0';
|
444 |
|
|
noPkt_in_daq_down_buf <= '1';
|
445 |
|
|
daq_down_buf_stop_read <= '0';
|
446 |
|
|
|
447 |
|
|
elsif link_tx_clk'event and link_tx_clk = '1' then
|
448 |
|
|
|
449 |
|
|
if daq_down_buf_read_gap='1' and data2send_stop='1' then
|
450 |
|
|
daq_down_buf_stop_read <= '1';
|
451 |
|
|
elsif daq_down_buf_stop_read='0' and data2send_stop='1' then
|
452 |
|
|
daq_down_buf_stop_read <= '0';
|
453 |
|
|
else
|
454 |
|
|
daq_down_buf_stop_read <= data2send_stop;
|
455 |
|
|
end if;
|
456 |
|
|
|
457 |
|
|
daq_down_split_rden <= not noPkt_in_daq_down_buf
|
458 |
|
|
-- maximal one read every four cycles
|
459 |
|
|
and not daq_down_buf_read_gap
|
460 |
|
|
and not daq_down_buf_stop_read
|
461 |
|
|
;
|
462 |
|
|
|
463 |
|
|
daq_down_buf_rd_valid <= daq_down_buf_rden and not daq_down_buf_empty;
|
464 |
|
|
|
465 |
|
|
if (daq_rv='1' and daq_rd_padded(64)='1')
|
466 |
|
|
and (daq_down_buf_rd_valid='1' and daq_down_buf_eop='1')
|
467 |
|
|
then
|
468 |
|
|
pkt_number_DAQ_down <= pkt_number_DAQ_down;
|
469 |
|
|
elsif daq_rv='1' and daq_rd_padded(64)='1' then
|
470 |
|
|
pkt_number_DAQ_down <= pkt_number_DAQ_down + '1';
|
471 |
|
|
elsif daq_down_buf_rd_valid='1' and daq_down_buf_eop='1' then
|
472 |
|
|
pkt_number_DAQ_down <= pkt_number_DAQ_down - '1';
|
473 |
|
|
else
|
474 |
|
|
pkt_number_DAQ_down <= pkt_number_DAQ_down;
|
475 |
|
|
end if;
|
476 |
|
|
|
477 |
|
|
if pkt_number_DAQ_down=C_ALL_ZEROS(8-1 downto 0) then
|
478 |
|
|
noPkt_in_daq_down_buf <= '1';
|
479 |
|
|
else
|
480 |
|
|
noPkt_in_daq_down_buf <= '0';
|
481 |
|
|
end if;
|
482 |
|
|
|
483 |
|
|
end if;
|
484 |
|
|
end process;
|
485 |
|
|
|
486 |
|
|
-- ----------------------------------------------
|
487 |
|
|
--
|
488 |
|
|
--
|
489 |
|
|
Syn_data2send_link:
|
490 |
|
|
process (link_tx_clk, protocol_rst )
|
491 |
|
|
begin
|
492 |
|
|
if protocol_rst = '1' then
|
493 |
|
|
data2send_start_i <= '0';
|
494 |
|
|
data2send_end_i <= '0';
|
495 |
|
|
data2send_i <= (OTHERS=>'0');
|
496 |
|
|
crc_error_send_i <= '0';
|
497 |
|
|
elsif link_tx_clk'event and link_tx_clk = '1' then
|
498 |
|
|
if daq_down_buf_rd_valid='1' then
|
499 |
|
|
data2send_start_i <= daq_down_buf_sop;
|
500 |
|
|
data2send_end_i <= daq_down_buf_eop;
|
501 |
|
|
data2send_i <= daq_down_buf_dout(64-1 downto 0);
|
502 |
|
|
else
|
503 |
|
|
data2send_start_i <= '0';
|
504 |
|
|
data2send_end_i <= '0';
|
505 |
|
|
data2send_i <= (OTHERS=>'0');
|
506 |
|
|
end if;
|
507 |
|
|
end if;
|
508 |
|
|
end process;
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
end architecture Behavioral;
|