1 |
11 |
barabba |
##############################################################
|
2 |
|
|
#
|
3 |
|
|
# Xilinx Core Generator version 13.3
|
4 |
|
|
# Date: Mon Mar 05 16:30:39 2012
|
5 |
|
|
#
|
6 |
|
|
##############################################################
|
7 |
|
|
#
|
8 |
|
|
# This file contains the customisation parameters for a
|
9 |
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
10 |
|
|
# that you do not manually alter this file as it may cause
|
11 |
|
|
# unexpected and unsupported behavior.
|
12 |
|
|
#
|
13 |
|
|
##############################################################
|
14 |
|
|
#
|
15 |
|
|
# Generated from component: xilinx.com:ip:v6_pcie:1.6
|
16 |
|
|
#
|
17 |
|
|
##############################################################
|
18 |
|
|
#
|
19 |
|
|
# BEGIN Project Options
|
20 |
|
|
SET addpads = false
|
21 |
|
|
SET asysymbol = true
|
22 |
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
23 |
|
|
SET createndf = false
|
24 |
|
|
SET designentry = VHDL
|
25 |
|
|
SET device = xc6vlx240t
|
26 |
|
|
SET devicefamily = virtex6
|
27 |
|
|
SET flowvendor = Other
|
28 |
|
|
SET formalverification = false
|
29 |
|
|
SET foundationsym = false
|
30 |
|
|
SET implementationfiletype = Ngc
|
31 |
|
|
SET package = ff1156
|
32 |
|
|
SET removerpms = false
|
33 |
|
|
SET simulationfiles = Behavioral
|
34 |
|
|
SET speedgrade = -1
|
35 |
|
|
SET verilogsim = false
|
36 |
|
|
SET vhdlsim = true
|
37 |
|
|
# END Project Options
|
38 |
|
|
# BEGIN Select
|
39 |
|
|
SELECT Virtex-6_Integrated_Block_for_PCI_Express family Xilinx,_Inc. 1.6
|
40 |
|
|
# END Select
|
41 |
|
|
# BEGIN Parameters
|
42 |
|
|
CSET acceptable_l0s_latency=No_limit
|
43 |
|
|
CSET acceptable_l1_latency=No_limit
|
44 |
|
|
CSET ack_nak_timeout_func=Absolute
|
45 |
|
|
CSET ack_nak_timeout_value=0000
|
46 |
|
|
CSET bar0_64bit=false
|
47 |
|
|
CSET bar0_enabled=true
|
48 |
|
|
CSET bar0_prefetchable=false
|
49 |
|
|
CSET bar0_scale=Kilobytes
|
50 |
|
|
CSET bar0_size=64
|
51 |
|
|
CSET bar0_type=Memory
|
52 |
|
|
CSET bar1_64bit=false
|
53 |
|
|
CSET bar1_enabled=true
|
54 |
|
|
CSET bar1_prefetchable=false
|
55 |
|
|
CSET bar1_scale=Megabytes
|
56 |
|
|
CSET bar1_size=1
|
57 |
|
|
CSET bar1_type=Memory
|
58 |
|
|
CSET bar2_64bit=false
|
59 |
|
|
CSET bar2_enabled=true
|
60 |
|
|
CSET bar2_prefetchable=false
|
61 |
|
|
CSET bar2_scale=Kilobytes
|
62 |
|
|
CSET bar2_size=4
|
63 |
|
|
CSET bar2_type=Memory
|
64 |
|
|
CSET bar3_64bit=false
|
65 |
|
|
CSET bar3_enabled=false
|
66 |
|
|
CSET bar3_prefetchable=false
|
67 |
|
|
CSET bar3_scale=Kilobytes
|
68 |
|
|
CSET bar3_size=2
|
69 |
|
|
CSET bar3_type=N/A
|
70 |
|
|
CSET bar4_64bit=false
|
71 |
|
|
CSET bar4_enabled=false
|
72 |
|
|
CSET bar4_prefetchable=false
|
73 |
|
|
CSET bar4_scale=Kilobytes
|
74 |
|
|
CSET bar4_size=2
|
75 |
|
|
CSET bar4_type=N/A
|
76 |
|
|
CSET bar5_enabled=false
|
77 |
|
|
CSET bar5_prefetchable=false
|
78 |
|
|
CSET bar5_scale=Kilobytes
|
79 |
|
|
CSET bar5_size=2
|
80 |
|
|
CSET bar5_type=N/A
|
81 |
|
|
CSET base_class_menu=Simple_communication_controllers
|
82 |
|
|
CSET buf_opt_bma=false
|
83 |
|
|
CSET cardbus_cis_pointer=00000000
|
84 |
|
|
CSET class_code_base=05
|
85 |
|
|
CSET class_code_interface=00
|
86 |
|
|
CSET class_code_sub=00
|
87 |
|
|
CSET component_name=v6_pcie_v1_6
|
88 |
|
|
CSET cost_table=1
|
89 |
|
|
CSET cpl_finite=false
|
90 |
|
|
CSET cpl_timeout_disable_sup=false
|
91 |
|
|
CSET cpl_timeout_range=Range_B
|
92 |
|
|
CSET d0_pme_support=true
|
93 |
|
|
CSET d0_power_consumed=0
|
94 |
|
|
CSET d0_power_consumed_factor=0
|
95 |
|
|
CSET d0_power_dissipated=0
|
96 |
|
|
CSET d0_power_dissipated_factor=0
|
97 |
|
|
CSET d1_pme_support=true
|
98 |
|
|
CSET d1_power_consumed=0
|
99 |
|
|
CSET d1_power_consumed_factor=0
|
100 |
|
|
CSET d1_power_dissipated=0
|
101 |
|
|
CSET d1_power_dissipated_factor=0
|
102 |
|
|
CSET d1_support=false
|
103 |
|
|
CSET d2_pme_support=true
|
104 |
|
|
CSET d2_power_consumed=0
|
105 |
|
|
CSET d2_power_consumed_factor=0
|
106 |
|
|
CSET d2_power_dissipated=0
|
107 |
|
|
CSET d2_power_dissipated_factor=0
|
108 |
|
|
CSET d2_support=false
|
109 |
|
|
CSET d3_power_consumed=0
|
110 |
|
|
CSET d3_power_consumed_factor=0
|
111 |
|
|
CSET d3_power_dissipated=0
|
112 |
|
|
CSET d3_power_dissipated_factor=0
|
113 |
|
|
CSET d3cold_pme_support=false
|
114 |
|
|
CSET d3hot_pme_support=true
|
115 |
|
|
CSET de_emph=0
|
116 |
|
|
CSET device_id=6014
|
117 |
|
|
CSET device_port_type=PCI_Express_Endpoint_device
|
118 |
|
|
CSET device_specific_initialization=false
|
119 |
|
|
CSET disable_tx_aspm_l0s=false
|
120 |
|
|
CSET dll_link_active_cap=false
|
121 |
|
|
CSET downstream_link_num=00
|
122 |
|
|
CSET dsn_enabled=true
|
123 |
|
|
CSET en_route_err_cor=false
|
124 |
|
|
CSET en_route_err_ftl=false
|
125 |
|
|
CSET en_route_err_nfl=false
|
126 |
|
|
CSET en_route_inta=false
|
127 |
|
|
CSET en_route_intb=false
|
128 |
|
|
CSET en_route_intc=false
|
129 |
|
|
CSET en_route_intd=false
|
130 |
|
|
CSET en_route_pm_pme=false
|
131 |
|
|
CSET en_route_pme_to=false
|
132 |
|
|
CSET en_route_pme_to_ack=false
|
133 |
|
|
CSET en_route_unlock=false
|
134 |
|
|
CSET enable_ack_nak_timer=false
|
135 |
|
|
CSET enable_lane_reversal=false
|
136 |
|
|
CSET enable_replay_timer=false
|
137 |
|
|
CSET enable_slot_clock_cfg=false
|
138 |
|
|
CSET expansion_rom_enabled=false
|
139 |
|
|
CSET expansion_rom_scale=Kilobytes
|
140 |
|
|
CSET expansion_rom_size=2
|
141 |
|
|
CSET ext_pci_cfg_space=false
|
142 |
|
|
CSET ext_pci_cfg_space_addr=3FF
|
143 |
|
|
CSET extended_tag_field=false
|
144 |
|
|
CSET force_no_scrambling=false
|
145 |
|
|
CSET hw_auton_spd_disable=false
|
146 |
|
|
CSET intx_generation=true
|
147 |
|
|
CSET io_base_limit_registers=Disabled
|
148 |
|
|
CSET legacy_interrupt=INTA
|
149 |
|
|
CSET link_speed=2.5_GT/s
|
150 |
|
|
CSET max_payload_size=512_bytes
|
151 |
|
|
CSET maximum_link_width=X4
|
152 |
|
|
CSET msi_64b=true
|
153 |
|
|
CSET msi_enabled=true
|
154 |
|
|
CSET msi_vec_mask=false
|
155 |
|
|
CSET msix_enabled=false
|
156 |
|
|
CSET msix_pba_bir=BAR_0
|
157 |
|
|
CSET msix_pba_offset=0
|
158 |
|
|
CSET msix_table_bir=BAR_0
|
159 |
|
|
CSET msix_table_offset=0
|
160 |
|
|
CSET msix_table_size=1
|
161 |
|
|
CSET multiple_message_capable=1_vector
|
162 |
|
|
CSET no_soft_reset=true
|
163 |
|
|
CSET pci_cfg_space=false
|
164 |
|
|
CSET pci_cfg_space_addr=3F
|
165 |
|
|
CSET pcie_blk_locn=X0Y0
|
166 |
|
|
CSET pcie_cap_slot_implemented=false
|
167 |
|
|
CSET pcie_debug_ports=false
|
168 |
|
|
CSET perf_level=High
|
169 |
|
|
CSET phantom_functions=No_function_number_bits_used
|
170 |
|
|
CSET pipe_pipeline=None
|
171 |
|
|
CSET prefetchable_memory_base_limit_registers=Disabled
|
172 |
|
|
CSET rcb=64_byte
|
173 |
|
|
CSET ref_clk_freq=100_MHz
|
174 |
|
|
CSET replay_timeout_func=Add
|
175 |
|
|
CSET replay_timeout_value=0026
|
176 |
|
|
CSET revision_id=06
|
177 |
|
|
CSET root_cap_crs=false
|
178 |
|
|
CSET slot_cap_attn_butn=false
|
179 |
|
|
CSET slot_cap_attn_ind=false
|
180 |
|
|
CSET slot_cap_elec_interlock=false
|
181 |
|
|
CSET slot_cap_hotplug_cap=false
|
182 |
|
|
CSET slot_cap_hotplug_surprise=false
|
183 |
|
|
CSET slot_cap_mrl=false
|
184 |
|
|
CSET slot_cap_no_cmd_comp_sup=false
|
185 |
|
|
CSET slot_cap_physical_slot_num=0
|
186 |
|
|
CSET slot_cap_pwr_ctrl=false
|
187 |
|
|
CSET slot_cap_pwr_ind=false
|
188 |
|
|
CSET slot_cap_pwr_limit_scale=0
|
189 |
|
|
CSET slot_cap_pwr_limit_value=0
|
190 |
|
|
CSET sub_class_interface_menu=Generic_XT_compatible_serial_controller
|
191 |
|
|
CSET subsystem_id=ABB3
|
192 |
|
|
CSET subsystem_vendor_id=0084
|
193 |
|
|
CSET trans_buf_pipeline=None
|
194 |
|
|
CSET trgt_link_speed=4'h1
|
195 |
|
|
CSET trim_tlp_digest=true
|
196 |
|
|
CSET upconfigure_capable=true
|
197 |
|
|
CSET user_clk_freq=125_default
|
198 |
|
|
CSET vc_cap_enabled=false
|
199 |
|
|
CSET vc_cap_reject_snoop=false
|
200 |
|
|
CSET vendor_id=10EE
|
201 |
|
|
CSET vsec_enabled=false
|
202 |
|
|
CSET xlnx_ref_board=ML_605
|
203 |
|
|
# END Parameters
|
204 |
|
|
GENERATE
|
205 |
|
|
# CRC: b6b709af
|