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barabba |
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-- Company: ziti
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-- Engineer: wgao
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--
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-- Create Date: 17:01:32 19 Jun 2009
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-- Design Name:
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-- Module Name: class_ctl - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity class_ctl is
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-- Generic (
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-- C_PRO_DAQ_WIDTH : integer := 16 ;
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-- C_PRO_DLM_WIDTH : integer := 4 ;
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-- C_PRO_CTL_WIDTH : integer := 16
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-- );
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Port (
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-- CTL Tx
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ctrl2send_start : OUT std_logic;
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ctrl2send_end : OUT std_logic;
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ctrl2send : OUT std_logic_vector(16-1 downto 0);
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ctrl2send_stop : IN std_logic;
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-- CTL Rx
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ctrl_rec_start : IN std_logic;
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ctrl_rec_end : IN std_logic;
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ctrl_rec : IN std_logic_vector(16-1 downto 0);
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ctrl_rec_stop : OUT std_logic;
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-- Common signals
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link_active : IN std_logic_vector(2-1 downto 0);
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link_tx_clk : IN std_logic;
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link_rx_clk : IN std_logic;
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-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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-- Fabric side: CTL Rx
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ctl_rv : IN std_logic;
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ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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ctl_rstop : OUT std_logic;
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-- Fabric side: CTL Tx
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ctl_ttake : IN std_logic;
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ctl_tv : OUT std_logic;
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ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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ctl_tstop : IN std_logic;
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-- Interrupter trigger
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CTL_irq : OUT std_logic;
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ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- Fabric side: Common signals
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trn_clk : IN std_logic;
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protocol_rst : IN std_logic
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);
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end entity class_ctl;
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architecture Behavioral of class_ctl is
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-- Standard synchronous FIFO
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component sfifo_256x36
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port (
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(36-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(36-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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clk : IN std_logic;
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rst : IN std_logic
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);
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end component;
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-- Standard asynchronous FIFO
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component v6_afifo_256x36
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port (
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wr_clk : IN std_logic;
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(36-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_clk : IN std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(36-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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rst : IN std_logic
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);
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end component;
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-- FWFT synchronous FIFO
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component sfifo_256x36c_fwft
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port (
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(36-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(36-1 downto 0);
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empty : OUT std_logic;
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prog_empty: OUT std_logic;
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data_count: OUT std_logic_vector (9-1 downto 0);
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clk : IN std_logic;
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rst : IN std_logic
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);
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end component;
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-- FWFT asynchronous FIFO
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component v6_afifo_256x36c_fwft
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port (
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wr_clk : IN std_logic;
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(36-1 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_clk : IN std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(36-1 downto 0);
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empty : OUT std_logic;
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prog_empty : OUT std_logic;
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rd_data_count : OUT std_logic_vector (9-1 downto 0);
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rst : IN std_logic
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);
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end component;
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-- Packet counter
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component v6_pkt_counter_1024
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port (
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wr_clk : IN std_logic;
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wr_en : IN std_logic;
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din : IN std_logic_VECTOR(0 downto 0);
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prog_full : OUT std_logic;
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full : OUT std_logic;
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rd_clk : IN std_logic;
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rd_en : IN std_logic;
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dout : OUT std_logic_VECTOR(0 downto 0);
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empty : OUT std_logic;
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prog_empty : OUT std_logic;
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rst : IN std_logic
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);
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end component;
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-- Interrupter trigger
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signal ctl_reset : std_logic;
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signal CTL_irq_i : std_logic;
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signal ctl_status_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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-- Fabric side: CTL Tx
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signal ctl_tv_i : std_logic;
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signal ctl_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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signal ctl_rstop_i : std_logic;
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-- protocol side: CTL Send
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signal ctrl2send_start_i : std_logic;
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signal ctrl2send_end_i : std_logic;
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signal ctrl2send_i : std_logic_vector(16-1 downto 0);
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signal ctrl_rec_stop_i : std_logic;
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signal ctl_down_buf_rden : std_logic;
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signal ctl_down_buf_dout : std_logic_vector(36-1 downto 0);
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signal ctl_down_buf_empty : std_logic;
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signal ctl_down_buf_afull : std_logic;
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signal ctl_rd_padded : std_logic_vector(36-1 downto 0);
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signal ctl_down_buf_rd_valid : std_logic :='0';
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signal ctl_down_buf_read_gap : std_logic;
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signal ctl_down_buf_eop : std_logic;
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signal ctl_down_buf_eop_r1 : std_logic :='0';
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signal ctrl2send_stop_r1 : std_logic :='0';
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signal ctl_down_buf_frame_rd : std_logic :='0';
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signal ctl_down_buf_stop_read : std_logic;
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signal pc_ctl_down_push : std_logic;
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signal pc_ctl_down_pop : std_logic;
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signal no_pkts_in_ctl_down_buf : std_logic;
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signal no_pkts_in_ctl_down_buf_r1: std_logic :='0';
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signal ctl_up_buf_wren : std_logic;
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signal ctl_up_buf_din : std_logic_vector(36-1 downto 0);
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signal ctl_up_buf_din_b1 : std_logic_vector(36-1 downto 0);
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signal ctl_up_buf_afull : std_logic;
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signal ctl_up_buf_re : std_logic;
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signal ctl_up_buf_dout : std_logic_vector(36-1 downto 0);
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signal ctl_up_buf_empty : std_logic;
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signal ctl_up_buf_dc_wire : std_logic_vector (9-1 downto 0);
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signal ctl_up_buf_dc_r1 : std_logic_vector (9-1 downto 0);
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signal ctl_up_buf_dc_plus_r1 : std_logic_vector (9-1 downto 0);
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signal ctl_up_buf_dc_i : std_logic_vector (9-1 downto 0);
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signal ctl_up_is_writing : std_logic;
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signal ctl_up_is_writing_r1 : std_logic;
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signal ctl_up_buf_rd_valid : std_logic;
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signal pc_ctl_up_push : std_logic;
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signal pc_ctl_up_pop : std_logic;
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signal no_pkts_in_ctl_up_buf : std_logic;
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signal no_pkts_in_ctl_up_buf_r1 : std_logic;
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begin
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-- Fabric side: CTL Tx
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ctl_tv <= ctl_tv_i ;
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ctl_td <= ctl_td_i ;
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ctl_rstop <= ctl_rstop_i ;
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-- protocol side: CTL Send
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ctrl2send_start <= ctrl2send_start_i ;
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ctrl2send_end <= ctrl2send_end_i ;
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ctrl2send <= ctrl2send_i ;
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ctrl_rec_stop <= ctrl_rec_stop_i ;
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ctrl_rec_stop_i <= ctl_up_buf_afull;
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ctl_rstop_i <= ctl_down_buf_afull;
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ctl_status <= ctl_status_i ;
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CTL_irq <= CTL_irq_i ;
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CTL_irq_i <= not ctl_up_buf_empty ;
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ctl_status_i <= X"000" & '0' & '0' & ctl_down_buf_afull & ctl_up_buf_empty
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& X"0" & '0' & '0' & ctl_up_buf_dc_i & no_pkts_in_ctl_up_buf_r1;
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-- ------------------------------------------------------------------------------
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--
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-- ------------------------------------------------------------------------------
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Synch_Local_Reset:
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process (trn_clk )
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begin
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if trn_clk'event and trn_clk = '1' then
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ctl_reset <= protocol_rst;
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end if;
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end process;
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-- ------------------------------------------------------------------------------
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-- CTL buffer from the host
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-- ------------------------------------------------------------------------------
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ctl_buf_downstream:
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v6_afifo_256x36
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port map (
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wr_clk => trn_clk , -- IN std_logic;
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wr_en => ctl_rv , -- IN std_logic;
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din => ctl_rd_padded , -- IN std_logic_VECTOR(35 downto 0);
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prog_full => ctl_down_buf_afull , -- ctl_rstop_i , -- OUT std_logic;
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full => open , -- OUT std_logic;
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rd_clk => link_tx_clk , -- IN std_logic;
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rd_en => ctl_down_buf_rden , -- IN std_logic;
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dout => ctl_down_buf_dout , -- OUT std_logic_VECTOR(35 downto 0);
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prog_empty => open , -- OUT std_logic;
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empty => ctl_down_buf_empty , -- OUT std_logic;
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rst => ctl_reset -- IN std_logic
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);
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ctl_rd_padded <= "0000" & ctl_rd;
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ctl_down_buf_eop <= ctl_down_buf_dout(16);
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ctl_down_buf_read_gap <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;
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ctl_down_buf_rden <= ctl_down_buf_frame_rd and not ctl_down_buf_read_gap;
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-- Packet counter: ABB -> ROC
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pc_ctl_buf_downstream:
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v6_pkt_counter_1024
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port map (
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wr_clk => trn_clk , -- IN std_logic;
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wr_en => pc_ctl_down_push , -- IN std_logic;
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din => "1" , -- IN std_logic_VECTOR(0 downto 0);
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prog_full => open , -- OUT std_logic;
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full => open , -- OUT std_logic;
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rd_clk => link_tx_clk , -- IN std_logic;
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rd_en => pc_ctl_down_pop , -- IN std_logic;
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dout => open , -- OUT std_logic_VECTOR(0 downto 0);
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empty => no_pkts_in_ctl_down_buf , -- OUT std_logic;
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prog_empty => open , -- OUT std_logic;
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rst => ctl_reset -- IN std_logic
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);
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Syn_pc_ctl_down_push:
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process (trn_clk, ctl_reset )
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begin
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if ctl_reset = '1' then
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pc_ctl_down_push <= '0';
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elsif trn_clk'event and trn_clk = '1' then
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pc_ctl_down_push <= ctl_rv and ctl_rd(16);
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end if;
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end process;
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Syn_pc_ctl_down_pop:
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process (link_tx_clk, ctl_reset )
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begin
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if ctl_reset = '1' then
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pc_ctl_down_pop <= '0';
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elsif link_tx_clk'event and link_tx_clk = '1' then
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pc_ctl_down_pop <= ctl_down_buf_rd_valid and ctl_down_buf_eop;
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end if;
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end process;
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---------------------------------------------------
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-- Downstream CTL buffer read and packets number
|
347 |
|
|
-- bit[17] : sof
|
348 |
|
|
-- bit[16] : eof
|
349 |
|
|
--
|
350 |
|
|
Delay_CTL_downstream_frame:
|
351 |
|
|
process (link_tx_clk )
|
352 |
|
|
begin
|
353 |
|
|
if link_tx_clk'event and link_tx_clk = '1' then
|
354 |
|
|
|
355 |
|
|
no_pkts_in_ctl_down_buf_r1 <= no_pkts_in_ctl_down_buf;
|
356 |
|
|
ctrl2send_stop_r1 <= ctrl2send_stop;
|
357 |
|
|
ctl_down_buf_rd_valid <= ctl_down_buf_rden and not ctl_down_buf_empty;
|
358 |
|
|
ctl_down_buf_eop_r1 <= ctl_down_buf_eop;
|
359 |
|
|
ctl_down_buf_frame_rd <= not no_pkts_in_ctl_down_buf_r1
|
360 |
|
|
and not ctl_down_buf_read_gap
|
361 |
|
|
and not ctl_down_buf_stop_read
|
362 |
|
|
;
|
363 |
|
|
end if;
|
364 |
|
|
end process;
|
365 |
|
|
|
366 |
|
|
--
|
367 |
|
|
Syn_rden_CTL_downstream_buf:
|
368 |
|
|
process (link_tx_clk, ctl_reset )
|
369 |
|
|
begin
|
370 |
|
|
if ctl_reset = '1' then
|
371 |
|
|
ctl_down_buf_stop_read <= '0';
|
372 |
|
|
elsif link_tx_clk'event and link_tx_clk = '1' then
|
373 |
|
|
if ctl_down_buf_read_gap='1' and ctrl2send_stop_r1='1' then
|
374 |
|
|
ctl_down_buf_stop_read <= '1';
|
375 |
|
|
elsif ctl_down_buf_stop_read='0' and ctrl2send_stop_r1='1' then
|
376 |
|
|
ctl_down_buf_stop_read <= '0';
|
377 |
|
|
else
|
378 |
|
|
ctl_down_buf_stop_read <= ctrl2send_stop_r1;
|
379 |
|
|
end if;
|
380 |
|
|
end if;
|
381 |
|
|
end process;
|
382 |
|
|
|
383 |
|
|
ctrl2send_start_i <= ctl_down_buf_dout(17);
|
384 |
|
|
ctrl2send_end_i <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;
|
385 |
|
|
ctrl2send_i <= ctl_down_buf_dout(16-1 downto 0);
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
-- ------------------------------------------------------------------------------
|
389 |
|
|
-- CTL buffer to the host
|
390 |
|
|
-- ------------------------------------------------------------------------------
|
391 |
|
|
ctl_buf_upstream:
|
392 |
|
|
v6_afifo_256x36c_fwft
|
393 |
|
|
port map (
|
394 |
|
|
wr_clk => link_rx_clk , -- IN std_logic;
|
395 |
|
|
wr_en => ctl_up_buf_wren , -- IN std_logic;
|
396 |
|
|
din => ctl_up_buf_din , -- IN std_logic_VECTOR(35 downto 0);
|
397 |
|
|
prog_full => ctl_up_buf_afull , -- ctrl_rec_stop_i , -- OUT std_logic;
|
398 |
|
|
full => open , -- OUT std_logic;
|
399 |
|
|
|
400 |
|
|
rd_clk => trn_clk , -- IN std_logic;
|
401 |
|
|
rd_en => ctl_up_buf_re , -- IN std_logic;
|
402 |
|
|
dout => ctl_up_buf_dout , -- OUT std_logic_VECTOR(35 downto 0);
|
403 |
|
|
prog_empty => open , -- OUT std_logic;
|
404 |
|
|
empty => ctl_up_buf_empty , -- OUT std_logic;
|
405 |
|
|
|
406 |
|
|
rd_data_count => ctl_up_buf_dc_wire , -- OUT std_logic_vector (9-1 downto 0 );
|
407 |
|
|
|
408 |
|
|
rst => ctl_reset -- IN std_logic
|
409 |
|
|
);
|
410 |
|
|
|
411 |
|
|
ctl_up_buf_re <= ctl_ttake;
|
412 |
|
|
ctl_up_buf_rd_valid <= ctl_up_buf_re and not ctl_up_buf_empty;
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
-- Special data count for FWFT FIFO
|
416 |
|
|
Syn_up_fifo_fwft_dc:
|
417 |
|
|
process (trn_clk, ctl_reset )
|
418 |
|
|
begin
|
419 |
|
|
if ctl_reset = '1' then
|
420 |
|
|
ctl_up_buf_dc_i <= (OTHERS=>'0');
|
421 |
|
|
ctl_up_buf_dc_r1 <= (OTHERS=>'0');
|
422 |
|
|
ctl_up_buf_dc_plus_r1 <= (OTHERS=>'0');
|
423 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
424 |
|
|
ctl_up_buf_dc_r1 <= ctl_up_buf_dc_wire;
|
425 |
|
|
ctl_up_buf_dc_plus_r1 <= ctl_up_buf_dc_wire + "10";
|
426 |
|
|
if ctl_up_buf_empty='1' then
|
427 |
|
|
ctl_up_buf_dc_i <= ctl_up_buf_dc_r1;
|
428 |
|
|
else
|
429 |
|
|
ctl_up_buf_dc_i <= ctl_up_buf_dc_plus_r1;
|
430 |
|
|
end if;
|
431 |
|
|
end if;
|
432 |
|
|
end process;
|
433 |
|
|
|
434 |
|
|
-- Packet counter: ROC -> ABB
|
435 |
|
|
pc_ctl_buf_upstream:
|
436 |
|
|
v6_pkt_counter_1024
|
437 |
|
|
port map (
|
438 |
|
|
wr_clk => link_rx_clk , -- IN std_logic;
|
439 |
|
|
wr_en => pc_ctl_up_push , -- IN std_logic;
|
440 |
|
|
din => "1" , -- IN std_logic_VECTOR(0 downto 0);
|
441 |
|
|
prog_full => open , -- OUT std_logic;
|
442 |
|
|
full => open , -- OUT std_logic;
|
443 |
|
|
|
444 |
|
|
rd_clk => trn_clk , -- IN std_logic;
|
445 |
|
|
rd_en => pc_ctl_up_pop , -- IN std_logic;
|
446 |
|
|
dout => open , -- OUT std_logic_VECTOR(0 downto 0);
|
447 |
|
|
empty => no_pkts_in_ctl_up_buf , -- OUT std_logic;
|
448 |
|
|
prog_empty => open , -- OUT std_logic;
|
449 |
|
|
|
450 |
|
|
rst => ctl_reset -- IN std_logic
|
451 |
|
|
);
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
Syn_pc_ctl_up_push:
|
455 |
|
|
process (link_rx_clk, ctl_reset )
|
456 |
|
|
begin
|
457 |
|
|
if ctl_reset = '1' then
|
458 |
|
|
pc_ctl_up_push <= '0';
|
459 |
|
|
elsif link_rx_clk'event and link_rx_clk = '1' then
|
460 |
|
|
pc_ctl_up_push <= ctl_up_buf_wren and ctl_up_buf_din(16);
|
461 |
|
|
end if;
|
462 |
|
|
end process;
|
463 |
|
|
|
464 |
|
|
Syn_pc_ctl_up_pop:
|
465 |
|
|
process (trn_clk, ctl_reset )
|
466 |
|
|
begin
|
467 |
|
|
if ctl_reset = '1' then
|
468 |
|
|
pc_ctl_up_pop <= '0';
|
469 |
|
|
no_pkts_in_ctl_up_buf_r1 <= '1';
|
470 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
471 |
|
|
pc_ctl_up_pop <= ctl_up_buf_rd_valid and ctl_up_buf_dout(16);
|
472 |
|
|
no_pkts_in_ctl_up_buf_r1 <= no_pkts_in_ctl_up_buf;
|
473 |
|
|
end if;
|
474 |
|
|
end process;
|
475 |
|
|
|
476 |
|
|
-- CTL direction: upstream
|
477 |
|
|
-- protocol side
|
478 |
|
|
Transfer_CTL_upstream_protocol:
|
479 |
|
|
process (link_rx_clk, ctl_reset )
|
480 |
|
|
begin
|
481 |
|
|
if ctl_reset = '1' then
|
482 |
|
|
ctl_up_buf_din_b1 <= (OTHERS=>'0');
|
483 |
|
|
ctl_up_buf_din <= (OTHERS=>'0');
|
484 |
|
|
ctl_up_buf_wren <= '0';
|
485 |
|
|
ctl_up_is_writing <= '0';
|
486 |
|
|
ctl_up_is_writing_r1 <= '0';
|
487 |
|
|
|
488 |
|
|
elsif link_rx_clk'event and link_rx_clk = '1' then
|
489 |
|
|
ctl_up_buf_din_b1 <= X"0000" & "00" & ctrl_rec_start & ctrl_rec_end & ctrl_rec;
|
490 |
|
|
ctl_up_buf_din <= ctl_up_buf_din_b1;
|
491 |
|
|
ctl_up_buf_wren <= (ctl_up_is_writing or ctl_up_is_writing_r1);
|
492 |
|
|
if ctrl_rec_start='1' and ctrl_rec_end='1' then
|
493 |
|
|
ctl_up_is_writing <= '0';
|
494 |
|
|
ctl_up_is_writing_r1 <= '1';
|
495 |
|
|
elsif ctrl_rec_start='1' then
|
496 |
|
|
ctl_up_is_writing <= '1';
|
497 |
|
|
ctl_up_is_writing_r1 <= ctl_up_is_writing;
|
498 |
|
|
elsif ctrl_rec_end='1' then
|
499 |
|
|
ctl_up_is_writing <= '0';
|
500 |
|
|
ctl_up_is_writing_r1 <= ctl_up_is_writing;
|
501 |
|
|
else
|
502 |
|
|
ctl_up_is_writing <= ctl_up_is_writing;
|
503 |
|
|
ctl_up_is_writing_r1 <= ctl_up_is_writing;
|
504 |
|
|
end if;
|
505 |
|
|
|
506 |
|
|
end if;
|
507 |
|
|
end process;
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
-- CTL direction: upstream
|
511 |
|
|
-- fabric side
|
512 |
|
|
Transfer_CTL_upstream_fabric:
|
513 |
|
|
process (trn_clk, ctl_reset )
|
514 |
|
|
begin
|
515 |
|
|
if ctl_reset = '1' then
|
516 |
|
|
ctl_tv_i <= '0';
|
517 |
|
|
ctl_td_i <= (OTHERS=>'0');
|
518 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
519 |
|
|
ctl_tv_i <= not ctl_up_buf_empty;
|
520 |
|
|
ctl_td_i <= ctl_up_buf_dout(C_DBUS_WIDTH/2-1 downto 0);
|
521 |
|
|
end if;
|
522 |
|
|
end process;
|
523 |
|
|
|
524 |
|
|
|
525 |
|
|
end architecture Behavioral;
|