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----------------------------------------------------------------------------------
-- Company:   ziti
-- Engineer:  wgao
-- 
-- Create Date:    17:01:32 19 Jun 2009
-- Design Name: 
-- Module Name:    protocol_IF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity protocol_IF is
--    Generic (
--             C_PRO_DAQ_WIDTH  :  integer  :=  16 ;
--             C_PRO_DLM_WIDTH  :  integer  :=   4 ;
--             C_PRO_CTL_WIDTH  :  integer  :=  16
--            );
    Port (
 
           -- DAQ Tx
           data2send_start          : OUT   std_logic;
           data2send_end            : OUT   std_logic;
           data2send                : OUT   std_logic_vector(64-1 downto 0);
           crc_error_send           : OUT   std_logic;
           data2send_stop           : IN    std_logic;
 
           -- DAQ Rx
           data_rec_start           : IN    std_logic;
           data_rec_end             : IN    std_logic;
           data_rec                 : IN    std_logic_vector(64-1 downto 0);
           crc_error_rec            : IN    std_logic;
           data_rec_stop            : OUT   std_logic;
 
--           -- [dg] DAQ Rx
--           dg_data_rec_start        : IN    std_logic;
--           dg_data_rec_end          : IN    std_logic;
--           dg_data_rec              : IN    std_logic_vector(16-1 downto 0);
--           dg_crc_error_rec         : IN    std_logic;
 
           -- CTL Tx
           ctrl2send_start          : OUT   std_logic;
           ctrl2send_end            : OUT   std_logic;
           ctrl2send                : OUT   std_logic_vector(16-1 downto 0);
           ctrl2send_stop           : IN    std_logic;
 
           -- CTL Rx
           ctrl_rec_start           : IN    std_logic;
           ctrl_rec_end             : IN    std_logic;
           ctrl_rec                 : IN    std_logic_vector(16-1 downto 0);
           ctrl_rec_stop            : OUT   std_logic;
 
--           -- [dg] CTL Rx
--           dg_ctrl_rec_start        : IN    std_logic;
--           dg_ctrl_rec_end          : IN    std_logic;
--           dg_ctrl_rec              : IN    std_logic_vector(16-1 downto 0);
 
           -- DLM Tx
           dlm2send_va              : OUT   std_logic;
           dlm2send_type            : OUT   std_logic_vector(4-1 downto 0);
 
           -- DLM Rx
           dlm_rec_va               : IN    std_logic;
           dlm_rec_type             : IN    std_logic_vector(4-1 downto 0);
 
--           -- [dg] DLM Rx
--           dg_dlm_rec_va            : IN    std_logic;
--           dg_dlm_rec_type          : IN    std_logic_vector(4-1 downto 0);
 
           -- Common signals
           link_tx_clk              : IN    std_logic;
           link_rx_clk              : IN    std_logic;
           link_active              : IN    std_logic_vector(2-1 downto 0);
           protocol_clk             : OUT   std_logic;
           protocol_res_n           : OUT   std_logic;
 
           -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
 
           -- Fabric side: DAQ Rx
           daq_rv                   : IN    std_logic;
           daq_rsof                 : IN    std_logic;
           daq_reof                 : IN    std_logic;
           daq_rd                   : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
           daq_rstop                : OUT   std_logic;
 
           -- Fabric side: DAQ Tx
           daq_tv                   : OUT   std_logic;
           daq_tsof                 : OUT   std_logic;
           daq_teof                 : OUT   std_logic;
           daq_td                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
           daq_tstop                : IN    std_logic;
 
           -- Fabric side: CTL Rx
           ctl_rv                   : IN    std_logic;
           ctl_rd                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
           ctl_rstop                : OUT   std_logic;
 
           -- Fabric side: CTL Tx
           ctl_ttake                : IN    std_logic;
           ctl_tv                   : OUT   std_logic;
           ctl_td                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
           ctl_tstop                : IN    std_logic;
 
           ctl_reset                : IN    std_logic;
           ctl_status               : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
           -- Fabric side: DLM Tx
           dlm_tv                   : IN    std_logic;
           dlm_td                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
           -- Fabric side: DLM Rx
           dlm_rv                   : OUT   std_logic;
           dlm_rd                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
           -- Interrupter triggers
           DAQ_irq                  : OUT   std_logic;
           CTL_irq                  : OUT   std_logic;
           DLM_irq                  : OUT   std_logic;
 
           -- Data generator table write port
           tab_sel                  : IN    STD_LOGIC;
           tab_we                   : IN    STD_LOGIC_VECTOR (2-1 downto 0);
           tab_wa                   : IN    STD_LOGIC_VECTOR (12-1 downto 0);
           tab_wd                   : IN    STD_LOGIC_VECTOR (64-1 downto 0);
 
           -- DG control/status signal
           dg_running               : OUT   STD_LOGIC;
           dg_mask                  : IN    STD_LOGIC;
           dg_rst                   : IN    STD_LOGIC;
 
           -- DG debug signal
           daq_start_led            : OUT   STD_LOGIC;
 
           -- Fabric side: Common signals
           trn_clk                  : IN    std_logic;
           protocol_link_act        : OUT   std_logic_vector(2-1 downto 0);
           protocol_rst             : IN    std_logic
 
          );
end entity protocol_IF;
 
 
architecture Behavioral of protocol_IF is
 
   -- Data generator
   COMPONENT abb_dgen
   PORT (
           -- Data generator table write port
           tab_sel            : IN    STD_LOGIC;
           tab_we             : IN    STD_LOGIC_VECTOR (2-1 downto 0);
           tab_wa             : IN    STD_LOGIC_VECTOR (12-1 downto 0);
           tab_wd             : IN    STD_LOGIC_VECTOR (64-1 downto 0);
 
 
           -- DAQ Rx
           data_rec_start     : OUT   std_logic;
           data_rec_end       : OUT   std_logic;
           data_rec           : OUT   std_logic_vector(64-1 downto 0);
           crc_error_rec      : OUT   std_logic;
           data_rec_stop      : IN    std_logic;
 
           -- CTL Rx
           ctrl_rec_start     : OUT   std_logic;
           ctrl_rec_end       : OUT   std_logic;
           ctrl_rec           : OUT   std_logic_vector(16-1 downto 0);
           ctrl_rec_stop      : IN    std_logic;
 
           -- DLM Rx
           dlm_rec_va         : OUT   std_logic;
           dlm_rec_type       : OUT   std_logic_vector(4-1 downto 0);
 
           -- status signal
           dg_running         : OUT   STD_LOGIC;
           daq_start_led      : OUT   STD_LOGIC;
 
           -- must signals
           dg_clk             : IN    STD_LOGIC;
           dg_mask            : IN    STD_LOGIC;
           dg_rst             : IN    STD_LOGIC
           );
   END COMPONENT;
 
 
   COMPONENT class_daq
   PORT(
        -- DAQ Tx
        data2send_start          : OUT   std_logic;
        data2send_end            : OUT   std_logic;
        data2send                : OUT   std_logic_vector(64-1 downto 0);
        crc_error_send           : OUT   std_logic;
        data2send_stop           : IN    std_logic;
 
        -- DAQ Rx
        data_rec_start           : IN    std_logic;
        data_rec_end             : IN    std_logic;
        data_rec                 : IN    std_logic_vector(64-1 downto 0);
        crc_error_rec            : IN    std_logic;
        data_rec_stop            : OUT   std_logic;
 
        -- Common signals
        link_tx_clk              : IN    std_logic;
        link_rx_clk              : IN    std_logic;
 
 
        -- Fabric side: DAQ Rx
        daq_rv                   : IN    std_logic;
        daq_rsof                 : IN    std_logic;
        daq_reof                 : IN    std_logic;
        daq_rd                   : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
        daq_rstop                : OUT   std_logic;
 
        -- Fabric side: DAQ Tx
        daq_tv                   : OUT   std_logic;
        daq_tsof                 : OUT   std_logic;
        daq_teof                 : OUT   std_logic;
        daq_td                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
        daq_tstop                : IN    std_logic;
 
        -- Interrupter trigger
        DAQ_irq                  : OUT   std_logic;
 
        -- Fabric side: Common signals
        trn_clk                  : IN    std_logic;
        protocol_rst             : IN    std_logic
       );
   END COMPONENT;
 
   COMPONENT class_ctl
   PORT(
        -- CTL Tx
        ctrl2send_start          : OUT   std_logic;
        ctrl2send_end            : OUT   std_logic;
        ctrl2send                : OUT   std_logic_vector(16-1 downto 0);
        ctrl2send_stop           : IN    std_logic;
 
        -- CTL Rx
        ctrl_rec_start           : IN    std_logic;
        ctrl_rec_end             : IN    std_logic;
        ctrl_rec                 : IN    std_logic_vector(16-1 downto 0);
        ctrl_rec_stop            : OUT   std_logic;
 
        -- Common signals
        link_active              : IN    std_logic_vector(2-1 downto 0);
        link_tx_clk              : IN    std_logic;
        link_rx_clk              : IN    std_logic;
 
 
        -- Fabric side: CTL Rx
        ctl_rv                   : IN    std_logic;
        ctl_rd                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
        ctl_rstop                : OUT   std_logic;
 
        -- Fabric side: CTL Tx
        ctl_ttake                : IN    std_logic;
        ctl_tv                   : OUT   std_logic;
        ctl_td                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
        ctl_tstop                : IN    std_logic;
 
        -- Interrupter trigger
        CTL_irq                  : OUT   std_logic;
        ctl_status               : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
        -- Fabric side: Common signals
        trn_clk                  : IN    std_logic;
        protocol_rst             : IN    std_logic
                );
   END COMPONENT;
 
   COMPONENT class_dlm
   PORT(
        -- DLM Tx
        dlm2send_va              : OUT   std_logic;
        dlm2send_type            : OUT   std_logic_vector(4-1 downto 0);
 
        -- DLM Rx
        dlm_rec_va               : IN    std_logic;
        dlm_rec_type             : IN    std_logic_vector(4-1 downto 0);
 
        -- Common signals
        link_tx_clk              : IN    std_logic;
        link_rx_clk              : IN    std_logic;
 
 
        -- Fabric side: DLM Rx
        dlm_tv                   : IN    std_logic;
        dlm_td                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
        -- Fabric side: DLM Tx
        dlm_rv                   : OUT   std_logic;
        dlm_rd                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
        -- Interrupter trigger
        DLM_irq                  : OUT   std_logic;
 
        -- Fabric side: Common signals
        trn_clk                  : IN    std_logic;
        protocol_rst             : IN    std_logic
                );
   END COMPONENT;
 
   -- Protocol module reset
   signal  protocol_link_act_i   : std_logic_vector(2-1 downto 0);
 
   -- Flow control signals
   signal  data_rec_stop_i       : std_logic;
   signal  ctrl_rec_stop_i       : std_logic;
 
 
   -- DAQ Tx
   signal  data2send_start_i     : std_logic;
   signal  data2send_end_i       : std_logic;
   signal  data2send_i           : std_logic_vector(64-1 downto 0);
   signal  crc_error_send_i      : std_logic;
   signal  data2send_stop_i      : std_logic;
 
   -- CTL Tx
   signal  ctrl2send_start_i     : std_logic;
   signal  ctrl2send_end_i       : std_logic;
   signal  ctrl2send_i           : std_logic_vector(16-1 downto 0);
   signal  ctrl2send_stop_i      : std_logic;
 
   -- DLM Tx
   signal  dlm2send_va_i         : std_logic;
   signal  dlm2send_type_i       : std_logic_vector(4-1 downto 0);
 
   -- [dg] DAQ Rx
   signal  dg_data_rec_start     : std_logic;
   signal  dg_data_rec_end       : std_logic;
   signal  dg_data_rec           : std_logic_vector(64-1 downto 0);
   signal  dg_crc_error_rec      : std_logic;
 
   -- [dg] CTL Rx
   signal  dg_ctrl_rec_start     : std_logic;
   signal  dg_ctrl_rec_end       : std_logic;
   signal  dg_ctrl_rec           : std_logic_vector(16-1 downto 0);
 
   -- [dg] DLM Rx
   signal  dg_dlm_rec_va         : std_logic;
   signal  dg_dlm_rec_type       : std_logic_vector(4-1 downto 0);
 
   -- DAQ Rx wire
   signal  data_rec_start_i      : std_logic;
   signal  data_rec_end_i        : std_logic;
   signal  data_rec_i            : std_logic_vector(64-1 downto 0);
   signal  crc_error_rec_i       : std_logic;
 
   -- CTL Rx wire
   signal  ctrl_rec_start_i      : std_logic;
   signal  ctrl_rec_end_i        : std_logic;
   signal  ctrl_rec_i            : std_logic_vector(16-1 downto 0);
 
   -- DLM Rx wire
   signal  dlm_rec_va_i          : std_logic;
   signal  dlm_rec_type_i        : std_logic_vector(4-1 downto 0);
 
 
begin
 
   protocol_clk       <= trn_clk;
   protocol_res_n     <= not protocol_rst;
   protocol_link_act  <= protocol_link_act_i;
 
   data2send_start    <= (data2send_start_i or dg_data_rec_start);
   data2send_end      <= (data2send_end_i   or dg_data_rec_end  );
   data2send          <= (data2send_i       or dg_data_rec      );
   crc_error_send     <= (crc_error_send_i  or dg_crc_error_rec );
   data2send_stop_i   <= data2send_stop  ;
 
   data_rec_start_i   <= data_rec_start  ;
   data_rec_end_i     <= data_rec_end    ;
   data_rec_i         <= data_rec        ;
   crc_error_rec_i    <= crc_error_rec   ;
   data_rec_stop      <= data_rec_stop_i;
 
   ctrl2send_start    <= (ctrl2send_start_i or dg_ctrl_rec_start  );
   ctrl2send_end      <= (ctrl2send_end_i   or dg_ctrl_rec_end    );
   ctrl2send          <= (ctrl2send_i       or dg_ctrl_rec        );
   ctrl2send_stop_i   <= ctrl2send_stop ;
 
   ctrl_rec_start_i   <= ctrl_rec_start ;
   ctrl_rec_end_i     <= ctrl_rec_end   ;
   ctrl_rec_i         <= ctrl_rec       ;
   ctrl_rec_stop      <= ctrl_rec_stop_i;
 
   dlm2send_va        <= (dlm2send_va_i    or dg_dlm_rec_va    );
   dlm2send_type      <= (dlm2send_type_i  or dg_dlm_rec_type  );
 
   dlm_rec_va_i       <= dlm_rec_va   ;
   dlm_rec_type_i     <= dlm_rec_type ;
 
 
   -- Protocol link active signal register
   Synch_protocol_link_act:
   process (trn_clk )
   begin
     if trn_clk'event and trn_clk = '1' then
       protocol_link_act_i <= link_active;
     end if;
   end process;
 
 
   -- Data generator implementation
   Gen_DataGen: if IMP_DATA_GENERATOR generate
 
   data_generator_0:
   abb_dgen
     port map (
          -- Data generator table write port
          tab_sel           =>  '1'               ,  -- IN    STD_LOGIC;
          tab_we            =>  tab_we            ,  -- IN    STD_LOGIC_VECTOR (8-1 downto 0);
          tab_wa            =>  tab_wa            ,  -- IN    STD_LOGIC_VECTOR (12-1 downto 0);
          tab_wd            =>  tab_wd            ,  -- IN    STD_LOGIC_VECTOR (64-1 downto 0);
 
          -- DAQ Rx
          data_rec_start    =>  dg_data_rec_start ,  -- OUT   std_logic;
          data_rec_end      =>  dg_data_rec_end   ,  -- OUT   std_logic;
          data_rec          =>  dg_data_rec       ,  -- OUT   std_logic_vector(16-1 downto 0);
          crc_error_rec     =>  dg_crc_error_rec  ,  -- OUT   std_logic;
          data_rec_stop     =>  data_rec_stop_i   ,  -- IN    std_logic;
 
          -- CTL Rx
          ctrl_rec_start    =>  dg_ctrl_rec_start ,  -- OUT   std_logic;
          ctrl_rec_end      =>  dg_ctrl_rec_end   ,  -- OUT   std_logic;
          ctrl_rec          =>  dg_ctrl_rec       ,  -- OUT   std_logic_vector(16-1 downto 0);
          ctrl_rec_stop     =>  ctrl_rec_stop_i   ,  -- IN    std_logic;
 
          -- DLM Rx
          dlm_rec_va        =>  dg_dlm_rec_va     ,  -- OUT   std_logic;
          dlm_rec_type      =>  dg_dlm_rec_type   ,  -- OUT   std_logic_vector(4-1 downto 0);
 
          -- status signals
          dg_running        =>  dg_running        ,  -- OUT   STD_LOGIC;
          daq_start_led     =>  daq_start_led     ,  -- OUT   STD_LOGIC;
 
          -- common signals
          dg_clk            =>  trn_clk           ,  -- IN    STD_LOGIC;
          dg_mask           =>  dg_mask           ,  -- IN    STD_LOGIC;
          dg_rst            =>  dg_rst               -- IN    STD_LOGIC
          );
 
   end generate;
 
 
   -- No data generator implementation
   NotGen_DataGen: if not IMP_DATA_GENERATOR generate
 
          -- debug signal
          daq_start_led        <=  '0';
 
          -- DAQ Rx
          dg_data_rec_start    <=  '0';
          dg_data_rec_end      <=  '0';
          dg_data_rec          <=  (OTHERS=>'0');
          dg_crc_error_rec     <=  '0';
 
          -- CTL Rx
          dg_ctrl_rec_start    <=  '0';
          dg_ctrl_rec_end      <=  '0';
          dg_ctrl_rec          <=  (OTHERS=>'0');
 
          -- DLM Rx
          dg_dlm_rec_va        <=  '0';
          dg_dlm_rec_type      <=  (OTHERS=>'0');
 
   end generate;
 
 
 
   module_class_daq:
   class_daq
   PORT MAP(
      -- DAQ Tx
      data2send_start          => data2send_start_i ,  -- OUT   std_logic;
      data2send_end            => data2send_end_i   ,  -- OUT   std_logic;
      data2send                => data2send_i       ,  -- OUT   std_logic_vector(16-1 downto 0);
      crc_error_send           => crc_error_send_i  ,  -- OUT   std_logic;
      data2send_stop           => data2send_stop_i  ,  -- IN    std_logic;
 
      -- DAQ Rx
      data_rec_start           => data_rec_start_i    ,  -- IN    std_logic;
      data_rec_end             => data_rec_end_i      ,  -- IN    std_logic;
      data_rec                 => data_rec_i          ,  -- IN    std_logic_vector(16-1 downto 0);
      crc_error_rec            => crc_error_rec_i     ,  -- IN    std_logic;
      data_rec_stop            => data_rec_stop_i     ,  -- OUT   std_logic;
 
      -- Common signals
      link_tx_clk              => link_tx_clk        ,  -- IN    std_logic;
      link_rx_clk              => link_tx_clk        ,  -- IN    std_logic;
 
 
      -- Fabric side - DAQ Rx
      daq_rv                   => daq_rv          ,  -- IN    std_logic;
      daq_rsof                 => daq_rsof        ,  -- IN    std_logic;
      daq_reof                 => daq_reof        ,  -- IN    std_logic;
      daq_rd                   => daq_rd          ,  -- IN    std_logic_vector(64-1 downto 0);
      daq_rstop                => daq_rstop       ,  -- OUT   std_logic;
 
      -- Fabric side - DAQ Tx
      daq_tv                   => daq_tv          ,  -- OUT   std_logic;
      daq_tsof                 => daq_tsof        ,  -- OUT   std_logic;
      daq_teof                 => daq_teof        ,  -- OUT   std_logic;
      daq_td                   => daq_td          ,  -- OUT   std_logic_vector(64-1 downto 0);
      daq_tstop                => daq_tstop       ,  -- IN    std_logic;
 
      -- Interrupter trigger
      DAQ_irq                  => DAQ_irq         ,  -- OUT   std_logic;
 
      -- Fabric side - Common signals
      trn_clk                  => trn_clk         ,  -- IN    std_logic;
      protocol_rst             => protocol_rst       -- IN    std_logic
   );
 
 
 
   module_class_ctl:
   class_ctl
   PORT MAP(
      -- CTL Tx
      ctrl2send_start          => ctrl2send_start_i   ,  -- OUT   std_logic;
      ctrl2send_end            => ctrl2send_end_i     ,  -- OUT   std_logic;
      ctrl2send                => ctrl2send_i         ,  -- OUT   std_logic_vector(32-1 downto 0);
      ctrl2send_stop           => ctrl2send_stop_i    ,  -- IN    std_logic;
 
      -- CTL Rx
      ctrl_rec_start           => ctrl_rec_start_i     ,  -- IN    std_logic;
      ctrl_rec_end             => ctrl_rec_end_i       ,  -- IN    std_logic;
      ctrl_rec                 => ctrl_rec_i           ,  -- IN    std_logic_vector(32-1 downto 0);
      ctrl_rec_stop            => ctrl_rec_stop_i      ,  -- OUT   std_logic;
 
      -- Common signals
      link_active              => link_active          ,  -- IN    std_logic_vector(2-1 downto 0);
      link_tx_clk              => link_tx_clk          ,  -- IN    std_logic;
      link_rx_clk              => link_tx_clk          ,  -- IN    std_logic;
 
 
      -- Fabric side - CTL Rx
      ctl_rv                   => ctl_rv           ,  -- IN    std_logic;
      ctl_rd                   => ctl_rd           ,  -- IN    std_logic_vector(32-1 downto 0);
      ctl_rstop                => ctl_rstop        ,  -- OUT   std_logic;
 
      -- Fabric side - CTL Tx
      ctl_ttake                => ctl_ttake        ,  -- IN    std_logic;
      ctl_tv                   => ctl_tv           ,  -- OUT   std_logic;
      ctl_td                   => ctl_td           ,  -- OUT   std_logic_vector(32-1 downto 0);
      ctl_tstop                => ctl_tstop        ,  -- IN    std_logic;
 
      -- Interrupter trigger
      CTL_irq                  => CTL_irq          ,  -- OUT   std_logic;
      ctl_status               => ctl_status       ,  -- OUT   std_logic_vector(32-1 downto 0);
 
      -- Fabric side - Common signals
      trn_clk                  => trn_clk          ,  -- IN    std_logic;
      protocol_rst             => ctl_reset           -- IN    std_logic
 
   );
 
 
   module_class_dlm:
   class_dlm
   PORT MAP(
      -- DLM Tx
      dlm2send_va              => dlm2send_va_i     ,  -- OUT   std_logic;
      dlm2send_type            => dlm2send_type_i   ,  -- OUT   std_logic_vector(4-1 downto 0);
 
      -- DLM Rx
      dlm_rec_va               => dlm_rec_va_i       ,  -- IN    std_logic;
      dlm_rec_type             => dlm_rec_type_i     ,  -- IN    std_logic_vector(4-1 downto 0);
 
      -- Common signals
      link_tx_clk              => link_tx_clk        ,  -- IN    std_logic;
      link_rx_clk              => link_tx_clk        ,  -- IN    std_logic;
 
 
      -- Fabric side - DLM Tx
      dlm_tv                   => dlm_tv          ,  -- IN    std_logic;
      dlm_td                   => dlm_td          ,  -- IN    std_logic_vector(4-1 downto 0);
 
      -- Fabric side - DLM Rx
      dlm_rv                   => dlm_rv          ,  -- OUT   std_logic;
      dlm_rd                   => dlm_rd          ,  -- OUT   std_logic_vector(4-1 downto 0);
 
      -- Interrupter trigger
      DLM_irq                  => DLM_irq         ,  -- OUT   std_logic;
 
      -- Fabric side - Common signals
      trn_clk                  => trn_clk         ,  -- IN    std_logic;
      protocol_rst             => protocol_rst       -- IN    std_logic
 
   );
 
 
end architecture Behavioral;

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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [protocol_if.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	11	barabba	`----------------------------------------------------------------------------------`
2			`-- Company: ziti`
3			`-- Engineer: wgao`
4			`--`
5			`-- Create Date: 17:01:32 19 Jun 2009`
6			`-- Design Name:`
7			`-- Module Name: protocol_IF - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`library work;`
26			`use work.abb64Package.all;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity protocol_IF is`
34			`-- Generic (`
35			`-- C_PRO_DAQ_WIDTH : integer := 16 ;`
36			`-- C_PRO_DLM_WIDTH : integer := 4 ;`
37			`-- C_PRO_CTL_WIDTH : integer := 16`
38			`-- );`
39			`Port (`
40
41			`-- DAQ Tx`
42			`data2send_start : OUT std_logic;`
43			`data2send_end : OUT std_logic;`
44			`data2send : OUT std_logic_vector(64-1 downto 0);`
45			`crc_error_send : OUT std_logic;`
46			`data2send_stop : IN std_logic;`
47
48			`-- DAQ Rx`
49			`data_rec_start : IN std_logic;`
50			`data_rec_end : IN std_logic;`
51			`data_rec : IN std_logic_vector(64-1 downto 0);`
52			`crc_error_rec : IN std_logic;`
53			`data_rec_stop : OUT std_logic;`
54
55			`-- -- [dg] DAQ Rx`
56			`-- dg_data_rec_start : IN std_logic;`
57			`-- dg_data_rec_end : IN std_logic;`
58			`-- dg_data_rec : IN std_logic_vector(16-1 downto 0);`
59			`-- dg_crc_error_rec : IN std_logic;`
60
61			`-- CTL Tx`
62			`ctrl2send_start : OUT std_logic;`
63			`ctrl2send_end : OUT std_logic;`
64			`ctrl2send : OUT std_logic_vector(16-1 downto 0);`
65			`ctrl2send_stop : IN std_logic;`
66
67			`-- CTL Rx`
68			`ctrl_rec_start : IN std_logic;`
69			`ctrl_rec_end : IN std_logic;`
70			`ctrl_rec : IN std_logic_vector(16-1 downto 0);`
71			`ctrl_rec_stop : OUT std_logic;`
72
73			`-- -- [dg] CTL Rx`
74			`-- dg_ctrl_rec_start : IN std_logic;`
75			`-- dg_ctrl_rec_end : IN std_logic;`
76			`-- dg_ctrl_rec : IN std_logic_vector(16-1 downto 0);`
77
78			`-- DLM Tx`
79			`dlm2send_va : OUT std_logic;`
80			`dlm2send_type : OUT std_logic_vector(4-1 downto 0);`
81
82			`-- DLM Rx`
83			`dlm_rec_va : IN std_logic;`
84			`dlm_rec_type : IN std_logic_vector(4-1 downto 0);`
85
86			`-- -- [dg] DLM Rx`
87			`-- dg_dlm_rec_va : IN std_logic;`
88			`-- dg_dlm_rec_type : IN std_logic_vector(4-1 downto 0);`
89
90			`-- Common signals`
91			`link_tx_clk : IN std_logic;`
92			`link_rx_clk : IN std_logic;`
93			`link_active : IN std_logic_vector(2-1 downto 0);`
94			`protocol_clk : OUT std_logic;`
95			`protocol_res_n : OUT std_logic;`
96
97			`-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --`
98
99			`-- Fabric side: DAQ Rx`
100			`daq_rv : IN std_logic;`
101			`daq_rsof : IN std_logic;`
102			`daq_reof : IN std_logic;`
103			`daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
104			`daq_rstop : OUT std_logic;`
105
106			`-- Fabric side: DAQ Tx`
107			`daq_tv : OUT std_logic;`
108			`daq_tsof : OUT std_logic;`
109			`daq_teof : OUT std_logic;`
110			`daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
111			`daq_tstop : IN std_logic;`
112
113			`-- Fabric side: CTL Rx`
114			`ctl_rv : IN std_logic;`
115			`ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
116			`ctl_rstop : OUT std_logic;`
117
118			`-- Fabric side: CTL Tx`
119			`ctl_ttake : IN std_logic;`
120			`ctl_tv : OUT std_logic;`
121			`ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
122			`ctl_tstop : IN std_logic;`
123
124			`ctl_reset : IN std_logic;`
125			`ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
126
127			`-- Fabric side: DLM Tx`
128			`dlm_tv : IN std_logic;`
129			`dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
130
131			`-- Fabric side: DLM Rx`
132			`dlm_rv : OUT std_logic;`
133			`dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
134
135			`-- Interrupter triggers`
136			`DAQ_irq : OUT std_logic;`
137			`CTL_irq : OUT std_logic;`
138			`DLM_irq : OUT std_logic;`
139
140			`-- Data generator table write port`
141			`tab_sel : IN STD_LOGIC;`
142			`tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);`
143			`tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);`
144			`tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);`
145
146			`-- DG control/status signal`
147			`dg_running : OUT STD_LOGIC;`
148			`dg_mask : IN STD_LOGIC;`
149			`dg_rst : IN STD_LOGIC;`
150
151			`-- DG debug signal`
152			`daq_start_led : OUT STD_LOGIC;`
153
154			`-- Fabric side: Common signals`
155			`trn_clk : IN std_logic;`
156			`protocol_link_act : OUT std_logic_vector(2-1 downto 0);`
157			`protocol_rst : IN std_logic`
158
159			`);`
160			`end entity protocol_IF;`
161
162
163			`architecture Behavioral of protocol_IF is`
164
165			`-- Data generator`
166			`COMPONENT abb_dgen`
167			`PORT (`
168			`-- Data generator table write port`
169			`tab_sel : IN STD_LOGIC;`
170			`tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);`
171			`tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);`
172			`tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);`
173
174
175			`-- DAQ Rx`
176			`data_rec_start : OUT std_logic;`
177			`data_rec_end : OUT std_logic;`
178			`data_rec : OUT std_logic_vector(64-1 downto 0);`
179			`crc_error_rec : OUT std_logic;`
180			`data_rec_stop : IN std_logic;`
181
182			`-- CTL Rx`
183			`ctrl_rec_start : OUT std_logic;`
184			`ctrl_rec_end : OUT std_logic;`
185			`ctrl_rec : OUT std_logic_vector(16-1 downto 0);`
186			`ctrl_rec_stop : IN std_logic;`
187
188			`-- DLM Rx`
189			`dlm_rec_va : OUT std_logic;`
190			`dlm_rec_type : OUT std_logic_vector(4-1 downto 0);`
191
192			`-- status signal`
193			`dg_running : OUT STD_LOGIC;`
194			`daq_start_led : OUT STD_LOGIC;`
195
196			`-- must signals`
197			`dg_clk : IN STD_LOGIC;`
198			`dg_mask : IN STD_LOGIC;`
199			`dg_rst : IN STD_LOGIC`
200			`);`
201			`END COMPONENT;`
202
203
204			`COMPONENT class_daq`
205			`PORT(`
206			`-- DAQ Tx`
207			`data2send_start : OUT std_logic;`
208			`data2send_end : OUT std_logic;`
209			`data2send : OUT std_logic_vector(64-1 downto 0);`
210			`crc_error_send : OUT std_logic;`
211			`data2send_stop : IN std_logic;`
212
213			`-- DAQ Rx`
214			`data_rec_start : IN std_logic;`
215			`data_rec_end : IN std_logic;`
216			`data_rec : IN std_logic_vector(64-1 downto 0);`
217			`crc_error_rec : IN std_logic;`
218			`data_rec_stop : OUT std_logic;`
219
220			`-- Common signals`
221			`link_tx_clk : IN std_logic;`
222			`link_rx_clk : IN std_logic;`
223
224
225			`-- Fabric side: DAQ Rx`
226			`daq_rv : IN std_logic;`
227			`daq_rsof : IN std_logic;`
228			`daq_reof : IN std_logic;`
229			`daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
230			`daq_rstop : OUT std_logic;`
231
232			`-- Fabric side: DAQ Tx`
233			`daq_tv : OUT std_logic;`
234			`daq_tsof : OUT std_logic;`
235			`daq_teof : OUT std_logic;`
236			`daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
237			`daq_tstop : IN std_logic;`
238
239			`-- Interrupter trigger`
240			`DAQ_irq : OUT std_logic;`
241
242			`-- Fabric side: Common signals`
243			`trn_clk : IN std_logic;`
244			`protocol_rst : IN std_logic`
245			`);`
246			`END COMPONENT;`
247
248			`COMPONENT class_ctl`
249			`PORT(`
250			`-- CTL Tx`
251			`ctrl2send_start : OUT std_logic;`
252			`ctrl2send_end : OUT std_logic;`
253			`ctrl2send : OUT std_logic_vector(16-1 downto 0);`
254			`ctrl2send_stop : IN std_logic;`
255
256			`-- CTL Rx`
257			`ctrl_rec_start : IN std_logic;`
258			`ctrl_rec_end : IN std_logic;`
259			`ctrl_rec : IN std_logic_vector(16-1 downto 0);`
260			`ctrl_rec_stop : OUT std_logic;`
261
262			`-- Common signals`
263			`link_active : IN std_logic_vector(2-1 downto 0);`
264			`link_tx_clk : IN std_logic;`
265			`link_rx_clk : IN std_logic;`
266
267
268			`-- Fabric side: CTL Rx`
269			`ctl_rv : IN std_logic;`
270			`ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
271			`ctl_rstop : OUT std_logic;`
272
273			`-- Fabric side: CTL Tx`
274			`ctl_ttake : IN std_logic;`
275			`ctl_tv : OUT std_logic;`
276			`ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
277			`ctl_tstop : IN std_logic;`
278
279			`-- Interrupter trigger`
280			`CTL_irq : OUT std_logic;`
281			`ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
282
283			`-- Fabric side: Common signals`
284			`trn_clk : IN std_logic;`
285			`protocol_rst : IN std_logic`
286			`);`
287			`END COMPONENT;`
288
289			`COMPONENT class_dlm`
290			`PORT(`
291			`-- DLM Tx`
292			`dlm2send_va : OUT std_logic;`
293			`dlm2send_type : OUT std_logic_vector(4-1 downto 0);`
294
295			`-- DLM Rx`
296			`dlm_rec_va : IN std_logic;`
297			`dlm_rec_type : IN std_logic_vector(4-1 downto 0);`
298
299			`-- Common signals`
300			`link_tx_clk : IN std_logic;`
301			`link_rx_clk : IN std_logic;`
302
303
304			`-- Fabric side: DLM Rx`
305			`dlm_tv : IN std_logic;`
306			`dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
307
308			`-- Fabric side: DLM Tx`
309			`dlm_rv : OUT std_logic;`
310			`dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
311
312			`-- Interrupter trigger`
313			`DLM_irq : OUT std_logic;`
314
315			`-- Fabric side: Common signals`
316			`trn_clk : IN std_logic;`
317			`protocol_rst : IN std_logic`
318			`);`
319			`END COMPONENT;`
320
321			`-- Protocol module reset`
322			`signal protocol_link_act_i : std_logic_vector(2-1 downto 0);`
323
324			`-- Flow control signals`
325			`signal data_rec_stop_i : std_logic;`
326			`signal ctrl_rec_stop_i : std_logic;`
327
328
329			`-- DAQ Tx`
330			`signal data2send_start_i : std_logic;`
331			`signal data2send_end_i : std_logic;`
332			`signal data2send_i : std_logic_vector(64-1 downto 0);`
333			`signal crc_error_send_i : std_logic;`
334			`signal data2send_stop_i : std_logic;`
335
336			`-- CTL Tx`
337			`signal ctrl2send_start_i : std_logic;`
338			`signal ctrl2send_end_i : std_logic;`
339			`signal ctrl2send_i : std_logic_vector(16-1 downto 0);`
340			`signal ctrl2send_stop_i : std_logic;`
341
342			`-- DLM Tx`
343			`signal dlm2send_va_i : std_logic;`
344			`signal dlm2send_type_i : std_logic_vector(4-1 downto 0);`
345
346			`-- [dg] DAQ Rx`
347			`signal dg_data_rec_start : std_logic;`
348			`signal dg_data_rec_end : std_logic;`
349			`signal dg_data_rec : std_logic_vector(64-1 downto 0);`
350			`signal dg_crc_error_rec : std_logic;`
351
352			`-- [dg] CTL Rx`
353			`signal dg_ctrl_rec_start : std_logic;`
354			`signal dg_ctrl_rec_end : std_logic;`
355			`signal dg_ctrl_rec : std_logic_vector(16-1 downto 0);`
356
357			`-- [dg] DLM Rx`
358			`signal dg_dlm_rec_va : std_logic;`
359			`signal dg_dlm_rec_type : std_logic_vector(4-1 downto 0);`
360
361			`-- DAQ Rx wire`
362			`signal data_rec_start_i : std_logic;`
363			`signal data_rec_end_i : std_logic;`
364			`signal data_rec_i : std_logic_vector(64-1 downto 0);`
365			`signal crc_error_rec_i : std_logic;`
366
367			`-- CTL Rx wire`
368			`signal ctrl_rec_start_i : std_logic;`
369			`signal ctrl_rec_end_i : std_logic;`
370			`signal ctrl_rec_i : std_logic_vector(16-1 downto 0);`
371
372			`-- DLM Rx wire`
373			`signal dlm_rec_va_i : std_logic;`
374			`signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);`
375
376
377			`begin`
378
379			`protocol_clk <= trn_clk;`
380			`protocol_res_n <= not protocol_rst;`
381			`protocol_link_act <= protocol_link_act_i;`
382
383			`data2send_start <= (data2send_start_i or dg_data_rec_start);`
384			`data2send_end <= (data2send_end_i or dg_data_rec_end );`
385			`data2send <= (data2send_i or dg_data_rec );`
386			`crc_error_send <= (crc_error_send_i or dg_crc_error_rec );`
387			`data2send_stop_i <= data2send_stop ;`
388
389			`data_rec_start_i <= data_rec_start ;`
390			`data_rec_end_i <= data_rec_end ;`
391			`data_rec_i <= data_rec ;`
392			`crc_error_rec_i <= crc_error_rec ;`
393			`data_rec_stop <= data_rec_stop_i;`
394
395			`ctrl2send_start <= (ctrl2send_start_i or dg_ctrl_rec_start );`
396			`ctrl2send_end <= (ctrl2send_end_i or dg_ctrl_rec_end );`
397			`ctrl2send <= (ctrl2send_i or dg_ctrl_rec );`
398			`ctrl2send_stop_i <= ctrl2send_stop ;`
399
400			`ctrl_rec_start_i <= ctrl_rec_start ;`
401			`ctrl_rec_end_i <= ctrl_rec_end ;`
402			`ctrl_rec_i <= ctrl_rec ;`
403			`ctrl_rec_stop <= ctrl_rec_stop_i;`
404
405			`dlm2send_va <= (dlm2send_va_i or dg_dlm_rec_va );`
406			`dlm2send_type <= (dlm2send_type_i or dg_dlm_rec_type );`
407
408			`dlm_rec_va_i <= dlm_rec_va ;`
409			`dlm_rec_type_i <= dlm_rec_type ;`
410
411
412			`-- Protocol link active signal register`
413			`Synch_protocol_link_act:`
414			`process (trn_clk )`
415			`begin`
416			`if trn_clk'event and trn_clk = '1' then`
417			`protocol_link_act_i <= link_active;`
418			`end if;`
419			`end process;`
420
421
422			`-- Data generator implementation`
423			`Gen_DataGen: if IMP_DATA_GENERATOR generate`
424
425			`data_generator_0:`
426			`abb_dgen`
427			`port map (`
428			`-- Data generator table write port`
429			`tab_sel => '1' , -- IN STD_LOGIC;`
430			`tab_we => tab_we , -- IN STD_LOGIC_VECTOR (8-1 downto 0);`
431			`tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);`
432			`tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);`
433
434			`-- DAQ Rx`
435			`data_rec_start => dg_data_rec_start , -- OUT std_logic;`
436			`data_rec_end => dg_data_rec_end , -- OUT std_logic;`
437			`data_rec => dg_data_rec , -- OUT std_logic_vector(16-1 downto 0);`
438			`crc_error_rec => dg_crc_error_rec , -- OUT std_logic;`
439			`data_rec_stop => data_rec_stop_i , -- IN std_logic;`
440
441			`-- CTL Rx`
442			`ctrl_rec_start => dg_ctrl_rec_start , -- OUT std_logic;`
443			`ctrl_rec_end => dg_ctrl_rec_end , -- OUT std_logic;`
444			`ctrl_rec => dg_ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);`
445			`ctrl_rec_stop => ctrl_rec_stop_i , -- IN std_logic;`
446
447			`-- DLM Rx`
448			`dlm_rec_va => dg_dlm_rec_va , -- OUT std_logic;`
449			`dlm_rec_type => dg_dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);`
450
451			`-- status signals`
452			`dg_running => dg_running , -- OUT STD_LOGIC;`
453			`daq_start_led => daq_start_led , -- OUT STD_LOGIC;`
454
455			`-- common signals`
456			`dg_clk => trn_clk , -- IN STD_LOGIC;`
457			`dg_mask => dg_mask , -- IN STD_LOGIC;`
458			`dg_rst => dg_rst -- IN STD_LOGIC`
459			`);`
460
461			`end generate;`
462
463
464			`-- No data generator implementation`
465			`NotGen_DataGen: if not IMP_DATA_GENERATOR generate`
466
467			`-- debug signal`
468			`daq_start_led <= '0';`
469
470			`-- DAQ Rx`
471			`dg_data_rec_start <= '0';`
472			`dg_data_rec_end <= '0';`
473			`dg_data_rec <= (OTHERS=>'0');`
474			`dg_crc_error_rec <= '0';`
475
476			`-- CTL Rx`
477			`dg_ctrl_rec_start <= '0';`
478			`dg_ctrl_rec_end <= '0';`
479			`dg_ctrl_rec <= (OTHERS=>'0');`
480
481			`-- DLM Rx`
482			`dg_dlm_rec_va <= '0';`
483			`dg_dlm_rec_type <= (OTHERS=>'0');`
484
485			`end generate;`
486
487
488
489			`module_class_daq:`
490			`class_daq`
491			`PORT MAP(`
492			`-- DAQ Tx`
493			`data2send_start => data2send_start_i , -- OUT std_logic;`
494			`data2send_end => data2send_end_i , -- OUT std_logic;`
495			`data2send => data2send_i , -- OUT std_logic_vector(16-1 downto 0);`
496			`crc_error_send => crc_error_send_i , -- OUT std_logic;`
497			`data2send_stop => data2send_stop_i , -- IN std_logic;`
498
499			`-- DAQ Rx`
500			`data_rec_start => data_rec_start_i , -- IN std_logic;`
501			`data_rec_end => data_rec_end_i , -- IN std_logic;`
502			`data_rec => data_rec_i , -- IN std_logic_vector(16-1 downto 0);`
503			`crc_error_rec => crc_error_rec_i , -- IN std_logic;`
504			`data_rec_stop => data_rec_stop_i , -- OUT std_logic;`
505
506			`-- Common signals`
507			`link_tx_clk => link_tx_clk , -- IN std_logic;`
508			`link_rx_clk => link_tx_clk , -- IN std_logic;`
509
510
511			`-- Fabric side - DAQ Rx`
512			`daq_rv => daq_rv , -- IN std_logic;`
513			`daq_rsof => daq_rsof , -- IN std_logic;`
514			`daq_reof => daq_reof , -- IN std_logic;`
515			`daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);`
516			`daq_rstop => daq_rstop , -- OUT std_logic;`
517
518			`-- Fabric side - DAQ Tx`
519			`daq_tv => daq_tv , -- OUT std_logic;`
520			`daq_tsof => daq_tsof , -- OUT std_logic;`
521			`daq_teof => daq_teof , -- OUT std_logic;`
522			`daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);`
523			`daq_tstop => daq_tstop , -- IN std_logic;`
524
525			`-- Interrupter trigger`
526			`DAQ_irq => DAQ_irq , -- OUT std_logic;`
527
528			`-- Fabric side - Common signals`
529			`trn_clk => trn_clk , -- IN std_logic;`
530			`protocol_rst => protocol_rst -- IN std_logic`
531			`);`
532
533
534
535			`module_class_ctl:`
536			`class_ctl`
537			`PORT MAP(`
538			`-- CTL Tx`
539			`ctrl2send_start => ctrl2send_start_i , -- OUT std_logic;`
540			`ctrl2send_end => ctrl2send_end_i , -- OUT std_logic;`
541			`ctrl2send => ctrl2send_i , -- OUT std_logic_vector(32-1 downto 0);`
542			`ctrl2send_stop => ctrl2send_stop_i , -- IN std_logic;`
543
544			`-- CTL Rx`
545			`ctrl_rec_start => ctrl_rec_start_i , -- IN std_logic;`
546			`ctrl_rec_end => ctrl_rec_end_i , -- IN std_logic;`
547			`ctrl_rec => ctrl_rec_i , -- IN std_logic_vector(32-1 downto 0);`
548			`ctrl_rec_stop => ctrl_rec_stop_i , -- OUT std_logic;`
549
550			`-- Common signals`
551			`link_active => link_active , -- IN std_logic_vector(2-1 downto 0);`
552			`link_tx_clk => link_tx_clk , -- IN std_logic;`
553			`link_rx_clk => link_tx_clk , -- IN std_logic;`
554
555
556			`-- Fabric side - CTL Rx`
557			`ctl_rv => ctl_rv , -- IN std_logic;`
558			`ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);`
559			`ctl_rstop => ctl_rstop , -- OUT std_logic;`
560
561			`-- Fabric side - CTL Tx`
562			`ctl_ttake => ctl_ttake , -- IN std_logic;`
563			`ctl_tv => ctl_tv , -- OUT std_logic;`
564			`ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);`
565			`ctl_tstop => ctl_tstop , -- IN std_logic;`
566
567			`-- Interrupter trigger`
568			`CTL_irq => CTL_irq , -- OUT std_logic;`
569			`ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);`
570
571			`-- Fabric side - Common signals`
572			`trn_clk => trn_clk , -- IN std_logic;`
573			`protocol_rst => ctl_reset -- IN std_logic`
574
575			`);`
576
577
578			`module_class_dlm:`
579			`class_dlm`
580			`PORT MAP(`
581			`-- DLM Tx`
582			`dlm2send_va => dlm2send_va_i , -- OUT std_logic;`
583			`dlm2send_type => dlm2send_type_i , -- OUT std_logic_vector(4-1 downto 0);`
584
585			`-- DLM Rx`
586			`dlm_rec_va => dlm_rec_va_i , -- IN std_logic;`
587			`dlm_rec_type => dlm_rec_type_i , -- IN std_logic_vector(4-1 downto 0);`
588
589			`-- Common signals`
590			`link_tx_clk => link_tx_clk , -- IN std_logic;`
591			`link_rx_clk => link_tx_clk , -- IN std_logic;`
592
593
594			`-- Fabric side - DLM Tx`
595			`dlm_tv => dlm_tv , -- IN std_logic;`
596			`dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);`
597
598			`-- Fabric side - DLM Rx`
599			`dlm_rv => dlm_rv , -- OUT std_logic;`
600			`dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);`
601
602			`-- Interrupter trigger`
603			`DLM_irq => DLM_irq , -- OUT std_logic;`
604
605			`-- Fabric side - Common signals`
606			`trn_clk => trn_clk , -- IN std_logic;`
607			`protocol_rst => protocol_rst -- IN std_logic`
608
609			`);`
610
611
612			`end architecture Behavioral;`