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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [RxIn_Delays.vhd] - Blame information for rev 13

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1 13 barabba
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Design Name: 
6
-- Module Name:    RxIn_Delay - Behavioral 
7
-- Project Name: 
8
-- Target Devices: 
9
-- Tool versions: 
10
-- Description: 
11
--
12
-- Dependencies: 
13
--
14
-- Revision 1.10 - MAX_SIZE_EXCEEDED recalculated for better timing. 31.03.2008
15
-- 
16
-- Revision 1.00 - first release. 20.02.2007
17
-- 
18
-- Additional Comments: Virtual channels resolution.
19
--
20
----------------------------------------------------------------------------------
21
 
22
library IEEE;
23
use IEEE.STD_LOGIC_1164.ALL;
24
use IEEE.STD_LOGIC_ARITH.ALL;
25
use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
 
27
library work;
28
use work.abb64Package.all;
29
 
30
-- Uncomment the following library declaration if instantiating
31
-- any Xilinx primitives in this code.
32
--library UNISIM;
33
--use UNISIM.VComponents.all;
34
 
35
entity RxIn_Delay is
36
    port (
37
      -- Common ports
38
      trn_clk            : IN  std_logic;
39
      trn_reset_n        : IN  std_logic;
40
      trn_lnk_up_n       : IN  std_logic;
41
 
42
      -- Transaction receive interface
43
      trn_rsof_n         : IN  std_logic;
44
      trn_reof_n         : IN  std_logic;
45
      trn_rd             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
46
      trn_rrem_n         : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
47
      trn_rerrfwd_n      : IN  std_logic;
48
      trn_rsrc_rdy_n     : IN  std_logic;
49
      trn_rsrc_dsc_n     : IN  std_logic;
50
      trn_rbar_hit_n     : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
51
      trn_rdst_rdy_n     : OUT std_logic;
52
      Pool_wrBuf_full    : IN  std_logic;
53
      Link_Buf_full      : IN  std_logic;
54
 
55
      -- Delay for one clock
56
      trn_rsof_n_dly     : OUT std_logic;
57
      trn_reof_n_dly     : OUT std_logic;
58
      trn_rd_dly         : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
59
      trn_rrem_n_dly     : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
60
      trn_rerrfwd_n_dly  : OUT std_logic;
61
      trn_rsrc_rdy_n_dly : OUT std_logic;
62
      trn_rdst_rdy_n_dly : OUT std_logic;
63
      trn_rsrc_dsc_n_dly : OUT std_logic;
64
      trn_rbar_hit_n_dly : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
65
 
66
 
67
      -- TLP resolution
68
      IORd_Type          : OUT std_logic;
69
      IOWr_Type          : OUT std_logic;
70
      MRd_Type           : OUT std_logic_vector(3 downto 0);
71
      MWr_Type           : OUT std_logic_vector(1 downto 0);
72
      CplD_Type          : OUT std_logic_vector(3 downto 0);
73
 
74
      -- From Cpl/D channel
75
      usDMA_dex_Tag      : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
76
      dsDMA_dex_Tag      : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
77
 
78
      -- To Memory request process modules
79
      Tlp_straddles_4KB  : OUT std_logic;
80
 
81
      -- To Cpl/D channel
82
      Tlp_has_4KB        : OUT std_logic;
83
      Tlp_has_1DW        : OUT std_logic;
84
      CplD_is_the_Last   : OUT std_logic;
85
      CplD_on_Pool       : OUT std_logic;
86
      CplD_on_EB         : OUT std_logic;
87
      Req_ID_Match       : OUT std_logic;
88
      usDex_Tag_Matched  : OUT std_logic;
89
      dsDex_Tag_Matched  : OUT std_logic;
90
      CplD_Tag           : OUT std_logic_vector(C_TAG_WIDTH-1 downto  0);
91
 
92
 
93
      -- Additional
94
      cfg_dcommand       : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
95
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
96
    );
97
 
98
end entity RxIn_Delay;
99
 
100
 
101
 
102
architecture Behavioral of RxIn_Delay is
103
 
104
 
105
-- Max Length Checking
106
   signal   Tlp_has_0_Length       :  std_logic;
107
   signal   Tlp_has_1DW_Length_i   :  std_logic;
108
   signal   MaxReadReqSize_Exceeded:  std_logic;
109
   signal   MaxPayloadSize_Exceeded:  std_logic;
110
 
111
   signal   Tlp_straddles_4KB_i    :  std_logic;
112
   signal   CarryIn_ALC            :  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
113
   signal   Tlp_has_4KB_i          :  std_logic;
114
   signal   cfg_MRS                :  std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
115
   signal   cfg_MPS                :  std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
116
 
117
   signal   cfg_MRS_decoded        :  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
118
   signal   cfg_MPS_decoded        :  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
119
 
120
   TYPE     CfgThreshold is ARRAY (C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE downto 0)
121
                                   of std_logic_vector (C_TLP_FLD_WIDTH_OF_LENG downto 0);
122
 
123
   signal   MaxSize_Thresholds     : CfgThreshold;
124
 
125
-- As one clock of delay
126
   signal   trn_rsof_n_r1          :  std_logic;
127
   signal   trn_reof_n_r1          :  std_logic;
128
   signal   trn_rrem_n_r1          :  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
129
   signal   trn_rd_r1              :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
130
   signal   trn_rerrfwd_n_r1       :  std_logic;
131
   signal   trn_rsrc_rdy_n_r1      :  std_logic;
132
   signal   trn_rdst_rdy_n_i       :  std_logic;
133
   signal   trn_rdst_rdy_n_r1      :  std_logic;
134
   signal   trn_rsrc_dsc_n_r1      :  std_logic;
135
   signal   trn_rbar_hit_n_r1      :  std_logic_vector(C_BAR_NUMBER-1 downto 0);
136
 
137
-- TLP type decision
138
   signal   TLP_is_MRd_BAR0_H3DW   :  std_logic;
139
   signal   TLP_is_MRd_BAR1_H3DW   :  std_logic;
140
   signal   TLP_is_MRd_BAR2_H3DW   :  std_logic;
141
   signal   TLP_is_MRd_BAR3_H3DW   :  std_logic;
142
 
143
   signal   TLP_is_MRd_BAR0_H4DW   :  std_logic;
144
   signal   TLP_is_MRd_BAR1_H4DW   :  std_logic;
145
   signal   TLP_is_MRd_BAR2_H4DW   :  std_logic;
146
   signal   TLP_is_MRd_BAR3_H4DW   :  std_logic;
147
 
148
   signal   TLP_is_MRdLk_BAR0_H3DW :  std_logic;
149
   signal   TLP_is_MRdLk_BAR1_H3DW :  std_logic;
150
   signal   TLP_is_MRdLk_BAR2_H3DW :  std_logic;
151
   signal   TLP_is_MRdLk_BAR3_H3DW :  std_logic;
152
 
153
   signal   TLP_is_MRdLk_BAR0_H4DW :  std_logic;
154
   signal   TLP_is_MRdLk_BAR1_H4DW :  std_logic;
155
   signal   TLP_is_MRdLk_BAR2_H4DW :  std_logic;
156
   signal   TLP_is_MRdLk_BAR3_H4DW :  std_logic;
157
 
158
   signal   TLP_is_MWr_BAR0_H3DW   :  std_logic;
159
   signal   TLP_is_MWr_BAR1_H3DW   :  std_logic;
160
   signal   TLP_is_MWr_BAR2_H3DW   :  std_logic;
161
   signal   TLP_is_MWr_BAR3_H3DW   :  std_logic;
162
 
163
   signal   TLP_is_MWr_BAR0_H4DW   :  std_logic;
164
   signal   TLP_is_MWr_BAR1_H4DW   :  std_logic;
165
   signal   TLP_is_MWr_BAR2_H4DW   :  std_logic;
166
   signal   TLP_is_MWr_BAR3_H4DW   :  std_logic;
167
 
168
   signal   TLP_is_IORd_BAR0       :  std_logic;
169
   signal   TLP_is_IORd_BAR1       :  std_logic;
170
   signal   TLP_is_IORd_BAR2       :  std_logic;
171
   signal   TLP_is_IORd_BAR3       :  std_logic;
172
 
173
   signal   TLP_is_IOWr_BAR0       :  std_logic;
174
   signal   TLP_is_IOWr_BAR1       :  std_logic;
175
   signal   TLP_is_IOWr_BAR2       :  std_logic;
176
   signal   TLP_is_IOWr_BAR3       :  std_logic;
177
 
178
   signal   TLP_is_IORd            :  std_logic;
179
   signal   TLP_is_IOWr            :  std_logic;
180
 
181
   signal   TLP_is_CplD            :  std_logic;
182
   signal   TLP_is_Cpl             :  std_logic;
183
   signal   TLP_is_CplDLk          :  std_logic;
184
   signal   TLP_is_CplLk           :  std_logic;
185
 
186
 
187
   signal   TLP_is_MRd_H3DW        :  std_logic;
188
   signal   TLP_is_MRd_H4DW        :  std_logic;
189
   signal   TLP_is_MRdLk_H3DW      :  std_logic;
190
   signal   TLP_is_MRdLk_H4DW      :  std_logic;
191
 
192
   signal   TLP_is_MWr_H3DW        :  std_logic;
193
   signal   TLP_is_MWr_H4DW        :  std_logic;
194
 
195
 
196
   signal   IORd_Type_i            :  std_logic;
197
   signal   IOWr_Type_i            :  std_logic;
198
   signal   MRd_Type_i             :  std_logic_vector(3 downto 0);
199
   signal   MWr_Type_i             :  std_logic_vector(1 downto 0);
200
   signal   CplD_Type_i            :  std_logic_vector(3 downto 0);
201
 
202
   signal   Req_ID_Match_i         :  std_logic;
203
 
204
   signal   usDex_Tag_Matched_i    :  std_logic;
205
   signal   dsDex_Tag_Matched_i    :  std_logic;
206
 
207
 
208
   -----------------------------------------------------------------
209
   -- Inbound DW counter
210
   signal   TLP_Payload_Address_i  : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
211
   signal   TLP_DW_Length_i        : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
212
   signal   TLP_Address_sig        : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG   downto 0);
213
   signal   MWr_on_Pool            :  std_logic;
214
   signal   MWr_on_EB              :  std_logic;
215
   signal   CplD_on_Pool_i         : std_logic;
216
   signal   CplD_on_EB_i           : std_logic;
217
   signal   CplD_is_the_Last_i     : std_logic;
218
   signal   CplD_Tag_i             : std_logic_vector(C_TAG_WIDTH-1 downto  0);
219
 
220
   --   Counter inside a TLP
221
   type TLPCntStates is            ( TK_RST
222
                                   , TK_Idle
223
--                                   , TK_MWr_3Hdr_B
224
                                   , TK_MWr_3Hdr_C
225
--                                   , TK_MWr_4Hdr_B
226
                                   , TK_MWr_4Hdr_C
227
--                                   , TK_MWr_4Hdr_D
228
--                                   , TK_CplD_Hdr_B
229
                                   , TK_CplD_Hdr_C
230
                                   , TK_Body
231
                                   );
232
 
233
   signal FSM_TLP_Cnt              : TLPCntStates;
234
 
235
   signal FSM_TLP_Cnt_r1           : TLPCntStates;
236
 
237
   --   CplD tag capture FSM (Address at tRAM)
238
   type AddrOnRAM_States is        ( AOtSt_RST
239
                                   , AOtSt_Idle
240
                                   , AOtSt_HdrA
241
                                   , AOtSt_HdrB
242
                                   , AOtSt_Body
243
                                   );
244
 
245
   signal FSM_AOtRAM               : AddrOnRAM_States;
246
 
247
 
248
begin
249
 
250
   trn_rdst_rdy_n        <=  trn_rdst_rdy_n_i     ;   -- and trn_rsof_n and trn_rsof_n_r1  ;
251
 
252
   -- Delay
253
   trn_rsof_n_dly        <=  trn_rsof_n_r1        ;
254
   trn_reof_n_dly        <=  trn_reof_n_r1        ;
255
   trn_rrem_n_dly        <=  trn_rrem_n_r1        ;
256
   trn_rd_dly            <=  trn_rd_r1            ;
257
   trn_rerrfwd_n_dly     <=  trn_rerrfwd_n_r1     ;
258
   trn_rsrc_rdy_n_dly    <=  trn_rsrc_rdy_n_r1    ;
259
   trn_rdst_rdy_n_dly    <=  trn_rdst_rdy_n_r1    ;   -- trn_rdst_rdy_n_r1    ;
260
   trn_rsrc_dsc_n_dly    <=  trn_rsrc_dsc_n_r1    ;
261
   trn_rbar_hit_n_dly    <=  trn_rbar_hit_n_r1    ;
262
 
263
 
264
   -- TLP resolution
265
   IORd_Type             <=  '0' ;                 -- IORd_Type_i          ;
266
   IOWr_Type             <=  '0' ;                 -- IOWr_Type_i          ;
267
   MRd_Type              <=  MRd_Type_i           ;
268
   MWr_Type              <=  MWr_Type_i           ;
269
   CplD_Type             <=  CplD_Type_i          ;
270
 
271
   -- To Cpl/D channel
272
   Req_ID_Match          <=  Req_ID_Match_i       ;
273
 
274
   usDex_Tag_Matched     <=  usDex_Tag_Matched_i  ;
275
   dsDex_Tag_Matched     <=  dsDex_Tag_Matched_i  ;
276
 
277
   CplD_Tag              <=  CplD_Tag_i           ;
278
   CplD_is_the_Last      <=  CplD_is_the_Last_i   ;
279
   CplD_on_Pool          <=  CplD_on_Pool_i       ;
280
   CplD_on_EB            <=  CplD_on_EB_i         ;
281
 
282
 
283
   Tlp_has_4KB           <=  Tlp_has_4KB_i        ;
284
   Tlp_has_1DW           <=  Tlp_has_1DW_Length_i ;
285
 
286
   Tlp_straddles_4KB     <=  '0';                  --Tlp_straddles_4KB_i  ;
287
 
288
 
289
   --  !! !! 
290
   MaxReadReqSize_Exceeded  <=  '0';
291
   MaxPayloadSize_Exceeded  <=  '0';
292
 
293
 
294
 
295
----------------------------------------------
296
--
297
-- Synchronous Registered: TLP_DW_Length
298
--                         Tlp_has_4KB
299
--                         Tlp_has_1DW_Length
300
--                         Tlp_has_0_Length
301
--
302
   FSM_TLP_1ST_DW_Info:
303
   process ( trn_clk, trn_reset_n)
304
   begin
305
      if trn_reset_n = '0' then
306
         TLP_DW_Length_i        <= (OTHERS => '0');
307
         Tlp_has_4KB_i          <= '0';
308
         Tlp_has_1DW_Length_i   <= '0';
309
         Tlp_has_0_Length       <= '0';
310
 
311
      elsif trn_clk'event and trn_clk = '1' then
312
         if trn_rsof_n='0' then
313
            TLP_DW_Length_i        <= trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
314
         else
315
            TLP_DW_Length_i        <= TLP_DW_Length_i;
316
         end if;
317
 
318
         if trn_rsof_n ='0' then
319
            if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) then
320
               Tlp_has_4KB_i <= '1' ;
321
            else
322
               Tlp_has_4KB_i <= '0' ;
323
            end if;
324
         else
325
            Tlp_has_4KB_i <= Tlp_has_4KB_i ;
326
         end if;
327
 
328
         if trn_rsof_n ='0' then
329
            if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
330
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
331
               Tlp_has_1DW_Length_i  <= '1';
332
            else
333
               Tlp_has_1DW_Length_i  <= '0';
334
            end if;
335
         else
336
            Tlp_has_1DW_Length_i  <= Tlp_has_1DW_Length_i;
337
         end if;
338
 
339
         if trn_rsof_n ='0' then
340
            if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
341
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
342
               and trn_rd(2)='0' then
343
               Tlp_has_0_Length  <= '1';
344
            else
345
               Tlp_has_0_Length  <= '0';
346
            end if;
347
         else
348
            Tlp_has_0_Length  <= Tlp_has_0_Length;
349
         end if;
350
 
351
      end if;
352
   end process;
353
 
354
 
355
 
356
---- --------------------------------------------------------------------------
357
--   -- Max Payload Size bits
358
--   cfg_MPS               <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
359
--
360
--   -- Max Read Request Size bits
361
--   cfg_MRS               <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
362
--
363
--
364
--
365
--   -- --------------------------------
366
--   -- Decoding MPS
367
--   --
368
--   Trn_Rx_Decoding_MPS:
369
--   process ( trn_clk )
370
--   begin
371
--      if trn_clk'event and trn_clk = '1' then
372
--
373
--         case cfg_MPS is
374
--           when CONV_STD_LOGIC_VECTOR(0, 3) =>
375
--              cfg_MPS_decoded   <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
376
--
377
--           when CONV_STD_LOGIC_VECTOR(1, 3) =>
378
--              cfg_MPS_decoded   <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
379
--
380
--           when CONV_STD_LOGIC_VECTOR(2, 3) =>
381
--              cfg_MPS_decoded   <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
382
--
383
--           when CONV_STD_LOGIC_VECTOR(3, 3) =>
384
--              cfg_MPS_decoded   <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
385
--
386
--           when CONV_STD_LOGIC_VECTOR(4, 3) =>
387
--              cfg_MPS_decoded   <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
388
--
389
--           when CONV_STD_LOGIC_VECTOR(5, 3) =>
390
--              cfg_MPS_decoded   <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
391
--
392
--           when Others =>
393
--              cfg_MPS_decoded   <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
394
--
395
--         end case;
396
--
397
--      end if;
398
--   end process;
399
--
400
--
401
--   -- --------------------------------
402
--   -- Decoding MRS
403
--   --
404
--   Trn_Rx_Decoding_MRS:
405
--   process ( trn_clk )
406
--   begin
407
--      if trn_clk'event and trn_clk = '1' then
408
--
409
--         case cfg_MRS is
410
--           when CONV_STD_LOGIC_VECTOR(0, 3) =>
411
--              cfg_MRS_decoded   <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
412
--
413
--           when CONV_STD_LOGIC_VECTOR(1, 3) =>
414
--              cfg_MRS_decoded   <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
415
--
416
--           when CONV_STD_LOGIC_VECTOR(2, 3) =>
417
--              cfg_MRS_decoded   <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
418
--
419
--           when CONV_STD_LOGIC_VECTOR(3, 3) =>
420
--              cfg_MRS_decoded   <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
421
--
422
--           when CONV_STD_LOGIC_VECTOR(4, 3) =>
423
--              cfg_MRS_decoded   <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
424
--
425
--           when CONV_STD_LOGIC_VECTOR(5, 3) =>
426
--              cfg_MRS_decoded   <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
427
--
428
--           when Others =>
429
--              cfg_MRS_decoded   <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
430
--
431
--         end case;
432
--
433
--      end if;
434
--   end process;
435
--
436
--
437
--   -------------------------------------------------------------
438
--   MaxSize_Thresholds(0) <= (CBIT_SENSE_OF_MAXSIZE=>'1', Others=>'0');
439
--   Gen_MaxSizes:
440
--   FOR i IN 1 TO C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE GENERATE
441
--     MaxSize_Thresholds(i) <= MaxSize_Thresholds(i-1)(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)&'0';
442
--   END GENERATE;
443
--
444
--   -- --------------------------------
445
--   -- Calculation of MPS exceed
446
--   --
447
--   Trn_Rx_MaxPayloadSize_Exceeded:
448
--   process ( trn_clk )
449
--   begin
450
--      if trn_clk'event and trn_clk = '1' then
451
--
452
--         case cfg_MPS_decoded is
453
--
454
----           when CONV_STD_LOGIC_VECTOR(1, 6)  =>   -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
455
----             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
456
----                MaxPayloadSize_Exceeded <= '1';
457
----             else
458
----                MaxPayloadSize_Exceeded <= '0';
459
----             end if;
460
--
461
--           when CONV_STD_LOGIC_VECTOR(2, 6)  =>   -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
462
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
463
--                MaxPayloadSize_Exceeded <= '1';
464
--             else
465
--                MaxPayloadSize_Exceeded <= '0';
466
--             end if;
467
--
468
--           when CONV_STD_LOGIC_VECTOR(4, 6)  =>   -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
469
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
470
--                MaxPayloadSize_Exceeded <= '1';
471
--             else
472
--                MaxPayloadSize_Exceeded <= '0';
473
--             end if;
474
--
475
--           when CONV_STD_LOGIC_VECTOR(8, 6)  =>   -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
476
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
477
--                MaxPayloadSize_Exceeded <= '1';
478
--             else
479
--                MaxPayloadSize_Exceeded <= '0';
480
--             end if;
481
--
482
--           when CONV_STD_LOGIC_VECTOR(16, 6)  =>   -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
483
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
484
--                MaxPayloadSize_Exceeded <= '1';
485
--             else
486
--                MaxPayloadSize_Exceeded <= '0';
487
--             end if;
488
--
489
--           when CONV_STD_LOGIC_VECTOR(32, 6)  =>   -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
490
--                MaxPayloadSize_Exceeded <= '0';            -- !!
491
--
492
--           when OTHERS  =>
493
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
494
--                MaxPayloadSize_Exceeded <= '1';
495
--             else
496
--                MaxPayloadSize_Exceeded <= '0';
497
--             end if;
498
--
499
--        end case;
500
--
501
--      end if;
502
--   end process;
503
--
504
--
505
--   -- --------------------------------
506
--   -- Calculation of MRS exceed
507
--   --
508
--   Trn_Rx_MaxReadReqSize_Exceeded:
509
--   process ( trn_clk )
510
--   begin
511
--      if trn_clk'event and trn_clk = '1' then
512
--
513
--         case cfg_MRS_decoded is
514
--
515
----           when CONV_STD_LOGIC_VECTOR(1, 6)  =>   -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
516
----             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
517
----                MaxReadReqSize_Exceeded <= '1';
518
----             else
519
----                MaxReadReqSize_Exceeded <= '0';
520
----             end if;
521
--
522
--           when CONV_STD_LOGIC_VECTOR(2, 6)  =>   -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
523
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
524
--                MaxReadReqSize_Exceeded <= '1';
525
--             else
526
--                MaxReadReqSize_Exceeded <= '0';
527
--             end if;
528
--
529
--           when CONV_STD_LOGIC_VECTOR(4, 6)  =>   -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
530
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
531
--                MaxReadReqSize_Exceeded <= '1';
532
--             else
533
--                MaxReadReqSize_Exceeded <= '0';
534
--             end if;
535
--
536
--           when CONV_STD_LOGIC_VECTOR(8, 6)  =>   -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
537
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
538
--                MaxReadReqSize_Exceeded <= '1';
539
--             else
540
--                MaxReadReqSize_Exceeded <= '0';
541
--             end if;
542
--
543
--           when CONV_STD_LOGIC_VECTOR(16, 6)  =>   -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
544
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
545
--                MaxReadReqSize_Exceeded <= '1';
546
--             else
547
--                MaxReadReqSize_Exceeded <= '0';
548
--             end if;
549
--
550
--           when CONV_STD_LOGIC_VECTOR(32, 6)  =>   -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
551
--                MaxReadReqSize_Exceeded <= '0';            -- !!
552
--
553
--           when OTHERS  =>
554
--             if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
555
--                MaxReadReqSize_Exceeded <= '1';
556
--             else
557
--                MaxReadReqSize_Exceeded <= '0';
558
--             end if;
559
--
560
--        end case;
561
--
562
--      end if;
563
--   end process;
564
 
565
 
566
 
567
 
568
   --    ---------------------------------------------------------
569
   ----  Pipelining all trn_rx input signals for one clock
570
   ----    to get better timing
571
   ---- 
572
   Trn_Rx_Inputs_Delayed:
573
   process ( trn_clk )
574
   begin
575
      if trn_clk'event and trn_clk = '1' then
576
         trn_rsof_n_r1      <= trn_rsof_n;
577
         trn_reof_n_r1      <= trn_reof_n;
578
         trn_rrem_n_r1      <= trn_rrem_n;
579
         trn_rd_r1          <= trn_rd;
580
         trn_rerrfwd_n_r1   <= trn_rerrfwd_n;
581
         trn_rsrc_rdy_n_r1  <= trn_rsrc_rdy_n;
582
         trn_rdst_rdy_n_r1  <= trn_rdst_rdy_n_i;
583
         trn_rsrc_dsc_n_r1  <= trn_rsrc_dsc_n;
584
         trn_rbar_hit_n_r1  <= trn_rbar_hit_n;
585
      end if;
586
   end process;
587
 
588
 
589
   -- -----------------------------------------
590
   -- TLP Types
591
   --
592
   TLP_Decision_Registered:
593
   process ( trn_clk, trn_reset_n)
594
   begin
595
      if trn_reset_n = '0' then
596
         TLP_is_MRd_H3DW   <= '0';
597
 
598
         TLP_is_MRdLk_H3DW <= '0';
599
 
600
         TLP_is_MRd_H4DW   <= '0';
601
 
602
         TLP_is_MRdLk_H4DW <= '0';
603
 
604
         TLP_is_MWr_H3DW   <= '0';
605
 
606
         TLP_is_MWr_H4DW   <= '0';
607
 
608
         TLP_is_IORd       <= '0';
609
 
610
         TLP_is_IOWr       <= '0';
611
 
612
         TLP_is_CplD       <= '0';
613
         TLP_is_CplDLk     <= '0';
614
         TLP_is_Cpl        <= '0';
615
         TLP_is_CplLk      <= '0';
616
 
617
      elsif trn_clk'event and trn_clk = '1' then
618
 
619
         -- IORd
620
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_NO_DATA
621
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
622
            and trn_rd(C_TLP_EP_BIT) ='0'
623
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
624
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
625
            and trn_rsrc_rdy_n ='0'
626
            and trn_rsof_n ='0'
627
            then
628
                TLP_is_IORd   <= '1';
629
         else
630
                TLP_is_IORd   <= '0';
631
         end if;
632
 
633
 
634
         -- IOWr
635
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_WITH_DATA
636
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
637
            and trn_rd(C_TLP_EP_BIT) ='0'
638
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
639
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
640
            and trn_rsrc_rdy_n ='0'
641
            and trn_rsof_n ='0'
642
            then
643
                TLP_is_IOWr   <= '1';
644
         else
645
                TLP_is_IOWr   <= '0';
646
         end if;
647
 
648
 
649
         -- MRd
650
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_NO_DATA
651
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
652
            and trn_rd(C_TLP_EP_BIT) ='0'
653
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
654
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
655
            and trn_rsrc_rdy_n ='0'
656
            and trn_rsof_n ='0'
657
            then
658
                TLP_is_MRd_H3DW   <= '1';
659
         else
660
                TLP_is_MRd_H3DW   <= '0';
661
         end if;
662
 
663
 
664
 
665
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT4_NO_DATA
666
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
667
            and trn_rd(C_TLP_EP_BIT) ='0'
668
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
669
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
670
            and trn_rsrc_rdy_n ='0'
671
            and trn_rsof_n ='0'
672
            then
673
                TLP_is_MRd_H4DW   <= '1';
674
         else
675
                TLP_is_MRd_H4DW   <= '0';
676
         end if;
677
 
678
 
679
         -- MRdLk
680
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_NO_DATA
681
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
682
            and trn_rd(C_TLP_EP_BIT) ='0'
683
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
684
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
685
            and trn_rsrc_rdy_n ='0'
686
            and trn_rsof_n ='0'
687
            then
688
                TLP_is_MRdLk_H3DW   <= '1';
689
         else
690
                TLP_is_MRdLk_H3DW   <= '0';
691
         end if;
692
 
693
 
694
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT4_NO_DATA
695
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
696
            and trn_rd(C_TLP_EP_BIT) ='0'
697
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
698
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
699
            and trn_rsrc_rdy_n ='0'
700
            and trn_rsof_n ='0'
701
            then
702
                TLP_is_MRdLk_H4DW   <= '1';
703
         else
704
                TLP_is_MRdLk_H4DW   <= '0';
705
         end if;
706
 
707
 
708
 
709
         -- MWr
710
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_WITH_DATA
711
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
712
            and trn_rd(C_TLP_EP_BIT) ='0'
713
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
714
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
715
            and trn_rsrc_rdy_n ='0'
716
            and trn_rsof_n ='0'
717
            then
718
                TLP_is_MWr_H3DW   <= '1';
719
         else
720
                TLP_is_MWr_H3DW   <= '0';
721
         end if;
722
 
723
 
724
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT4_WITH_DATA
725
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
726
            and trn_rd(C_TLP_EP_BIT) ='0'
727
--            and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
728
            and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
729
            and trn_rsrc_rdy_n ='0'
730
            and trn_rsof_n ='0'
731
            then
732
                TLP_is_MWr_H4DW   <= '1';
733
         else
734
                TLP_is_MWr_H4DW   <= '0';
735
         end if;
736
 
737
 
738
 
739
         -- CplD, Cpl/CplDLk, CplLk
740
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_WITH_DATA
741
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
742
            and trn_rd(C_TLP_EP_BIT) ='0'
743
            and trn_rsrc_rdy_n ='0'
744
            and trn_rsof_n ='0'
745
            then
746
                TLP_is_CplD     <= '1';
747
         else
748
                TLP_is_CplD     <= '0';
749
         end if;
750
 
751
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_WITH_DATA
752
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
753
            and trn_rd(C_TLP_EP_BIT) ='0'
754
            and trn_rsrc_rdy_n ='0'
755
            and trn_rsof_n ='0'
756
            then
757
                TLP_is_CplDLk   <= '1';
758
         else
759
                TLP_is_CplDLk   <= '0';
760
         end if;
761
 
762
 
763
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_NO_DATA
764
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
765
            and trn_rd(C_TLP_EP_BIT) ='0'
766
            and trn_rsrc_rdy_n ='0'
767
            and trn_rsof_n ='0'
768
            then
769
                TLP_is_Cpl      <= '1';
770
         else
771
                TLP_is_Cpl      <= '0';
772
         end if;
773
 
774
         if     trn_rd(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)  = C_FMT3_NO_DATA
775
            and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
776
            and trn_rd(C_TLP_EP_BIT) ='0'
777
            and trn_rsrc_rdy_n ='0'
778
            and trn_rsof_n ='0'
779
            then
780
                TLP_is_CplLk    <= '1';
781
         else
782
                TLP_is_CplLk    <= '0';
783
         end if;
784
 
785
      end if;
786
   end process;
787
 
788
 
789
-- --------------------------------------------------------------------------
790
--   TLP_is_IORd        <=  TLP_is_IORd_BAR0       or TLP_is_IORd_BAR1;
791
--   TLP_is_IOWr        <=  TLP_is_IOWr_BAR0       or TLP_is_IOWr_BAR1;
792
 
793
--   TLP_is_MRd_H3DW    <=  TLP_is_MRd_BAR0_H3DW   or TLP_is_MRd_BAR1_H3DW;
794
--   TLP_is_MRdLk_H3DW  <=  TLP_is_MRdLk_BAR0_H3DW or TLP_is_MRdLk_BAR1_H3DW;
795
 
796
--   TLP_is_MRd_H4DW    <=  TLP_is_MRd_BAR0_H4DW   or TLP_is_MRd_BAR1_H4DW;
797
--   TLP_is_MRdLk_H4DW  <=  TLP_is_MRdLk_BAR0_H4DW or TLP_is_MRdLk_BAR1_H4DW;
798
 
799
--   TLP_is_MWr_H3DW    <=  TLP_is_MWr_BAR0_H3DW   or TLP_is_MWr_BAR1_H3DW;
800
 
801
--   TLP_is_MWr_H4DW    <=  TLP_is_MWr_BAR0_H4DW   or TLP_is_MWr_BAR1_H4DW;
802
 
803
-- --------------------------------------------------------------------------
804
 
805
   IORd_Type_i    <= TLP_is_IORd and Tlp_has_1DW_Length_i;
806
   IOWr_Type_i    <= TLP_is_IOWr and Tlp_has_1DW_Length_i;
807
 
808
 
809
   MRd_Type_i     <= (TLP_is_MRd_H3DW   and not MaxReadReqSize_Exceeded)
810
                   & (TLP_is_MRdLk_H3DW and not MaxReadReqSize_Exceeded)
811
                   & (TLP_is_MRd_H4DW   and not MaxReadReqSize_Exceeded)
812
                   & (TLP_is_MRdLk_H4DW and not MaxReadReqSize_Exceeded)
813
                   ;
814
 
815
   MWr_Type_i     <= (TLP_is_MWr_H3DW   and not MaxPayloadSize_Exceeded)
816
                   & (TLP_is_MWr_H4DW   and not MaxPayloadSize_Exceeded)
817
                   ;
818
 
819
   CplD_Type_i    <= (TLP_is_CplD       and not MaxPayloadSize_Exceeded)
820
                   & (TLP_is_Cpl        and not MaxPayloadSize_Exceeded)
821
                   & (TLP_is_CplDLk     and not MaxPayloadSize_Exceeded)
822
                   & (TLP_is_CplLk      and not MaxPayloadSize_Exceeded)
823
                   ;
824
 
825
 
826
   ---------------------------------------------------
827
   --
828
   -- Synchronous Registered: TLP_Header_Resolution
829
   --
830
   FSM_TLP_Header_Resolution:
831
   process ( trn_clk, trn_reset_n)
832
   begin
833
      if trn_reset_n = '0' then
834
         FSM_TLP_Cnt           <= TK_RST;
835
         TLP_Payload_Address_i <= (OTHERS => '1');
836
         MWr_on_Pool           <= '0';
837
         CplD_on_Pool_i        <= '0';
838
         CplD_on_EB_i          <= '0';
839
         trn_rdst_rdy_n_i      <= '1';
840
 
841
      elsif trn_clk'event and trn_clk = '1' then
842
 
843
        -- States transition
844
        case FSM_TLP_Cnt is
845
 
846
          when TK_RST =>
847
              FSM_TLP_Cnt           <= TK_Idle;
848
              trn_rdst_rdy_n_i      <= '1';
849
 
850
          when TK_Idle =>
851
            trn_rdst_rdy_n_i      <= '0';
852
            if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
853
               and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
854
               and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
855
               then
856
              FSM_TLP_Cnt    <= TK_MWr_3Hdr_C;
857
            elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
858
               and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="11"
859
               and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
860
               then
861
              FSM_TLP_Cnt    <= TK_MWr_4Hdr_C;
862
            elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
863
               and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
864
               and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
865
               then
866
              FSM_TLP_Cnt    <= TK_CplD_Hdr_C;
867
            else
868
              FSM_TLP_Cnt    <= TK_Idle;
869
            end if;
870
 
871
 
872
          when TK_MWr_3Hdr_C =>
873
            trn_rdst_rdy_n_i      <= '0';
874
            if trn_reof_n='0' and trn_reof_n_r1='1' then  -- falling edge
875
              FSM_TLP_Cnt    <= TK_Idle;
876
            elsif trn_rsrc_rdy_n='1' then
877
              FSM_TLP_Cnt    <= TK_MWr_3Hdr_C;
878
            else
879
              FSM_TLP_Cnt    <= TK_Body;
880
            end if;
881
 
882
          when TK_MWr_4Hdr_C =>
883
            trn_rdst_rdy_n_i      <= '0';
884
            if trn_reof_n='0' and trn_reof_n_r1='1' then  -- falling edge
885
              FSM_TLP_Cnt    <= TK_Idle;
886
            elsif trn_rsrc_rdy_n='1' then
887
              FSM_TLP_Cnt    <= TK_MWr_4Hdr_C;
888
            else
889
              FSM_TLP_Cnt    <= TK_Body;      -- TK_MWr_4Hdr_D;
890
            end if;
891
 
892
 
893
          when TK_Cpld_Hdr_C =>
894
            trn_rdst_rdy_n_i      <= '0';
895
            if trn_reof_n='0' and trn_reof_n_r1='1' then  -- falling edge
896
              FSM_TLP_Cnt    <= TK_Idle;
897
            elsif trn_rsrc_rdy_n='1' then
898
              FSM_TLP_Cnt    <= TK_Cpld_Hdr_C;
899
            else
900
              FSM_TLP_Cnt    <= TK_Body;
901
            end if;
902
 
903
 
904
          when TK_Body =>
905
            if trn_reof_n='0' and trn_reof_n_r1='1' then  -- falling edge
906
              FSM_TLP_Cnt    <= TK_Idle;
907
              trn_rdst_rdy_n_i      <= '0';
908
            else
909
              FSM_TLP_Cnt    <= TK_Body;
910
              trn_rdst_rdy_n_i      <= ((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
911
                                    or ((MWr_on_EB or CplD_on_EB_i) and Link_Buf_full)
912
                                    ;
913
            end if;
914
 
915
 
916
          when OTHERS  =>
917
              FSM_TLP_Cnt    <= TK_RST;
918
 
919
        end case;
920
 
921
 
922
        -- MWr_on_Pool
923
        case FSM_TLP_Cnt is
924
 
925
          when TK_RST =>
926
              MWr_on_Pool   <= '0';
927
              MWr_on_EB     <= '0';
928
 
929
          when TK_Idle =>
930
            if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
931
               and trn_rd(C_TLP_FMT_BIT_TOP) = '1'
932
               and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
933
               then
934
              MWr_on_Pool   <= not trn_rbar_hit_n(CINT_DDR_SPACE_BAR);
935
              MWr_on_EB     <= not trn_rbar_hit_n(CINT_FIFO_SPACE_BAR);
936
            else
937
              MWr_on_Pool   <= MWr_on_Pool;
938
              MWr_on_EB     <= MWr_on_EB;
939
            end if;
940
 
941
 
942
          when OTHERS  =>
943
              MWr_on_Pool   <= MWr_on_Pool;
944
              MWr_on_EB     <= MWr_on_EB;
945
 
946
        end case;
947
 
948
 
949
        -- CplD_on_Pool
950
        case FSM_TLP_Cnt is
951
 
952
          when TK_RST =>
953
              CplD_on_Pool_i  <= '0';
954
              CplD_on_EB_i    <= '0';
955
 
956
          when TK_Idle =>
957
              CplD_on_Pool_i  <= '0';
958
              CplD_on_EB_i    <= '0';
959
 
960
          when TK_CplD_Hdr_C =>
961
--            if trn_rsof_n='0' and trn_rsrc_rdy_n='0' 
962
--               and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10" 
963
--               and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01" 
964
--               then
965
              CplD_on_Pool_i  <= not trn_rd(C_CPLD_TAG_BIT_TOP) and not trn_rd(C_CPLD_TAG_BIT_TOP-1);
966
              CplD_on_EB_i    <= not trn_rd(C_CPLD_TAG_BIT_TOP) and trn_rd(C_CPLD_TAG_BIT_TOP-1);
967
--            else
968
--              CplD_on_Pool_i  <= CplD_on_Pool_i;
969
--              CplD_on_EB_i    <= CplD_on_EB_i;
970
--            end if;
971
 
972
 
973
          when OTHERS  =>
974
              CplD_on_Pool_i  <= CplD_on_Pool_i;
975
              CplD_on_EB_i    <= CplD_on_EB_i;
976
 
977
        end case;
978
 
979
 
980
        -- CplD_Tag
981
        case FSM_TLP_Cnt is
982
 
983
          when TK_RST =>
984
              CplD_Tag_i    <= (OTHERS => '1');
985
 
986
--          when TK_Idle =>
987
--              CplD_Tag_i    <= CplD_Tag_i;
988
 
989
          when TK_CplD_Hdr_C =>
990
--            if trn_reof_n='0' then
991
--              CplD_Tag_i    <= (OTHERS => '1');
992
--            els
993
            if trn_rsrc_rdy_n='0' -- and trn_rdst_rdy_n='0' 
994
               then
995
              CplD_Tag_i    <= trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT);
996
            else
997
              CplD_Tag_i    <= CplD_Tag_i;
998
            end if;
999
 
1000
          when OTHERS  =>
1001
              CplD_Tag_i    <= CplD_Tag_i;
1002
 
1003
        end case;
1004
 
1005
 
1006
      end if;
1007
   end process;
1008
 
1009
 
1010
   ---------------------------------------------------
1011
   --
1012
   -- Synchronous Registered: CplD_is_the_Last
1013
   --
1014
   Syn_Calc_CplD_is_the_Last:
1015
   process ( trn_clk, trn_reset_n)
1016
   begin
1017
      if trn_reset_n = '0' then
1018
         CplD_is_the_Last_i    <= '0';
1019
 
1020
      elsif trn_clk'event and trn_clk = '1' then
1021
 
1022
         if trn_rsof_n='0' and trn_rsrc_rdy_n='0' then
1023
            if trn_rd(C_TLP_TYPE_BIT_TOP-1)= '1'
1024
               and (trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2)=trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
1025
               or trn_rd(1 downto 0)=CONV_STD_LOGIC_VECTOR(1, 2))  -- Zero-length
1026
               then
1027
               CplD_is_the_Last_i <= '1';
1028
            else
1029
               CplD_is_the_Last_i <= '0';
1030
            end if;
1031
         else
1032
           CplD_is_the_Last_i  <= CplD_is_the_Last_i;
1033
         end if;
1034
 
1035
      end if;
1036
   end process;
1037
 
1038
   ---------------------------------------------------
1039
   --
1040
   -- Synchronous Delay: FSM_TLP_Cnt
1041
   --
1042
   SynDelay_FSM_TLP_Cnt:
1043
   process ( trn_clk )
1044
   begin
1045
      if trn_clk'event and trn_clk = '1' then
1046
         FSM_TLP_Cnt_r1   <=  FSM_TLP_Cnt;
1047
      end if;
1048
   end process;
1049
 
1050
 
1051
---- --------------------------------------------------------------------------
1052
--
1053
--   TLP_Address_sig      <=  '0' & trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
1054
--
1055
---------------------------------------------------------------------------------------
1056
---- Calculates the Address-Length combination carry-in
1057
--   TLP_Calc_CarryIn_ALC:
1058
--   process ( trn_clk, trn_reset_n)
1059
--   begin
1060
--      if trn_reset_n = '0' then
1061
--         CarryIn_ALC    <= (OTHERS =>'0');
1062
--      elsif trn_clk'event and trn_clk = '1' then
1063
--         CarryIn_ALC    <= ('0'& TLP_DW_Length_i) + TLP_Address_sig;
1064
--      end if;
1065
--   end process;
1066
--
1067
--
1068
--   ---------------------------------------------------
1069
--   --
1070
--   -- Synchronous Registered: Tlp_straddles_4KB
1071
--   --
1072
--   FSM_Output_Tlp_straddles_4KB:
1073
--   process ( trn_clk, trn_reset_n)
1074
--   begin
1075
--      if trn_reset_n = '0' then
1076
--         Tlp_straddles_4KB_i   <= '0';
1077
--
1078
--      elsif trn_clk'event and trn_clk = '1' then
1079
--
1080
--        case FSM_TLP_Cnt_r1 is
1081
--
1082
--          when TK_RST =>
1083
--              Tlp_straddles_4KB_i   <= '0';
1084
--
1085
--          when TK_MWr_3Hdr_C =>
1086
--            if Tlp_has_4KB_i='1'
1087
--               and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) 
1088
--                   /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
1089
--               then
1090
--               Tlp_straddles_4KB_i <= '1';
1091
--            else
1092
--               Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
1093
--            end if;
1094
--
1095
--          when TK_MWr_4Hdr_D =>
1096
--            if Tlp_has_4KB_i='1'
1097
--               and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) 
1098
--                   /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
1099
--               then
1100
--               Tlp_straddles_4KB_i <= '1';
1101
--            else
1102
--               Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
1103
--            end if;
1104
--
1105
--
1106
--          when OTHERS  =>
1107
--              Tlp_straddles_4KB_i <= Tlp_straddles_4KB_i;
1108
--
1109
--        end case;
1110
--
1111
--      end if;
1112
--   end process;
1113
--
1114
 
1115
 
1116
 
1117
   --  ---------------------------------------------------------
1118
   --  To Cpl/D channel as indicator when ReqID matched
1119
   --  
1120
   TLP_ReqID_Matched:
1121
   process ( trn_clk, trn_reset_n)
1122
   begin
1123
      if trn_reset_n = '0' then
1124
          Req_ID_Match_i      <= '0';
1125
      elsif trn_clk'event and trn_clk = '1' then
1126
        if trn_rd(C_CPLD_REQID_BIT_TOP downto C_CPLD_REQID_BIT_BOT)=localID then
1127
          Req_ID_Match_i      <= '1';
1128
        else
1129
          Req_ID_Match_i      <= '0';
1130
        end if;
1131
      end if;
1132
   end process;
1133
 
1134
 
1135
   --  ------------------------------------------------------------
1136
   --  To Cpl/D channel as indicator when us Tag_Descriptor matched
1137
   --  
1138
   TLP_usDexTag_Matched:
1139
   process ( trn_clk, trn_reset_n)
1140
   begin
1141
      if trn_reset_n = '0' then
1142
          usDex_Tag_Matched_i      <= '0';
1143
      elsif trn_clk'event and trn_clk = '1' then
1144
        if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag then
1145
          usDex_Tag_Matched_i      <= '1';
1146
        else
1147
          usDex_Tag_Matched_i      <= '0';
1148
        end if;
1149
      end if;
1150
   end process;
1151
 
1152
 
1153
   --  ------------------------------------------------------------
1154
   --  To Cpl/D channel as indicator when ds Tag_Descriptor matched
1155
   --  
1156
   TLP_dsDexTag_Matched:
1157
   process ( trn_clk, trn_reset_n)
1158
   begin
1159
      if trn_reset_n = '0' then
1160
          dsDex_Tag_Matched_i      <= '0';
1161
      elsif trn_clk'event and trn_clk = '1' then
1162
        if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag then
1163
          dsDex_Tag_Matched_i      <= '1';
1164
        else
1165
          dsDex_Tag_Matched_i      <= '0';
1166
        end if;
1167
      end if;
1168
   end process;
1169
 
1170
 
1171
end architecture Behavioral;

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