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##-----------------------------------------------------------------------------
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##
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## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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##
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## This file contains confidential and proprietary information of Xilinx, Inc.
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## and is protected under U.S. and international copyright and other
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## intellectual property laws.
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##
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## DISCLAIMER
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##
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## This disclaimer is not a license and does not grant any rights to the
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## materials distributed herewith. Except as otherwise provided in a valid
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## license issued to you by Xilinx, and to the maximum extent permitted by
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## applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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## FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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## IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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## MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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## and (2) Xilinx shall not be liable (whether in contract or tort, including
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## negligence, or under any other theory of liability) for any loss or damage
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## of any kind or nature related to, arising under or in connection with these
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## materials, including for any direct, or any indirect, special, incidental,
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## or consequential loss or damage (including loss of data, profits, goodwill,
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## or any type of loss or damage suffered as a result of any action brought by
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## a third party) even if such damage or loss was reasonably foreseeable or
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## Xilinx had been advised of the possibility of the same.
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##
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## CRITICAL APPLICATIONS
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##
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## Xilinx products are not designed or intended to be fail-safe, or for use in
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## any application requiring fail-safe performance, such as life-support or
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## safety devices or systems, Class III medical devices, nuclear facilities,
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## applications related to the deployment of airbags, or any other
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## applications that could lead to death, personal injury, or severe property
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## or environmental damage (individually and collectively, "Critical
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## Applications"). Customer assumes the sole risk and liability of any use of
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## Xilinx products in Critical Applications, subject only to applicable laws
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## and regulations governing limitations on product liability.
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##
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## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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## AT ALL TIMES.
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##
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##-----------------------------------------------------------------------------
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## Project : Virtex-6 Integrated Block for PCI Express
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## File : xilinx_pcie_2_0_ep_v6_04_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf
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#
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###############################################################################
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# Define Device, Package And Speed Grade
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###############################################################################
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CONFIG PART = xc6vlx240t-ff1156-1;
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###############################################################################
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# Pinout and Related I/O Constraints
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###############################################################################
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#
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# SYS reset (input) signal. The sys_reset_n signal should be
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# obtained from the PCI Express interface if possible. For
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# slot based form factors, a system reset signal is usually
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# present on the connector. For cable based form factors, a
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# system reset signal may not be available. In this case, the
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# system reset signal must be generated locally by some form of
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# supervisory circuit. You may change the IOSTANDARD and LOC
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# to suit your requirements and VCCO voltage banking rules.
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#
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NET "sys_reset_n" TIG;
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NET "sys_reset_n" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
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#
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#
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# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
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# signals are the PCI Express reference clock. Virtex-6 GT
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# Transceiver architecture requires the use of a dedicated clock
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# resources (FPGA input pins) associated with each GT Transceiver.
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# To use these pins an IBUFDS primitive (refclk_ibuf) is
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# instantiated in user's design.
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# Please refer to the Virtex-6 GT Transceiver User Guide
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# (UG) for guidelines regarding clock resource selection.
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#
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#NET "sys_clk_n" LOC = P6;
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#NET "sys_clk_p" LOC = P5;
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INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;
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#
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# Transceiver instance placement. This constraint selects the
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# transceivers to be used, which also dictates the pinout for the
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# transmit and receive differential pairs. Please refer to the
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# Virtex-6 GT Transceiver User Guide (UG) for more information.
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#
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# PCIe Lane 0
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;
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# PCIe Lane 1
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14;
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# PCIe Lane 2
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13;
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# PCIe Lane 3
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12;
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# PCIe Lane 4
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[4].GTX" LOC = GTXE1_X0Y11;
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# PCIe Lane 5
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[5].GTX" LOC = GTXE1_X0Y10;
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# PCIe Lane 6
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[6].GTX" LOC = GTXE1_X0Y9;
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# PCIe Lane 7
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[7].GTX" LOC = GTXE1_X0Y8;
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#
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# PCI Express Block placement. This constraint selects the PCI Express
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# Block to be used.
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#
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INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;
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# SIMONE aggiunti da v1.3 to v1.6
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INST "make4Lanes.pcieCore/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;
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# SIMONE aggiunti da v1.3 to v1.6
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###############################################################################
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# Timing Constraints
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###############################################################################
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#
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# Timing requirements and related constraints.
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#
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NET "sys_clk_c" TNM_NET = "SYSCLK" ;
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NET "make4Lanes.pcieCore/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;
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NET "make4Lanes.pcieCore/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
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TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 % ;
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TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 100 ;
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TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;
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PIN "make4Lanes.pcieCore/trn_reset_n_int_i.CLR" TIG ;
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PIN "make4Lanes.pcieCore/trn_reset_n_i.CLR" TIG ;
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PIN "make4Lanes.pcieCore/pcie_clocking_i/mmcm_adv_i.RST" TIG ;
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TIMESPEC "TS_RESETN" = FROM FFS(*) TO FFS(trn_reset_n_i) 8 ns;
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###############################################################################
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# Physical Constraints
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###############################################################################
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INST "make4Lanes.pcieCore/*" AREA_GROUP = "AG_core" ;
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AREA_GROUP "AG_core" RANGE = SLICE_X136Y147:SLICE_X155Y120 ;
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###############################################################################
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# End
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###############################################################################
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#### Module LEDs_8Bit constraints
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Net LEDs_IO_pin<0> LOC = AC22;
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Net LEDs_IO_pin<1> LOC = AC24;
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Net LEDs_IO_pin<2> LOC = AE22;
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Net LEDs_IO_pin<3> LOC = AE23;
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Net LEDs_IO_pin<4> LOC = AB23;
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Net LEDs_IO_pin<5> LOC = AG23;
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Net LEDs_IO_pin<6> LOC = AE24;
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Net LEDs_IO_pin<7> LOC = AD24;
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Net LEDs_IO_pin<*> IOSTANDARD=LVCMOS25;
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NET "userclk_66MHz" PERIOD = 66.6 MHz HIGH 50%;
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NET "userclk_66MHz" LOC = "U23";
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NET "userclk_200MHz_n" LOC = "H9";
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NET "userclk_200MHz_p" LOC = "J9";
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NET "userclk_200MHz_p" PERIOD = 200 MHz HIGH 50%;
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#### Module DIP_Switches constraints
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#Net dummy_pin_in<0> LOC=D22;
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#Net dummy_pin_in<1> LOC=C22;
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#Net dummy_pin_in<2> LOC=L21;
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##Net SWITCH_pin<3> LOC=L20;
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##Net SWITCH_pin<4> LOC=C18;
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##Net SWITCH_pin<5> LOC=B18;
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##Net SWITCH_pin<6> LOC=K22;
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##Net SWITCH_pin<7> LOC=K21;
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#Net dummy_pin_in<*> IOSTANDARD = SSTL15;
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