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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [PCIe_UserLogic_00.vhd] - Blame information for rev 13

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1 13 barabba
 
2
-------------------------------------------------------------------
3
-- System Generator version 13.2 VHDL source file.
4
--
5
-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This
6
-- text/file contains proprietary, confidential information of Xilinx,
7
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
8
-- copied and/or disclosed only pursuant to the terms of a valid license
9
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
10
-- this text/file solely for design, simulation, implementation and
11
-- creation of design files limited to Xilinx devices or technologies.
12
-- Use with non-Xilinx devices or technologies is expressly prohibited
13
-- and immediately terminates your license unless covered by a separate
14
-- agreement.
15
--
16
-- Xilinx is providing this design, code, or information "as is" solely
17
-- for use in developing programs and solutions for Xilinx devices.  By
18
-- providing this design, code, or information as one possible
19
-- implementation of this feature, application or standard, Xilinx is
20
-- making no representation that this implementation is free from any
21
-- claims of infringement.  You are responsible for obtaining any rights
22
-- you may require for your implementation.  Xilinx expressly disclaims
23
-- any warranty whatsoever with respect to the adequacy of the
24
-- implementation, including but not limited to warranties of
25
-- merchantability or fitness for a particular purpose.
26
--
27
-- Xilinx products are not intended for use in life support appliances,
28
-- devices, or systems.  Use in such applications is expressly prohibited.
29
--
30
-- Any modifications that are made to the source code are done at the user's
31
-- sole risk and will be unsupported.
32
--
33
-- This copyright and support notice must be retained as part of this
34
-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights
35
-- reserved.
36
-------------------------------------------------------------------
37
 
38
-------------------------------------------------------------------
39
-- System Generator version 13.2 VHDL source file.
40
--
41
-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This
42
-- text/file contains proprietary, confidential information of Xilinx,
43
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
44
-- copied and/or disclosed only pursuant to the terms of a valid license
45
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
46
-- this text/file solely for design, simulation, implementation and
47
-- creation of design files limited to Xilinx devices or technologies.
48
-- Use with non-Xilinx devices or technologies is expressly prohibited
49
-- and immediately terminates your license unless covered by a separate
50
-- agreement.
51
--
52
-- Xilinx is providing this design, code, or information "as is" solely
53
-- for use in developing programs and solutions for Xilinx devices.  By
54
-- providing this design, code, or information as one possible
55
-- implementation of this feature, application or standard, Xilinx is
56
-- making no representation that this implementation is free from any
57
-- claims of infringement.  You are responsible for obtaining any rights
58
-- you may require for your implementation.  Xilinx expressly disclaims
59
-- any warranty whatsoever with respect to the adequacy of the
60
-- implementation, including but not limited to warranties of
61
-- merchantability or fitness for a particular purpose.
62
--
63
-- Xilinx products are not intended for use in life support appliances,
64
-- devices, or systems.  Use in such applications is expressly prohibited.
65
--
66
-- Any modifications that are made to the source code are done at the user's
67
-- sole risk and will be unsupported.
68
--
69
-- This copyright and support notice must be retained as part of this
70
-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights
71
-- reserved.
72
-------------------------------------------------------------------
73
library IEEE;
74
use IEEE.std_logic_1164.all;
75
use IEEE.numeric_std.all;
76
package conv_pkg is
77
    constant simulating : boolean := false
78
      -- synopsys translate_off
79
        or true
80
      -- synopsys translate_on
81
    ;
82
    constant xlUnsigned : integer := 1;
83
    constant xlSigned : integer := 2;
84
    constant xlFloat : integer := 3;
85
    constant xlWrap : integer := 1;
86
    constant xlSaturate : integer := 2;
87
    constant xlTruncate : integer := 1;
88
    constant xlRound : integer := 2;
89
    constant xlRoundBanker : integer := 3;
90
    constant xlAddMode : integer := 1;
91
    constant xlSubMode : integer := 2;
92
    attribute black_box : boolean;
93
    attribute syn_black_box : boolean;
94
    attribute fpga_dont_touch: string;
95
    attribute box_type :  string;
96
    attribute keep : string;
97
    attribute syn_keep : boolean;
98
    function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
99
    function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
100
    function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
101
    function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
102
    function unsigned_to_signed(inp : unsigned) return signed;
103
    function signed_to_unsigned(inp : signed) return unsigned;
104
    function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
105
    function all_same(inp: std_logic_vector) return boolean;
106
    function all_zeros(inp: std_logic_vector) return boolean;
107
    function is_point_five(inp: std_logic_vector) return boolean;
108
    function all_ones(inp: std_logic_vector) return boolean;
109
    function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
110
                           old_arith, new_width, new_bin_pt, new_arith,
111
                           quantization, overflow : INTEGER)
112
        return std_logic_vector;
113
    function cast (inp : std_logic_vector; old_bin_pt,
114
                   new_width, new_bin_pt, new_arith : INTEGER)
115
        return std_logic_vector;
116
    function shift_division_result(quotient, fraction: std_logic_vector;
117
                                   fraction_width, shift_value, shift_dir: INTEGER)
118
        return std_logic_vector;
119
    function shift_op (inp: std_logic_vector;
120
                       result_width, shift_value, shift_dir: INTEGER)
121
        return std_logic_vector;
122
    function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
123
        return std_logic_vector;
124
    function s2u_slice (inp : signed; upper, lower : INTEGER)
125
        return unsigned;
126
    function u2u_slice (inp : unsigned; upper, lower : INTEGER)
127
        return unsigned;
128
    function s2s_cast (inp : signed; old_bin_pt,
129
                   new_width, new_bin_pt : INTEGER)
130
        return signed;
131
    function u2s_cast (inp : unsigned; old_bin_pt,
132
                   new_width, new_bin_pt : INTEGER)
133
        return signed;
134
    function s2u_cast (inp : signed; old_bin_pt,
135
                   new_width, new_bin_pt : INTEGER)
136
        return unsigned;
137
    function u2u_cast (inp : unsigned; old_bin_pt,
138
                   new_width, new_bin_pt : INTEGER)
139
        return unsigned;
140
    function u2v_cast (inp : unsigned; old_bin_pt,
141
                   new_width, new_bin_pt : INTEGER)
142
        return std_logic_vector;
143
    function s2v_cast (inp : signed; old_bin_pt,
144
                   new_width, new_bin_pt : INTEGER)
145
        return std_logic_vector;
146
    function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
147
                    new_width, new_bin_pt, new_arith : INTEGER)
148
        return std_logic_vector;
149
    function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
150
                                old_arith, new_width, new_bin_pt,
151
                                new_arith : INTEGER) return std_logic_vector;
152
    function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
153
                                old_arith, new_width, new_bin_pt,
154
                                new_arith : INTEGER) return std_logic_vector;
155
    function max_signed(width : INTEGER) return std_logic_vector;
156
    function min_signed(width : INTEGER) return std_logic_vector;
157
    function saturation_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
158
                              old_arith, new_width, new_bin_pt, new_arith
159
                              : INTEGER) return std_logic_vector;
160
    function wrap_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
161
                        old_arith, new_width, new_bin_pt, new_arith : INTEGER)
162
                        return std_logic_vector;
163
    function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
164
    function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
165
        return INTEGER;
166
    function sign_ext(inp : std_logic_vector; new_width : INTEGER)
167
        return std_logic_vector;
168
    function zero_ext(inp : std_logic_vector; new_width : INTEGER)
169
        return std_logic_vector;
170
    function zero_ext(inp : std_logic; new_width : INTEGER)
171
        return std_logic_vector;
172
    function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
173
        return std_logic_vector;
174
    function align_input(inp : std_logic_vector; old_width, delta, new_arith,
175
                          new_width: INTEGER)
176
        return std_logic_vector;
177
    function pad_LSB(inp : std_logic_vector; new_width: integer)
178
        return std_logic_vector;
179
    function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
180
        return std_logic_vector;
181
    function max(L, R: INTEGER) return INTEGER;
182
    function min(L, R: INTEGER) return INTEGER;
183
    function "="(left,right: STRING) return boolean;
184
    function boolean_to_signed (inp : boolean; width: integer)
185
        return signed;
186
    function boolean_to_unsigned (inp : boolean; width: integer)
187
        return unsigned;
188
    function boolean_to_vector (inp : boolean)
189
        return std_logic_vector;
190
    function std_logic_to_vector (inp : std_logic)
191
        return std_logic_vector;
192
    function integer_to_std_logic_vector (inp : integer;  width, arith : integer)
193
        return std_logic_vector;
194
    function std_logic_vector_to_integer (inp : std_logic_vector;  arith : integer)
195
        return integer;
196
    function std_logic_to_integer(constant inp : std_logic := '0')
197
        return integer;
198
    function bin_string_element_to_std_logic_vector (inp : string;  width, index : integer)
199
        return std_logic_vector;
200
    function bin_string_to_std_logic_vector (inp : string)
201
        return std_logic_vector;
202
    function hex_string_to_std_logic_vector (inp : string; width : integer)
203
        return std_logic_vector;
204
    function makeZeroBinStr (width : integer) return STRING;
205
    function and_reduce(inp: std_logic_vector) return std_logic;
206
    -- synopsys translate_off
207
    function is_binary_string_invalid (inp : string)
208
        return boolean;
209
    function is_binary_string_undefined (inp : string)
210
        return boolean;
211
    function is_XorU(inp : std_logic_vector)
212
        return boolean;
213
    function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
214
        return real;
215
    function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
216
        return real;
217
    function real_to_std_logic_vector (inp : real;  width, bin_pt, arith : integer)
218
        return std_logic_vector;
219
    function real_string_to_std_logic_vector (inp : string;  width, bin_pt, arith : integer)
220
        return std_logic_vector;
221
    constant display_precision : integer := 20;
222
    function real_to_string (inp : real) return string;
223
    function valid_bin_string(inp : string) return boolean;
224
    function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
225
    function std_logic_to_bin_string(inp : std_logic) return string;
226
    function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
227
        return string;
228
    function real_to_bin_string(inp : real;  width, bin_pt, arith : integer)
229
        return string;
230
    type stdlogic_to_char_t is array(std_logic) of character;
231
    constant to_char : stdlogic_to_char_t := (
232
        'U' => 'U',
233
        'X' => 'X',
234
        '0' => '0',
235
        '1' => '1',
236
        'Z' => 'Z',
237
        'W' => 'W',
238
        'L' => 'L',
239
        'H' => 'H',
240
        '-' => '-');
241
    -- synopsys translate_on
242
end conv_pkg;
243
package body conv_pkg is
244
    function std_logic_vector_to_unsigned(inp : std_logic_vector)
245
        return unsigned
246
    is
247
    begin
248
        return unsigned (inp);
249
    end;
250
    function unsigned_to_std_logic_vector(inp : unsigned)
251
        return std_logic_vector
252
    is
253
    begin
254
        return std_logic_vector(inp);
255
    end;
256
    function std_logic_vector_to_signed(inp : std_logic_vector)
257
        return signed
258
    is
259
    begin
260
        return  signed (inp);
261
    end;
262
    function signed_to_std_logic_vector(inp : signed)
263
        return std_logic_vector
264
    is
265
    begin
266
        return std_logic_vector(inp);
267
    end;
268
    function unsigned_to_signed (inp : unsigned)
269
        return signed
270
    is
271
    begin
272
        return signed(std_logic_vector(inp));
273
    end;
274
    function signed_to_unsigned (inp : signed)
275
        return unsigned
276
    is
277
    begin
278
        return unsigned(std_logic_vector(inp));
279
    end;
280
    function pos(inp : std_logic_vector; arith : INTEGER)
281
        return boolean
282
    is
283
        constant width : integer := inp'length;
284
        variable vec : std_logic_vector(width-1 downto 0);
285
    begin
286
        vec := inp;
287
        if arith = xlUnsigned then
288
            return true;
289
        else
290
            if vec(width-1) = '0' then
291
                return true;
292
            else
293
                return false;
294
            end if;
295
        end if;
296
        return true;
297
    end;
298
    function max_signed(width : INTEGER)
299
        return std_logic_vector
300
    is
301
        variable ones : std_logic_vector(width-2 downto 0);
302
        variable result : std_logic_vector(width-1 downto 0);
303
    begin
304
        ones := (others => '1');
305
        result(width-1) := '0';
306
        result(width-2 downto 0) := ones;
307
        return result;
308
    end;
309
    function min_signed(width : INTEGER)
310
        return std_logic_vector
311
    is
312
        variable zeros : std_logic_vector(width-2 downto 0);
313
        variable result : std_logic_vector(width-1 downto 0);
314
    begin
315
        zeros := (others => '0');
316
        result(width-1) := '1';
317
        result(width-2 downto 0) := zeros;
318
        return result;
319
    end;
320
    function and_reduce(inp: std_logic_vector) return std_logic
321
    is
322
        variable result: std_logic;
323
        constant width : integer := inp'length;
324
        variable vec : std_logic_vector(width-1 downto 0);
325
    begin
326
        vec := inp;
327
        result := vec(0);
328
        if width > 1 then
329
            for i in 1 to width-1 loop
330
                result := result and vec(i);
331
            end loop;
332
        end if;
333
        return result;
334
    end;
335
    function all_same(inp: std_logic_vector) return boolean
336
    is
337
        variable result: boolean;
338
        constant width : integer := inp'length;
339
        variable vec : std_logic_vector(width-1 downto 0);
340
    begin
341
        vec := inp;
342
        result := true;
343
        if width > 0 then
344
            for i in 1 to width-1 loop
345
                if vec(i) /= vec(0) then
346
                    result := false;
347
                end if;
348
            end loop;
349
        end if;
350
        return result;
351
    end;
352
    function all_zeros(inp: std_logic_vector)
353
        return boolean
354
    is
355
        constant width : integer := inp'length;
356
        variable vec : std_logic_vector(width-1 downto 0);
357
        variable zero : std_logic_vector(width-1 downto 0);
358
        variable result : boolean;
359
    begin
360
        zero := (others => '0');
361
        vec := inp;
362
        -- synopsys translate_off
363
        if (is_XorU(vec)) then
364
            return false;
365
        end if;
366
         -- synopsys translate_on
367
        if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
368
            result := true;
369
        else
370
            result := false;
371
        end if;
372
        return result;
373
    end;
374
    function is_point_five(inp: std_logic_vector)
375
        return boolean
376
    is
377
        constant width : integer := inp'length;
378
        variable vec : std_logic_vector(width-1 downto 0);
379
        variable result : boolean;
380
    begin
381
        vec := inp;
382
        -- synopsys translate_off
383
        if (is_XorU(vec)) then
384
            return false;
385
        end if;
386
         -- synopsys translate_on
387
        if (width > 1) then
388
           if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
389
               result := true;
390
           else
391
               result := false;
392
           end if;
393
        else
394
           if (vec(width-1) = '1') then
395
               result := true;
396
           else
397
               result := false;
398
           end if;
399
        end if;
400
        return result;
401
    end;
402
    function all_ones(inp: std_logic_vector)
403
        return boolean
404
    is
405
        constant width : integer := inp'length;
406
        variable vec : std_logic_vector(width-1 downto 0);
407
        variable one : std_logic_vector(width-1 downto 0);
408
        variable result : boolean;
409
    begin
410
        one := (others => '1');
411
        vec := inp;
412
        -- synopsys translate_off
413
        if (is_XorU(vec)) then
414
            return false;
415
        end if;
416
         -- synopsys translate_on
417
        if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
418
            result := true;
419
        else
420
            result := false;
421
        end if;
422
        return result;
423
    end;
424
    function full_precision_num_width(quantization, overflow, old_width,
425
                                      old_bin_pt, old_arith,
426
                                      new_width, new_bin_pt, new_arith : INTEGER)
427
        return integer
428
    is
429
        variable result : integer;
430
    begin
431
        result := old_width + 2;
432
        return result;
433
    end;
434
    function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
435
                                 old_arith, new_width, new_bin_pt, new_arith
436
                                 : INTEGER)
437
        return integer
438
    is
439
        variable right_of_dp, left_of_dp, result : integer;
440
    begin
441
        right_of_dp := max(new_bin_pt, old_bin_pt);
442
        left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
443
        result := (old_width + 2) + (new_bin_pt - old_bin_pt);
444
        return result;
445
    end;
446
    function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
447
                           old_arith, new_width, new_bin_pt, new_arith,
448
                           quantization, overflow : INTEGER)
449
        return std_logic_vector
450
    is
451
        constant fp_width : integer :=
452
            full_precision_num_width(quantization, overflow, old_width,
453
                                     old_bin_pt, old_arith, new_width,
454
                                     new_bin_pt, new_arith);
455
        constant fp_bin_pt : integer := old_bin_pt;
456
        constant fp_arith : integer := old_arith;
457
        variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
458
        constant q_width : integer :=
459
            quantized_num_width(quantization, overflow, old_width, old_bin_pt,
460
                                old_arith, new_width, new_bin_pt, new_arith);
461
        constant q_bin_pt : integer := new_bin_pt;
462
        constant q_arith : integer := old_arith;
463
        variable quantized_result : std_logic_vector(q_width-1 downto 0);
464
        variable result : std_logic_vector(new_width-1 downto 0);
465
    begin
466
        result := (others => '0');
467
        full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
468
                                      fp_arith);
469
        if (quantization = xlRound) then
470
            quantized_result := round_towards_inf(full_precision_result,
471
                                                  fp_width, fp_bin_pt,
472
                                                  fp_arith, q_width, q_bin_pt,
473
                                                  q_arith);
474
        elsif (quantization = xlRoundBanker) then
475
            quantized_result := round_towards_even(full_precision_result,
476
                                                  fp_width, fp_bin_pt,
477
                                                  fp_arith, q_width, q_bin_pt,
478
                                                  q_arith);
479
        else
480
            quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
481
                                      fp_arith, q_width, q_bin_pt, q_arith);
482
        end if;
483
        if (overflow = xlSaturate) then
484
            result := saturation_arith(quantized_result, q_width, q_bin_pt,
485
                                       q_arith, new_width, new_bin_pt, new_arith);
486
        else
487
             result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
488
                                  new_width, new_bin_pt, new_arith);
489
        end if;
490
        return result;
491
    end;
492
    function cast (inp : std_logic_vector; old_bin_pt, new_width,
493
                   new_bin_pt, new_arith : INTEGER)
494
        return std_logic_vector
495
    is
496
        constant old_width : integer := inp'length;
497
        constant left_of_dp : integer := (new_width - new_bin_pt)
498
                                         - (old_width - old_bin_pt);
499
        constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
500
        variable vec : std_logic_vector(old_width-1 downto 0);
501
        variable result : std_logic_vector(new_width-1 downto 0);
502
        variable j   : integer;
503
    begin
504
        vec := inp;
505
        for i in new_width-1 downto 0 loop
506
            j := i - right_of_dp;
507
            if ( j > old_width-1) then
508
                if (new_arith = xlUnsigned) then
509
                    result(i) := '0';
510
                else
511
                    result(i) := vec(old_width-1);
512
                end if;
513
            elsif ( j >= 0) then
514
                result(i) := vec(j);
515
            else
516
                result(i) := '0';
517
            end if;
518
        end loop;
519
        return result;
520
    end;
521
    function shift_division_result(quotient, fraction: std_logic_vector;
522
                                   fraction_width, shift_value, shift_dir: INTEGER)
523
        return std_logic_vector
524
    is
525
        constant q_width : integer := quotient'length;
526
        constant f_width : integer := fraction'length;
527
        constant vec_MSB : integer := q_width+f_width-1;
528
        constant result_MSB : integer := q_width+fraction_width-1;
529
        constant result_LSB : integer := vec_MSB-result_MSB;
530
        variable vec : std_logic_vector(vec_MSB downto 0);
531
        variable result : std_logic_vector(result_MSB downto 0);
532
    begin
533
        vec := ( quotient & fraction );
534
        if shift_dir = 1 then
535
            for i in vec_MSB downto 0 loop
536
                if (i < shift_value) then
537
                     vec(i) := '0';
538
                else
539
                    vec(i) := vec(i-shift_value);
540
                end if;
541
            end loop;
542
        else
543
            for i in 0 to vec_MSB loop
544
                if (i > vec_MSB-shift_value) then
545
                    vec(i) := vec(vec_MSB);
546
                else
547
                    vec(i) := vec(i+shift_value);
548
                end if;
549
            end loop;
550
        end if;
551
        result := vec(vec_MSB downto result_LSB);
552
        return result;
553
    end;
554
    function shift_op (inp: std_logic_vector;
555
                       result_width, shift_value, shift_dir: INTEGER)
556
        return std_logic_vector
557
    is
558
        constant inp_width : integer := inp'length;
559
        constant vec_MSB : integer := inp_width-1;
560
        constant result_MSB : integer := result_width-1;
561
        constant result_LSB : integer := vec_MSB-result_MSB;
562
        variable vec : std_logic_vector(vec_MSB downto 0);
563
        variable result : std_logic_vector(result_MSB downto 0);
564
    begin
565
        vec := inp;
566
        if shift_dir = 1 then
567
            for i in vec_MSB downto 0 loop
568
                if (i < shift_value) then
569
                     vec(i) := '0';
570
                else
571
                    vec(i) := vec(i-shift_value);
572
                end if;
573
            end loop;
574
        else
575
            for i in 0 to vec_MSB loop
576
                if (i > vec_MSB-shift_value) then
577
                    vec(i) := vec(vec_MSB);
578
                else
579
                    vec(i) := vec(i+shift_value);
580
                end if;
581
            end loop;
582
        end if;
583
        result := vec(vec_MSB downto result_LSB);
584
        return result;
585
    end;
586
    function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
587
      return std_logic_vector
588
    is
589
    begin
590
        return inp(upper downto lower);
591
    end;
592
    function s2u_slice (inp : signed; upper, lower : INTEGER)
593
      return unsigned
594
    is
595
    begin
596
        return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
597
    end;
598
    function u2u_slice (inp : unsigned; upper, lower : INTEGER)
599
      return unsigned
600
    is
601
    begin
602
        return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
603
    end;
604
    function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
605
        return signed
606
    is
607
    begin
608
        return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
609
    end;
610
    function s2u_cast (inp : signed; old_bin_pt, new_width,
611
                   new_bin_pt : INTEGER)
612
        return unsigned
613
    is
614
    begin
615
        return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
616
    end;
617
    function u2s_cast (inp : unsigned; old_bin_pt, new_width,
618
                   new_bin_pt : INTEGER)
619
        return signed
620
    is
621
    begin
622
        return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
623
    end;
624
    function u2u_cast (inp : unsigned; old_bin_pt, new_width,
625
                   new_bin_pt : INTEGER)
626
        return unsigned
627
    is
628
    begin
629
        return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
630
    end;
631
    function u2v_cast (inp : unsigned; old_bin_pt, new_width,
632
                   new_bin_pt : INTEGER)
633
        return std_logic_vector
634
    is
635
    begin
636
        return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
637
    end;
638
    function s2v_cast (inp : signed; old_bin_pt, new_width,
639
                   new_bin_pt : INTEGER)
640
        return std_logic_vector
641
    is
642
    begin
643
        return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
644
    end;
645
    function boolean_to_signed (inp : boolean; width : integer)
646
        return signed
647
    is
648
        variable result : signed(width - 1 downto 0);
649
    begin
650
        result := (others => '0');
651
        if inp then
652
          result(0) := '1';
653
        else
654
          result(0) := '0';
655
        end if;
656
        return result;
657
    end;
658
    function boolean_to_unsigned (inp : boolean; width : integer)
659
        return unsigned
660
    is
661
        variable result : unsigned(width - 1 downto 0);
662
    begin
663
        result := (others => '0');
664
        if inp then
665
          result(0) := '1';
666
        else
667
          result(0) := '0';
668
        end if;
669
        return result;
670
    end;
671
    function boolean_to_vector (inp : boolean)
672
        return std_logic_vector
673
    is
674
        variable result : std_logic_vector(1 - 1 downto 0);
675
    begin
676
        result := (others => '0');
677
        if inp then
678
          result(0) := '1';
679
        else
680
          result(0) := '0';
681
        end if;
682
        return result;
683
    end;
684
    function std_logic_to_vector (inp : std_logic)
685
        return std_logic_vector
686
    is
687
        variable result : std_logic_vector(1 - 1 downto 0);
688
    begin
689
        result(0) := inp;
690
        return result;
691
    end;
692
    function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
693
                                new_width, new_bin_pt, new_arith : INTEGER)
694
        return std_logic_vector
695
    is
696
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
697
        variable vec : std_logic_vector(old_width-1 downto 0);
698
        variable result : std_logic_vector(new_width-1 downto 0);
699
    begin
700
        vec := inp;
701
        if right_of_dp >= 0 then
702
            if new_arith = xlUnsigned then
703
                result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
704
            else
705
                result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
706
            end if;
707
        else
708
            if new_arith = xlUnsigned then
709
                result := zero_ext(pad_LSB(vec, old_width +
710
                                           abs(right_of_dp)), new_width);
711
            else
712
                result := sign_ext(pad_LSB(vec, old_width +
713
                                           abs(right_of_dp)), new_width);
714
            end if;
715
        end if;
716
        return result;
717
    end;
718
    function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
719
                                old_arith, new_width, new_bin_pt, new_arith
720
                                : INTEGER)
721
        return std_logic_vector
722
    is
723
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
724
        constant expected_new_width : integer :=  old_width - right_of_dp  + 1;
725
        variable vec : std_logic_vector(old_width-1 downto 0);
726
        variable one_or_zero : std_logic_vector(new_width-1 downto 0);
727
        variable truncated_val : std_logic_vector(new_width-1 downto 0);
728
        variable result : std_logic_vector(new_width-1 downto 0);
729
    begin
730
        vec := inp;
731
        if right_of_dp >= 0 then
732
            if new_arith = xlUnsigned then
733
                truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
734
                                          new_width);
735
            else
736
                truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
737
                                          new_width);
738
            end if;
739
        else
740
            if new_arith = xlUnsigned then
741
                truncated_val := zero_ext(pad_LSB(vec, old_width +
742
                                                  abs(right_of_dp)), new_width);
743
            else
744
                truncated_val := sign_ext(pad_LSB(vec, old_width +
745
                                                  abs(right_of_dp)), new_width);
746
            end if;
747
        end if;
748
        one_or_zero := (others => '0');
749
        if (new_arith = xlSigned) then
750
            if (vec(old_width-1) = '0') then
751
                one_or_zero(0) := '1';
752
            end if;
753
            if (right_of_dp >= 2) and (right_of_dp <= old_width) then
754
                if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
755
                    one_or_zero(0) := '1';
756
                end if;
757
            end if;
758
            if (right_of_dp >= 1) and (right_of_dp <= old_width) then
759
                if vec(right_of_dp-1) = '0' then
760
                    one_or_zero(0) := '0';
761
                end if;
762
            else
763
                one_or_zero(0) := '0';
764
            end if;
765
        else
766
            if (right_of_dp >= 1) and (right_of_dp <= old_width) then
767
                one_or_zero(0) :=  vec(right_of_dp-1);
768
            end if;
769
        end if;
770
        if new_arith = xlSigned then
771
            result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
772
                                                 std_logic_vector_to_signed(one_or_zero));
773
        else
774
            result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
775
                                                  std_logic_vector_to_unsigned(one_or_zero));
776
        end if;
777
        return result;
778
    end;
779
    function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
780
                                old_arith, new_width, new_bin_pt, new_arith
781
                                : INTEGER)
782
        return std_logic_vector
783
    is
784
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
785
        constant expected_new_width : integer :=  old_width - right_of_dp  + 1;
786
        variable vec : std_logic_vector(old_width-1 downto 0);
787
        variable one_or_zero : std_logic_vector(new_width-1 downto 0);
788
        variable truncated_val : std_logic_vector(new_width-1 downto 0);
789
        variable result : std_logic_vector(new_width-1 downto 0);
790
    begin
791
        vec := inp;
792
        if right_of_dp >= 0 then
793
            if new_arith = xlUnsigned then
794
                truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
795
                                          new_width);
796
            else
797
                truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
798
                                          new_width);
799
            end if;
800
        else
801
            if new_arith = xlUnsigned then
802
                truncated_val := zero_ext(pad_LSB(vec, old_width +
803
                                                  abs(right_of_dp)), new_width);
804
            else
805
                truncated_val := sign_ext(pad_LSB(vec, old_width +
806
                                                  abs(right_of_dp)), new_width);
807
            end if;
808
        end if;
809
        one_or_zero := (others => '0');
810
        if (right_of_dp >= 1) and (right_of_dp <= old_width) then
811
            if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
812
                one_or_zero(0) :=  vec(right_of_dp-1);
813
            else
814
                one_or_zero(0) :=  vec(right_of_dp);
815
            end if;
816
        end if;
817
        if new_arith = xlSigned then
818
            result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
819
                                                 std_logic_vector_to_signed(one_or_zero));
820
        else
821
            result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
822
                                                  std_logic_vector_to_unsigned(one_or_zero));
823
        end if;
824
        return result;
825
    end;
826
    function saturation_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
827
                              old_arith, new_width, new_bin_pt, new_arith
828
                              : INTEGER)
829
        return std_logic_vector
830
    is
831
        constant left_of_dp : integer := (old_width - old_bin_pt) -
832
                                         (new_width - new_bin_pt);
833
        variable vec : std_logic_vector(old_width-1 downto 0);
834
        variable result : std_logic_vector(new_width-1 downto 0);
835
        variable overflow : boolean;
836
    begin
837
        vec := inp;
838
        overflow := true;
839
        result := (others => '0');
840
        if (new_width >= old_width) then
841
            overflow := false;
842
        end if;
843
        if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
844
            if all_same(vec(old_width-1 downto new_width-1)) then
845
                overflow := false;
846
            end if;
847
        end if;
848
        if (old_arith = xlSigned and new_arith = xlUnsigned) then
849
            if (old_width > new_width) then
850
                if all_zeros(vec(old_width-1 downto new_width)) then
851
                    overflow := false;
852
                end if;
853
            else
854
                if (old_width = new_width) then
855
                    if (vec(new_width-1) = '0') then
856
                        overflow := false;
857
                    end if;
858
                end if;
859
            end if;
860
        end if;
861
        if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
862
            if (old_width > new_width) then
863
                if all_zeros(vec(old_width-1 downto new_width)) then
864
                    overflow := false;
865
                end if;
866
            else
867
                if (old_width = new_width) then
868
                    overflow := false;
869
                end if;
870
            end if;
871
        end if;
872
        if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
873
            if all_same(vec(old_width-1 downto new_width-1)) then
874
                overflow := false;
875
            end if;
876
        end if;
877
        if overflow then
878
            if new_arith = xlSigned then
879
                if vec(old_width-1) = '0' then
880
                    result := max_signed(new_width);
881
                else
882
                    result := min_signed(new_width);
883
                end if;
884
            else
885
                if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
886
                    result := (others => '0');
887
                else
888
                    result := (others => '1');
889
                end if;
890
            end if;
891
        else
892
            if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
893
                if (vec(old_width-1) = '1') then
894
                    vec := (others => '0');
895
                end if;
896
            end if;
897
            if new_width <= old_width then
898
                result := vec(new_width-1 downto 0);
899
            else
900
                if new_arith = xlUnsigned then
901
                    result := zero_ext(vec, new_width);
902
                else
903
                    result := sign_ext(vec, new_width);
904
                end if;
905
            end if;
906
        end if;
907
        return result;
908
    end;
909
   function wrap_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
910
                       old_arith, new_width, new_bin_pt, new_arith : INTEGER)
911
        return std_logic_vector
912
    is
913
        variable result : std_logic_vector(new_width-1 downto 0);
914
        variable result_arith : integer;
915
    begin
916
        if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
917
            result_arith := xlSigned;
918
        end if;
919
        result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
920
        return result;
921
    end;
922
    function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
923
    begin
924
        return max(a_bin_pt, b_bin_pt);
925
    end;
926
    function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
927
        return INTEGER is
928
    begin
929
        return  max(a_width - a_bin_pt, b_width - b_bin_pt);
930
    end;
931
    function pad_LSB(inp : std_logic_vector; new_width: integer)
932
        return STD_LOGIC_VECTOR
933
    is
934
        constant orig_width : integer := inp'length;
935
        variable vec : std_logic_vector(orig_width-1 downto 0);
936
        variable result : std_logic_vector(new_width-1 downto 0);
937
        variable pos : integer;
938
        constant pad_pos : integer := new_width - orig_width - 1;
939
    begin
940
        vec := inp;
941
        pos := new_width-1;
942
        if (new_width >= orig_width) then
943
            for i in orig_width-1 downto 0 loop
944
                result(pos) := vec(i);
945
                pos := pos - 1;
946
            end loop;
947
            if pad_pos >= 0 then
948
                for i in pad_pos downto 0 loop
949
                    result(i) := '0';
950
                end loop;
951
            end if;
952
        end if;
953
        return result;
954
    end;
955
    function sign_ext(inp : std_logic_vector; new_width : INTEGER)
956
        return std_logic_vector
957
    is
958
        constant old_width : integer := inp'length;
959
        variable vec : std_logic_vector(old_width-1 downto 0);
960
        variable result : std_logic_vector(new_width-1 downto 0);
961
    begin
962
        vec := inp;
963
        if new_width >= old_width then
964
            result(old_width-1 downto 0) := vec;
965
            if new_width-1 >= old_width then
966
                for i in new_width-1 downto old_width loop
967
                    result(i) := vec(old_width-1);
968
                end loop;
969
            end if;
970
        else
971
            result(new_width-1 downto 0) := vec(new_width-1 downto 0);
972
        end if;
973
        return result;
974
    end;
975
    function zero_ext(inp : std_logic_vector; new_width : INTEGER)
976
        return std_logic_vector
977
    is
978
        constant old_width : integer := inp'length;
979
        variable vec : std_logic_vector(old_width-1 downto 0);
980
        variable result : std_logic_vector(new_width-1 downto 0);
981
    begin
982
        vec := inp;
983
        if new_width >= old_width then
984
            result(old_width-1 downto 0) := vec;
985
            if new_width-1 >= old_width then
986
                for i in new_width-1 downto old_width loop
987
                    result(i) := '0';
988
                end loop;
989
            end if;
990
        else
991
            result(new_width-1 downto 0) := vec(new_width-1 downto 0);
992
        end if;
993
        return result;
994
    end;
995
    function zero_ext(inp : std_logic; new_width : INTEGER)
996
        return std_logic_vector
997
    is
998
        variable result : std_logic_vector(new_width-1 downto 0);
999
    begin
1000
        result(0) := inp;
1001
        for i in new_width-1 downto 1 loop
1002
            result(i) := '0';
1003
        end loop;
1004
        return result;
1005
    end;
1006
    function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
1007
        return std_logic_vector
1008
    is
1009
        constant orig_width : integer := inp'length;
1010
        variable vec : std_logic_vector(orig_width-1 downto 0);
1011
        variable result : std_logic_vector(new_width-1 downto 0);
1012
    begin
1013
        vec := inp;
1014
        if arith = xlUnsigned then
1015
            result := zero_ext(vec, new_width);
1016
        else
1017
            result := sign_ext(vec, new_width);
1018
        end if;
1019
        return result;
1020
    end;
1021
    function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
1022
        return STD_LOGIC_VECTOR
1023
    is
1024
        constant orig_width : integer := inp'length;
1025
        variable vec : std_logic_vector(orig_width-1 downto 0);
1026
        variable result : std_logic_vector(new_width-1 downto 0);
1027
        variable pos : integer;
1028
    begin
1029
        vec := inp;
1030
        pos := new_width-1;
1031
        if (arith = xlUnsigned) then
1032
            result(pos) := '0';
1033
            pos := pos - 1;
1034
        else
1035
            result(pos) := vec(orig_width-1);
1036
            pos := pos - 1;
1037
        end if;
1038
        if (new_width >= orig_width) then
1039
            for i in orig_width-1 downto 0 loop
1040
                result(pos) := vec(i);
1041
                pos := pos - 1;
1042
            end loop;
1043
            if pos >= 0 then
1044
                for i in pos downto 0 loop
1045
                    result(i) := '0';
1046
                end loop;
1047
            end if;
1048
        end if;
1049
        return result;
1050
    end;
1051
    function align_input(inp : std_logic_vector; old_width, delta, new_arith,
1052
                         new_width: INTEGER)
1053
        return std_logic_vector
1054
    is
1055
        variable vec : std_logic_vector(old_width-1 downto 0);
1056
        variable padded_inp : std_logic_vector((old_width + delta)-1  downto 0);
1057
        variable result : std_logic_vector(new_width-1 downto 0);
1058
    begin
1059
        vec := inp;
1060
        if delta > 0 then
1061
            padded_inp := pad_LSB(vec, old_width+delta);
1062
            result := extend_MSB(padded_inp, new_width, new_arith);
1063
        else
1064
            result := extend_MSB(vec, new_width, new_arith);
1065
        end if;
1066
        return result;
1067
    end;
1068
    function max(L, R: INTEGER) return INTEGER is
1069
    begin
1070
        if L > R then
1071
            return L;
1072
        else
1073
            return R;
1074
        end if;
1075
    end;
1076
    function min(L, R: INTEGER) return INTEGER is
1077
    begin
1078
        if L < R then
1079
            return L;
1080
        else
1081
            return R;
1082
        end if;
1083
    end;
1084
    function "="(left,right: STRING) return boolean is
1085
    begin
1086
        if (left'length /= right'length) then
1087
            return false;
1088
        else
1089
            test : for i in 1 to left'length loop
1090
                if left(i) /= right(i) then
1091
                    return false;
1092
                end if;
1093
            end loop test;
1094
            return true;
1095
        end if;
1096
    end;
1097
    -- synopsys translate_off
1098
    function is_binary_string_invalid (inp : string)
1099
        return boolean
1100
    is
1101
        variable vec : string(1 to inp'length);
1102
        variable result : boolean;
1103
    begin
1104
        vec := inp;
1105
        result := false;
1106
        for i in 1 to vec'length loop
1107
            if ( vec(i) = 'X' ) then
1108
                result := true;
1109
            end if;
1110
        end loop;
1111
        return result;
1112
    end;
1113
    function is_binary_string_undefined (inp : string)
1114
        return boolean
1115
    is
1116
        variable vec : string(1 to inp'length);
1117
        variable result : boolean;
1118
    begin
1119
        vec := inp;
1120
        result := false;
1121
        for i in 1 to vec'length loop
1122
            if ( vec(i) = 'U' ) then
1123
                result := true;
1124
            end if;
1125
        end loop;
1126
        return result;
1127
    end;
1128
    function is_XorU(inp : std_logic_vector)
1129
        return boolean
1130
    is
1131
        constant width : integer := inp'length;
1132
        variable vec : std_logic_vector(width-1 downto 0);
1133
        variable result : boolean;
1134
    begin
1135
        vec := inp;
1136
        result := false;
1137
        for i in 0 to width-1 loop
1138
            if (vec(i) = 'U') or (vec(i) = 'X') then
1139
                result := true;
1140
            end if;
1141
        end loop;
1142
        return result;
1143
    end;
1144
    function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
1145
        return real
1146
    is
1147
        variable  vec : std_logic_vector(inp'length-1 downto 0);
1148
        variable result, shift_val, undefined_real : real;
1149
        variable neg_num : boolean;
1150
    begin
1151
        vec := inp;
1152
        result := 0.0;
1153
        neg_num := false;
1154
        if vec(inp'length-1) = '1' then
1155
            neg_num := true;
1156
        end if;
1157
        for i in 0 to inp'length-1 loop
1158
            if  vec(i) = 'U' or vec(i) = 'X' then
1159
                return undefined_real;
1160
            end if;
1161
            if arith = xlSigned then
1162
                if neg_num then
1163
                    if vec(i) = '0' then
1164
                        result := result + 2.0**i;
1165
                    end if;
1166
                else
1167
                    if vec(i) = '1' then
1168
                        result := result + 2.0**i;
1169
                    end if;
1170
                end if;
1171
            else
1172
                if vec(i) = '1' then
1173
                    result := result + 2.0**i;
1174
                end if;
1175
            end if;
1176
        end loop;
1177
        if arith = xlSigned then
1178
            if neg_num then
1179
                result := result + 1.0;
1180
                result := result * (-1.0);
1181
            end if;
1182
        end if;
1183
        shift_val := 2.0**(-1*bin_pt);
1184
        result := result * shift_val;
1185
        return result;
1186
    end;
1187
    function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
1188
        return real
1189
    is
1190
        variable result : real := 0.0;
1191
    begin
1192
        if inp = '1' then
1193
            result := 1.0;
1194
        end if;
1195
        if arith = xlSigned then
1196
            assert false
1197
                report "It doesn't make sense to convert a 1 bit number to a signed real.";
1198
        end if;
1199
        return result;
1200
    end;
1201
    -- synopsys translate_on
1202
    function integer_to_std_logic_vector (inp : integer;  width, arith : integer)
1203
        return std_logic_vector
1204
    is
1205
        variable result : std_logic_vector(width-1 downto 0);
1206
        variable unsigned_val : unsigned(width-1 downto 0);
1207
        variable signed_val : signed(width-1 downto 0);
1208
    begin
1209
        if (arith = xlSigned) then
1210
            signed_val := to_signed(inp, width);
1211
            result := signed_to_std_logic_vector(signed_val);
1212
        else
1213
            unsigned_val := to_unsigned(inp, width);
1214
            result := unsigned_to_std_logic_vector(unsigned_val);
1215
        end if;
1216
        return result;
1217
    end;
1218
    function std_logic_vector_to_integer (inp : std_logic_vector;  arith : integer)
1219
        return integer
1220
    is
1221
        constant width : integer := inp'length;
1222
        variable unsigned_val : unsigned(width-1 downto 0);
1223
        variable signed_val : signed(width-1 downto 0);
1224
        variable result : integer;
1225
    begin
1226
        if (arith = xlSigned) then
1227
            signed_val := std_logic_vector_to_signed(inp);
1228
            result := to_integer(signed_val);
1229
        else
1230
            unsigned_val := std_logic_vector_to_unsigned(inp);
1231
            result := to_integer(unsigned_val);
1232
        end if;
1233
        return result;
1234
    end;
1235
    function std_logic_to_integer(constant inp : std_logic := '0')
1236
        return integer
1237
    is
1238
    begin
1239
        if inp = '1' then
1240
            return 1;
1241
        else
1242
            return 0;
1243
        end if;
1244
    end;
1245
    function makeZeroBinStr (width : integer) return STRING is
1246
        variable result : string(1 to width+3);
1247
    begin
1248
        result(1) := '0';
1249
        result(2) := 'b';
1250
        for i in 3 to width+2 loop
1251
            result(i) := '0';
1252
        end loop;
1253
        result(width+3) := '.';
1254
        return result;
1255
    end;
1256
    -- synopsys translate_off
1257
    function real_string_to_std_logic_vector (inp : string;  width, bin_pt, arith : integer)
1258
        return std_logic_vector
1259
    is
1260
        variable result : std_logic_vector(width-1 downto 0);
1261
    begin
1262
        result := (others => '0');
1263
        return result;
1264
    end;
1265
    function real_to_std_logic_vector (inp : real;  width, bin_pt, arith : integer)
1266
        return std_logic_vector
1267
    is
1268
        variable real_val : real;
1269
        variable int_val : integer;
1270
        variable result : std_logic_vector(width-1 downto 0) := (others => '0');
1271
        variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
1272
        variable signed_val : signed(width-1 downto 0) := (others => '0');
1273
    begin
1274
        real_val := inp;
1275
        int_val := integer(real_val * 2.0**(bin_pt));
1276
        if (arith = xlSigned) then
1277
            signed_val := to_signed(int_val, width);
1278
            result := signed_to_std_logic_vector(signed_val);
1279
        else
1280
            unsigned_val := to_unsigned(int_val, width);
1281
            result := unsigned_to_std_logic_vector(unsigned_val);
1282
        end if;
1283
        return result;
1284
    end;
1285
    -- synopsys translate_on
1286
    function valid_bin_string (inp : string)
1287
        return boolean
1288
    is
1289
        variable vec : string(1 to inp'length);
1290
    begin
1291
        vec := inp;
1292
        if (vec(1) = '0' and vec(2) = 'b') then
1293
            return true;
1294
        else
1295
            return false;
1296
        end if;
1297
    end;
1298
    function hex_string_to_std_logic_vector(inp: string; width : integer)
1299
        return std_logic_vector is
1300
        constant strlen       : integer := inp'LENGTH;
1301
        variable result       : std_logic_vector(width-1 downto 0);
1302
        variable bitval       : std_logic_vector((strlen*4)-1 downto 0);
1303
        variable posn         : integer;
1304
        variable ch           : character;
1305
        variable vec          : string(1 to strlen);
1306
    begin
1307
        vec := inp;
1308
        result := (others => '0');
1309
        posn := (strlen*4)-1;
1310
        for i in 1 to strlen loop
1311
            ch := vec(i);
1312
            case ch is
1313
                when '0' => bitval(posn downto posn-3) := "0000";
1314
                when '1' => bitval(posn downto posn-3) := "0001";
1315
                when '2' => bitval(posn downto posn-3) := "0010";
1316
                when '3' => bitval(posn downto posn-3) := "0011";
1317
                when '4' => bitval(posn downto posn-3) := "0100";
1318
                when '5' => bitval(posn downto posn-3) := "0101";
1319
                when '6' => bitval(posn downto posn-3) := "0110";
1320
                when '7' => bitval(posn downto posn-3) := "0111";
1321
                when '8' => bitval(posn downto posn-3) := "1000";
1322
                when '9' => bitval(posn downto posn-3) := "1001";
1323
                when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
1324
                when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
1325
                when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
1326
                when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
1327
                when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
1328
                when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
1329
                when others => bitval(posn downto posn-3) := "XXXX";
1330
                               -- synopsys translate_off
1331
                               ASSERT false
1332
                                   REPORT "Invalid hex value" SEVERITY ERROR;
1333
                               -- synopsys translate_on
1334
            end case;
1335
            posn := posn - 4;
1336
        end loop;
1337
        if (width <= strlen*4) then
1338
            result :=  bitval(width-1 downto 0);
1339
        else
1340
            result((strlen*4)-1 downto 0) := bitval;
1341
        end if;
1342
        return result;
1343
    end;
1344
    function bin_string_to_std_logic_vector (inp : string)
1345
        return std_logic_vector
1346
    is
1347
        variable pos : integer;
1348
        variable vec : string(1 to inp'length);
1349
        variable result : std_logic_vector(inp'length-1 downto 0);
1350
    begin
1351
        vec := inp;
1352
        pos := inp'length-1;
1353
        result := (others => '0');
1354
        for i in 1 to vec'length loop
1355
            -- synopsys translate_off
1356
            if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U')  then
1357
                assert false
1358
                    report "Input string is larger than output std_logic_vector. Truncating output.";
1359
                return result;
1360
            end if;
1361
            -- synopsys translate_on
1362
            if vec(i) = '0' then
1363
                result(pos) := '0';
1364
                pos := pos - 1;
1365
            end if;
1366
            if vec(i) = '1' then
1367
                result(pos) := '1';
1368
                pos := pos - 1;
1369
            end if;
1370
            -- synopsys translate_off
1371
            if (vec(i) = 'X' or vec(i) = 'U') then
1372
                result(pos) := 'U';
1373
                pos := pos - 1;
1374
            end if;
1375
            -- synopsys translate_on
1376
        end loop;
1377
        return result;
1378
    end;
1379
    function bin_string_element_to_std_logic_vector (inp : string;  width, index : integer)
1380
        return std_logic_vector
1381
    is
1382
        constant str_width : integer := width + 4;
1383
        constant inp_len : integer := inp'length;
1384
        constant num_elements : integer := (inp_len + 1)/str_width;
1385
        constant reverse_index : integer := (num_elements-1) - index;
1386
        variable left_pos : integer;
1387
        variable right_pos : integer;
1388
        variable vec : string(1 to inp'length);
1389
        variable result : std_logic_vector(width-1 downto 0);
1390
    begin
1391
        vec := inp;
1392
        result := (others => '0');
1393
        if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
1394
            left_pos := 1;
1395
            right_pos := width + 3;
1396
            result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
1397
        end if;
1398
        if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
1399
            left_pos := (reverse_index * str_width) + 1;
1400
            right_pos := left_pos + width + 2;
1401
            result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
1402
        end if;
1403
        return result;
1404
    end;
1405
   -- synopsys translate_off
1406
    function std_logic_vector_to_bin_string(inp : std_logic_vector)
1407
        return string
1408
    is
1409
        variable vec : std_logic_vector(1 to inp'length);
1410
        variable result : string(vec'range);
1411
    begin
1412
        vec := inp;
1413
        for i in vec'range loop
1414
            result(i) := to_char(vec(i));
1415
        end loop;
1416
        return result;
1417
    end;
1418
    function std_logic_to_bin_string(inp : std_logic)
1419
        return string
1420
    is
1421
        variable result : string(1 to 3);
1422
    begin
1423
        result(1) := '0';
1424
        result(2) := 'b';
1425
        result(3) := to_char(inp);
1426
        return result;
1427
    end;
1428
    function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
1429
        return string
1430
    is
1431
        variable width : integer := inp'length;
1432
        variable vec : std_logic_vector(width-1 downto 0);
1433
        variable str_pos : integer;
1434
        variable result : string(1 to width+3);
1435
    begin
1436
        vec := inp;
1437
        str_pos := 1;
1438
        result(str_pos) := '0';
1439
        str_pos := 2;
1440
        result(str_pos) := 'b';
1441
        str_pos := 3;
1442
        for i in width-1 downto 0  loop
1443
            if (((width+3) - bin_pt) = str_pos) then
1444
                result(str_pos) := '.';
1445
                str_pos := str_pos + 1;
1446
            end if;
1447
            result(str_pos) := to_char(vec(i));
1448
            str_pos := str_pos + 1;
1449
        end loop;
1450
        if (bin_pt = 0) then
1451
            result(str_pos) := '.';
1452
        end if;
1453
        return result;
1454
    end;
1455
    function real_to_bin_string(inp : real;  width, bin_pt, arith : integer)
1456
        return string
1457
    is
1458
        variable result : string(1 to width);
1459
        variable vec : std_logic_vector(width-1 downto 0);
1460
    begin
1461
        vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
1462
        result := std_logic_vector_to_bin_string(vec);
1463
        return result;
1464
    end;
1465
    function real_to_string (inp : real) return string
1466
    is
1467
        variable result : string(1 to display_precision) := (others => ' ');
1468
    begin
1469
        result(real'image(inp)'range) := real'image(inp);
1470
        return result;
1471
    end;
1472
    -- synopsys translate_on
1473
end conv_pkg;
1474
 
1475
-------------------------------------------------------------------
1476
-- System Generator version 13.2 VHDL source file.
1477
--
1478
-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This
1479
-- text/file contains proprietary, confidential information of Xilinx,
1480
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
1481
-- copied and/or disclosed only pursuant to the terms of a valid license
1482
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1483
-- this text/file solely for design, simulation, implementation and
1484
-- creation of design files limited to Xilinx devices or technologies.
1485
-- Use with non-Xilinx devices or technologies is expressly prohibited
1486
-- and immediately terminates your license unless covered by a separate
1487
-- agreement.
1488
--
1489
-- Xilinx is providing this design, code, or information "as is" solely
1490
-- for use in developing programs and solutions for Xilinx devices.  By
1491
-- providing this design, code, or information as one possible
1492
-- implementation of this feature, application or standard, Xilinx is
1493
-- making no representation that this implementation is free from any
1494
-- claims of infringement.  You are responsible for obtaining any rights
1495
-- you may require for your implementation.  Xilinx expressly disclaims
1496
-- any warranty whatsoever with respect to the adequacy of the
1497
-- implementation, including but not limited to warranties of
1498
-- merchantability or fitness for a particular purpose.
1499
--
1500
-- Xilinx products are not intended for use in life support appliances,
1501
-- devices, or systems.  Use in such applications is expressly prohibited.
1502
--
1503
-- Any modifications that are made to the source code are done at the user's
1504
-- sole risk and will be unsupported.
1505
--
1506
-- This copyright and support notice must be retained as part of this
1507
-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights
1508
-- reserved.
1509
-------------------------------------------------------------------
1510
-- synopsys translate_off
1511
library unisim;
1512
use unisim.vcomponents.all;
1513
-- synopsys translate_on
1514
library IEEE;
1515
use IEEE.std_logic_1164.all;
1516
use work.conv_pkg.all;
1517
entity single_reg_w_init is
1518
  generic (
1519
    width: integer := 8;
1520
    init_index: integer := 0;
1521
    init_value: bit_vector := b"0000"
1522
  );
1523
  port (
1524
    i: in std_logic_vector(width - 1 downto 0);
1525
    ce: in std_logic;
1526
    clr: in std_logic;
1527
    clk: in std_logic;
1528
    o: out std_logic_vector(width - 1 downto 0)
1529
  );
1530
end single_reg_w_init;
1531
architecture structural of single_reg_w_init is
1532
  function build_init_const(width: integer;
1533
                            init_index: integer;
1534
                            init_value: bit_vector)
1535
    return std_logic_vector
1536
  is
1537
    variable result: std_logic_vector(width - 1 downto 0);
1538
  begin
1539
    if init_index = 0 then
1540
      result := (others => '0');
1541
    elsif init_index = 1 then
1542
      result := (others => '0');
1543
      result(0) := '1';
1544
    else
1545
      result := to_stdlogicvector(init_value);
1546
    end if;
1547
    return result;
1548
  end;
1549
  component fdre
1550
    port (
1551
      q: out std_ulogic;
1552
      d: in  std_ulogic;
1553
      c: in  std_ulogic;
1554
      ce: in  std_ulogic;
1555
      r: in  std_ulogic
1556
    );
1557
  end component;
1558
  attribute syn_black_box of fdre: component is true;
1559
  attribute fpga_dont_touch of fdre: component is "true";
1560
  component fdse
1561
    port (
1562
      q: out std_ulogic;
1563
      d: in  std_ulogic;
1564
      c: in  std_ulogic;
1565
      ce: in  std_ulogic;
1566
      s: in  std_ulogic
1567
    );
1568
  end component;
1569
  attribute syn_black_box of fdse: component is true;
1570
  attribute fpga_dont_touch of fdse: component is "true";
1571
  constant init_const: std_logic_vector(width - 1 downto 0)
1572
    := build_init_const(width, init_index, init_value);
1573
begin
1574
  fd_prim_array: for index in 0 to width - 1 generate
1575
    bit_is_0: if (init_const(index) = '0') generate
1576
      fdre_comp: fdre
1577
        port map (
1578
          c => clk,
1579
          d => i(index),
1580
          q => o(index),
1581
          ce => ce,
1582
          r => clr
1583
        );
1584
    end generate;
1585
    bit_is_1: if (init_const(index) = '1') generate
1586
      fdse_comp: fdse
1587
        port map (
1588
          c => clk,
1589
          d => i(index),
1590
          q => o(index),
1591
          ce => ce,
1592
          s => clr
1593
        );
1594
    end generate;
1595
  end generate;
1596
end architecture structural;
1597
-- synopsys translate_off
1598
library unisim;
1599
use unisim.vcomponents.all;
1600
-- synopsys translate_on
1601
library IEEE;
1602
use IEEE.std_logic_1164.all;
1603
use work.conv_pkg.all;
1604
entity synth_reg_w_init is
1605
  generic (
1606
    width: integer := 8;
1607
    init_index: integer := 0;
1608
    init_value: bit_vector := b"0000";
1609
    latency: integer := 1
1610
  );
1611
  port (
1612
    i: in std_logic_vector(width - 1 downto 0);
1613
    ce: in std_logic;
1614
    clr: in std_logic;
1615
    clk: in std_logic;
1616
    o: out std_logic_vector(width - 1 downto 0)
1617
  );
1618
end synth_reg_w_init;
1619
architecture structural of synth_reg_w_init is
1620
  component single_reg_w_init
1621
    generic (
1622
      width: integer := 8;
1623
      init_index: integer := 0;
1624
      init_value: bit_vector := b"0000"
1625
    );
1626
    port (
1627
      i: in std_logic_vector(width - 1 downto 0);
1628
      ce: in std_logic;
1629
      clr: in std_logic;
1630
      clk: in std_logic;
1631
      o: out std_logic_vector(width - 1 downto 0)
1632
    );
1633
  end component;
1634
  signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
1635
  signal dly_clr: std_logic;
1636
begin
1637
  latency_eq_0: if (latency = 0) generate
1638
    o <= i;
1639
  end generate;
1640
  latency_gt_0: if (latency >= 1) generate
1641
    dly_i((latency + 1) * width - 1 downto latency * width) <= i
1642
      after 200 ps;
1643
    dly_clr <= clr after 200 ps;
1644
    fd_array: for index in latency downto 1 generate
1645
       reg_comp: single_reg_w_init
1646
          generic map (
1647
            width => width,
1648
            init_index => init_index,
1649
            init_value => init_value
1650
          )
1651
          port map (
1652
            clk => clk,
1653
            i => dly_i((index + 1) * width - 1 downto index * width),
1654
            o => dly_i(index * width - 1 downto (index - 1) * width),
1655
            ce => ce,
1656
            clr => dly_clr
1657
          );
1658
    end generate;
1659
    o <= dly_i(width - 1 downto 0);
1660
  end generate;
1661
end structural;
1662
 
1663
-------------------------------------------------------------------
1664
-- System Generator version 13.2 VHDL source file.
1665
--
1666
-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This
1667
-- text/file contains proprietary, confidential information of Xilinx,
1668
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
1669
-- copied and/or disclosed only pursuant to the terms of a valid license
1670
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1671
-- this text/file solely for design, simulation, implementation and
1672
-- creation of design files limited to Xilinx devices or technologies.
1673
-- Use with non-Xilinx devices or technologies is expressly prohibited
1674
-- and immediately terminates your license unless covered by a separate
1675
-- agreement.
1676
--
1677
-- Xilinx is providing this design, code, or information "as is" solely
1678
-- for use in developing programs and solutions for Xilinx devices.  By
1679
-- providing this design, code, or information as one possible
1680
-- implementation of this feature, application or standard, Xilinx is
1681
-- making no representation that this implementation is free from any
1682
-- claims of infringement.  You are responsible for obtaining any rights
1683
-- you may require for your implementation.  Xilinx expressly disclaims
1684
-- any warranty whatsoever with respect to the adequacy of the
1685
-- implementation, including but not limited to warranties of
1686
-- merchantability or fitness for a particular purpose.
1687
--
1688
-- Xilinx products are not intended for use in life support appliances,
1689
-- devices, or systems.  Use in such applications is expressly prohibited.
1690
--
1691
-- Any modifications that are made to the source code are done at the user's
1692
-- sole risk and will be unsupported.
1693
--
1694
-- This copyright and support notice must be retained as part of this
1695
-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights
1696
-- reserved.
1697
-------------------------------------------------------------------
1698
library IEEE;
1699
use IEEE.std_logic_1164.all;
1700
entity xland2 is
1701
  port (
1702
    a : in std_logic;
1703
    b : in std_logic;
1704
    dout : out std_logic
1705
    );
1706
end xland2;
1707
architecture behavior of xland2 is
1708
begin
1709
    dout <= a and b;
1710
end behavior;
1711
 
1712
-------------------------------------------------------------------
1713
-- System Generator version 13.2 VHDL source file.
1714
--
1715
-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This
1716
-- text/file contains proprietary, confidential information of Xilinx,
1717
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
1718
-- copied and/or disclosed only pursuant to the terms of a valid license
1719
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1720
-- this text/file solely for design, simulation, implementation and
1721
-- creation of design files limited to Xilinx devices or technologies.
1722
-- Use with non-Xilinx devices or technologies is expressly prohibited
1723
-- and immediately terminates your license unless covered by a separate
1724
-- agreement.
1725
--
1726
-- Xilinx is providing this design, code, or information "as is" solely
1727
-- for use in developing programs and solutions for Xilinx devices.  By
1728
-- providing this design, code, or information as one possible
1729
-- implementation of this feature, application or standard, Xilinx is
1730
-- making no representation that this implementation is free from any
1731
-- claims of infringement.  You are responsible for obtaining any rights
1732
-- you may require for your implementation.  Xilinx expressly disclaims
1733
-- any warranty whatsoever with respect to the adequacy of the
1734
-- implementation, including but not limited to warranties of
1735
-- merchantability or fitness for a particular purpose.
1736
--
1737
-- Xilinx products are not intended for use in life support appliances,
1738
-- devices, or systems.  Use in such applications is expressly prohibited.
1739
--
1740
-- Any modifications that are made to the source code are done at the user's
1741
-- sole risk and will be unsupported.
1742
--
1743
-- This copyright and support notice must be retained as part of this
1744
-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights
1745
-- reserved.
1746
-------------------------------------------------------------------
1747
library IEEE;
1748
use IEEE.std_logic_1164.all;
1749
entity xlaxi_rst_gen is
1750
  generic (
1751
    has_aresetn: integer := -1
1752
  );
1753
  port (
1754
    aclk: in std_logic;
1755
    i_aresetn : in std_logic;
1756
    ce : in std_logic;
1757
    o_aresetn : out std_logic
1758
    );
1759
end xlaxi_rst_gen;
1760
architecture behavior of xlaxi_rst_gen is
1761
  signal reset_gen1: std_logic  := '0';
1762
  signal reset_gen_d1: std_logic        := '0';
1763
  signal reset_gen_d2: std_logic := '0';
1764
begin
1765
        o_aresetn <= reset_gen_d2 when (has_aresetn = 0)
1766
                else not ( (not i_aresetn) and ce );
1767
 process(aclk)
1768
 begin
1769
         if(aclk'event AND aclk = '1') then
1770
                         reset_gen1 <= '1';
1771
                         reset_gen_d1 <= reset_gen1;
1772
                         reset_gen_d2 <= reset_gen_d1;
1773
        end if;
1774
 end process;
1775
end behavior;
1776
library IEEE;
1777
use IEEE.std_logic_1164.all;
1778
use work.conv_pkg.all;
1779
 
1780
entity PCIe_UserLogic_00 is
1781
  port (
1782
    bram_rd_dout: in std_logic_vector(63 downto 0);
1783
    debug_in_1i: in std_logic_vector(31 downto 0);
1784
    debug_in_2i: in std_logic_vector(31 downto 0);
1785
    debug_in_3i: in std_logic_vector(31 downto 0);
1786
    debug_in_4i: in std_logic_vector(31 downto 0);
1787
    dma_host2board_busy: in std_logic;
1788
    dma_host2board_done: in std_logic;
1789
    fifo_rd_count: in std_logic_vector(14 downto 0);
1790
    fifo_rd_dout: in std_logic_vector(71 downto 0);
1791
    fifo_rd_empty: in std_logic;
1792
    fifo_rd_pempty: in std_logic;
1793
    fifo_rd_valid: in std_logic;
1794
    fifo_wr_count: in std_logic_vector(14 downto 0);
1795
    fifo_wr_full: in std_logic;
1796
    fifo_wr_pfull: in std_logic;
1797
    inout_logic_cw_ce: in std_logic := '1';
1798
    inout_logic_cw_clk: in std_logic;
1799
    reg01_td: in std_logic_vector(31 downto 0);
1800
    reg01_tv: in std_logic;
1801
    reg02_td: in std_logic_vector(31 downto 0);
1802
    reg02_tv: in std_logic;
1803
    reg03_td: in std_logic_vector(31 downto 0);
1804
    reg03_tv: in std_logic;
1805
    reg04_td: in std_logic_vector(31 downto 0);
1806
    reg04_tv: in std_logic;
1807
    reg05_td: in std_logic_vector(31 downto 0);
1808
    reg05_tv: in std_logic;
1809
    reg06_td: in std_logic_vector(31 downto 0);
1810
    reg06_tv: in std_logic;
1811
    reg07_td: in std_logic_vector(31 downto 0);
1812
    reg07_tv: in std_logic;
1813
    reg08_td: in std_logic_vector(31 downto 0);
1814
    reg08_tv: in std_logic;
1815
    reg09_td: in std_logic_vector(31 downto 0);
1816
    reg09_tv: in std_logic;
1817
    reg10_td: in std_logic_vector(31 downto 0);
1818
    reg10_tv: in std_logic;
1819
    reg11_td: in std_logic_vector(31 downto 0);
1820
    reg11_tv: in std_logic;
1821
    reg12_td: in std_logic_vector(31 downto 0);
1822
    reg12_tv: in std_logic;
1823
    reg13_td: in std_logic_vector(31 downto 0);
1824
    reg13_tv: in std_logic;
1825
    reg14_td: in std_logic_vector(31 downto 0);
1826
    reg14_tv: in std_logic;
1827
    rst_i: in std_logic;
1828
    user_logic_cw_ce: in std_logic := '1';
1829
    user_logic_cw_clk: in std_logic;
1830
    bram_rd_addr: out std_logic_vector(11 downto 0);
1831
    bram_wr_addr: out std_logic_vector(11 downto 0);
1832
    bram_wr_din: out std_logic_vector(63 downto 0);
1833
    bram_wr_en: out std_logic_vector(7 downto 0);
1834
    fifo_rd_en: out std_logic;
1835
    fifo_wr_din: out std_logic_vector(71 downto 0);
1836
    fifo_wr_en: out std_logic;
1837
    reg01_rd: out std_logic_vector(31 downto 0);
1838
    reg01_rv: out std_logic;
1839
    reg02_rd: out std_logic_vector(31 downto 0);
1840
    reg02_rv: out std_logic;
1841
    reg03_rd: out std_logic_vector(31 downto 0);
1842
    reg03_rv: out std_logic;
1843
    reg04_rd: out std_logic_vector(31 downto 0);
1844
    reg04_rv: out std_logic;
1845
    reg05_rd: out std_logic_vector(31 downto 0);
1846
    reg05_rv: out std_logic;
1847
    reg06_rd: out std_logic_vector(31 downto 0);
1848
    reg06_rv: out std_logic;
1849
    reg07_rd: out std_logic_vector(31 downto 0);
1850
    reg07_rv: out std_logic;
1851
    reg08_rd: out std_logic_vector(31 downto 0);
1852
    reg08_rv: out std_logic;
1853
    reg09_rd: out std_logic_vector(31 downto 0);
1854
    reg09_rv: out std_logic;
1855
    reg10_rd: out std_logic_vector(31 downto 0);
1856
    reg10_rv: out std_logic;
1857
    reg11_rd: out std_logic_vector(31 downto 0);
1858
    reg11_rv: out std_logic;
1859
    reg12_rd: out std_logic_vector(31 downto 0);
1860
    reg12_rv: out std_logic;
1861
    reg13_rd: out std_logic_vector(31 downto 0);
1862
    reg13_rv: out std_logic;
1863
    reg14_rd: out std_logic_vector(31 downto 0);
1864
    reg14_rv: out std_logic;
1865
    rst_o: out std_logic;
1866
    user_int_1o: out std_logic;
1867
    user_int_2o: out std_logic;
1868
    user_int_3o: out std_logic
1869
  );
1870
end PCIe_UserLogic_00;
1871
 
1872
architecture structural of PCIe_UserLogic_00 is
1873
  component inout_logic_cw
1874
    port (
1875
      ce: in std_logic := '1';
1876
      clk: in std_logic;
1877
      debug_in_1i: in std_logic_vector(31 downto 0);
1878
      debug_in_2i: in std_logic_vector(31 downto 0);
1879
      debug_in_3i: in std_logic_vector(31 downto 0);
1880
      debug_in_4i: in std_logic_vector(31 downto 0);
1881
      dma_host2board_busy: in std_logic;
1882
      dma_host2board_done: in std_logic;
1883
      from_register10_data_out: in std_logic_vector(31 downto 0);
1884
      from_register11_data_out: in std_logic_vector(31 downto 0);
1885
      from_register12_data_out: in std_logic_vector(0 downto 0);
1886
      from_register13_data_out: in std_logic_vector(31 downto 0);
1887
      from_register14_data_out: in std_logic_vector(0 downto 0);
1888
      from_register15_data_out: in std_logic_vector(31 downto 0);
1889
      from_register16_data_out: in std_logic_vector(0 downto 0);
1890
      from_register17_data_out: in std_logic_vector(31 downto 0);
1891
      from_register18_data_out: in std_logic_vector(0 downto 0);
1892
      from_register19_data_out: in std_logic_vector(31 downto 0);
1893
      from_register1_data_out: in std_logic_vector(0 downto 0);
1894
      from_register20_data_out: in std_logic_vector(0 downto 0);
1895
      from_register21_data_out: in std_logic_vector(31 downto 0);
1896
      from_register22_data_out: in std_logic_vector(0 downto 0);
1897
      from_register23_data_out: in std_logic_vector(31 downto 0);
1898
      from_register24_data_out: in std_logic_vector(0 downto 0);
1899
      from_register25_data_out: in std_logic_vector(31 downto 0);
1900
      from_register26_data_out: in std_logic_vector(0 downto 0);
1901
      from_register27_data_out: in std_logic_vector(31 downto 0);
1902
      from_register28_data_out: in std_logic_vector(0 downto 0);
1903
      from_register2_data_out: in std_logic_vector(0 downto 0);
1904
      from_register3_data_out: in std_logic_vector(31 downto 0);
1905
      from_register4_data_out: in std_logic_vector(0 downto 0);
1906
      from_register5_data_out: in std_logic_vector(31 downto 0);
1907
      from_register6_data_out: in std_logic_vector(0 downto 0);
1908
      from_register7_data_out: in std_logic_vector(31 downto 0);
1909
      from_register8_data_out: in std_logic_vector(31 downto 0);
1910
      from_register9_data_out: in std_logic_vector(0 downto 0);
1911
      reg01_td: in std_logic_vector(31 downto 0);
1912
      reg01_tv: in std_logic;
1913
      reg02_td: in std_logic_vector(31 downto 0);
1914
      reg02_tv: in std_logic;
1915
      reg03_td: in std_logic_vector(31 downto 0);
1916
      reg03_tv: in std_logic;
1917
      reg04_td: in std_logic_vector(31 downto 0);
1918
      reg04_tv: in std_logic;
1919
      reg05_td: in std_logic_vector(31 downto 0);
1920
      reg05_tv: in std_logic;
1921
      reg06_td: in std_logic_vector(31 downto 0);
1922
      reg06_tv: in std_logic;
1923
      reg07_td: in std_logic_vector(31 downto 0);
1924
      reg07_tv: in std_logic;
1925
      reg08_td: in std_logic_vector(31 downto 0);
1926
      reg08_tv: in std_logic;
1927
      reg09_td: in std_logic_vector(31 downto 0);
1928
      reg09_tv: in std_logic;
1929
      reg10_td: in std_logic_vector(31 downto 0);
1930
      reg10_tv: in std_logic;
1931
      reg11_td: in std_logic_vector(31 downto 0);
1932
      reg11_tv: in std_logic;
1933
      reg12_td: in std_logic_vector(31 downto 0);
1934
      reg12_tv: in std_logic;
1935
      reg13_td: in std_logic_vector(31 downto 0);
1936
      reg13_tv: in std_logic;
1937
      reg14_td: in std_logic_vector(31 downto 0);
1938
      reg14_tv: in std_logic;
1939
      to_register10_dout: in std_logic_vector(0 downto 0);
1940
      to_register11_dout: in std_logic_vector(31 downto 0);
1941
      to_register12_dout: in std_logic_vector(0 downto 0);
1942
      to_register13_dout: in std_logic_vector(31 downto 0);
1943
      to_register14_dout: in std_logic_vector(0 downto 0);
1944
      to_register15_dout: in std_logic_vector(31 downto 0);
1945
      to_register16_dout: in std_logic_vector(0 downto 0);
1946
      to_register17_dout: in std_logic_vector(31 downto 0);
1947
      to_register18_dout: in std_logic_vector(0 downto 0);
1948
      to_register19_dout: in std_logic_vector(0 downto 0);
1949
      to_register1_dout: in std_logic_vector(31 downto 0);
1950
      to_register20_dout: in std_logic_vector(31 downto 0);
1951
      to_register21_dout: in std_logic_vector(0 downto 0);
1952
      to_register22_dout: in std_logic_vector(31 downto 0);
1953
      to_register23_dout: in std_logic_vector(0 downto 0);
1954
      to_register24_dout: in std_logic_vector(31 downto 0);
1955
      to_register25_dout: in std_logic_vector(0 downto 0);
1956
      to_register26_dout: in std_logic_vector(31 downto 0);
1957
      to_register27_dout: in std_logic_vector(0 downto 0);
1958
      to_register28_dout: in std_logic_vector(31 downto 0);
1959
      to_register29_dout: in std_logic_vector(0 downto 0);
1960
      to_register2_dout: in std_logic_vector(31 downto 0);
1961
      to_register30_dout: in std_logic_vector(31 downto 0);
1962
      to_register31_dout: in std_logic_vector(0 downto 0);
1963
      to_register32_dout: in std_logic_vector(31 downto 0);
1964
      to_register33_dout: in std_logic_vector(0 downto 0);
1965
      to_register34_dout: in std_logic_vector(31 downto 0);
1966
      to_register3_dout: in std_logic_vector(0 downto 0);
1967
      to_register4_dout: in std_logic_vector(0 downto 0);
1968
      to_register5_dout: in std_logic_vector(31 downto 0);
1969
      to_register6_dout: in std_logic_vector(31 downto 0);
1970
      to_register7_dout: in std_logic_vector(31 downto 0);
1971
      to_register8_dout: in std_logic_vector(0 downto 0);
1972
      to_register9_dout: in std_logic_vector(31 downto 0);
1973
      reg01_rd: out std_logic_vector(31 downto 0);
1974
      reg01_rv: out std_logic;
1975
      reg02_rd: out std_logic_vector(31 downto 0);
1976
      reg02_rv: out std_logic;
1977
      reg03_rd: out std_logic_vector(31 downto 0);
1978
      reg03_rv: out std_logic;
1979
      reg04_rd: out std_logic_vector(31 downto 0);
1980
      reg04_rv: out std_logic;
1981
      reg05_rd: out std_logic_vector(31 downto 0);
1982
      reg05_rv: out std_logic;
1983
      reg06_rd: out std_logic_vector(31 downto 0);
1984
      reg06_rv: out std_logic;
1985
      reg07_rd: out std_logic_vector(31 downto 0);
1986
      reg07_rv: out std_logic;
1987
      reg08_rd: out std_logic_vector(31 downto 0);
1988
      reg08_rv: out std_logic;
1989
      reg09_rd: out std_logic_vector(31 downto 0);
1990
      reg09_rv: out std_logic;
1991
      reg10_rd: out std_logic_vector(31 downto 0);
1992
      reg10_rv: out std_logic;
1993
      reg11_rd: out std_logic_vector(31 downto 0);
1994
      reg11_rv: out std_logic;
1995
      reg12_rd: out std_logic_vector(31 downto 0);
1996
      reg12_rv: out std_logic;
1997
      reg13_rd: out std_logic_vector(31 downto 0);
1998
      reg13_rv: out std_logic;
1999
      reg14_rd: out std_logic_vector(31 downto 0);
2000
      reg14_rv: out std_logic;
2001
      to_register10_ce: out std_logic;
2002
      to_register10_clk: out std_logic;
2003
      to_register10_clr: out std_logic;
2004
      to_register10_data_in: out std_logic_vector(0 downto 0);
2005
      to_register10_en: out std_logic_vector(0 downto 0);
2006
      to_register11_ce: out std_logic;
2007
      to_register11_clk: out std_logic;
2008
      to_register11_clr: out std_logic;
2009
      to_register11_data_in: out std_logic_vector(31 downto 0);
2010
      to_register11_en: out std_logic_vector(0 downto 0);
2011
      to_register12_ce: out std_logic;
2012
      to_register12_clk: out std_logic;
2013
      to_register12_clr: out std_logic;
2014
      to_register12_data_in: out std_logic_vector(0 downto 0);
2015
      to_register12_en: out std_logic_vector(0 downto 0);
2016
      to_register13_ce: out std_logic;
2017
      to_register13_clk: out std_logic;
2018
      to_register13_clr: out std_logic;
2019
      to_register13_data_in: out std_logic_vector(31 downto 0);
2020
      to_register13_en: out std_logic_vector(0 downto 0);
2021
      to_register14_ce: out std_logic;
2022
      to_register14_clk: out std_logic;
2023
      to_register14_clr: out std_logic;
2024
      to_register14_data_in: out std_logic_vector(0 downto 0);
2025
      to_register14_en: out std_logic_vector(0 downto 0);
2026
      to_register15_ce: out std_logic;
2027
      to_register15_clk: out std_logic;
2028
      to_register15_clr: out std_logic;
2029
      to_register15_data_in: out std_logic_vector(31 downto 0);
2030
      to_register15_en: out std_logic_vector(0 downto 0);
2031
      to_register16_ce: out std_logic;
2032
      to_register16_clk: out std_logic;
2033
      to_register16_clr: out std_logic;
2034
      to_register16_data_in: out std_logic_vector(0 downto 0);
2035
      to_register16_en: out std_logic_vector(0 downto 0);
2036
      to_register17_ce: out std_logic;
2037
      to_register17_clk: out std_logic;
2038
      to_register17_clr: out std_logic;
2039
      to_register17_data_in: out std_logic_vector(31 downto 0);
2040
      to_register17_en: out std_logic_vector(0 downto 0);
2041
      to_register18_ce: out std_logic;
2042
      to_register18_clk: out std_logic;
2043
      to_register18_clr: out std_logic;
2044
      to_register18_data_in: out std_logic_vector(0 downto 0);
2045
      to_register18_en: out std_logic_vector(0 downto 0);
2046
      to_register19_ce: out std_logic;
2047
      to_register19_clk: out std_logic;
2048
      to_register19_clr: out std_logic;
2049
      to_register19_data_in: out std_logic_vector(0 downto 0);
2050
      to_register19_en: out std_logic_vector(0 downto 0);
2051
      to_register1_ce: out std_logic;
2052
      to_register1_clk: out std_logic;
2053
      to_register1_clr: out std_logic;
2054
      to_register1_data_in: out std_logic_vector(31 downto 0);
2055
      to_register1_en: out std_logic_vector(0 downto 0);
2056
      to_register20_ce: out std_logic;
2057
      to_register20_clk: out std_logic;
2058
      to_register20_clr: out std_logic;
2059
      to_register20_data_in: out std_logic_vector(31 downto 0);
2060
      to_register20_en: out std_logic_vector(0 downto 0);
2061
      to_register21_ce: out std_logic;
2062
      to_register21_clk: out std_logic;
2063
      to_register21_clr: out std_logic;
2064
      to_register21_data_in: out std_logic_vector(0 downto 0);
2065
      to_register21_en: out std_logic_vector(0 downto 0);
2066
      to_register22_ce: out std_logic;
2067
      to_register22_clk: out std_logic;
2068
      to_register22_clr: out std_logic;
2069
      to_register22_data_in: out std_logic_vector(31 downto 0);
2070
      to_register22_en: out std_logic_vector(0 downto 0);
2071
      to_register23_ce: out std_logic;
2072
      to_register23_clk: out std_logic;
2073
      to_register23_clr: out std_logic;
2074
      to_register23_data_in: out std_logic_vector(0 downto 0);
2075
      to_register23_en: out std_logic_vector(0 downto 0);
2076
      to_register24_ce: out std_logic;
2077
      to_register24_clk: out std_logic;
2078
      to_register24_clr: out std_logic;
2079
      to_register24_data_in: out std_logic_vector(31 downto 0);
2080
      to_register24_en: out std_logic_vector(0 downto 0);
2081
      to_register25_ce: out std_logic;
2082
      to_register25_clk: out std_logic;
2083
      to_register25_clr: out std_logic;
2084
      to_register25_data_in: out std_logic_vector(0 downto 0);
2085
      to_register25_en: out std_logic_vector(0 downto 0);
2086
      to_register26_ce: out std_logic;
2087
      to_register26_clk: out std_logic;
2088
      to_register26_clr: out std_logic;
2089
      to_register26_data_in: out std_logic_vector(31 downto 0);
2090
      to_register26_en: out std_logic_vector(0 downto 0);
2091
      to_register27_ce: out std_logic;
2092
      to_register27_clk: out std_logic;
2093
      to_register27_clr: out std_logic;
2094
      to_register27_data_in: out std_logic_vector(0 downto 0);
2095
      to_register27_en: out std_logic_vector(0 downto 0);
2096
      to_register28_ce: out std_logic;
2097
      to_register28_clk: out std_logic;
2098
      to_register28_clr: out std_logic;
2099
      to_register28_data_in: out std_logic_vector(31 downto 0);
2100
      to_register28_en: out std_logic_vector(0 downto 0);
2101
      to_register29_ce: out std_logic;
2102
      to_register29_clk: out std_logic;
2103
      to_register29_clr: out std_logic;
2104
      to_register29_data_in: out std_logic_vector(0 downto 0);
2105
      to_register29_en: out std_logic_vector(0 downto 0);
2106
      to_register2_ce: out std_logic;
2107
      to_register2_clk: out std_logic;
2108
      to_register2_clr: out std_logic;
2109
      to_register2_data_in: out std_logic_vector(31 downto 0);
2110
      to_register2_en: out std_logic_vector(0 downto 0);
2111
      to_register30_ce: out std_logic;
2112
      to_register30_clk: out std_logic;
2113
      to_register30_clr: out std_logic;
2114
      to_register30_data_in: out std_logic_vector(31 downto 0);
2115
      to_register30_en: out std_logic_vector(0 downto 0);
2116
      to_register31_ce: out std_logic;
2117
      to_register31_clk: out std_logic;
2118
      to_register31_clr: out std_logic;
2119
      to_register31_data_in: out std_logic_vector(0 downto 0);
2120
      to_register31_en: out std_logic_vector(0 downto 0);
2121
      to_register32_ce: out std_logic;
2122
      to_register32_clk: out std_logic;
2123
      to_register32_clr: out std_logic;
2124
      to_register32_data_in: out std_logic_vector(31 downto 0);
2125
      to_register32_en: out std_logic_vector(0 downto 0);
2126
      to_register33_ce: out std_logic;
2127
      to_register33_clk: out std_logic;
2128
      to_register33_clr: out std_logic;
2129
      to_register33_data_in: out std_logic_vector(0 downto 0);
2130
      to_register33_en: out std_logic_vector(0 downto 0);
2131
      to_register34_ce: out std_logic;
2132
      to_register34_clk: out std_logic;
2133
      to_register34_clr: out std_logic;
2134
      to_register34_data_in: out std_logic_vector(31 downto 0);
2135
      to_register34_en: out std_logic_vector(0 downto 0);
2136
      to_register3_ce: out std_logic;
2137
      to_register3_clk: out std_logic;
2138
      to_register3_clr: out std_logic;
2139
      to_register3_data_in: out std_logic_vector(0 downto 0);
2140
      to_register3_en: out std_logic_vector(0 downto 0);
2141
      to_register4_ce: out std_logic;
2142
      to_register4_clk: out std_logic;
2143
      to_register4_clr: out std_logic;
2144
      to_register4_data_in: out std_logic_vector(0 downto 0);
2145
      to_register4_en: out std_logic_vector(0 downto 0);
2146
      to_register5_ce: out std_logic;
2147
      to_register5_clk: out std_logic;
2148
      to_register5_clr: out std_logic;
2149
      to_register5_data_in: out std_logic_vector(31 downto 0);
2150
      to_register5_en: out std_logic_vector(0 downto 0);
2151
      to_register6_ce: out std_logic;
2152
      to_register6_clk: out std_logic;
2153
      to_register6_clr: out std_logic;
2154
      to_register6_data_in: out std_logic_vector(31 downto 0);
2155
      to_register6_en: out std_logic_vector(0 downto 0);
2156
      to_register7_ce: out std_logic;
2157
      to_register7_clk: out std_logic;
2158
      to_register7_clr: out std_logic;
2159
      to_register7_data_in: out std_logic_vector(31 downto 0);
2160
      to_register7_en: out std_logic_vector(0 downto 0);
2161
      to_register8_ce: out std_logic;
2162
      to_register8_clk: out std_logic;
2163
      to_register8_clr: out std_logic;
2164
      to_register8_data_in: out std_logic_vector(0 downto 0);
2165
      to_register8_en: out std_logic_vector(0 downto 0);
2166
      to_register9_ce: out std_logic;
2167
      to_register9_clk: out std_logic;
2168
      to_register9_clr: out std_logic;
2169
      to_register9_data_in: out std_logic_vector(31 downto 0);
2170
      to_register9_en: out std_logic_vector(0 downto 0)
2171
    );
2172
  end component;
2173
  attribute syn_black_box: boolean;
2174
  attribute syn_black_box of inout_logic_cw: component is true;
2175
  attribute box_type: string;
2176
  attribute box_type of inout_logic_cw: component is "black_box";
2177
  attribute syn_noprune: boolean;
2178
  attribute optimize_primitives: boolean;
2179
  attribute dont_touch: boolean;
2180
  attribute syn_noprune of inout_logic_cw: component is true;
2181
  attribute optimize_primitives of inout_logic_cw: component is false;
2182
  attribute dont_touch of inout_logic_cw: component is true;
2183
 
2184
  component user_logic_cw
2185
    port (
2186
      bram_rd_dout: in std_logic_vector(63 downto 0);
2187
      ce: in std_logic := '1';
2188
      clk: in std_logic;
2189
      fifo_rd_count: in std_logic_vector(14 downto 0);
2190
      fifo_rd_dout: in std_logic_vector(71 downto 0);
2191
      fifo_rd_empty: in std_logic;
2192
      fifo_rd_pempty: in std_logic;
2193
      fifo_rd_valid: in std_logic;
2194
      fifo_wr_count: in std_logic_vector(14 downto 0);
2195
      fifo_wr_full: in std_logic;
2196
      fifo_wr_pfull: in std_logic;
2197
      from_register10_data_out: in std_logic_vector(0 downto 0);
2198
      from_register11_data_out: in std_logic_vector(31 downto 0);
2199
      from_register12_data_out: in std_logic_vector(0 downto 0);
2200
      from_register13_data_out: in std_logic_vector(31 downto 0);
2201
      from_register14_data_out: in std_logic_vector(0 downto 0);
2202
      from_register15_data_out: in std_logic_vector(0 downto 0);
2203
      from_register16_data_out: in std_logic_vector(0 downto 0);
2204
      from_register17_data_out: in std_logic_vector(31 downto 0);
2205
      from_register18_data_out: in std_logic_vector(0 downto 0);
2206
      from_register19_data_out: in std_logic_vector(31 downto 0);
2207
      from_register1_data_out: in std_logic_vector(31 downto 0);
2208
      from_register20_data_out: in std_logic_vector(31 downto 0);
2209
      from_register21_data_out: in std_logic_vector(0 downto 0);
2210
      from_register22_data_out: in std_logic_vector(31 downto 0);
2211
      from_register23_data_out: in std_logic_vector(0 downto 0);
2212
      from_register24_data_out: in std_logic_vector(31 downto 0);
2213
      from_register25_data_out: in std_logic_vector(0 downto 0);
2214
      from_register26_data_out: in std_logic_vector(31 downto 0);
2215
      from_register27_data_out: in std_logic_vector(0 downto 0);
2216
      from_register28_data_out: in std_logic_vector(31 downto 0);
2217
      from_register29_data_out: in std_logic_vector(0 downto 0);
2218
      from_register2_data_out: in std_logic_vector(31 downto 0);
2219
      from_register30_data_out: in std_logic_vector(31 downto 0);
2220
      from_register31_data_out: in std_logic_vector(0 downto 0);
2221
      from_register32_data_out: in std_logic_vector(31 downto 0);
2222
      from_register33_data_out: in std_logic_vector(0 downto 0);
2223
      from_register3_data_out: in std_logic_vector(31 downto 0);
2224
      from_register4_data_out: in std_logic_vector(0 downto 0);
2225
      from_register5_data_out: in std_logic_vector(31 downto 0);
2226
      from_register6_data_out: in std_logic_vector(0 downto 0);
2227
      from_register7_data_out: in std_logic_vector(31 downto 0);
2228
      from_register8_data_out: in std_logic_vector(0 downto 0);
2229
      from_register9_data_out: in std_logic_vector(31 downto 0);
2230
      from_register_data_out: in std_logic_vector(31 downto 0);
2231
      rst_i: in std_logic;
2232
      to_register10_dout: in std_logic_vector(0 downto 0);
2233
      to_register11_dout: in std_logic_vector(0 downto 0);
2234
      to_register12_dout: in std_logic_vector(0 downto 0);
2235
      to_register13_dout: in std_logic_vector(31 downto 0);
2236
      to_register14_dout: in std_logic_vector(0 downto 0);
2237
      to_register15_dout: in std_logic_vector(31 downto 0);
2238
      to_register16_dout: in std_logic_vector(0 downto 0);
2239
      to_register17_dout: in std_logic_vector(31 downto 0);
2240
      to_register18_dout: in std_logic_vector(0 downto 0);
2241
      to_register19_dout: in std_logic_vector(31 downto 0);
2242
      to_register1_dout: in std_logic_vector(0 downto 0);
2243
      to_register20_dout: in std_logic_vector(0 downto 0);
2244
      to_register21_dout: in std_logic_vector(31 downto 0);
2245
      to_register22_dout: in std_logic_vector(0 downto 0);
2246
      to_register23_dout: in std_logic_vector(31 downto 0);
2247
      to_register24_dout: in std_logic_vector(0 downto 0);
2248
      to_register25_dout: in std_logic_vector(31 downto 0);
2249
      to_register26_dout: in std_logic_vector(0 downto 0);
2250
      to_register27_dout: in std_logic_vector(31 downto 0);
2251
      to_register2_dout: in std_logic_vector(31 downto 0);
2252
      to_register3_dout: in std_logic_vector(31 downto 0);
2253
      to_register4_dout: in std_logic_vector(0 downto 0);
2254
      to_register5_dout: in std_logic_vector(0 downto 0);
2255
      to_register6_dout: in std_logic_vector(31 downto 0);
2256
      to_register7_dout: in std_logic_vector(0 downto 0);
2257
      to_register8_dout: in std_logic_vector(31 downto 0);
2258
      to_register9_dout: in std_logic_vector(31 downto 0);
2259
      to_register_dout: in std_logic_vector(31 downto 0);
2260
      bram_rd_addr: out std_logic_vector(11 downto 0);
2261
      bram_wr_addr: out std_logic_vector(11 downto 0);
2262
      bram_wr_din: out std_logic_vector(63 downto 0);
2263
      bram_wr_en: out std_logic_vector(7 downto 0);
2264
      fifo_rd_en: out std_logic;
2265
      fifo_wr_din: out std_logic_vector(71 downto 0);
2266
      fifo_wr_en: out std_logic;
2267
      rst_o: out std_logic;
2268
      to_register10_ce: out std_logic;
2269
      to_register10_clk: out std_logic;
2270
      to_register10_clr: out std_logic;
2271
      to_register10_data_in: out std_logic_vector(0 downto 0);
2272
      to_register10_en: out std_logic_vector(0 downto 0);
2273
      to_register11_ce: out std_logic;
2274
      to_register11_clk: out std_logic;
2275
      to_register11_clr: out std_logic;
2276
      to_register11_data_in: out std_logic_vector(0 downto 0);
2277
      to_register11_en: out std_logic_vector(0 downto 0);
2278
      to_register12_ce: out std_logic;
2279
      to_register12_clk: out std_logic;
2280
      to_register12_clr: out std_logic;
2281
      to_register12_data_in: out std_logic_vector(0 downto 0);
2282
      to_register12_en: out std_logic_vector(0 downto 0);
2283
      to_register13_ce: out std_logic;
2284
      to_register13_clk: out std_logic;
2285
      to_register13_clr: out std_logic;
2286
      to_register13_data_in: out std_logic_vector(31 downto 0);
2287
      to_register13_en: out std_logic_vector(0 downto 0);
2288
      to_register14_ce: out std_logic;
2289
      to_register14_clk: out std_logic;
2290
      to_register14_clr: out std_logic;
2291
      to_register14_data_in: out std_logic_vector(0 downto 0);
2292
      to_register14_en: out std_logic_vector(0 downto 0);
2293
      to_register15_ce: out std_logic;
2294
      to_register15_clk: out std_logic;
2295
      to_register15_clr: out std_logic;
2296
      to_register15_data_in: out std_logic_vector(31 downto 0);
2297
      to_register15_en: out std_logic_vector(0 downto 0);
2298
      to_register16_ce: out std_logic;
2299
      to_register16_clk: out std_logic;
2300
      to_register16_clr: out std_logic;
2301
      to_register16_data_in: out std_logic_vector(0 downto 0);
2302
      to_register16_en: out std_logic_vector(0 downto 0);
2303
      to_register17_ce: out std_logic;
2304
      to_register17_clk: out std_logic;
2305
      to_register17_clr: out std_logic;
2306
      to_register17_data_in: out std_logic_vector(31 downto 0);
2307
      to_register17_en: out std_logic_vector(0 downto 0);
2308
      to_register18_ce: out std_logic;
2309
      to_register18_clk: out std_logic;
2310
      to_register18_clr: out std_logic;
2311
      to_register18_data_in: out std_logic_vector(0 downto 0);
2312
      to_register18_en: out std_logic_vector(0 downto 0);
2313
      to_register19_ce: out std_logic;
2314
      to_register19_clk: out std_logic;
2315
      to_register19_clr: out std_logic;
2316
      to_register19_data_in: out std_logic_vector(31 downto 0);
2317
      to_register19_en: out std_logic_vector(0 downto 0);
2318
      to_register1_ce: out std_logic;
2319
      to_register1_clk: out std_logic;
2320
      to_register1_clr: out std_logic;
2321
      to_register1_data_in: out std_logic_vector(0 downto 0);
2322
      to_register1_en: out std_logic_vector(0 downto 0);
2323
      to_register20_ce: out std_logic;
2324
      to_register20_clk: out std_logic;
2325
      to_register20_clr: out std_logic;
2326
      to_register20_data_in: out std_logic_vector(0 downto 0);
2327
      to_register20_en: out std_logic_vector(0 downto 0);
2328
      to_register21_ce: out std_logic;
2329
      to_register21_clk: out std_logic;
2330
      to_register21_clr: out std_logic;
2331
      to_register21_data_in: out std_logic_vector(31 downto 0);
2332
      to_register21_en: out std_logic_vector(0 downto 0);
2333
      to_register22_ce: out std_logic;
2334
      to_register22_clk: out std_logic;
2335
      to_register22_clr: out std_logic;
2336
      to_register22_data_in: out std_logic_vector(0 downto 0);
2337
      to_register22_en: out std_logic_vector(0 downto 0);
2338
      to_register23_ce: out std_logic;
2339
      to_register23_clk: out std_logic;
2340
      to_register23_clr: out std_logic;
2341
      to_register23_data_in: out std_logic_vector(31 downto 0);
2342
      to_register23_en: out std_logic_vector(0 downto 0);
2343
      to_register24_ce: out std_logic;
2344
      to_register24_clk: out std_logic;
2345
      to_register24_clr: out std_logic;
2346
      to_register24_data_in: out std_logic_vector(0 downto 0);
2347
      to_register24_en: out std_logic_vector(0 downto 0);
2348
      to_register25_ce: out std_logic;
2349
      to_register25_clk: out std_logic;
2350
      to_register25_clr: out std_logic;
2351
      to_register25_data_in: out std_logic_vector(31 downto 0);
2352
      to_register25_en: out std_logic_vector(0 downto 0);
2353
      to_register26_ce: out std_logic;
2354
      to_register26_clk: out std_logic;
2355
      to_register26_clr: out std_logic;
2356
      to_register26_data_in: out std_logic_vector(0 downto 0);
2357
      to_register26_en: out std_logic_vector(0 downto 0);
2358
      to_register27_ce: out std_logic;
2359
      to_register27_clk: out std_logic;
2360
      to_register27_clr: out std_logic;
2361
      to_register27_data_in: out std_logic_vector(31 downto 0);
2362
      to_register27_en: out std_logic_vector(0 downto 0);
2363
      to_register2_ce: out std_logic;
2364
      to_register2_clk: out std_logic;
2365
      to_register2_clr: out std_logic;
2366
      to_register2_data_in: out std_logic_vector(31 downto 0);
2367
      to_register2_en: out std_logic_vector(0 downto 0);
2368
      to_register3_ce: out std_logic;
2369
      to_register3_clk: out std_logic;
2370
      to_register3_clr: out std_logic;
2371
      to_register3_data_in: out std_logic_vector(31 downto 0);
2372
      to_register3_en: out std_logic_vector(0 downto 0);
2373
      to_register4_ce: out std_logic;
2374
      to_register4_clk: out std_logic;
2375
      to_register4_clr: out std_logic;
2376
      to_register4_data_in: out std_logic_vector(0 downto 0);
2377
      to_register4_en: out std_logic_vector(0 downto 0);
2378
      to_register5_ce: out std_logic;
2379
      to_register5_clk: out std_logic;
2380
      to_register5_clr: out std_logic;
2381
      to_register5_data_in: out std_logic_vector(0 downto 0);
2382
      to_register5_en: out std_logic_vector(0 downto 0);
2383
      to_register6_ce: out std_logic;
2384
      to_register6_clk: out std_logic;
2385
      to_register6_clr: out std_logic;
2386
      to_register6_data_in: out std_logic_vector(31 downto 0);
2387
      to_register6_en: out std_logic_vector(0 downto 0);
2388
      to_register7_ce: out std_logic;
2389
      to_register7_clk: out std_logic;
2390
      to_register7_clr: out std_logic;
2391
      to_register7_data_in: out std_logic_vector(0 downto 0);
2392
      to_register7_en: out std_logic_vector(0 downto 0);
2393
      to_register8_ce: out std_logic;
2394
      to_register8_clk: out std_logic;
2395
      to_register8_clr: out std_logic;
2396
      to_register8_data_in: out std_logic_vector(31 downto 0);
2397
      to_register8_en: out std_logic_vector(0 downto 0);
2398
      to_register9_ce: out std_logic;
2399
      to_register9_clk: out std_logic;
2400
      to_register9_clr: out std_logic;
2401
      to_register9_data_in: out std_logic_vector(31 downto 0);
2402
      to_register9_en: out std_logic_vector(0 downto 0);
2403
      to_register_ce: out std_logic;
2404
      to_register_clk: out std_logic;
2405
      to_register_clr: out std_logic;
2406
      to_register_data_in: out std_logic_vector(31 downto 0);
2407
      to_register_en: out std_logic_vector(0 downto 0);
2408
      user_int_1o: out std_logic;
2409
      user_int_2o: out std_logic;
2410
      user_int_3o: out std_logic
2411
    );
2412
  end component;
2413
  attribute syn_black_box of user_logic_cw: component is true;
2414
  attribute box_type of user_logic_cw: component is "black_box";
2415
  attribute syn_noprune of user_logic_cw: component is true;
2416
  attribute optimize_primitives of user_logic_cw: component is false;
2417
  attribute dont_touch of user_logic_cw: component is true;
2418
 
2419
  signal DMA_Host2Board_Busy_reg_ce: std_logic;
2420
  signal DMA_Host2Board_Done_reg_ce: std_logic;
2421
  signal clk: std_logic;
2422
  signal clk_x0: std_logic;
2423
  signal debug1i_reg_ce: std_logic;
2424
  signal debug2i_reg_ce: std_logic;
2425
  signal debug3i_reg_ce: std_logic;
2426
  signal debug4i_reg_ce: std_logic;
2427
  signal from_register10_data_out: std_logic_vector(31 downto 0);
2428
  signal from_register10_data_out_x0: std_logic;
2429
  signal from_register11_data_out: std_logic_vector(31 downto 0);
2430
  signal from_register11_data_out_x0: std_logic_vector(31 downto 0);
2431
  signal from_register12_data_out: std_logic;
2432
  signal from_register12_data_out_x0: std_logic;
2433
  signal from_register13_data_out: std_logic_vector(31 downto 0);
2434
  signal from_register13_data_out_x0: std_logic_vector(31 downto 0);
2435
  signal from_register14_data_out: std_logic;
2436
  signal from_register14_data_out_x0: std_logic;
2437
  signal from_register15_data_out: std_logic_vector(31 downto 0);
2438
  signal from_register15_data_out_x0: std_logic;
2439
  signal from_register16_data_out: std_logic;
2440
  signal from_register16_data_out_x0: std_logic;
2441
  signal from_register17_data_out: std_logic_vector(31 downto 0);
2442
  signal from_register17_data_out_x0: std_logic_vector(31 downto 0);
2443
  signal from_register18_data_out: std_logic;
2444
  signal from_register18_data_out_x0: std_logic;
2445
  signal from_register19_data_out: std_logic_vector(31 downto 0);
2446
  signal from_register19_data_out_x0: std_logic_vector(31 downto 0);
2447
  signal from_register1_data_out: std_logic;
2448
  signal from_register1_data_out_x0: std_logic_vector(31 downto 0);
2449
  signal from_register20_data_out: std_logic;
2450
  signal from_register20_data_out_x0: std_logic_vector(31 downto 0);
2451
  signal from_register21_data_out: std_logic_vector(31 downto 0);
2452
  signal from_register21_data_out_x0: std_logic;
2453
  signal from_register22_data_out: std_logic;
2454
  signal from_register22_data_out_x0: std_logic_vector(31 downto 0);
2455
  signal from_register23_data_out: std_logic_vector(31 downto 0);
2456
  signal from_register23_data_out_x0: std_logic;
2457
  signal from_register24_data_out: std_logic;
2458
  signal from_register24_data_out_x0: std_logic_vector(31 downto 0);
2459
  signal from_register25_data_out: std_logic_vector(31 downto 0);
2460
  signal from_register25_data_out_x0: std_logic;
2461
  signal from_register26_data_out: std_logic;
2462
  signal from_register26_data_out_x0: std_logic_vector(31 downto 0);
2463
  signal from_register27_data_out: std_logic_vector(31 downto 0);
2464
  signal from_register27_data_out_x0: std_logic;
2465
  signal from_register28_data_out: std_logic;
2466
  signal from_register28_data_out_x0: std_logic_vector(31 downto 0);
2467
  signal from_register29_data_out: std_logic;
2468
  signal from_register2_data_out: std_logic;
2469
  signal from_register2_data_out_x0: std_logic_vector(31 downto 0);
2470
  signal from_register30_data_out: std_logic_vector(31 downto 0);
2471
  signal from_register31_data_out: std_logic;
2472
  signal from_register32_data_out: std_logic_vector(31 downto 0);
2473
  signal from_register33_data_out: std_logic;
2474
  signal from_register3_data_out: std_logic_vector(31 downto 0);
2475
  signal from_register3_data_out_x0: std_logic_vector(31 downto 0);
2476
  signal from_register4_data_out: std_logic;
2477
  signal from_register4_data_out_x0: std_logic;
2478
  signal from_register5_data_out: std_logic_vector(31 downto 0);
2479
  signal from_register5_data_out_x0: std_logic_vector(31 downto 0);
2480
  signal from_register6_data_out: std_logic;
2481
  signal from_register6_data_out_x0: std_logic;
2482
  signal from_register7_data_out: std_logic_vector(31 downto 0);
2483
  signal from_register7_data_out_x0: std_logic_vector(31 downto 0);
2484
  signal from_register8_data_out: std_logic_vector(31 downto 0);
2485
  signal from_register8_data_out_x0: std_logic;
2486
  signal from_register9_data_out: std_logic;
2487
  signal from_register9_data_out_x0: std_logic_vector(31 downto 0);
2488
  signal from_register_data_out: std_logic_vector(31 downto 0);
2489
  signal register01rd_reg_ce: std_logic;
2490
  signal register01rv_reg_ce: std_logic;
2491
  signal register01td_reg_ce: std_logic;
2492
  signal register01tv_reg_ce: std_logic;
2493
  signal register02rd_reg_ce: std_logic;
2494
  signal register02rv_reg_ce: std_logic;
2495
  signal register02td_reg_ce: std_logic;
2496
  signal register02tv_reg_ce: std_logic;
2497
  signal register03rd_reg_ce: std_logic;
2498
  signal register03rv_reg_ce: std_logic;
2499
  signal register03td_reg_ce: std_logic;
2500
  signal register03tv_reg_ce: std_logic;
2501
  signal register04rd_reg_ce: std_logic;
2502
  signal register04rv_reg_ce: std_logic;
2503
  signal register04td_reg_ce: std_logic;
2504
  signal register04tv_reg_ce: std_logic;
2505
  signal register05rd_reg_ce: std_logic;
2506
  signal register05rv_reg_ce: std_logic;
2507
  signal register05td_reg_ce: std_logic;
2508
  signal register05tv_reg_ce: std_logic;
2509
  signal register06rd_reg_ce: std_logic;
2510
  signal register06rv_reg_ce: std_logic;
2511
  signal register06td_reg_ce: std_logic;
2512
  signal register06tv_reg_ce: std_logic;
2513
  signal register07rd_reg_ce: std_logic;
2514
  signal register07rv_reg_ce: std_logic;
2515
  signal register07td_reg_ce: std_logic;
2516
  signal register07tv_reg_ce: std_logic;
2517
  signal register08rd_reg_ce: std_logic;
2518
  signal register08rv_reg_ce: std_logic;
2519
  signal register08td_reg_ce: std_logic;
2520
  signal register08tv_reg_ce: std_logic;
2521
  signal register09rd_reg_ce: std_logic;
2522
  signal register09rv_reg_ce: std_logic;
2523
  signal register09td_reg_ce: std_logic;
2524
  signal register09tv_reg_ce: std_logic;
2525
  signal register10rd_reg_ce: std_logic;
2526
  signal register10rv_reg_ce: std_logic;
2527
  signal register10td_reg_ce: std_logic;
2528
  signal register10tv_reg_ce: std_logic;
2529
  signal register11rd_reg_ce: std_logic;
2530
  signal register11rv_reg_ce: std_logic;
2531
  signal register11td_reg_ce: std_logic;
2532
  signal register11tv_reg_ce: std_logic;
2533
  signal register12rd_reg_ce: std_logic;
2534
  signal register12rv_reg_ce: std_logic;
2535
  signal register12td_reg_ce: std_logic;
2536
  signal register12tv_reg_ce: std_logic;
2537
  signal register13rd_reg_ce: std_logic;
2538
  signal register13rv_reg_ce: std_logic;
2539
  signal register13td_reg_ce: std_logic;
2540
  signal register13tv_reg_ce: std_logic;
2541
  signal register14rd_reg_ce: std_logic;
2542
  signal register14rv_reg_ce: std_logic;
2543
  signal register14td_reg_ce: std_logic;
2544
  signal register14tv_reg_ce: std_logic;
2545
  signal sysgen_dut_to_register10_ce: std_logic;
2546
  signal sysgen_dut_to_register10_ce_x0: std_logic;
2547
  signal sysgen_dut_to_register10_clk: std_logic;
2548
  signal sysgen_dut_to_register10_clk_x0: std_logic;
2549
  signal sysgen_dut_to_register10_clr: std_logic;
2550
  signal sysgen_dut_to_register10_clr_x0: std_logic;
2551
  signal sysgen_dut_to_register10_data_in: std_logic;
2552
  signal sysgen_dut_to_register10_data_in_x0: std_logic;
2553
  signal sysgen_dut_to_register10_en: std_logic;
2554
  signal sysgen_dut_to_register10_en_x0: std_logic;
2555
  signal sysgen_dut_to_register11_ce: std_logic;
2556
  signal sysgen_dut_to_register11_ce_x0: std_logic;
2557
  signal sysgen_dut_to_register11_clk: std_logic;
2558
  signal sysgen_dut_to_register11_clk_x0: std_logic;
2559
  signal sysgen_dut_to_register11_clr: std_logic;
2560
  signal sysgen_dut_to_register11_clr_x0: std_logic;
2561
  signal sysgen_dut_to_register11_data_in: std_logic_vector(31 downto 0);
2562
  signal sysgen_dut_to_register11_data_in_x0: std_logic;
2563
  signal sysgen_dut_to_register11_en: std_logic;
2564
  signal sysgen_dut_to_register11_en_x0: std_logic;
2565
  signal sysgen_dut_to_register12_ce: std_logic;
2566
  signal sysgen_dut_to_register12_ce_x0: std_logic;
2567
  signal sysgen_dut_to_register12_clk: std_logic;
2568
  signal sysgen_dut_to_register12_clk_x0: std_logic;
2569
  signal sysgen_dut_to_register12_clr: std_logic;
2570
  signal sysgen_dut_to_register12_clr_x0: std_logic;
2571
  signal sysgen_dut_to_register12_data_in: std_logic;
2572
  signal sysgen_dut_to_register12_data_in_x0: std_logic;
2573
  signal sysgen_dut_to_register12_en: std_logic;
2574
  signal sysgen_dut_to_register12_en_x0: std_logic;
2575
  signal sysgen_dut_to_register13_ce: std_logic;
2576
  signal sysgen_dut_to_register13_ce_x0: std_logic;
2577
  signal sysgen_dut_to_register13_clk: std_logic;
2578
  signal sysgen_dut_to_register13_clk_x0: std_logic;
2579
  signal sysgen_dut_to_register13_clr: std_logic;
2580
  signal sysgen_dut_to_register13_clr_x0: std_logic;
2581
  signal sysgen_dut_to_register13_data_in: std_logic_vector(31 downto 0);
2582
  signal sysgen_dut_to_register13_data_in_x0: std_logic_vector(31 downto 0);
2583
  signal sysgen_dut_to_register13_en: std_logic;
2584
  signal sysgen_dut_to_register13_en_x0: std_logic;
2585
  signal sysgen_dut_to_register14_ce: std_logic;
2586
  signal sysgen_dut_to_register14_ce_x0: std_logic;
2587
  signal sysgen_dut_to_register14_clk: std_logic;
2588
  signal sysgen_dut_to_register14_clk_x0: std_logic;
2589
  signal sysgen_dut_to_register14_clr: std_logic;
2590
  signal sysgen_dut_to_register14_clr_x0: std_logic;
2591
  signal sysgen_dut_to_register14_data_in: std_logic;
2592
  signal sysgen_dut_to_register14_data_in_x0: std_logic;
2593
  signal sysgen_dut_to_register14_en: std_logic;
2594
  signal sysgen_dut_to_register14_en_x0: std_logic;
2595
  signal sysgen_dut_to_register15_ce: std_logic;
2596
  signal sysgen_dut_to_register15_ce_x0: std_logic;
2597
  signal sysgen_dut_to_register15_clk: std_logic;
2598
  signal sysgen_dut_to_register15_clk_x0: std_logic;
2599
  signal sysgen_dut_to_register15_clr: std_logic;
2600
  signal sysgen_dut_to_register15_clr_x0: std_logic;
2601
  signal sysgen_dut_to_register15_data_in: std_logic_vector(31 downto 0);
2602
  signal sysgen_dut_to_register15_data_in_x0: std_logic_vector(31 downto 0);
2603
  signal sysgen_dut_to_register15_en: std_logic;
2604
  signal sysgen_dut_to_register15_en_x0: std_logic;
2605
  signal sysgen_dut_to_register16_ce: std_logic;
2606
  signal sysgen_dut_to_register16_ce_x0: std_logic;
2607
  signal sysgen_dut_to_register16_clk: std_logic;
2608
  signal sysgen_dut_to_register16_clk_x0: std_logic;
2609
  signal sysgen_dut_to_register16_clr: std_logic;
2610
  signal sysgen_dut_to_register16_clr_x0: std_logic;
2611
  signal sysgen_dut_to_register16_data_in: std_logic;
2612
  signal sysgen_dut_to_register16_data_in_x0: std_logic;
2613
  signal sysgen_dut_to_register16_en: std_logic;
2614
  signal sysgen_dut_to_register16_en_x0: std_logic;
2615
  signal sysgen_dut_to_register17_ce: std_logic;
2616
  signal sysgen_dut_to_register17_ce_x0: std_logic;
2617
  signal sysgen_dut_to_register17_clk: std_logic;
2618
  signal sysgen_dut_to_register17_clk_x0: std_logic;
2619
  signal sysgen_dut_to_register17_clr: std_logic;
2620
  signal sysgen_dut_to_register17_clr_x0: std_logic;
2621
  signal sysgen_dut_to_register17_data_in: std_logic_vector(31 downto 0);
2622
  signal sysgen_dut_to_register17_data_in_x0: std_logic_vector(31 downto 0);
2623
  signal sysgen_dut_to_register17_en: std_logic;
2624
  signal sysgen_dut_to_register17_en_x0: std_logic;
2625
  signal sysgen_dut_to_register18_ce: std_logic;
2626
  signal sysgen_dut_to_register18_ce_x0: std_logic;
2627
  signal sysgen_dut_to_register18_clk: std_logic;
2628
  signal sysgen_dut_to_register18_clk_x0: std_logic;
2629
  signal sysgen_dut_to_register18_clr: std_logic;
2630
  signal sysgen_dut_to_register18_clr_x0: std_logic;
2631
  signal sysgen_dut_to_register18_data_in: std_logic;
2632
  signal sysgen_dut_to_register18_data_in_x0: std_logic;
2633
  signal sysgen_dut_to_register18_en: std_logic;
2634
  signal sysgen_dut_to_register18_en_x0: std_logic;
2635
  signal sysgen_dut_to_register19_ce: std_logic;
2636
  signal sysgen_dut_to_register19_ce_x0: std_logic;
2637
  signal sysgen_dut_to_register19_clk: std_logic;
2638
  signal sysgen_dut_to_register19_clk_x0: std_logic;
2639
  signal sysgen_dut_to_register19_clr: std_logic;
2640
  signal sysgen_dut_to_register19_clr_x0: std_logic;
2641
  signal sysgen_dut_to_register19_data_in: std_logic;
2642
  signal sysgen_dut_to_register19_data_in_x0: std_logic_vector(31 downto 0);
2643
  signal sysgen_dut_to_register19_en: std_logic;
2644
  signal sysgen_dut_to_register19_en_x0: std_logic;
2645
  signal sysgen_dut_to_register1_ce: std_logic;
2646
  signal sysgen_dut_to_register1_ce_x0: std_logic;
2647
  signal sysgen_dut_to_register1_clk: std_logic;
2648
  signal sysgen_dut_to_register1_clk_x0: std_logic;
2649
  signal sysgen_dut_to_register1_clr: std_logic;
2650
  signal sysgen_dut_to_register1_clr_x0: std_logic;
2651
  signal sysgen_dut_to_register1_data_in: std_logic_vector(31 downto 0);
2652
  signal sysgen_dut_to_register1_data_in_x0: std_logic;
2653
  signal sysgen_dut_to_register1_en: std_logic;
2654
  signal sysgen_dut_to_register1_en_x0: std_logic;
2655
  signal sysgen_dut_to_register20_ce: std_logic;
2656
  signal sysgen_dut_to_register20_ce_x0: std_logic;
2657
  signal sysgen_dut_to_register20_clk: std_logic;
2658
  signal sysgen_dut_to_register20_clk_x0: std_logic;
2659
  signal sysgen_dut_to_register20_clr: std_logic;
2660
  signal sysgen_dut_to_register20_clr_x0: std_logic;
2661
  signal sysgen_dut_to_register20_data_in: std_logic_vector(31 downto 0);
2662
  signal sysgen_dut_to_register20_data_in_x0: std_logic;
2663
  signal sysgen_dut_to_register20_en: std_logic;
2664
  signal sysgen_dut_to_register20_en_x0: std_logic;
2665
  signal sysgen_dut_to_register21_ce: std_logic;
2666
  signal sysgen_dut_to_register21_ce_x0: std_logic;
2667
  signal sysgen_dut_to_register21_clk: std_logic;
2668
  signal sysgen_dut_to_register21_clk_x0: std_logic;
2669
  signal sysgen_dut_to_register21_clr: std_logic;
2670
  signal sysgen_dut_to_register21_clr_x0: std_logic;
2671
  signal sysgen_dut_to_register21_data_in: std_logic;
2672
  signal sysgen_dut_to_register21_data_in_x0: std_logic_vector(31 downto 0);
2673
  signal sysgen_dut_to_register21_en: std_logic;
2674
  signal sysgen_dut_to_register21_en_x0: std_logic;
2675
  signal sysgen_dut_to_register22_ce: std_logic;
2676
  signal sysgen_dut_to_register22_ce_x0: std_logic;
2677
  signal sysgen_dut_to_register22_clk: std_logic;
2678
  signal sysgen_dut_to_register22_clk_x0: std_logic;
2679
  signal sysgen_dut_to_register22_clr: std_logic;
2680
  signal sysgen_dut_to_register22_clr_x0: std_logic;
2681
  signal sysgen_dut_to_register22_data_in: std_logic_vector(31 downto 0);
2682
  signal sysgen_dut_to_register22_data_in_x0: std_logic;
2683
  signal sysgen_dut_to_register22_en: std_logic;
2684
  signal sysgen_dut_to_register22_en_x0: std_logic;
2685
  signal sysgen_dut_to_register23_ce: std_logic;
2686
  signal sysgen_dut_to_register23_ce_x0: std_logic;
2687
  signal sysgen_dut_to_register23_clk: std_logic;
2688
  signal sysgen_dut_to_register23_clk_x0: std_logic;
2689
  signal sysgen_dut_to_register23_clr: std_logic;
2690
  signal sysgen_dut_to_register23_clr_x0: std_logic;
2691
  signal sysgen_dut_to_register23_data_in: std_logic;
2692
  signal sysgen_dut_to_register23_data_in_x0: std_logic_vector(31 downto 0);
2693
  signal sysgen_dut_to_register23_en: std_logic;
2694
  signal sysgen_dut_to_register23_en_x0: std_logic;
2695
  signal sysgen_dut_to_register24_ce: std_logic;
2696
  signal sysgen_dut_to_register24_ce_x0: std_logic;
2697
  signal sysgen_dut_to_register24_clk: std_logic;
2698
  signal sysgen_dut_to_register24_clk_x0: std_logic;
2699
  signal sysgen_dut_to_register24_clr: std_logic;
2700
  signal sysgen_dut_to_register24_clr_x0: std_logic;
2701
  signal sysgen_dut_to_register24_data_in: std_logic_vector(31 downto 0);
2702
  signal sysgen_dut_to_register24_data_in_x0: std_logic;
2703
  signal sysgen_dut_to_register24_en: std_logic;
2704
  signal sysgen_dut_to_register24_en_x0: std_logic;
2705
  signal sysgen_dut_to_register25_ce: std_logic;
2706
  signal sysgen_dut_to_register25_ce_x0: std_logic;
2707
  signal sysgen_dut_to_register25_clk: std_logic;
2708
  signal sysgen_dut_to_register25_clk_x0: std_logic;
2709
  signal sysgen_dut_to_register25_clr: std_logic;
2710
  signal sysgen_dut_to_register25_clr_x0: std_logic;
2711
  signal sysgen_dut_to_register25_data_in: std_logic;
2712
  signal sysgen_dut_to_register25_data_in_x0: std_logic_vector(31 downto 0);
2713
  signal sysgen_dut_to_register25_en: std_logic;
2714
  signal sysgen_dut_to_register25_en_x0: std_logic;
2715
  signal sysgen_dut_to_register26_ce: std_logic;
2716
  signal sysgen_dut_to_register26_ce_x0: std_logic;
2717
  signal sysgen_dut_to_register26_clk: std_logic;
2718
  signal sysgen_dut_to_register26_clk_x0: std_logic;
2719
  signal sysgen_dut_to_register26_clr: std_logic;
2720
  signal sysgen_dut_to_register26_clr_x0: std_logic;
2721
  signal sysgen_dut_to_register26_data_in: std_logic_vector(31 downto 0);
2722
  signal sysgen_dut_to_register26_data_in_x0: std_logic;
2723
  signal sysgen_dut_to_register26_en: std_logic;
2724
  signal sysgen_dut_to_register26_en_x0: std_logic;
2725
  signal sysgen_dut_to_register27_ce: std_logic;
2726
  signal sysgen_dut_to_register27_ce_x0: std_logic;
2727
  signal sysgen_dut_to_register27_clk: std_logic;
2728
  signal sysgen_dut_to_register27_clk_x0: std_logic;
2729
  signal sysgen_dut_to_register27_clr: std_logic;
2730
  signal sysgen_dut_to_register27_clr_x0: std_logic;
2731
  signal sysgen_dut_to_register27_data_in: std_logic;
2732
  signal sysgen_dut_to_register27_data_in_x0: std_logic_vector(31 downto 0);
2733
  signal sysgen_dut_to_register27_en: std_logic;
2734
  signal sysgen_dut_to_register27_en_x0: std_logic;
2735
  signal sysgen_dut_to_register28_ce: std_logic;
2736
  signal sysgen_dut_to_register28_clk: std_logic;
2737
  signal sysgen_dut_to_register28_clr: std_logic;
2738
  signal sysgen_dut_to_register28_data_in: std_logic_vector(31 downto 0);
2739
  signal sysgen_dut_to_register28_en: std_logic;
2740
  signal sysgen_dut_to_register29_ce: std_logic;
2741
  signal sysgen_dut_to_register29_clk: std_logic;
2742
  signal sysgen_dut_to_register29_clr: std_logic;
2743
  signal sysgen_dut_to_register29_data_in: std_logic;
2744
  signal sysgen_dut_to_register29_en: std_logic;
2745
  signal sysgen_dut_to_register2_ce: std_logic;
2746
  signal sysgen_dut_to_register2_ce_x0: std_logic;
2747
  signal sysgen_dut_to_register2_clk: std_logic;
2748
  signal sysgen_dut_to_register2_clk_x0: std_logic;
2749
  signal sysgen_dut_to_register2_clr: std_logic;
2750
  signal sysgen_dut_to_register2_clr_x0: std_logic;
2751
  signal sysgen_dut_to_register2_data_in: std_logic_vector(31 downto 0);
2752
  signal sysgen_dut_to_register2_data_in_x0: std_logic_vector(31 downto 0);
2753
  signal sysgen_dut_to_register2_en: std_logic;
2754
  signal sysgen_dut_to_register2_en_x0: std_logic;
2755
  signal sysgen_dut_to_register30_ce: std_logic;
2756
  signal sysgen_dut_to_register30_clk: std_logic;
2757
  signal sysgen_dut_to_register30_clr: std_logic;
2758
  signal sysgen_dut_to_register30_data_in: std_logic_vector(31 downto 0);
2759
  signal sysgen_dut_to_register30_en: std_logic;
2760
  signal sysgen_dut_to_register31_ce: std_logic;
2761
  signal sysgen_dut_to_register31_clk: std_logic;
2762
  signal sysgen_dut_to_register31_clr: std_logic;
2763
  signal sysgen_dut_to_register31_data_in: std_logic;
2764
  signal sysgen_dut_to_register31_en: std_logic;
2765
  signal sysgen_dut_to_register32_ce: std_logic;
2766
  signal sysgen_dut_to_register32_clk: std_logic;
2767
  signal sysgen_dut_to_register32_clr: std_logic;
2768
  signal sysgen_dut_to_register32_data_in: std_logic_vector(31 downto 0);
2769
  signal sysgen_dut_to_register32_en: std_logic;
2770
  signal sysgen_dut_to_register33_ce: std_logic;
2771
  signal sysgen_dut_to_register33_clk: std_logic;
2772
  signal sysgen_dut_to_register33_clr: std_logic;
2773
  signal sysgen_dut_to_register33_data_in: std_logic;
2774
  signal sysgen_dut_to_register33_en: std_logic;
2775
  signal sysgen_dut_to_register34_ce: std_logic;
2776
  signal sysgen_dut_to_register34_clk: std_logic;
2777
  signal sysgen_dut_to_register34_clr: std_logic;
2778
  signal sysgen_dut_to_register34_data_in: std_logic_vector(31 downto 0);
2779
  signal sysgen_dut_to_register34_en: std_logic;
2780
  signal sysgen_dut_to_register3_ce: std_logic;
2781
  signal sysgen_dut_to_register3_ce_x0: std_logic;
2782
  signal sysgen_dut_to_register3_clk: std_logic;
2783
  signal sysgen_dut_to_register3_clk_x0: std_logic;
2784
  signal sysgen_dut_to_register3_clr: std_logic;
2785
  signal sysgen_dut_to_register3_clr_x0: std_logic;
2786
  signal sysgen_dut_to_register3_data_in: std_logic;
2787
  signal sysgen_dut_to_register3_data_in_x0: std_logic_vector(31 downto 0);
2788
  signal sysgen_dut_to_register3_en: std_logic;
2789
  signal sysgen_dut_to_register3_en_x0: std_logic;
2790
  signal sysgen_dut_to_register4_ce: std_logic;
2791
  signal sysgen_dut_to_register4_ce_x0: std_logic;
2792
  signal sysgen_dut_to_register4_clk: std_logic;
2793
  signal sysgen_dut_to_register4_clk_x0: std_logic;
2794
  signal sysgen_dut_to_register4_clr: std_logic;
2795
  signal sysgen_dut_to_register4_clr_x0: std_logic;
2796
  signal sysgen_dut_to_register4_data_in: std_logic;
2797
  signal sysgen_dut_to_register4_data_in_x0: std_logic;
2798
  signal sysgen_dut_to_register4_en: std_logic;
2799
  signal sysgen_dut_to_register4_en_x0: std_logic;
2800
  signal sysgen_dut_to_register5_ce: std_logic;
2801
  signal sysgen_dut_to_register5_ce_x0: std_logic;
2802
  signal sysgen_dut_to_register5_clk: std_logic;
2803
  signal sysgen_dut_to_register5_clk_x0: std_logic;
2804
  signal sysgen_dut_to_register5_clr: std_logic;
2805
  signal sysgen_dut_to_register5_clr_x0: std_logic;
2806
  signal sysgen_dut_to_register5_data_in: std_logic_vector(31 downto 0);
2807
  signal sysgen_dut_to_register5_data_in_x0: std_logic;
2808
  signal sysgen_dut_to_register5_en: std_logic;
2809
  signal sysgen_dut_to_register5_en_x0: std_logic;
2810
  signal sysgen_dut_to_register6_ce: std_logic;
2811
  signal sysgen_dut_to_register6_ce_x0: std_logic;
2812
  signal sysgen_dut_to_register6_clk: std_logic;
2813
  signal sysgen_dut_to_register6_clk_x0: std_logic;
2814
  signal sysgen_dut_to_register6_clr: std_logic;
2815
  signal sysgen_dut_to_register6_clr_x0: std_logic;
2816
  signal sysgen_dut_to_register6_data_in: std_logic_vector(31 downto 0);
2817
  signal sysgen_dut_to_register6_data_in_x0: std_logic_vector(31 downto 0);
2818
  signal sysgen_dut_to_register6_en: std_logic;
2819
  signal sysgen_dut_to_register6_en_x0: std_logic;
2820
  signal sysgen_dut_to_register7_ce: std_logic;
2821
  signal sysgen_dut_to_register7_ce_x0: std_logic;
2822
  signal sysgen_dut_to_register7_clk: std_logic;
2823
  signal sysgen_dut_to_register7_clk_x0: std_logic;
2824
  signal sysgen_dut_to_register7_clr: std_logic;
2825
  signal sysgen_dut_to_register7_clr_x0: std_logic;
2826
  signal sysgen_dut_to_register7_data_in: std_logic_vector(31 downto 0);
2827
  signal sysgen_dut_to_register7_data_in_x0: std_logic;
2828
  signal sysgen_dut_to_register7_en: std_logic;
2829
  signal sysgen_dut_to_register7_en_x0: std_logic;
2830
  signal sysgen_dut_to_register8_ce: std_logic;
2831
  signal sysgen_dut_to_register8_ce_x0: std_logic;
2832
  signal sysgen_dut_to_register8_clk: std_logic;
2833
  signal sysgen_dut_to_register8_clk_x0: std_logic;
2834
  signal sysgen_dut_to_register8_clr: std_logic;
2835
  signal sysgen_dut_to_register8_clr_x0: std_logic;
2836
  signal sysgen_dut_to_register8_data_in: std_logic;
2837
  signal sysgen_dut_to_register8_data_in_x0: std_logic_vector(31 downto 0);
2838
  signal sysgen_dut_to_register8_en: std_logic;
2839
  signal sysgen_dut_to_register8_en_x0: std_logic;
2840
  signal sysgen_dut_to_register9_ce: std_logic;
2841
  signal sysgen_dut_to_register9_ce_x0: std_logic;
2842
  signal sysgen_dut_to_register9_clk: std_logic;
2843
  signal sysgen_dut_to_register9_clk_x0: std_logic;
2844
  signal sysgen_dut_to_register9_clr: std_logic;
2845
  signal sysgen_dut_to_register9_clr_x0: std_logic;
2846
  signal sysgen_dut_to_register9_data_in: std_logic_vector(31 downto 0);
2847
  signal sysgen_dut_to_register9_data_in_x0: std_logic_vector(31 downto 0);
2848
  signal sysgen_dut_to_register9_en: std_logic;
2849
  signal sysgen_dut_to_register9_en_x0: std_logic;
2850
  signal sysgen_dut_to_register_ce: std_logic;
2851
  signal sysgen_dut_to_register_clk: std_logic;
2852
  signal sysgen_dut_to_register_clr: std_logic;
2853
  signal sysgen_dut_to_register_data_in: std_logic_vector(31 downto 0);
2854
  signal sysgen_dut_to_register_en: std_logic;
2855
  signal x: std_logic;
2856
  signal x_x0: std_logic;
2857
  signal x_x1: std_logic_vector(31 downto 0);
2858
  signal x_x10: std_logic;
2859
  signal x_x11: std_logic_vector(31 downto 0);
2860
  signal x_x12: std_logic;
2861
  signal x_x13: std_logic_vector(31 downto 0);
2862
  signal x_x14: std_logic;
2863
  signal x_x15: std_logic_vector(31 downto 0);
2864
  signal x_x16: std_logic;
2865
  signal x_x17: std_logic_vector(31 downto 0);
2866
  signal x_x18: std_logic;
2867
  signal x_x19: std_logic_vector(31 downto 0);
2868
  signal x_x2: std_logic_vector(31 downto 0);
2869
  signal x_x20: std_logic;
2870
  signal x_x21: std_logic_vector(31 downto 0);
2871
  signal x_x22: std_logic;
2872
  signal x_x23: std_logic_vector(31 downto 0);
2873
  signal x_x24: std_logic;
2874
  signal x_x25: std_logic_vector(31 downto 0);
2875
  signal x_x26: std_logic;
2876
  signal x_x27: std_logic_vector(31 downto 0);
2877
  signal x_x28: std_logic;
2878
  signal x_x29: std_logic_vector(31 downto 0);
2879
  signal x_x3: std_logic_vector(31 downto 0);
2880
  signal x_x30: std_logic;
2881
  signal x_x31: std_logic_vector(31 downto 0);
2882
  signal x_x32: std_logic;
2883
  signal x_x33: std_logic_vector(31 downto 0);
2884
  signal x_x34: std_logic;
2885
  signal x_x35: std_logic_vector(31 downto 0);
2886
  signal x_x36: std_logic;
2887
  signal x_x37: std_logic_vector(31 downto 0);
2888
  signal x_x38: std_logic;
2889
  signal x_x39: std_logic_vector(31 downto 0);
2890
  signal x_x4: std_logic_vector(31 downto 0);
2891
  signal x_x40: std_logic;
2892
  signal x_x41: std_logic_vector(31 downto 0);
2893
  signal x_x42: std_logic;
2894
  signal x_x43: std_logic_vector(31 downto 0);
2895
  signal x_x44: std_logic;
2896
  signal x_x45: std_logic_vector(31 downto 0);
2897
  signal x_x46: std_logic;
2898
  signal x_x47: std_logic_vector(31 downto 0);
2899
  signal x_x48: std_logic;
2900
  signal x_x49: std_logic_vector(31 downto 0);
2901
  signal x_x5: std_logic;
2902
  signal x_x50: std_logic;
2903
  signal x_x51: std_logic_vector(31 downto 0);
2904
  signal x_x52: std_logic;
2905
  signal x_x53: std_logic_vector(31 downto 0);
2906
  signal x_x54: std_logic;
2907
  signal x_x55: std_logic_vector(31 downto 0);
2908
  signal x_x56: std_logic;
2909
  signal x_x57: std_logic_vector(31 downto 0);
2910
  signal x_x58: std_logic;
2911
  signal x_x59: std_logic_vector(31 downto 0);
2912
  signal x_x6: std_logic;
2913
  signal x_x60: std_logic;
2914
  signal x_x61: std_logic_vector(31 downto 0);
2915
  signal x_x62: std_logic;
2916
  signal x_x63: std_logic_vector(11 downto 0);
2917
  signal x_x64: std_logic_vector(63 downto 0);
2918
  signal x_x65: std_logic_vector(11 downto 0);
2919
  signal x_x66: std_logic_vector(63 downto 0);
2920
  signal x_x67: std_logic_vector(7 downto 0);
2921
  signal x_x68: std_logic;
2922
  signal x_x69: std_logic;
2923
  signal x_x7: std_logic_vector(31 downto 0);
2924
  signal x_x70: std_logic_vector(14 downto 0);
2925
  signal x_x71: std_logic_vector(71 downto 0);
2926
  signal x_x72: std_logic;
2927
  signal x_x73: std_logic;
2928
  signal x_x74: std_logic;
2929
  signal x_x75: std_logic;
2930
  signal x_x76: std_logic_vector(14 downto 0);
2931
  signal x_x77: std_logic_vector(71 downto 0);
2932
  signal x_x78: std_logic;
2933
  signal x_x79: std_logic;
2934
  signal x_x8: std_logic;
2935
  signal x_x80: std_logic;
2936
  signal x_x81: std_logic;
2937
  signal x_x82: std_logic;
2938
  signal x_x83: std_logic;
2939
  signal x_x84: std_logic;
2940
  signal x_x85: std_logic;
2941
  signal x_x9: std_logic_vector(31 downto 0);
2942
 
2943
begin
2944
  x_x64 <= bram_rd_dout;
2945
  x_x1 <= debug_in_1i;
2946
  x_x2 <= debug_in_2i;
2947
  x_x3 <= debug_in_3i;
2948
  x_x4 <= debug_in_4i;
2949
  x_x5 <= dma_host2board_busy;
2950
  x_x6 <= dma_host2board_done;
2951
  x_x70 <= fifo_rd_count;
2952
  x_x71 <= fifo_rd_dout;
2953
  x_x72 <= fifo_rd_empty;
2954
  x_x74 <= fifo_rd_pempty;
2955
  x_x75 <= fifo_rd_valid;
2956
  x_x76 <= fifo_wr_count;
2957
  x_x79 <= fifo_wr_full;
2958
  x_x80 <= fifo_wr_pfull;
2959
  x <= inout_logic_cw_ce;
2960
  x_x0 <= inout_logic_cw_clk;
2961
  x_x9 <= reg01_td;
2962
  x_x10 <= reg01_tv;
2963
  x_x13 <= reg02_td;
2964
  x_x14 <= reg02_tv;
2965
  x_x17 <= reg03_td;
2966
  x_x18 <= reg03_tv;
2967
  x_x21 <= reg04_td;
2968
  x_x22 <= reg04_tv;
2969
  x_x25 <= reg05_td;
2970
  x_x26 <= reg05_tv;
2971
  x_x29 <= reg06_td;
2972
  x_x30 <= reg06_tv;
2973
  x_x33 <= reg07_td;
2974
  x_x34 <= reg07_tv;
2975
  x_x37 <= reg08_td;
2976
  x_x38 <= reg08_tv;
2977
  x_x41 <= reg09_td;
2978
  x_x42 <= reg09_tv;
2979
  x_x45 <= reg10_td;
2980
  x_x46 <= reg10_tv;
2981
  x_x49 <= reg11_td;
2982
  x_x50 <= reg11_tv;
2983
  x_x53 <= reg12_td;
2984
  x_x54 <= reg12_tv;
2985
  x_x57 <= reg13_td;
2986
  x_x58 <= reg13_tv;
2987
  x_x61 <= reg14_td;
2988
  x_x62 <= reg14_tv;
2989
  x_x81 <= rst_i;
2990
  x_x68 <= user_logic_cw_ce;
2991
  x_x69 <= user_logic_cw_clk;
2992
  bram_rd_addr <= x_x63;
2993
  bram_wr_addr <= x_x65;
2994
  bram_wr_din <= x_x66;
2995
  bram_wr_en <= x_x67;
2996
  fifo_rd_en <= x_x73;
2997
  fifo_wr_din <= x_x77;
2998
  fifo_wr_en <= x_x78;
2999
  reg01_rd <= x_x7;
3000
  reg01_rv <= x_x8;
3001
  reg02_rd <= x_x11;
3002
  reg02_rv <= x_x12;
3003
  reg03_rd <= x_x15;
3004
  reg03_rv <= x_x16;
3005
  reg04_rd <= x_x19;
3006
  reg04_rv <= x_x20;
3007
  reg05_rd <= x_x23;
3008
  reg05_rv <= x_x24;
3009
  reg06_rd <= x_x27;
3010
  reg06_rv <= x_x28;
3011
  reg07_rd <= x_x31;
3012
  reg07_rv <= x_x32;
3013
  reg08_rd <= x_x35;
3014
  reg08_rv <= x_x36;
3015
  reg09_rd <= x_x39;
3016
  reg09_rv <= x_x40;
3017
  reg10_rd <= x_x43;
3018
  reg10_rv <= x_x44;
3019
  reg11_rd <= x_x47;
3020
  reg11_rv <= x_x48;
3021
  reg12_rd <= x_x51;
3022
  reg12_rv <= x_x52;
3023
  reg13_rd <= x_x55;
3024
  reg13_rv <= x_x56;
3025
  reg14_rd <= x_x59;
3026
  reg14_rv <= x_x60;
3027
  rst_o <= x_x82;
3028
  user_int_1o <= x_x83;
3029
  user_int_2o <= x_x84;
3030
  user_int_3o <= x_x85;
3031
 
3032
  DMA_Host2Board_Busy_ce_and2_comp: entity work.xland2
3033
    port map (
3034
      a => sysgen_dut_to_register18_ce,
3035
      b => sysgen_dut_to_register18_en,
3036
      dout => DMA_Host2Board_Busy_reg_ce
3037
    );
3038
 
3039
  DMA_Host2Board_Busy_x0: entity work.synth_reg_w_init
3040
    generic map (
3041
      width => 1,
3042
      init_index => 2,
3043
      init_value => b"0",
3044
      latency => 1
3045
    )
3046
    port map (
3047
      ce => DMA_Host2Board_Busy_reg_ce,
3048
      clk => sysgen_dut_to_register18_clk,
3049
      clr => sysgen_dut_to_register18_clr,
3050
      i(0) => sysgen_dut_to_register18_data_in,
3051
      o(0) => from_register16_data_out_x0
3052
    );
3053
 
3054
  DMA_Host2Board_Done_ce_and2_comp: entity work.xland2
3055
    port map (
3056
      a => sysgen_dut_to_register19_ce,
3057
      b => sysgen_dut_to_register19_en,
3058
      dout => DMA_Host2Board_Done_reg_ce
3059
    );
3060
 
3061
  DMA_Host2Board_Done_x0: entity work.synth_reg_w_init
3062
    generic map (
3063
      width => 1,
3064
      init_index => 2,
3065
      init_value => b"0",
3066
      latency => 1
3067
    )
3068
    port map (
3069
      ce => DMA_Host2Board_Done_reg_ce,
3070
      clk => sysgen_dut_to_register19_clk,
3071
      clr => sysgen_dut_to_register19_clr,
3072
      i(0) => sysgen_dut_to_register19_data_in,
3073
      o(0) => from_register15_data_out_x0
3074
    );
3075
 
3076
  debug1i: entity work.synth_reg_w_init
3077
    generic map (
3078
      width => 32,
3079
      init_index => 2,
3080
      init_value => b"00000000000000000000000000000000",
3081
      latency => 1
3082
    )
3083
    port map (
3084
      ce => debug1i_reg_ce,
3085
      clk => sysgen_dut_to_register6_clk,
3086
      clr => sysgen_dut_to_register6_clr,
3087
      i => sysgen_dut_to_register6_data_in,
3088
      o => from_register_data_out
3089
    );
3090
 
3091
  debug1i_ce_and2_comp: entity work.xland2
3092
    port map (
3093
      a => sysgen_dut_to_register6_ce,
3094
      b => sysgen_dut_to_register6_en,
3095
      dout => debug1i_reg_ce
3096
    );
3097
 
3098
  debug2i: entity work.synth_reg_w_init
3099
    generic map (
3100
      width => 32,
3101
      init_index => 2,
3102
      init_value => b"00000000000000000000000000000000",
3103
      latency => 1
3104
    )
3105
    port map (
3106
      ce => debug2i_reg_ce,
3107
      clk => sysgen_dut_to_register1_clk,
3108
      clr => sysgen_dut_to_register1_clr,
3109
      i => sysgen_dut_to_register1_data_in,
3110
      o => from_register1_data_out_x0
3111
    );
3112
 
3113
  debug2i_ce_and2_comp: entity work.xland2
3114
    port map (
3115
      a => sysgen_dut_to_register1_ce,
3116
      b => sysgen_dut_to_register1_en,
3117
      dout => debug2i_reg_ce
3118
    );
3119
 
3120
  debug3i: entity work.synth_reg_w_init
3121
    generic map (
3122
      width => 32,
3123
      init_index => 2,
3124
      init_value => b"00000000000000000000000000000000",
3125
      latency => 1
3126
    )
3127
    port map (
3128
      ce => debug3i_reg_ce,
3129
      clk => sysgen_dut_to_register2_clk,
3130
      clr => sysgen_dut_to_register2_clr,
3131
      i => sysgen_dut_to_register2_data_in,
3132
      o => from_register2_data_out_x0
3133
    );
3134
 
3135
  debug3i_ce_and2_comp: entity work.xland2
3136
    port map (
3137
      a => sysgen_dut_to_register2_ce,
3138
      b => sysgen_dut_to_register2_en,
3139
      dout => debug3i_reg_ce
3140
    );
3141
 
3142
  debug4i: entity work.synth_reg_w_init
3143
    generic map (
3144
      width => 32,
3145
      init_index => 2,
3146
      init_value => b"00000000000000000000000000000000",
3147
      latency => 1
3148
    )
3149
    port map (
3150
      ce => debug4i_reg_ce,
3151
      clk => sysgen_dut_to_register20_clk,
3152
      clr => sysgen_dut_to_register20_clr,
3153
      i => sysgen_dut_to_register20_data_in,
3154
      o => from_register19_data_out_x0
3155
    );
3156
 
3157
  debug4i_ce_and2_comp: entity work.xland2
3158
    port map (
3159
      a => sysgen_dut_to_register20_ce,
3160
      b => sysgen_dut_to_register20_en,
3161
      dout => debug4i_reg_ce
3162
    );
3163
 
3164
  register01rd: entity work.synth_reg_w_init
3165
    generic map (
3166
      width => 32,
3167
      init_index => 2,
3168
      init_value => b"00000000000000000000000000000000",
3169
      latency => 1
3170
    )
3171
    port map (
3172
      ce => register01rd_reg_ce,
3173
      clk => sysgen_dut_to_register_clk,
3174
      clr => sysgen_dut_to_register_clr,
3175
      i => sysgen_dut_to_register_data_in,
3176
      o => from_register3_data_out
3177
    );
3178
 
3179
  register01rd_ce_and2_comp: entity work.xland2
3180
    port map (
3181
      a => sysgen_dut_to_register_ce,
3182
      b => sysgen_dut_to_register_en,
3183
      dout => register01rd_reg_ce
3184
    );
3185
 
3186
  register01rv: entity work.synth_reg_w_init
3187
    generic map (
3188
      width => 1,
3189
      init_index => 2,
3190
      init_value => b"0",
3191
      latency => 1
3192
    )
3193
    port map (
3194
      ce => register01rv_reg_ce,
3195
      clk => sysgen_dut_to_register1_clk_x0,
3196
      clr => sysgen_dut_to_register1_clr_x0,
3197
      i(0) => sysgen_dut_to_register1_data_in_x0,
3198
      o(0) => from_register1_data_out
3199
    );
3200
 
3201
  register01rv_ce_and2_comp: entity work.xland2
3202
    port map (
3203
      a => sysgen_dut_to_register1_ce_x0,
3204
      b => sysgen_dut_to_register1_en_x0,
3205
      dout => register01rv_reg_ce
3206
    );
3207
 
3208
  register01td: entity work.synth_reg_w_init
3209
    generic map (
3210
      width => 32,
3211
      init_index => 2,
3212
      init_value => b"00000000000000000000000000000000",
3213
      latency => 1
3214
    )
3215
    port map (
3216
      ce => register01td_reg_ce,
3217
      clk => sysgen_dut_to_register7_clk,
3218
      clr => sysgen_dut_to_register7_clr,
3219
      i => sysgen_dut_to_register7_data_in,
3220
      o => from_register3_data_out_x0
3221
    );
3222
 
3223
  register01td_ce_and2_comp: entity work.xland2
3224
    port map (
3225
      a => sysgen_dut_to_register7_ce,
3226
      b => sysgen_dut_to_register7_en,
3227
      dout => register01td_reg_ce
3228
    );
3229
 
3230
  register01tv: entity work.synth_reg_w_init
3231
    generic map (
3232
      width => 1,
3233
      init_index => 2,
3234
      init_value => b"0",
3235
      latency => 1
3236
    )
3237
    port map (
3238
      ce => register01tv_reg_ce,
3239
      clk => sysgen_dut_to_register3_clk,
3240
      clr => sysgen_dut_to_register3_clr,
3241
      i(0) => sysgen_dut_to_register3_data_in,
3242
      o(0) => from_register4_data_out_x0
3243
    );
3244
 
3245
  register01tv_ce_and2_comp: entity work.xland2
3246
    port map (
3247
      a => sysgen_dut_to_register3_ce,
3248
      b => sysgen_dut_to_register3_en,
3249
      dout => register01tv_reg_ce
3250
    );
3251
 
3252
  register02rd: entity work.synth_reg_w_init
3253
    generic map (
3254
      width => 32,
3255
      init_index => 2,
3256
      init_value => b"00000000000000000000000000000000",
3257
      latency => 1
3258
    )
3259
    port map (
3260
      ce => register02rd_reg_ce,
3261
      clk => sysgen_dut_to_register2_clk_x0,
3262
      clr => sysgen_dut_to_register2_clr_x0,
3263
      i => sysgen_dut_to_register2_data_in_x0,
3264
      o => from_register5_data_out
3265
    );
3266
 
3267
  register02rd_ce_and2_comp: entity work.xland2
3268
    port map (
3269
      a => sysgen_dut_to_register2_ce_x0,
3270
      b => sysgen_dut_to_register2_en_x0,
3271
      dout => register02rd_reg_ce
3272
    );
3273
 
3274
  register02rv: entity work.synth_reg_w_init
3275
    generic map (
3276
      width => 1,
3277
      init_index => 2,
3278
      init_value => b"0",
3279
      latency => 1
3280
    )
3281
    port map (
3282
      ce => register02rv_reg_ce,
3283
      clk => sysgen_dut_to_register4_clk_x0,
3284
      clr => sysgen_dut_to_register4_clr_x0,
3285
      i(0) => sysgen_dut_to_register4_data_in_x0,
3286
      o(0) => from_register2_data_out
3287
    );
3288
 
3289
  register02rv_ce_and2_comp: entity work.xland2
3290
    port map (
3291
      a => sysgen_dut_to_register4_ce_x0,
3292
      b => sysgen_dut_to_register4_en_x0,
3293
      dout => register02rv_reg_ce
3294
    );
3295
 
3296
  register02td: entity work.synth_reg_w_init
3297
    generic map (
3298
      width => 32,
3299
      init_index => 2,
3300
      init_value => b"00000000000000000000000000000000",
3301
      latency => 1
3302
    )
3303
    port map (
3304
      ce => register02td_reg_ce,
3305
      clk => sysgen_dut_to_register5_clk,
3306
      clr => sysgen_dut_to_register5_clr,
3307
      i => sysgen_dut_to_register5_data_in,
3308
      o => from_register5_data_out_x0
3309
    );
3310
 
3311
  register02td_ce_and2_comp: entity work.xland2
3312
    port map (
3313
      a => sysgen_dut_to_register5_ce,
3314
      b => sysgen_dut_to_register5_en,
3315
      dout => register02td_reg_ce
3316
    );
3317
 
3318
  register02tv: entity work.synth_reg_w_init
3319
    generic map (
3320
      width => 1,
3321
      init_index => 2,
3322
      init_value => b"0",
3323
      latency => 1
3324
    )
3325
    port map (
3326
      ce => register02tv_reg_ce,
3327
      clk => sysgen_dut_to_register4_clk,
3328
      clr => sysgen_dut_to_register4_clr,
3329
      i(0) => sysgen_dut_to_register4_data_in,
3330
      o(0) => from_register6_data_out_x0
3331
    );
3332
 
3333
  register02tv_ce_and2_comp: entity work.xland2
3334
    port map (
3335
      a => sysgen_dut_to_register4_ce,
3336
      b => sysgen_dut_to_register4_en,
3337
      dout => register02tv_reg_ce
3338
    );
3339
 
3340
  register03rd: entity work.synth_reg_w_init
3341
    generic map (
3342
      width => 32,
3343
      init_index => 2,
3344
      init_value => b"00000000000000000000000000000000",
3345
      latency => 1
3346
    )
3347
    port map (
3348
      ce => register03rd_reg_ce,
3349
      clk => sysgen_dut_to_register3_clk_x0,
3350
      clr => sysgen_dut_to_register3_clr_x0,
3351
      i => sysgen_dut_to_register3_data_in_x0,
3352
      o => from_register7_data_out
3353
    );
3354
 
3355
  register03rd_ce_and2_comp: entity work.xland2
3356
    port map (
3357
      a => sysgen_dut_to_register3_ce_x0,
3358
      b => sysgen_dut_to_register3_en_x0,
3359
      dout => register03rd_reg_ce
3360
    );
3361
 
3362
  register03rv: entity work.synth_reg_w_init
3363
    generic map (
3364
      width => 1,
3365
      init_index => 2,
3366
      init_value => b"0",
3367
      latency => 1
3368
    )
3369
    port map (
3370
      ce => register03rv_reg_ce,
3371
      clk => sysgen_dut_to_register5_clk_x0,
3372
      clr => sysgen_dut_to_register5_clr_x0,
3373
      i(0) => sysgen_dut_to_register5_data_in_x0,
3374
      o(0) => from_register6_data_out
3375
    );
3376
 
3377
  register03rv_ce_and2_comp: entity work.xland2
3378
    port map (
3379
      a => sysgen_dut_to_register5_ce_x0,
3380
      b => sysgen_dut_to_register5_en_x0,
3381
      dout => register03rv_reg_ce
3382
    );
3383
 
3384
  register03td: entity work.synth_reg_w_init
3385
    generic map (
3386
      width => 32,
3387
      init_index => 2,
3388
      init_value => b"00000000000000000000000000000000",
3389
      latency => 1
3390
    )
3391
    port map (
3392
      ce => register03td_reg_ce,
3393
      clk => sysgen_dut_to_register9_clk,
3394
      clr => sysgen_dut_to_register9_clr,
3395
      i => sysgen_dut_to_register9_data_in,
3396
      o => from_register7_data_out_x0
3397
    );
3398
 
3399
  register03td_ce_and2_comp: entity work.xland2
3400
    port map (
3401
      a => sysgen_dut_to_register9_ce,
3402
      b => sysgen_dut_to_register9_en,
3403
      dout => register03td_reg_ce
3404
    );
3405
 
3406
  register03tv: entity work.synth_reg_w_init
3407
    generic map (
3408
      width => 1,
3409
      init_index => 2,
3410
      init_value => b"0",
3411
      latency => 1
3412
    )
3413
    port map (
3414
      ce => register03tv_reg_ce,
3415
      clk => sysgen_dut_to_register8_clk,
3416
      clr => sysgen_dut_to_register8_clr,
3417
      i(0) => sysgen_dut_to_register8_data_in,
3418
      o(0) => from_register8_data_out_x0
3419
    );
3420
 
3421
  register03tv_ce_and2_comp: entity work.xland2
3422
    port map (
3423
      a => sysgen_dut_to_register8_ce,
3424
      b => sysgen_dut_to_register8_en,
3425
      dout => register03tv_reg_ce
3426
    );
3427
 
3428
  register04rd: entity work.synth_reg_w_init
3429
    generic map (
3430
      width => 32,
3431
      init_index => 2,
3432
      init_value => b"00000000000000000000000000000000",
3433
      latency => 1
3434
    )
3435
    port map (
3436
      ce => register04rd_reg_ce,
3437
      clk => sysgen_dut_to_register6_clk_x0,
3438
      clr => sysgen_dut_to_register6_clr_x0,
3439
      i => sysgen_dut_to_register6_data_in_x0,
3440
      o => from_register8_data_out
3441
    );
3442
 
3443
  register04rd_ce_and2_comp: entity work.xland2
3444
    port map (
3445
      a => sysgen_dut_to_register6_ce_x0,
3446
      b => sysgen_dut_to_register6_en_x0,
3447
      dout => register04rd_reg_ce
3448
    );
3449
 
3450
  register04rv: entity work.synth_reg_w_init
3451
    generic map (
3452
      width => 1,
3453
      init_index => 2,
3454
      init_value => b"0",
3455
      latency => 1
3456
    )
3457
    port map (
3458
      ce => register04rv_reg_ce,
3459
      clk => sysgen_dut_to_register7_clk_x0,
3460
      clr => sysgen_dut_to_register7_clr_x0,
3461
      i(0) => sysgen_dut_to_register7_data_in_x0,
3462
      o(0) => from_register4_data_out
3463
    );
3464
 
3465
  register04rv_ce_and2_comp: entity work.xland2
3466
    port map (
3467
      a => sysgen_dut_to_register7_ce_x0,
3468
      b => sysgen_dut_to_register7_en_x0,
3469
      dout => register04rv_reg_ce
3470
    );
3471
 
3472
  register04td: entity work.synth_reg_w_init
3473
    generic map (
3474
      width => 32,
3475
      init_index => 2,
3476
      init_value => b"00000000000000000000000000000000",
3477
      latency => 1
3478
    )
3479
    port map (
3480
      ce => register04td_reg_ce,
3481
      clk => sysgen_dut_to_register11_clk,
3482
      clr => sysgen_dut_to_register11_clr,
3483
      i => sysgen_dut_to_register11_data_in,
3484
      o => from_register9_data_out_x0
3485
    );
3486
 
3487
  register04td_ce_and2_comp: entity work.xland2
3488
    port map (
3489
      a => sysgen_dut_to_register11_ce,
3490
      b => sysgen_dut_to_register11_en,
3491
      dout => register04td_reg_ce
3492
    );
3493
 
3494
  register04tv: entity work.synth_reg_w_init
3495
    generic map (
3496
      width => 1,
3497
      init_index => 2,
3498
      init_value => b"0",
3499
      latency => 1
3500
    )
3501
    port map (
3502
      ce => register04tv_reg_ce,
3503
      clk => sysgen_dut_to_register10_clk,
3504
      clr => sysgen_dut_to_register10_clr,
3505
      i(0) => sysgen_dut_to_register10_data_in,
3506
      o(0) => from_register10_data_out_x0
3507
    );
3508
 
3509
  register04tv_ce_and2_comp: entity work.xland2
3510
    port map (
3511
      a => sysgen_dut_to_register10_ce,
3512
      b => sysgen_dut_to_register10_en,
3513
      dout => register04tv_reg_ce
3514
    );
3515
 
3516
  register05rd: entity work.synth_reg_w_init
3517
    generic map (
3518
      width => 32,
3519
      init_index => 2,
3520
      init_value => b"00000000000000000000000000000000",
3521
      latency => 1
3522
    )
3523
    port map (
3524
      ce => register05rd_reg_ce,
3525
      clk => sysgen_dut_to_register8_clk_x0,
3526
      clr => sysgen_dut_to_register8_clr_x0,
3527
      i => sysgen_dut_to_register8_data_in_x0,
3528
      o => from_register10_data_out
3529
    );
3530
 
3531
  register05rd_ce_and2_comp: entity work.xland2
3532
    port map (
3533
      a => sysgen_dut_to_register8_ce_x0,
3534
      b => sysgen_dut_to_register8_en_x0,
3535
      dout => register05rd_reg_ce
3536
    );
3537
 
3538
  register05rv: entity work.synth_reg_w_init
3539
    generic map (
3540
      width => 1,
3541
      init_index => 2,
3542
      init_value => b"0",
3543
      latency => 1
3544
    )
3545
    port map (
3546
      ce => register05rv_reg_ce,
3547
      clk => sysgen_dut_to_register10_clk_x0,
3548
      clr => sysgen_dut_to_register10_clr_x0,
3549
      i(0) => sysgen_dut_to_register10_data_in_x0,
3550
      o(0) => from_register9_data_out
3551
    );
3552
 
3553
  register05rv_ce_and2_comp: entity work.xland2
3554
    port map (
3555
      a => sysgen_dut_to_register10_ce_x0,
3556
      b => sysgen_dut_to_register10_en_x0,
3557
      dout => register05rv_reg_ce
3558
    );
3559
 
3560
  register05td: entity work.synth_reg_w_init
3561
    generic map (
3562
      width => 32,
3563
      init_index => 2,
3564
      init_value => b"00000000000000000000000000000000",
3565
      latency => 1
3566
    )
3567
    port map (
3568
      ce => register05td_reg_ce,
3569
      clk => sysgen_dut_to_register13_clk,
3570
      clr => sysgen_dut_to_register13_clr,
3571
      i => sysgen_dut_to_register13_data_in,
3572
      o => from_register11_data_out_x0
3573
    );
3574
 
3575
  register05td_ce_and2_comp: entity work.xland2
3576
    port map (
3577
      a => sysgen_dut_to_register13_ce,
3578
      b => sysgen_dut_to_register13_en,
3579
      dout => register05td_reg_ce
3580
    );
3581
 
3582
  register05tv: entity work.synth_reg_w_init
3583
    generic map (
3584
      width => 1,
3585
      init_index => 2,
3586
      init_value => b"0",
3587
      latency => 1
3588
    )
3589
    port map (
3590
      ce => register05tv_reg_ce,
3591
      clk => sysgen_dut_to_register12_clk,
3592
      clr => sysgen_dut_to_register12_clr,
3593
      i(0) => sysgen_dut_to_register12_data_in,
3594
      o(0) => from_register12_data_out_x0
3595
    );
3596
 
3597
  register05tv_ce_and2_comp: entity work.xland2
3598
    port map (
3599
      a => sysgen_dut_to_register12_ce,
3600
      b => sysgen_dut_to_register12_en,
3601
      dout => register05tv_reg_ce
3602
    );
3603
 
3604
  register06rd: entity work.synth_reg_w_init
3605
    generic map (
3606
      width => 32,
3607
      init_index => 2,
3608
      init_value => b"00000000000000000000000000000000",
3609
      latency => 1
3610
    )
3611
    port map (
3612
      ce => register06rd_reg_ce,
3613
      clk => sysgen_dut_to_register9_clk_x0,
3614
      clr => sysgen_dut_to_register9_clr_x0,
3615
      i => sysgen_dut_to_register9_data_in_x0,
3616
      o => from_register11_data_out
3617
    );
3618
 
3619
  register06rd_ce_and2_comp: entity work.xland2
3620
    port map (
3621
      a => sysgen_dut_to_register9_ce_x0,
3622
      b => sysgen_dut_to_register9_en_x0,
3623
      dout => register06rd_reg_ce
3624
    );
3625
 
3626
  register06rv: entity work.synth_reg_w_init
3627
    generic map (
3628
      width => 1,
3629
      init_index => 2,
3630
      init_value => b"0",
3631
      latency => 1
3632
    )
3633
    port map (
3634
      ce => register06rv_reg_ce,
3635
      clk => sysgen_dut_to_register11_clk_x0,
3636
      clr => sysgen_dut_to_register11_clr_x0,
3637
      i(0) => sysgen_dut_to_register11_data_in_x0,
3638
      o(0) => from_register12_data_out
3639
    );
3640
 
3641
  register06rv_ce_and2_comp: entity work.xland2
3642
    port map (
3643
      a => sysgen_dut_to_register11_ce_x0,
3644
      b => sysgen_dut_to_register11_en_x0,
3645
      dout => register06rv_reg_ce
3646
    );
3647
 
3648
  register06td: entity work.synth_reg_w_init
3649
    generic map (
3650
      width => 32,
3651
      init_index => 2,
3652
      init_value => b"00000000000000000000000000000000",
3653
      latency => 1
3654
    )
3655
    port map (
3656
      ce => register06td_reg_ce,
3657
      clk => sysgen_dut_to_register15_clk,
3658
      clr => sysgen_dut_to_register15_clr,
3659
      i => sysgen_dut_to_register15_data_in,
3660
      o => from_register13_data_out_x0
3661
    );
3662
 
3663
  register06td_ce_and2_comp: entity work.xland2
3664
    port map (
3665
      a => sysgen_dut_to_register15_ce,
3666
      b => sysgen_dut_to_register15_en,
3667
      dout => register06td_reg_ce
3668
    );
3669
 
3670
  register06tv: entity work.synth_reg_w_init
3671
    generic map (
3672
      width => 1,
3673
      init_index => 2,
3674
      init_value => b"0",
3675
      latency => 1
3676
    )
3677
    port map (
3678
      ce => register06tv_reg_ce,
3679
      clk => sysgen_dut_to_register14_clk,
3680
      clr => sysgen_dut_to_register14_clr,
3681
      i(0) => sysgen_dut_to_register14_data_in,
3682
      o(0) => from_register14_data_out_x0
3683
    );
3684
 
3685
  register06tv_ce_and2_comp: entity work.xland2
3686
    port map (
3687
      a => sysgen_dut_to_register14_ce,
3688
      b => sysgen_dut_to_register14_en,
3689
      dout => register06tv_reg_ce
3690
    );
3691
 
3692
  register07rd: entity work.synth_reg_w_init
3693
    generic map (
3694
      width => 32,
3695
      init_index => 2,
3696
      init_value => b"00000000000000000000000000000000",
3697
      latency => 1
3698
    )
3699
    port map (
3700
      ce => register07rd_reg_ce,
3701
      clk => sysgen_dut_to_register13_clk_x0,
3702
      clr => sysgen_dut_to_register13_clr_x0,
3703
      i => sysgen_dut_to_register13_data_in_x0,
3704
      o => from_register13_data_out
3705
    );
3706
 
3707
  register07rd_ce_and2_comp: entity work.xland2
3708
    port map (
3709
      a => sysgen_dut_to_register13_ce_x0,
3710
      b => sysgen_dut_to_register13_en_x0,
3711
      dout => register07rd_reg_ce
3712
    );
3713
 
3714
  register07rv: entity work.synth_reg_w_init
3715
    generic map (
3716
      width => 1,
3717
      init_index => 2,
3718
      init_value => b"0",
3719
      latency => 1
3720
    )
3721
    port map (
3722
      ce => register07rv_reg_ce,
3723
      clk => sysgen_dut_to_register12_clk_x0,
3724
      clr => sysgen_dut_to_register12_clr_x0,
3725
      i(0) => sysgen_dut_to_register12_data_in_x0,
3726
      o(0) => from_register14_data_out
3727
    );
3728
 
3729
  register07rv_ce_and2_comp: entity work.xland2
3730
    port map (
3731
      a => sysgen_dut_to_register12_ce_x0,
3732
      b => sysgen_dut_to_register12_en_x0,
3733
      dout => register07rv_reg_ce
3734
    );
3735
 
3736
  register07td: entity work.synth_reg_w_init
3737
    generic map (
3738
      width => 32,
3739
      init_index => 2,
3740
      init_value => b"00000000000000000000000000000000",
3741
      latency => 1
3742
    )
3743
    port map (
3744
      ce => register07td_reg_ce,
3745
      clk => sysgen_dut_to_register17_clk,
3746
      clr => sysgen_dut_to_register17_clr,
3747
      i => sysgen_dut_to_register17_data_in,
3748
      o => from_register17_data_out_x0
3749
    );
3750
 
3751
  register07td_ce_and2_comp: entity work.xland2
3752
    port map (
3753
      a => sysgen_dut_to_register17_ce,
3754
      b => sysgen_dut_to_register17_en,
3755
      dout => register07td_reg_ce
3756
    );
3757
 
3758
  register07tv: entity work.synth_reg_w_init
3759
    generic map (
3760
      width => 1,
3761
      init_index => 2,
3762
      init_value => b"0",
3763
      latency => 1
3764
    )
3765
    port map (
3766
      ce => register07tv_reg_ce,
3767
      clk => sysgen_dut_to_register16_clk,
3768
      clr => sysgen_dut_to_register16_clr,
3769
      i(0) => sysgen_dut_to_register16_data_in,
3770
      o(0) => from_register18_data_out_x0
3771
    );
3772
 
3773
  register07tv_ce_and2_comp: entity work.xland2
3774
    port map (
3775
      a => sysgen_dut_to_register16_ce,
3776
      b => sysgen_dut_to_register16_en,
3777
      dout => register07tv_reg_ce
3778
    );
3779
 
3780
  register08rd: entity work.synth_reg_w_init
3781
    generic map (
3782
      width => 32,
3783
      init_index => 2,
3784
      init_value => b"00000000000000000000000000000000",
3785
      latency => 1
3786
    )
3787
    port map (
3788
      ce => register08rd_reg_ce,
3789
      clk => sysgen_dut_to_register15_clk_x0,
3790
      clr => sysgen_dut_to_register15_clr_x0,
3791
      i => sysgen_dut_to_register15_data_in_x0,
3792
      o => from_register15_data_out
3793
    );
3794
 
3795
  register08rd_ce_and2_comp: entity work.xland2
3796
    port map (
3797
      a => sysgen_dut_to_register15_ce_x0,
3798
      b => sysgen_dut_to_register15_en_x0,
3799
      dout => register08rd_reg_ce
3800
    );
3801
 
3802
  register08rv: entity work.synth_reg_w_init
3803
    generic map (
3804
      width => 1,
3805
      init_index => 2,
3806
      init_value => b"0",
3807
      latency => 1
3808
    )
3809
    port map (
3810
      ce => register08rv_reg_ce,
3811
      clk => sysgen_dut_to_register14_clk_x0,
3812
      clr => sysgen_dut_to_register14_clr_x0,
3813
      i(0) => sysgen_dut_to_register14_data_in_x0,
3814
      o(0) => from_register16_data_out
3815
    );
3816
 
3817
  register08rv_ce_and2_comp: entity work.xland2
3818
    port map (
3819
      a => sysgen_dut_to_register14_ce_x0,
3820
      b => sysgen_dut_to_register14_en_x0,
3821
      dout => register08rv_reg_ce
3822
    );
3823
 
3824
  register08td: entity work.synth_reg_w_init
3825
    generic map (
3826
      width => 32,
3827
      init_index => 2,
3828
      init_value => b"00000000000000000000000000000000",
3829
      latency => 1
3830
    )
3831
    port map (
3832
      ce => register08td_reg_ce,
3833
      clk => sysgen_dut_to_register26_clk,
3834
      clr => sysgen_dut_to_register26_clr,
3835
      i => sysgen_dut_to_register26_data_in,
3836
      o => from_register20_data_out_x0
3837
    );
3838
 
3839
  register08td_ce_and2_comp: entity work.xland2
3840
    port map (
3841
      a => sysgen_dut_to_register26_ce,
3842
      b => sysgen_dut_to_register26_en,
3843
      dout => register08td_reg_ce
3844
    );
3845
 
3846
  register08tv: entity work.synth_reg_w_init
3847
    generic map (
3848
      width => 1,
3849
      init_index => 2,
3850
      init_value => b"0",
3851
      latency => 1
3852
    )
3853
    port map (
3854
      ce => register08tv_reg_ce,
3855
      clk => sysgen_dut_to_register25_clk,
3856
      clr => sysgen_dut_to_register25_clr,
3857
      i(0) => sysgen_dut_to_register25_data_in,
3858
      o(0) => from_register21_data_out_x0
3859
    );
3860
 
3861
  register08tv_ce_and2_comp: entity work.xland2
3862
    port map (
3863
      a => sysgen_dut_to_register25_ce,
3864
      b => sysgen_dut_to_register25_en,
3865
      dout => register08tv_reg_ce
3866
    );
3867
 
3868
  register09rd: entity work.synth_reg_w_init
3869
    generic map (
3870
      width => 32,
3871
      init_index => 2,
3872
      init_value => b"00000000000000000000000000000000",
3873
      latency => 1
3874
    )
3875
    port map (
3876
      ce => register09rd_reg_ce,
3877
      clk => sysgen_dut_to_register17_clk_x0,
3878
      clr => sysgen_dut_to_register17_clr_x0,
3879
      i => sysgen_dut_to_register17_data_in_x0,
3880
      o => from_register17_data_out
3881
    );
3882
 
3883
  register09rd_ce_and2_comp: entity work.xland2
3884
    port map (
3885
      a => sysgen_dut_to_register17_ce_x0,
3886
      b => sysgen_dut_to_register17_en_x0,
3887
      dout => register09rd_reg_ce
3888
    );
3889
 
3890
  register09rv: entity work.synth_reg_w_init
3891
    generic map (
3892
      width => 1,
3893
      init_index => 2,
3894
      init_value => b"0",
3895
      latency => 1
3896
    )
3897
    port map (
3898
      ce => register09rv_reg_ce,
3899
      clk => sysgen_dut_to_register16_clk_x0,
3900
      clr => sysgen_dut_to_register16_clr_x0,
3901
      i(0) => sysgen_dut_to_register16_data_in_x0,
3902
      o(0) => from_register18_data_out
3903
    );
3904
 
3905
  register09rv_ce_and2_comp: entity work.xland2
3906
    port map (
3907
      a => sysgen_dut_to_register16_ce_x0,
3908
      b => sysgen_dut_to_register16_en_x0,
3909
      dout => register09rv_reg_ce
3910
    );
3911
 
3912
  register09td: entity work.synth_reg_w_init
3913
    generic map (
3914
      width => 32,
3915
      init_index => 2,
3916
      init_value => b"00000000000000000000000000000000",
3917
      latency => 1
3918
    )
3919
    port map (
3920
      ce => register09td_reg_ce,
3921
      clk => sysgen_dut_to_register22_clk,
3922
      clr => sysgen_dut_to_register22_clr,
3923
      i => sysgen_dut_to_register22_data_in,
3924
      o => from_register22_data_out_x0
3925
    );
3926
 
3927
  register09td_ce_and2_comp: entity work.xland2
3928
    port map (
3929
      a => sysgen_dut_to_register22_ce,
3930
      b => sysgen_dut_to_register22_en,
3931
      dout => register09td_reg_ce
3932
    );
3933
 
3934
  register09tv: entity work.synth_reg_w_init
3935
    generic map (
3936
      width => 1,
3937
      init_index => 2,
3938
      init_value => b"0",
3939
      latency => 1
3940
    )
3941
    port map (
3942
      ce => register09tv_reg_ce,
3943
      clk => sysgen_dut_to_register21_clk,
3944
      clr => sysgen_dut_to_register21_clr,
3945
      i(0) => sysgen_dut_to_register21_data_in,
3946
      o(0) => from_register23_data_out_x0
3947
    );
3948
 
3949
  register09tv_ce_and2_comp: entity work.xland2
3950
    port map (
3951
      a => sysgen_dut_to_register21_ce,
3952
      b => sysgen_dut_to_register21_en,
3953
      dout => register09tv_reg_ce
3954
    );
3955
 
3956
  register10rd: entity work.synth_reg_w_init
3957
    generic map (
3958
      width => 32,
3959
      init_index => 2,
3960
      init_value => b"00000000000000000000000000000000",
3961
      latency => 1
3962
    )
3963
    port map (
3964
      ce => register10rd_reg_ce,
3965
      clk => sysgen_dut_to_register19_clk_x0,
3966
      clr => sysgen_dut_to_register19_clr_x0,
3967
      i => sysgen_dut_to_register19_data_in_x0,
3968
      o => from_register19_data_out
3969
    );
3970
 
3971
  register10rd_ce_and2_comp: entity work.xland2
3972
    port map (
3973
      a => sysgen_dut_to_register19_ce_x0,
3974
      b => sysgen_dut_to_register19_en_x0,
3975
      dout => register10rd_reg_ce
3976
    );
3977
 
3978
  register10rv: entity work.synth_reg_w_init
3979
    generic map (
3980
      width => 1,
3981
      init_index => 2,
3982
      init_value => b"0",
3983
      latency => 1
3984
    )
3985
    port map (
3986
      ce => register10rv_reg_ce,
3987
      clk => sysgen_dut_to_register18_clk_x0,
3988
      clr => sysgen_dut_to_register18_clr_x0,
3989
      i(0) => sysgen_dut_to_register18_data_in_x0,
3990
      o(0) => from_register20_data_out
3991
    );
3992
 
3993
  register10rv_ce_and2_comp: entity work.xland2
3994
    port map (
3995
      a => sysgen_dut_to_register18_ce_x0,
3996
      b => sysgen_dut_to_register18_en_x0,
3997
      dout => register10rv_reg_ce
3998
    );
3999
 
4000
  register10td: entity work.synth_reg_w_init
4001
    generic map (
4002
      width => 32,
4003
      init_index => 2,
4004
      init_value => b"00000000000000000000000000000000",
4005
      latency => 1
4006
    )
4007
    port map (
4008
      ce => register10td_reg_ce,
4009
      clk => sysgen_dut_to_register24_clk,
4010
      clr => sysgen_dut_to_register24_clr,
4011
      i => sysgen_dut_to_register24_data_in,
4012
      o => from_register24_data_out_x0
4013
    );
4014
 
4015
  register10td_ce_and2_comp: entity work.xland2
4016
    port map (
4017
      a => sysgen_dut_to_register24_ce,
4018
      b => sysgen_dut_to_register24_en,
4019
      dout => register10td_reg_ce
4020
    );
4021
 
4022
  register10tv: entity work.synth_reg_w_init
4023
    generic map (
4024
      width => 1,
4025
      init_index => 2,
4026
      init_value => b"0",
4027
      latency => 1
4028
    )
4029
    port map (
4030
      ce => register10tv_reg_ce,
4031
      clk => sysgen_dut_to_register23_clk,
4032
      clr => sysgen_dut_to_register23_clr,
4033
      i(0) => sysgen_dut_to_register23_data_in,
4034
      o(0) => from_register25_data_out_x0
4035
    );
4036
 
4037
  register10tv_ce_and2_comp: entity work.xland2
4038
    port map (
4039
      a => sysgen_dut_to_register23_ce,
4040
      b => sysgen_dut_to_register23_en,
4041
      dout => register10tv_reg_ce
4042
    );
4043
 
4044
  register11rd: entity work.synth_reg_w_init
4045
    generic map (
4046
      width => 32,
4047
      init_index => 2,
4048
      init_value => b"00000000000000000000000000000000",
4049
      latency => 1
4050
    )
4051
    port map (
4052
      ce => register11rd_reg_ce,
4053
      clk => sysgen_dut_to_register21_clk_x0,
4054
      clr => sysgen_dut_to_register21_clr_x0,
4055
      i => sysgen_dut_to_register21_data_in_x0,
4056
      o => from_register21_data_out
4057
    );
4058
 
4059
  register11rd_ce_and2_comp: entity work.xland2
4060
    port map (
4061
      a => sysgen_dut_to_register21_ce_x0,
4062
      b => sysgen_dut_to_register21_en_x0,
4063
      dout => register11rd_reg_ce
4064
    );
4065
 
4066
  register11rv: entity work.synth_reg_w_init
4067
    generic map (
4068
      width => 1,
4069
      init_index => 2,
4070
      init_value => b"0",
4071
      latency => 1
4072
    )
4073
    port map (
4074
      ce => register11rv_reg_ce,
4075
      clk => sysgen_dut_to_register20_clk_x0,
4076
      clr => sysgen_dut_to_register20_clr_x0,
4077
      i(0) => sysgen_dut_to_register20_data_in_x0,
4078
      o(0) => from_register22_data_out
4079
    );
4080
 
4081
  register11rv_ce_and2_comp: entity work.xland2
4082
    port map (
4083
      a => sysgen_dut_to_register20_ce_x0,
4084
      b => sysgen_dut_to_register20_en_x0,
4085
      dout => register11rv_reg_ce
4086
    );
4087
 
4088
  register11td: entity work.synth_reg_w_init
4089
    generic map (
4090
      width => 32,
4091
      init_index => 2,
4092
      init_value => b"00000000000000000000000000000000",
4093
      latency => 1
4094
    )
4095
    port map (
4096
      ce => register11td_reg_ce,
4097
      clk => sysgen_dut_to_register28_clk,
4098
      clr => sysgen_dut_to_register28_clr,
4099
      i => sysgen_dut_to_register28_data_in,
4100
      o => from_register26_data_out_x0
4101
    );
4102
 
4103
  register11td_ce_and2_comp: entity work.xland2
4104
    port map (
4105
      a => sysgen_dut_to_register28_ce,
4106
      b => sysgen_dut_to_register28_en,
4107
      dout => register11td_reg_ce
4108
    );
4109
 
4110
  register11tv: entity work.synth_reg_w_init
4111
    generic map (
4112
      width => 1,
4113
      init_index => 2,
4114
      init_value => b"0",
4115
      latency => 1
4116
    )
4117
    port map (
4118
      ce => register11tv_reg_ce,
4119
      clk => sysgen_dut_to_register27_clk,
4120
      clr => sysgen_dut_to_register27_clr,
4121
      i(0) => sysgen_dut_to_register27_data_in,
4122
      o(0) => from_register27_data_out_x0
4123
    );
4124
 
4125
  register11tv_ce_and2_comp: entity work.xland2
4126
    port map (
4127
      a => sysgen_dut_to_register27_ce,
4128
      b => sysgen_dut_to_register27_en,
4129
      dout => register11tv_reg_ce
4130
    );
4131
 
4132
  register12rd: entity work.synth_reg_w_init
4133
    generic map (
4134
      width => 32,
4135
      init_index => 2,
4136
      init_value => b"00000000000000000000000000000000",
4137
      latency => 1
4138
    )
4139
    port map (
4140
      ce => register12rd_reg_ce,
4141
      clk => sysgen_dut_to_register23_clk_x0,
4142
      clr => sysgen_dut_to_register23_clr_x0,
4143
      i => sysgen_dut_to_register23_data_in_x0,
4144
      o => from_register23_data_out
4145
    );
4146
 
4147
  register12rd_ce_and2_comp: entity work.xland2
4148
    port map (
4149
      a => sysgen_dut_to_register23_ce_x0,
4150
      b => sysgen_dut_to_register23_en_x0,
4151
      dout => register12rd_reg_ce
4152
    );
4153
 
4154
  register12rv: entity work.synth_reg_w_init
4155
    generic map (
4156
      width => 1,
4157
      init_index => 2,
4158
      init_value => b"0",
4159
      latency => 1
4160
    )
4161
    port map (
4162
      ce => register12rv_reg_ce,
4163
      clk => sysgen_dut_to_register22_clk_x0,
4164
      clr => sysgen_dut_to_register22_clr_x0,
4165
      i(0) => sysgen_dut_to_register22_data_in_x0,
4166
      o(0) => from_register24_data_out
4167
    );
4168
 
4169
  register12rv_ce_and2_comp: entity work.xland2
4170
    port map (
4171
      a => sysgen_dut_to_register22_ce_x0,
4172
      b => sysgen_dut_to_register22_en_x0,
4173
      dout => register12rv_reg_ce
4174
    );
4175
 
4176
  register12td: entity work.synth_reg_w_init
4177
    generic map (
4178
      width => 32,
4179
      init_index => 2,
4180
      init_value => b"00000000000000000000000000000000",
4181
      latency => 1
4182
    )
4183
    port map (
4184
      ce => register12td_reg_ce,
4185
      clk => sysgen_dut_to_register30_clk,
4186
      clr => sysgen_dut_to_register30_clr,
4187
      i => sysgen_dut_to_register30_data_in,
4188
      o => from_register28_data_out_x0
4189
    );
4190
 
4191
  register12td_ce_and2_comp: entity work.xland2
4192
    port map (
4193
      a => sysgen_dut_to_register30_ce,
4194
      b => sysgen_dut_to_register30_en,
4195
      dout => register12td_reg_ce
4196
    );
4197
 
4198
  register12tv: entity work.synth_reg_w_init
4199
    generic map (
4200
      width => 1,
4201
      init_index => 2,
4202
      init_value => b"0",
4203
      latency => 1
4204
    )
4205
    port map (
4206
      ce => register12tv_reg_ce,
4207
      clk => sysgen_dut_to_register29_clk,
4208
      clr => sysgen_dut_to_register29_clr,
4209
      i(0) => sysgen_dut_to_register29_data_in,
4210
      o(0) => from_register29_data_out
4211
    );
4212
 
4213
  register12tv_ce_and2_comp: entity work.xland2
4214
    port map (
4215
      a => sysgen_dut_to_register29_ce,
4216
      b => sysgen_dut_to_register29_en,
4217
      dout => register12tv_reg_ce
4218
    );
4219
 
4220
  register13rd: entity work.synth_reg_w_init
4221
    generic map (
4222
      width => 32,
4223
      init_index => 2,
4224
      init_value => b"00000000000000000000000000000000",
4225
      latency => 1
4226
    )
4227
    port map (
4228
      ce => register13rd_reg_ce,
4229
      clk => sysgen_dut_to_register25_clk_x0,
4230
      clr => sysgen_dut_to_register25_clr_x0,
4231
      i => sysgen_dut_to_register25_data_in_x0,
4232
      o => from_register25_data_out
4233
    );
4234
 
4235
  register13rd_ce_and2_comp: entity work.xland2
4236
    port map (
4237
      a => sysgen_dut_to_register25_ce_x0,
4238
      b => sysgen_dut_to_register25_en_x0,
4239
      dout => register13rd_reg_ce
4240
    );
4241
 
4242
  register13rv: entity work.synth_reg_w_init
4243
    generic map (
4244
      width => 1,
4245
      init_index => 2,
4246
      init_value => b"0",
4247
      latency => 1
4248
    )
4249
    port map (
4250
      ce => register13rv_reg_ce,
4251
      clk => sysgen_dut_to_register24_clk_x0,
4252
      clr => sysgen_dut_to_register24_clr_x0,
4253
      i(0) => sysgen_dut_to_register24_data_in_x0,
4254
      o(0) => from_register26_data_out
4255
    );
4256
 
4257
  register13rv_ce_and2_comp: entity work.xland2
4258
    port map (
4259
      a => sysgen_dut_to_register24_ce_x0,
4260
      b => sysgen_dut_to_register24_en_x0,
4261
      dout => register13rv_reg_ce
4262
    );
4263
 
4264
  register13td: entity work.synth_reg_w_init
4265
    generic map (
4266
      width => 32,
4267
      init_index => 2,
4268
      init_value => b"00000000000000000000000000000000",
4269
      latency => 1
4270
    )
4271
    port map (
4272
      ce => register13td_reg_ce,
4273
      clk => sysgen_dut_to_register32_clk,
4274
      clr => sysgen_dut_to_register32_clr,
4275
      i => sysgen_dut_to_register32_data_in,
4276
      o => from_register30_data_out
4277
    );
4278
 
4279
  register13td_ce_and2_comp: entity work.xland2
4280
    port map (
4281
      a => sysgen_dut_to_register32_ce,
4282
      b => sysgen_dut_to_register32_en,
4283
      dout => register13td_reg_ce
4284
    );
4285
 
4286
  register13tv: entity work.synth_reg_w_init
4287
    generic map (
4288
      width => 1,
4289
      init_index => 2,
4290
      init_value => b"0",
4291
      latency => 1
4292
    )
4293
    port map (
4294
      ce => register13tv_reg_ce,
4295
      clk => sysgen_dut_to_register31_clk,
4296
      clr => sysgen_dut_to_register31_clr,
4297
      i(0) => sysgen_dut_to_register31_data_in,
4298
      o(0) => from_register31_data_out
4299
    );
4300
 
4301
  register13tv_ce_and2_comp: entity work.xland2
4302
    port map (
4303
      a => sysgen_dut_to_register31_ce,
4304
      b => sysgen_dut_to_register31_en,
4305
      dout => register13tv_reg_ce
4306
    );
4307
 
4308
  register14rd: entity work.synth_reg_w_init
4309
    generic map (
4310
      width => 32,
4311
      init_index => 2,
4312
      init_value => b"00000000000000000000000000000000",
4313
      latency => 1
4314
    )
4315
    port map (
4316
      ce => register14rd_reg_ce,
4317
      clk => sysgen_dut_to_register27_clk_x0,
4318
      clr => sysgen_dut_to_register27_clr_x0,
4319
      i => sysgen_dut_to_register27_data_in_x0,
4320
      o => from_register27_data_out
4321
    );
4322
 
4323
  register14rd_ce_and2_comp: entity work.xland2
4324
    port map (
4325
      a => sysgen_dut_to_register27_ce_x0,
4326
      b => sysgen_dut_to_register27_en_x0,
4327
      dout => register14rd_reg_ce
4328
    );
4329
 
4330
  register14rv: entity work.synth_reg_w_init
4331
    generic map (
4332
      width => 1,
4333
      init_index => 2,
4334
      init_value => b"0",
4335
      latency => 1
4336
    )
4337
    port map (
4338
      ce => register14rv_reg_ce,
4339
      clk => sysgen_dut_to_register26_clk_x0,
4340
      clr => sysgen_dut_to_register26_clr_x0,
4341
      i(0) => sysgen_dut_to_register26_data_in_x0,
4342
      o(0) => from_register28_data_out
4343
    );
4344
 
4345
  register14rv_ce_and2_comp: entity work.xland2
4346
    port map (
4347
      a => sysgen_dut_to_register26_ce_x0,
4348
      b => sysgen_dut_to_register26_en_x0,
4349
      dout => register14rv_reg_ce
4350
    );
4351
 
4352
  register14td: entity work.synth_reg_w_init
4353
    generic map (
4354
      width => 32,
4355
      init_index => 2,
4356
      init_value => b"00000000000000000000000000000000",
4357
      latency => 1
4358
    )
4359
    port map (
4360
      ce => register14td_reg_ce,
4361
      clk => sysgen_dut_to_register34_clk,
4362
      clr => sysgen_dut_to_register34_clr,
4363
      i => sysgen_dut_to_register34_data_in,
4364
      o => from_register32_data_out
4365
    );
4366
 
4367
  register14td_ce_and2_comp: entity work.xland2
4368
    port map (
4369
      a => sysgen_dut_to_register34_ce,
4370
      b => sysgen_dut_to_register34_en,
4371
      dout => register14td_reg_ce
4372
    );
4373
 
4374
  register14tv: entity work.synth_reg_w_init
4375
    generic map (
4376
      width => 1,
4377
      init_index => 2,
4378
      init_value => b"0",
4379
      latency => 1
4380
    )
4381
    port map (
4382
      ce => register14tv_reg_ce,
4383
      clk => sysgen_dut_to_register33_clk,
4384
      clr => sysgen_dut_to_register33_clr,
4385
      i(0) => sysgen_dut_to_register33_data_in,
4386
      o(0) => from_register33_data_out
4387
    );
4388
 
4389
  register14tv_ce_and2_comp: entity work.xland2
4390
    port map (
4391
      a => sysgen_dut_to_register33_ce,
4392
      b => sysgen_dut_to_register33_en,
4393
      dout => register14tv_reg_ce
4394
    );
4395
 
4396
  top_level_0: inout_logic_cw
4397
    port map (
4398
      ce => x,
4399
      clk => x_x0,
4400
      debug_in_1i => x_x1,
4401
      debug_in_2i => x_x2,
4402
      debug_in_3i => x_x3,
4403
      debug_in_4i => x_x4,
4404
      dma_host2board_busy => x_x5,
4405
      dma_host2board_done => x_x6,
4406
      from_register10_data_out => from_register10_data_out,
4407
      from_register11_data_out => from_register11_data_out,
4408
      from_register12_data_out(0) => from_register12_data_out,
4409
      from_register13_data_out => from_register13_data_out,
4410
      from_register14_data_out(0) => from_register14_data_out,
4411
      from_register15_data_out => from_register15_data_out,
4412
      from_register16_data_out(0) => from_register16_data_out,
4413
      from_register17_data_out => from_register17_data_out,
4414
      from_register18_data_out(0) => from_register18_data_out,
4415
      from_register19_data_out => from_register19_data_out,
4416
      from_register1_data_out(0) => from_register1_data_out,
4417
      from_register20_data_out(0) => from_register20_data_out,
4418
      from_register21_data_out => from_register21_data_out,
4419
      from_register22_data_out(0) => from_register22_data_out,
4420
      from_register23_data_out => from_register23_data_out,
4421
      from_register24_data_out(0) => from_register24_data_out,
4422
      from_register25_data_out => from_register25_data_out,
4423
      from_register26_data_out(0) => from_register26_data_out,
4424
      from_register27_data_out => from_register27_data_out,
4425
      from_register28_data_out(0) => from_register28_data_out,
4426
      from_register2_data_out(0) => from_register2_data_out,
4427
      from_register3_data_out => from_register3_data_out,
4428
      from_register4_data_out(0) => from_register4_data_out,
4429
      from_register5_data_out => from_register5_data_out,
4430
      from_register6_data_out(0) => from_register6_data_out,
4431
      from_register7_data_out => from_register7_data_out,
4432
      from_register8_data_out => from_register8_data_out,
4433
      from_register9_data_out(0) => from_register9_data_out,
4434
      reg01_td => x_x9,
4435
      reg01_tv => x_x10,
4436
      reg02_td => x_x13,
4437
      reg02_tv => x_x14,
4438
      reg03_td => x_x17,
4439
      reg03_tv => x_x18,
4440
      reg04_td => x_x21,
4441
      reg04_tv => x_x22,
4442
      reg05_td => x_x25,
4443
      reg05_tv => x_x26,
4444
      reg06_td => x_x29,
4445
      reg06_tv => x_x30,
4446
      reg07_td => x_x33,
4447
      reg07_tv => x_x34,
4448
      reg08_td => x_x37,
4449
      reg08_tv => x_x38,
4450
      reg09_td => x_x41,
4451
      reg09_tv => x_x42,
4452
      reg10_td => x_x45,
4453
      reg10_tv => x_x46,
4454
      reg11_td => x_x49,
4455
      reg11_tv => x_x50,
4456
      reg12_td => x_x53,
4457
      reg12_tv => x_x54,
4458
      reg13_td => x_x57,
4459
      reg13_tv => x_x58,
4460
      reg14_td => x_x61,
4461
      reg14_tv => x_x62,
4462
      to_register10_dout(0) => from_register10_data_out_x0,
4463
      to_register11_dout => from_register9_data_out_x0,
4464
      to_register12_dout(0) => from_register12_data_out_x0,
4465
      to_register13_dout => from_register11_data_out_x0,
4466
      to_register14_dout(0) => from_register14_data_out_x0,
4467
      to_register15_dout => from_register13_data_out_x0,
4468
      to_register16_dout(0) => from_register18_data_out_x0,
4469
      to_register17_dout => from_register17_data_out_x0,
4470
      to_register18_dout(0) => from_register16_data_out_x0,
4471
      to_register19_dout(0) => from_register15_data_out_x0,
4472
      to_register1_dout => from_register1_data_out_x0,
4473
      to_register20_dout => from_register19_data_out_x0,
4474
      to_register21_dout(0) => from_register23_data_out_x0,
4475
      to_register22_dout => from_register22_data_out_x0,
4476
      to_register23_dout(0) => from_register25_data_out_x0,
4477
      to_register24_dout => from_register24_data_out_x0,
4478
      to_register25_dout(0) => from_register21_data_out_x0,
4479
      to_register26_dout => from_register20_data_out_x0,
4480
      to_register27_dout(0) => from_register27_data_out_x0,
4481
      to_register28_dout => from_register26_data_out_x0,
4482
      to_register29_dout(0) => from_register29_data_out,
4483
      to_register2_dout => from_register2_data_out_x0,
4484
      to_register30_dout => from_register28_data_out_x0,
4485
      to_register31_dout(0) => from_register31_data_out,
4486
      to_register32_dout => from_register30_data_out,
4487
      to_register33_dout(0) => from_register33_data_out,
4488
      to_register34_dout => from_register32_data_out,
4489
      to_register3_dout(0) => from_register4_data_out_x0,
4490
      to_register4_dout(0) => from_register6_data_out_x0,
4491
      to_register5_dout => from_register5_data_out_x0,
4492
      to_register6_dout => from_register_data_out,
4493
      to_register7_dout => from_register3_data_out_x0,
4494
      to_register8_dout(0) => from_register8_data_out_x0,
4495
      to_register9_dout => from_register7_data_out_x0,
4496
      reg01_rd => x_x7,
4497
      reg01_rv => x_x8,
4498
      reg02_rd => x_x11,
4499
      reg02_rv => x_x12,
4500
      reg03_rd => x_x15,
4501
      reg03_rv => x_x16,
4502
      reg04_rd => x_x19,
4503
      reg04_rv => x_x20,
4504
      reg05_rd => x_x23,
4505
      reg05_rv => x_x24,
4506
      reg06_rd => x_x27,
4507
      reg06_rv => x_x28,
4508
      reg07_rd => x_x31,
4509
      reg07_rv => x_x32,
4510
      reg08_rd => x_x35,
4511
      reg08_rv => x_x36,
4512
      reg09_rd => x_x39,
4513
      reg09_rv => x_x40,
4514
      reg10_rd => x_x43,
4515
      reg10_rv => x_x44,
4516
      reg11_rd => x_x47,
4517
      reg11_rv => x_x48,
4518
      reg12_rd => x_x51,
4519
      reg12_rv => x_x52,
4520
      reg13_rd => x_x55,
4521
      reg13_rv => x_x56,
4522
      reg14_rd => x_x59,
4523
      reg14_rv => x_x60,
4524
      to_register10_ce => sysgen_dut_to_register10_ce,
4525
      to_register10_clk => sysgen_dut_to_register10_clk,
4526
      to_register10_clr => sysgen_dut_to_register10_clr,
4527
      to_register10_data_in(0) => sysgen_dut_to_register10_data_in,
4528
      to_register10_en(0) => sysgen_dut_to_register10_en,
4529
      to_register11_ce => sysgen_dut_to_register11_ce,
4530
      to_register11_clk => sysgen_dut_to_register11_clk,
4531
      to_register11_clr => sysgen_dut_to_register11_clr,
4532
      to_register11_data_in => sysgen_dut_to_register11_data_in,
4533
      to_register11_en(0) => sysgen_dut_to_register11_en,
4534
      to_register12_ce => sysgen_dut_to_register12_ce,
4535
      to_register12_clk => sysgen_dut_to_register12_clk,
4536
      to_register12_clr => sysgen_dut_to_register12_clr,
4537
      to_register12_data_in(0) => sysgen_dut_to_register12_data_in,
4538
      to_register12_en(0) => sysgen_dut_to_register12_en,
4539
      to_register13_ce => sysgen_dut_to_register13_ce,
4540
      to_register13_clk => sysgen_dut_to_register13_clk,
4541
      to_register13_clr => sysgen_dut_to_register13_clr,
4542
      to_register13_data_in => sysgen_dut_to_register13_data_in,
4543
      to_register13_en(0) => sysgen_dut_to_register13_en,
4544
      to_register14_ce => sysgen_dut_to_register14_ce,
4545
      to_register14_clk => sysgen_dut_to_register14_clk,
4546
      to_register14_clr => sysgen_dut_to_register14_clr,
4547
      to_register14_data_in(0) => sysgen_dut_to_register14_data_in,
4548
      to_register14_en(0) => sysgen_dut_to_register14_en,
4549
      to_register15_ce => sysgen_dut_to_register15_ce,
4550
      to_register15_clk => sysgen_dut_to_register15_clk,
4551
      to_register15_clr => sysgen_dut_to_register15_clr,
4552
      to_register15_data_in => sysgen_dut_to_register15_data_in,
4553
      to_register15_en(0) => sysgen_dut_to_register15_en,
4554
      to_register16_ce => sysgen_dut_to_register16_ce,
4555
      to_register16_clk => sysgen_dut_to_register16_clk,
4556
      to_register16_clr => sysgen_dut_to_register16_clr,
4557
      to_register16_data_in(0) => sysgen_dut_to_register16_data_in,
4558
      to_register16_en(0) => sysgen_dut_to_register16_en,
4559
      to_register17_ce => sysgen_dut_to_register17_ce,
4560
      to_register17_clk => sysgen_dut_to_register17_clk,
4561
      to_register17_clr => sysgen_dut_to_register17_clr,
4562
      to_register17_data_in => sysgen_dut_to_register17_data_in,
4563
      to_register17_en(0) => sysgen_dut_to_register17_en,
4564
      to_register18_ce => sysgen_dut_to_register18_ce,
4565
      to_register18_clk => sysgen_dut_to_register18_clk,
4566
      to_register18_clr => sysgen_dut_to_register18_clr,
4567
      to_register18_data_in(0) => sysgen_dut_to_register18_data_in,
4568
      to_register18_en(0) => sysgen_dut_to_register18_en,
4569
      to_register19_ce => sysgen_dut_to_register19_ce,
4570
      to_register19_clk => sysgen_dut_to_register19_clk,
4571
      to_register19_clr => sysgen_dut_to_register19_clr,
4572
      to_register19_data_in(0) => sysgen_dut_to_register19_data_in,
4573
      to_register19_en(0) => sysgen_dut_to_register19_en,
4574
      to_register1_ce => sysgen_dut_to_register1_ce,
4575
      to_register1_clk => sysgen_dut_to_register1_clk,
4576
      to_register1_clr => sysgen_dut_to_register1_clr,
4577
      to_register1_data_in => sysgen_dut_to_register1_data_in,
4578
      to_register1_en(0) => sysgen_dut_to_register1_en,
4579
      to_register20_ce => sysgen_dut_to_register20_ce,
4580
      to_register20_clk => sysgen_dut_to_register20_clk,
4581
      to_register20_clr => sysgen_dut_to_register20_clr,
4582
      to_register20_data_in => sysgen_dut_to_register20_data_in,
4583
      to_register20_en(0) => sysgen_dut_to_register20_en,
4584
      to_register21_ce => sysgen_dut_to_register21_ce,
4585
      to_register21_clk => sysgen_dut_to_register21_clk,
4586
      to_register21_clr => sysgen_dut_to_register21_clr,
4587
      to_register21_data_in(0) => sysgen_dut_to_register21_data_in,
4588
      to_register21_en(0) => sysgen_dut_to_register21_en,
4589
      to_register22_ce => sysgen_dut_to_register22_ce,
4590
      to_register22_clk => sysgen_dut_to_register22_clk,
4591
      to_register22_clr => sysgen_dut_to_register22_clr,
4592
      to_register22_data_in => sysgen_dut_to_register22_data_in,
4593
      to_register22_en(0) => sysgen_dut_to_register22_en,
4594
      to_register23_ce => sysgen_dut_to_register23_ce,
4595
      to_register23_clk => sysgen_dut_to_register23_clk,
4596
      to_register23_clr => sysgen_dut_to_register23_clr,
4597
      to_register23_data_in(0) => sysgen_dut_to_register23_data_in,
4598
      to_register23_en(0) => sysgen_dut_to_register23_en,
4599
      to_register24_ce => sysgen_dut_to_register24_ce,
4600
      to_register24_clk => sysgen_dut_to_register24_clk,
4601
      to_register24_clr => sysgen_dut_to_register24_clr,
4602
      to_register24_data_in => sysgen_dut_to_register24_data_in,
4603
      to_register24_en(0) => sysgen_dut_to_register24_en,
4604
      to_register25_ce => sysgen_dut_to_register25_ce,
4605
      to_register25_clk => sysgen_dut_to_register25_clk,
4606
      to_register25_clr => sysgen_dut_to_register25_clr,
4607
      to_register25_data_in(0) => sysgen_dut_to_register25_data_in,
4608
      to_register25_en(0) => sysgen_dut_to_register25_en,
4609
      to_register26_ce => sysgen_dut_to_register26_ce,
4610
      to_register26_clk => sysgen_dut_to_register26_clk,
4611
      to_register26_clr => sysgen_dut_to_register26_clr,
4612
      to_register26_data_in => sysgen_dut_to_register26_data_in,
4613
      to_register26_en(0) => sysgen_dut_to_register26_en,
4614
      to_register27_ce => sysgen_dut_to_register27_ce,
4615
      to_register27_clk => sysgen_dut_to_register27_clk,
4616
      to_register27_clr => sysgen_dut_to_register27_clr,
4617
      to_register27_data_in(0) => sysgen_dut_to_register27_data_in,
4618
      to_register27_en(0) => sysgen_dut_to_register27_en,
4619
      to_register28_ce => sysgen_dut_to_register28_ce,
4620
      to_register28_clk => sysgen_dut_to_register28_clk,
4621
      to_register28_clr => sysgen_dut_to_register28_clr,
4622
      to_register28_data_in => sysgen_dut_to_register28_data_in,
4623
      to_register28_en(0) => sysgen_dut_to_register28_en,
4624
      to_register29_ce => sysgen_dut_to_register29_ce,
4625
      to_register29_clk => sysgen_dut_to_register29_clk,
4626
      to_register29_clr => sysgen_dut_to_register29_clr,
4627
      to_register29_data_in(0) => sysgen_dut_to_register29_data_in,
4628
      to_register29_en(0) => sysgen_dut_to_register29_en,
4629
      to_register2_ce => sysgen_dut_to_register2_ce,
4630
      to_register2_clk => sysgen_dut_to_register2_clk,
4631
      to_register2_clr => sysgen_dut_to_register2_clr,
4632
      to_register2_data_in => sysgen_dut_to_register2_data_in,
4633
      to_register2_en(0) => sysgen_dut_to_register2_en,
4634
      to_register30_ce => sysgen_dut_to_register30_ce,
4635
      to_register30_clk => sysgen_dut_to_register30_clk,
4636
      to_register30_clr => sysgen_dut_to_register30_clr,
4637
      to_register30_data_in => sysgen_dut_to_register30_data_in,
4638
      to_register30_en(0) => sysgen_dut_to_register30_en,
4639
      to_register31_ce => sysgen_dut_to_register31_ce,
4640
      to_register31_clk => sysgen_dut_to_register31_clk,
4641
      to_register31_clr => sysgen_dut_to_register31_clr,
4642
      to_register31_data_in(0) => sysgen_dut_to_register31_data_in,
4643
      to_register31_en(0) => sysgen_dut_to_register31_en,
4644
      to_register32_ce => sysgen_dut_to_register32_ce,
4645
      to_register32_clk => sysgen_dut_to_register32_clk,
4646
      to_register32_clr => sysgen_dut_to_register32_clr,
4647
      to_register32_data_in => sysgen_dut_to_register32_data_in,
4648
      to_register32_en(0) => sysgen_dut_to_register32_en,
4649
      to_register33_ce => sysgen_dut_to_register33_ce,
4650
      to_register33_clk => sysgen_dut_to_register33_clk,
4651
      to_register33_clr => sysgen_dut_to_register33_clr,
4652
      to_register33_data_in(0) => sysgen_dut_to_register33_data_in,
4653
      to_register33_en(0) => sysgen_dut_to_register33_en,
4654
      to_register34_ce => sysgen_dut_to_register34_ce,
4655
      to_register34_clk => sysgen_dut_to_register34_clk,
4656
      to_register34_clr => sysgen_dut_to_register34_clr,
4657
      to_register34_data_in => sysgen_dut_to_register34_data_in,
4658
      to_register34_en(0) => sysgen_dut_to_register34_en,
4659
      to_register3_ce => sysgen_dut_to_register3_ce,
4660
      to_register3_clk => sysgen_dut_to_register3_clk,
4661
      to_register3_clr => sysgen_dut_to_register3_clr,
4662
      to_register3_data_in(0) => sysgen_dut_to_register3_data_in,
4663
      to_register3_en(0) => sysgen_dut_to_register3_en,
4664
      to_register4_ce => sysgen_dut_to_register4_ce,
4665
      to_register4_clk => sysgen_dut_to_register4_clk,
4666
      to_register4_clr => sysgen_dut_to_register4_clr,
4667
      to_register4_data_in(0) => sysgen_dut_to_register4_data_in,
4668
      to_register4_en(0) => sysgen_dut_to_register4_en,
4669
      to_register5_ce => sysgen_dut_to_register5_ce,
4670
      to_register5_clk => sysgen_dut_to_register5_clk,
4671
      to_register5_clr => sysgen_dut_to_register5_clr,
4672
      to_register5_data_in => sysgen_dut_to_register5_data_in,
4673
      to_register5_en(0) => sysgen_dut_to_register5_en,
4674
      to_register6_ce => sysgen_dut_to_register6_ce,
4675
      to_register6_clk => sysgen_dut_to_register6_clk,
4676
      to_register6_clr => sysgen_dut_to_register6_clr,
4677
      to_register6_data_in => sysgen_dut_to_register6_data_in,
4678
      to_register6_en(0) => sysgen_dut_to_register6_en,
4679
      to_register7_ce => sysgen_dut_to_register7_ce,
4680
      to_register7_clk => sysgen_dut_to_register7_clk,
4681
      to_register7_clr => sysgen_dut_to_register7_clr,
4682
      to_register7_data_in => sysgen_dut_to_register7_data_in,
4683
      to_register7_en(0) => sysgen_dut_to_register7_en,
4684
      to_register8_ce => sysgen_dut_to_register8_ce,
4685
      to_register8_clk => sysgen_dut_to_register8_clk,
4686
      to_register8_clr => sysgen_dut_to_register8_clr,
4687
      to_register8_data_in(0) => sysgen_dut_to_register8_data_in,
4688
      to_register8_en(0) => sysgen_dut_to_register8_en,
4689
      to_register9_ce => sysgen_dut_to_register9_ce,
4690
      to_register9_clk => sysgen_dut_to_register9_clk,
4691
      to_register9_clr => sysgen_dut_to_register9_clr,
4692
      to_register9_data_in => sysgen_dut_to_register9_data_in,
4693
      to_register9_en(0) => sysgen_dut_to_register9_en
4694
    );
4695
 
4696
  top_level_1: user_logic_cw
4697
    port map (
4698
      bram_rd_dout => x_x64,
4699
      ce => x_x68,
4700
      clk => x_x69,
4701
      fifo_rd_count => x_x70,
4702
      fifo_rd_dout => x_x71,
4703
      fifo_rd_empty => x_x72,
4704
      fifo_rd_pempty => x_x74,
4705
      fifo_rd_valid => x_x75,
4706
      fifo_wr_count => x_x76,
4707
      fifo_wr_full => x_x79,
4708
      fifo_wr_pfull => x_x80,
4709
      from_register10_data_out(0) => from_register10_data_out_x0,
4710
      from_register11_data_out => from_register11_data_out_x0,
4711
      from_register12_data_out(0) => from_register12_data_out_x0,
4712
      from_register13_data_out => from_register13_data_out_x0,
4713
      from_register14_data_out(0) => from_register14_data_out_x0,
4714
      from_register15_data_out(0) => from_register15_data_out_x0,
4715
      from_register16_data_out(0) => from_register16_data_out_x0,
4716
      from_register17_data_out => from_register17_data_out_x0,
4717
      from_register18_data_out(0) => from_register18_data_out_x0,
4718
      from_register19_data_out => from_register19_data_out_x0,
4719
      from_register1_data_out => from_register1_data_out_x0,
4720
      from_register20_data_out => from_register20_data_out_x0,
4721
      from_register21_data_out(0) => from_register21_data_out_x0,
4722
      from_register22_data_out => from_register22_data_out_x0,
4723
      from_register23_data_out(0) => from_register23_data_out_x0,
4724
      from_register24_data_out => from_register24_data_out_x0,
4725
      from_register25_data_out(0) => from_register25_data_out_x0,
4726
      from_register26_data_out => from_register26_data_out_x0,
4727
      from_register27_data_out(0) => from_register27_data_out_x0,
4728
      from_register28_data_out => from_register28_data_out_x0,
4729
      from_register29_data_out(0) => from_register29_data_out,
4730
      from_register2_data_out => from_register2_data_out_x0,
4731
      from_register30_data_out => from_register30_data_out,
4732
      from_register31_data_out(0) => from_register31_data_out,
4733
      from_register32_data_out => from_register32_data_out,
4734
      from_register33_data_out(0) => from_register33_data_out,
4735
      from_register3_data_out => from_register3_data_out_x0,
4736
      from_register4_data_out(0) => from_register4_data_out_x0,
4737
      from_register5_data_out => from_register5_data_out_x0,
4738
      from_register6_data_out(0) => from_register6_data_out_x0,
4739
      from_register7_data_out => from_register7_data_out_x0,
4740
      from_register8_data_out(0) => from_register8_data_out_x0,
4741
      from_register9_data_out => from_register9_data_out_x0,
4742
      from_register_data_out => from_register_data_out,
4743
      rst_i => x_x81,
4744
      to_register10_dout(0) => from_register9_data_out,
4745
      to_register11_dout(0) => from_register12_data_out,
4746
      to_register12_dout(0) => from_register14_data_out,
4747
      to_register13_dout => from_register13_data_out,
4748
      to_register14_dout(0) => from_register16_data_out,
4749
      to_register15_dout => from_register15_data_out,
4750
      to_register16_dout(0) => from_register18_data_out,
4751
      to_register17_dout => from_register17_data_out,
4752
      to_register18_dout(0) => from_register20_data_out,
4753
      to_register19_dout => from_register19_data_out,
4754
      to_register1_dout(0) => from_register1_data_out,
4755
      to_register20_dout(0) => from_register22_data_out,
4756
      to_register21_dout => from_register21_data_out,
4757
      to_register22_dout(0) => from_register24_data_out,
4758
      to_register23_dout => from_register23_data_out,
4759
      to_register24_dout(0) => from_register26_data_out,
4760
      to_register25_dout => from_register25_data_out,
4761
      to_register26_dout(0) => from_register28_data_out,
4762
      to_register27_dout => from_register27_data_out,
4763
      to_register2_dout => from_register5_data_out,
4764
      to_register3_dout => from_register7_data_out,
4765
      to_register4_dout(0) => from_register2_data_out,
4766
      to_register5_dout(0) => from_register6_data_out,
4767
      to_register6_dout => from_register8_data_out,
4768
      to_register7_dout(0) => from_register4_data_out,
4769
      to_register8_dout => from_register10_data_out,
4770
      to_register9_dout => from_register11_data_out,
4771
      to_register_dout => from_register3_data_out,
4772
      bram_rd_addr => x_x63,
4773
      bram_wr_addr => x_x65,
4774
      bram_wr_din => x_x66,
4775
      bram_wr_en => x_x67,
4776
      fifo_rd_en => x_x73,
4777
      fifo_wr_din => x_x77,
4778
      fifo_wr_en => x_x78,
4779
      rst_o => x_x82,
4780
      to_register10_ce => sysgen_dut_to_register10_ce_x0,
4781
      to_register10_clk => sysgen_dut_to_register10_clk_x0,
4782
      to_register10_clr => sysgen_dut_to_register10_clr_x0,
4783
      to_register10_data_in(0) => sysgen_dut_to_register10_data_in_x0,
4784
      to_register10_en(0) => sysgen_dut_to_register10_en_x0,
4785
      to_register11_ce => sysgen_dut_to_register11_ce_x0,
4786
      to_register11_clk => sysgen_dut_to_register11_clk_x0,
4787
      to_register11_clr => sysgen_dut_to_register11_clr_x0,
4788
      to_register11_data_in(0) => sysgen_dut_to_register11_data_in_x0,
4789
      to_register11_en(0) => sysgen_dut_to_register11_en_x0,
4790
      to_register12_ce => sysgen_dut_to_register12_ce_x0,
4791
      to_register12_clk => sysgen_dut_to_register12_clk_x0,
4792
      to_register12_clr => sysgen_dut_to_register12_clr_x0,
4793
      to_register12_data_in(0) => sysgen_dut_to_register12_data_in_x0,
4794
      to_register12_en(0) => sysgen_dut_to_register12_en_x0,
4795
      to_register13_ce => sysgen_dut_to_register13_ce_x0,
4796
      to_register13_clk => sysgen_dut_to_register13_clk_x0,
4797
      to_register13_clr => sysgen_dut_to_register13_clr_x0,
4798
      to_register13_data_in => sysgen_dut_to_register13_data_in_x0,
4799
      to_register13_en(0) => sysgen_dut_to_register13_en_x0,
4800
      to_register14_ce => sysgen_dut_to_register14_ce_x0,
4801
      to_register14_clk => sysgen_dut_to_register14_clk_x0,
4802
      to_register14_clr => sysgen_dut_to_register14_clr_x0,
4803
      to_register14_data_in(0) => sysgen_dut_to_register14_data_in_x0,
4804
      to_register14_en(0) => sysgen_dut_to_register14_en_x0,
4805
      to_register15_ce => sysgen_dut_to_register15_ce_x0,
4806
      to_register15_clk => sysgen_dut_to_register15_clk_x0,
4807
      to_register15_clr => sysgen_dut_to_register15_clr_x0,
4808
      to_register15_data_in => sysgen_dut_to_register15_data_in_x0,
4809
      to_register15_en(0) => sysgen_dut_to_register15_en_x0,
4810
      to_register16_ce => sysgen_dut_to_register16_ce_x0,
4811
      to_register16_clk => sysgen_dut_to_register16_clk_x0,
4812
      to_register16_clr => sysgen_dut_to_register16_clr_x0,
4813
      to_register16_data_in(0) => sysgen_dut_to_register16_data_in_x0,
4814
      to_register16_en(0) => sysgen_dut_to_register16_en_x0,
4815
      to_register17_ce => sysgen_dut_to_register17_ce_x0,
4816
      to_register17_clk => sysgen_dut_to_register17_clk_x0,
4817
      to_register17_clr => sysgen_dut_to_register17_clr_x0,
4818
      to_register17_data_in => sysgen_dut_to_register17_data_in_x0,
4819
      to_register17_en(0) => sysgen_dut_to_register17_en_x0,
4820
      to_register18_ce => sysgen_dut_to_register18_ce_x0,
4821
      to_register18_clk => sysgen_dut_to_register18_clk_x0,
4822
      to_register18_clr => sysgen_dut_to_register18_clr_x0,
4823
      to_register18_data_in(0) => sysgen_dut_to_register18_data_in_x0,
4824
      to_register18_en(0) => sysgen_dut_to_register18_en_x0,
4825
      to_register19_ce => sysgen_dut_to_register19_ce_x0,
4826
      to_register19_clk => sysgen_dut_to_register19_clk_x0,
4827
      to_register19_clr => sysgen_dut_to_register19_clr_x0,
4828
      to_register19_data_in => sysgen_dut_to_register19_data_in_x0,
4829
      to_register19_en(0) => sysgen_dut_to_register19_en_x0,
4830
      to_register1_ce => sysgen_dut_to_register1_ce_x0,
4831
      to_register1_clk => sysgen_dut_to_register1_clk_x0,
4832
      to_register1_clr => sysgen_dut_to_register1_clr_x0,
4833
      to_register1_data_in(0) => sysgen_dut_to_register1_data_in_x0,
4834
      to_register1_en(0) => sysgen_dut_to_register1_en_x0,
4835
      to_register20_ce => sysgen_dut_to_register20_ce_x0,
4836
      to_register20_clk => sysgen_dut_to_register20_clk_x0,
4837
      to_register20_clr => sysgen_dut_to_register20_clr_x0,
4838
      to_register20_data_in(0) => sysgen_dut_to_register20_data_in_x0,
4839
      to_register20_en(0) => sysgen_dut_to_register20_en_x0,
4840
      to_register21_ce => sysgen_dut_to_register21_ce_x0,
4841
      to_register21_clk => sysgen_dut_to_register21_clk_x0,
4842
      to_register21_clr => sysgen_dut_to_register21_clr_x0,
4843
      to_register21_data_in => sysgen_dut_to_register21_data_in_x0,
4844
      to_register21_en(0) => sysgen_dut_to_register21_en_x0,
4845
      to_register22_ce => sysgen_dut_to_register22_ce_x0,
4846
      to_register22_clk => sysgen_dut_to_register22_clk_x0,
4847
      to_register22_clr => sysgen_dut_to_register22_clr_x0,
4848
      to_register22_data_in(0) => sysgen_dut_to_register22_data_in_x0,
4849
      to_register22_en(0) => sysgen_dut_to_register22_en_x0,
4850
      to_register23_ce => sysgen_dut_to_register23_ce_x0,
4851
      to_register23_clk => sysgen_dut_to_register23_clk_x0,
4852
      to_register23_clr => sysgen_dut_to_register23_clr_x0,
4853
      to_register23_data_in => sysgen_dut_to_register23_data_in_x0,
4854
      to_register23_en(0) => sysgen_dut_to_register23_en_x0,
4855
      to_register24_ce => sysgen_dut_to_register24_ce_x0,
4856
      to_register24_clk => sysgen_dut_to_register24_clk_x0,
4857
      to_register24_clr => sysgen_dut_to_register24_clr_x0,
4858
      to_register24_data_in(0) => sysgen_dut_to_register24_data_in_x0,
4859
      to_register24_en(0) => sysgen_dut_to_register24_en_x0,
4860
      to_register25_ce => sysgen_dut_to_register25_ce_x0,
4861
      to_register25_clk => sysgen_dut_to_register25_clk_x0,
4862
      to_register25_clr => sysgen_dut_to_register25_clr_x0,
4863
      to_register25_data_in => sysgen_dut_to_register25_data_in_x0,
4864
      to_register25_en(0) => sysgen_dut_to_register25_en_x0,
4865
      to_register26_ce => sysgen_dut_to_register26_ce_x0,
4866
      to_register26_clk => sysgen_dut_to_register26_clk_x0,
4867
      to_register26_clr => sysgen_dut_to_register26_clr_x0,
4868
      to_register26_data_in(0) => sysgen_dut_to_register26_data_in_x0,
4869
      to_register26_en(0) => sysgen_dut_to_register26_en_x0,
4870
      to_register27_ce => sysgen_dut_to_register27_ce_x0,
4871
      to_register27_clk => sysgen_dut_to_register27_clk_x0,
4872
      to_register27_clr => sysgen_dut_to_register27_clr_x0,
4873
      to_register27_data_in => sysgen_dut_to_register27_data_in_x0,
4874
      to_register27_en(0) => sysgen_dut_to_register27_en_x0,
4875
      to_register2_ce => sysgen_dut_to_register2_ce_x0,
4876
      to_register2_clk => sysgen_dut_to_register2_clk_x0,
4877
      to_register2_clr => sysgen_dut_to_register2_clr_x0,
4878
      to_register2_data_in => sysgen_dut_to_register2_data_in_x0,
4879
      to_register2_en(0) => sysgen_dut_to_register2_en_x0,
4880
      to_register3_ce => sysgen_dut_to_register3_ce_x0,
4881
      to_register3_clk => sysgen_dut_to_register3_clk_x0,
4882
      to_register3_clr => sysgen_dut_to_register3_clr_x0,
4883
      to_register3_data_in => sysgen_dut_to_register3_data_in_x0,
4884
      to_register3_en(0) => sysgen_dut_to_register3_en_x0,
4885
      to_register4_ce => sysgen_dut_to_register4_ce_x0,
4886
      to_register4_clk => sysgen_dut_to_register4_clk_x0,
4887
      to_register4_clr => sysgen_dut_to_register4_clr_x0,
4888
      to_register4_data_in(0) => sysgen_dut_to_register4_data_in_x0,
4889
      to_register4_en(0) => sysgen_dut_to_register4_en_x0,
4890
      to_register5_ce => sysgen_dut_to_register5_ce_x0,
4891
      to_register5_clk => sysgen_dut_to_register5_clk_x0,
4892
      to_register5_clr => sysgen_dut_to_register5_clr_x0,
4893
      to_register5_data_in(0) => sysgen_dut_to_register5_data_in_x0,
4894
      to_register5_en(0) => sysgen_dut_to_register5_en_x0,
4895
      to_register6_ce => sysgen_dut_to_register6_ce_x0,
4896
      to_register6_clk => sysgen_dut_to_register6_clk_x0,
4897
      to_register6_clr => sysgen_dut_to_register6_clr_x0,
4898
      to_register6_data_in => sysgen_dut_to_register6_data_in_x0,
4899
      to_register6_en(0) => sysgen_dut_to_register6_en_x0,
4900
      to_register7_ce => sysgen_dut_to_register7_ce_x0,
4901
      to_register7_clk => sysgen_dut_to_register7_clk_x0,
4902
      to_register7_clr => sysgen_dut_to_register7_clr_x0,
4903
      to_register7_data_in(0) => sysgen_dut_to_register7_data_in_x0,
4904
      to_register7_en(0) => sysgen_dut_to_register7_en_x0,
4905
      to_register8_ce => sysgen_dut_to_register8_ce_x0,
4906
      to_register8_clk => sysgen_dut_to_register8_clk_x0,
4907
      to_register8_clr => sysgen_dut_to_register8_clr_x0,
4908
      to_register8_data_in => sysgen_dut_to_register8_data_in_x0,
4909
      to_register8_en(0) => sysgen_dut_to_register8_en_x0,
4910
      to_register9_ce => sysgen_dut_to_register9_ce_x0,
4911
      to_register9_clk => sysgen_dut_to_register9_clk_x0,
4912
      to_register9_clr => sysgen_dut_to_register9_clr_x0,
4913
      to_register9_data_in => sysgen_dut_to_register9_data_in_x0,
4914
      to_register9_en(0) => sysgen_dut_to_register9_en_x0,
4915
      to_register_ce => sysgen_dut_to_register_ce,
4916
      to_register_clk => sysgen_dut_to_register_clk,
4917
      to_register_clr => sysgen_dut_to_register_clr,
4918
      to_register_data_in => sysgen_dut_to_register_data_in,
4919
      to_register_en(0) => sysgen_dut_to_register_en,
4920
      user_int_1o => x_x83,
4921
      user_int_2o => x_x84,
4922
      user_int_3o => x_x85
4923
    );
4924
 
4925
end structural;

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