Subversion Repositories pcie_sg_dma

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 986: Assignment to to_register10_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 987: Assignment to to_register11_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 988: Assignment to to_register12_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 989: Assignment to to_register13_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 990: Assignment to to_register14_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 991: Assignment to to_register15_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 992: Assignment to to_register16_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 993: Assignment to to_register17_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 994: Assignment to to_register18_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 995: Assignment to to_register19_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 996: Assignment to to_register1_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 997: Assignment to to_register20_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 998: Assignment to to_register21_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 999: Assignment to to_register22_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1000: Assignment to to_register23_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1001: Assignment to to_register24_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1002: Assignment to to_register25_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1003: Assignment to to_register26_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1004: Assignment to to_register27_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1005: Assignment to to_register28_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1006: Assignment to to_register29_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1007: Assignment to to_register2_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1008: Assignment to to_register30_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1009: Assignment to to_register31_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1010: Assignment to to_register32_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1011: Assignment to to_register33_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1012: Assignment to to_register34_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1013: Assignment to to_register3_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1014: Assignment to to_register4_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1015: Assignment to to_register5_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1016: Assignment to to_register6_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1017: Assignment to to_register7_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1018: Assignment to to_register8_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1019: Assignment to to_register9_dout_net ignored, since the identifier is never used

"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic.vhd" Line 1727: <fdre> remains a black-box since it has no binding entity.

Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.

Input <to_register10_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register11_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register12_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register13_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register14_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register15_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register16_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register17_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register18_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register19_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register1_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register20_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register21_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register22_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register23_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register24_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register25_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register26_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register27_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register28_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register29_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register2_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register30_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register31_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register32_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register33_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register34_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register3_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register4_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register5_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register6_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register7_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register8_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <to_register9_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port <clr> of the instance <xlclockdriver> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port <ce_logic> of the instance <xlclockdriver> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 254: Output port <o> of the instance <clr_reg> is unconnected or connected to loadless signal.

Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Unit <inout_logic>: instances <constant1>, <constant5> of unit <constant_6293007044> are equivalent, second instance is removed

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <inout_logic_cw>. This FF/Latch will be trimmed during the optimization process.

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.