OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis.1] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0.0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5.0,
14 
    'base_system_period_simulink' => 8.0E-9,
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0.0,
19 
    'clock_loc' => '',
20 
    'clock_wrapper' => 'Clock Enables',
21 
    'clock_wrapper_sgadvanced' => '',
22 
    'compilation' => 'NGC Netlist',
23 
    'compilation_lut' => {
24 
      'keys' => [
25 
        'HDL Netlist',
26 
        'Bitstream',
27 
        'NGC Netlist',
28 
      ],
29 
      'values' => [
30 
        'target1',
31 
        'target2',
32 
        'target3',
33 
      ],
34 
    },
35 
    'compilation_target' => 'NGC Netlist',
36 
    'core_generation' => 1.0,
37 
    'core_generation_sgadvanced' => '',
38 
    'core_is_deployed' => 0.0,
39 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c46e83d2645affbd5',
40 
    'coregen_part_family' => 'virtex6',
41 
    'createTestbench' => 0,
42 
    'create_interface_document' => 'off',
43 
    'dbl_ovrd' => -1.0,
44 
    'dbl_ovrd_sgadvanced' => '',
45 
    'dcm_info' => {},
46 
    'dcm_input_clock_period' => 5.0,
47 
    'deprecated_control' => 'off',
48 
    'deprecated_control_sgadvanced' => '',
49 
    'design' => 'inout_logic',
50 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
51 
    'device' => 'xc6vlx240t-1ff1156',
52 
    'device_speed' => '-1',
53 
    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
54 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
55 
    'entityNamingInstrs' => {
56 
      'nameMap' => undef,
57 
      'namesAlreadyUsed' => undef,
58 
    },
59 
    'eval_field' => '0',
60 
    'fileAttributes' => {
61 
      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
62 
    },
63 
    'files' => [
64 
      'xlpersistentdff.ngc',
65 
      'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen/perl_results.vhd',
66 
      'nonleaf_results.vhd',
67 
      'synopsis',
68 
    ],
69 
    'fxdptinstalled' => 1.0,
70 
    'generateUsing71FrontEnd' => 1,
71 
    'generating_island_subsystem_handle' => 2084.00048828125,
72 
    'generating_subsystem_handle' => 2084.00048828125,
73 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
74 
    'has_advanced_control' => '0',
75 
    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
76 
    'hdlKind' => 'vhdl',
77 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
78 
    'impl_file' => 'ISE Defaults*',
79 
    'incr_netlist' => 'off',
80 
    'incr_netlist_sgadvanced' => '',
81 
    'infoedit' => ' System Generator',
82 
    'isCombinatorial' => 1,
83 
    'isdeployed' => 0,
84 
    'ise_version' => '13.3i',
85 
    'master_sysgen_token_handle' => 2085.00048828125,
86 
    'matlab' => 'C:/Programmi/MATLAB/R2010b',
87 
    'matlab_fixedpoint' => 1.0,
88 
    'mdlHandle' => 2083.00048828125,
89 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
90 
    'modelDiagnostics' => [
91 
      {
92 
        'count' => 351.0,
93 
        'isMask' => 0.0,
94 
        'type' => 'PCIe_UserLogic_00 Total blocks',
95 
      },
96 
      {
97 
        'count' => 4.0,
98 
        'isMask' => 0.0,
99 
        'type' => 'DiscretePulseGenerator',
100 
      },
101 
      {
102 
        'count' => 339.0,
103 
        'isMask' => 0.0,
104 
        'type' => 'S-Function',
105 
      },
106 
      {
107 
        'count' => 4.0,
108 
        'isMask' => 0.0,
109 
        'type' => 'SubSystem',
110 
      },
111 
      {
112 
        'count' => 4.0,
113 
        'isMask' => 0.0,
114 
        'type' => 'Terminator',
115 
      },
116 
      {
117 
        'count' => 1.0,
118 
        'isMask' => 1.0,
119 
        'type' => 'Xilinx ChipScope Block',
120 
      },
121 
      {
122 
        'count' => 23.0,
123 
        'isMask' => 1.0,
124 
        'type' => 'Xilinx Constant Block Block',
125 
      },
126 
      {
127 
        'count' => 1.0,
128 
        'isMask' => 1.0,
129 
        'type' => 'Xilinx Counter Block',
130 
      },
131 
      {
132 
        'count' => 44.0,
133 
        'isMask' => 1.0,
134 
        'type' => 'Xilinx Gateway In Block',
135 
      },
136 
      {
137 
        'count' => 39.0,
138 
        'isMask' => 1.0,
139 
        'type' => 'Xilinx Gateway Out Block',
140 
      },
141 
      {
142 
        'count' => 2.0,
143 
        'isMask' => 1.0,
144 
        'type' => 'Xilinx Inverter Block',
145 
      },
146 
      {
147 
        'count' => 1.0,
148 
        'isMask' => 1.0,
149 
        'type' => 'Xilinx Logical Block Block',
150 
      },
151 
      {
152 
        'count' => 89.0,
153 
        'isMask' => 1.0,
154 
        'type' => 'Xilinx Register Block',
155 
      },
156 
      {
157 
        'count' => 62.0,
158 
        'isMask' => 1.0,
159 
        'type' => 'Xilinx Shared Memory Based From Register Block',
160 
      },
161 
      {
162 
        'count' => 62.0,
163 
        'isMask' => 1.0,
164 
        'type' => 'Xilinx Shared Memory Based To Register Block',
165 
      },
166 
      {
167 
        'count' => 1.0,
168 
        'isMask' => 1.0,
169 
        'type' => 'Xilinx Subsystem Generator Block',
170 
      },
171 
      {
172 
        'count' => 2.0,
173 
        'isMask' => 1.0,
174 
        'type' => 'Xilinx System Generator Block',
175 
      },
176 
      {
177 
        'count' => 14.0,
178 
        'isMask' => 1.0,
179 
        'type' => 'Xilinx Type Converter Block',
180 
      },
181 
    ],
182 
    'model_globals_initialized' => 1.0,
183 
    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
184 
    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
185 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
186 
    'ngc_config' => {
187 
      'include_cf' => 1,
188 
      'include_clockwrapper' => 1.0,
189 
    },
190 
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
191 
    'num_sim_cycles' => '1250000000',
192 
    'package' => 'ff1156',
193 
    'part' => 'xc6vlx240t',
194 
    'partFamily' => 'virtex6',
195 
    'port_data_types_enabled' => 1.0,
196 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
197 
    'preserve_hierarchy' => 0.0,
198 
    'proj_type' => 'Project Navigator',
199 
    'proj_type_sgadvanced' => '',
200 
    'run_coregen' => 'off',
201 
    'run_coregen_sgadvanced' => '',
202 
    'sample_time_colors_enabled' => 1.0,
203 
    'sampletimecolors' => 1.0,
204 
    'settings_fcn' => 'xlngcsettings',
205 
    'sg_blockgui_xml' => '',
206 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
207 
    'sg_list_contents' => '',
208 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
209 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
210 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
211 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
212 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
213 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
214 
fprintf(\'\',\'COMMENT: end icon graphics\');
215 
fprintf(\'\',\'COMMENT: begin icon text\');
216 
fprintf(\'\',\'COMMENT: end icon text\');',
217 
    'sg_version' => '',
218 
    'sggui_pos' => '-1,-1,-1,-1',
219 
    'simulation_island_subsystem_handle' => 2084.00048828125,
220 
    'simulinkName' => 'parking_lot',
221 
    'simulink_accelerator_running' => 0.0,
222 
    'simulink_debugger_running' => 0.0,
223 
    'simulink_period' => 8.0E-9,
224 
    'speed' => '-1',
225 
    'synth_file' => 'XST Defaults*',
226 
    'synthesisTool' => 'XST',
227 
    'synthesis_language' => 'vhdl',
228 
    'synthesis_tool' => 'XST',
229 
    'synthesis_tool_sgadvanced' => '',
230 
    'sysclk_period' => 5.0,
231 
    'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
232 
    'sysgenRoot' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
233 
    'sysgenTokenSettings' => {
234 
      'Impl_file' => 'ISE Defaults',
235 
      'Impl_file_sgadvanced' => '',
236 
      'Synth_file' => 'XST Defaults',
237 
      'Synth_file_sgadvanced' => '',
238 
      'base_system_period_hardware' => 5.0,
239 
      'base_system_period_simulink' => 8.0E-9,
240 
      'block_icon_display' => 'Default',
241 
      'block_type' => 'sysgen',
242 
      'block_version' => '',
243 
      'ce_clr' => 0.0,
244 
      'clock_loc' => '',
245 
      'clock_wrapper' => 'Clock Enables',
246 
      'clock_wrapper_sgadvanced' => '',
247 
      'compilation' => 'NGC Netlist',
248 
      'compilation_lut' => {
249 
        'keys' => [
250 
          'HDL Netlist',
251 
          'Bitstream',
252 
          'NGC Netlist',
253 
        ],
254 
        'values' => [
255 
          'target1',
256 
          'target2',
257 
          'target3',
258 
        ],
259 
      },
260 
      'core_generation' => 1.0,
261 
      'core_generation_sgadvanced' => '',
262 
      'coregen_part_family' => 'virtex6',
263 
      'create_interface_document' => 'off',
264 
      'dbl_ovrd' => -1.0,
265 
      'dbl_ovrd_sgadvanced' => '',
266 
      'dcm_input_clock_period' => 5.0,
267 
      'deprecated_control' => 'off',
268 
      'deprecated_control_sgadvanced' => '',
269 
      'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
270 
      'eval_field' => '0',
271 
      'has_advanced_control' => '0',
272 
      'impl_file' => 'ISE Defaults*',
273 
      'incr_netlist' => 'off',
274 
      'incr_netlist_sgadvanced' => '',
275 
      'infoedit' => ' System Generator',
276 
      'master_sysgen_token_handle' => 2085.00048828125,
277 
      'ngc_config' => {
278 
        'include_cf' => 1,
279 
        'include_clockwrapper' => 1.0,
280 
      },
281 
      'package' => 'ff1156',
282 
      'part' => 'xc6vlx240t',
283 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
284 
      'preserve_hierarchy' => 0.0,
285 
      'proj_type' => 'Project Navigator',
286 
      'proj_type_sgadvanced' => '',
287 
      'run_coregen' => 'off',
288 
      'run_coregen_sgadvanced' => '',
289 
      'settings_fcn' => 'xlngcsettings',
290 
      'sg_blockgui_xml' => '',
291 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
292 
      'sg_list_contents' => '',
293 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
294 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
295 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
296 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
297 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
298 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
299 
fprintf(\'\',\'COMMENT: end icon graphics\');
300 
fprintf(\'\',\'COMMENT: begin icon text\');
301 
fprintf(\'\',\'COMMENT: end icon text\');',
302 
      'sggui_pos' => '-1,-1,-1,-1',
303 
      'simulation_island_subsystem_handle' => 2084.00048828125,
304 
      'simulink_period' => 8.0E-9,
305 
      'speed' => '-1',
306 
      'synth_file' => 'XST Defaults*',
307 
      'synthesis_language' => 'vhdl',
308 
      'synthesis_tool' => 'XST',
309 
      'synthesis_tool_sgadvanced' => '',
310 
      'sysclk_period' => 5.0,
311 
      'testbench' => 0,
312 
      'testbench_sgadvanced' => '',
313 
      'trim_vbits' => 1.0,
314 
      'trim_vbits_sgadvanced' => '',
315 
      'xilinx_device' => 'xc6vlx240t-1ff1156',
316 
      'xilinxfamily' => 'virtex6',
317 
    },
318 
    'sysgen_Root' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
319 
    'systemClockPeriod' => 5.0,
320 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
321 
    'testbench' => 0,
322 
    'testbench_sgadvanced' => '',
323 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
324 
    'trim_vbits' => 1.0,
325 
    'trim_vbits_sgadvanced' => '',
326 
    'use_ce_syn_keep' => 1,
327 
    'use_strict_names' => 1,
328 
    'user_tips_enabled' => 0.0,
329 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
330 
    'using71Netlister' => 1,
331 
    'verilog_files' => [
332 
      'conv_pkg.v',
333 
      'synth_reg.v',
334 
      'synth_reg_w_init.v',
335 
      'convert_type.v',
336 
    ],
337 
    'version' => '',
338 
    'vhdl_files' => [
339 
      'conv_pkg.vhd',
340 
      'synth_reg.vhd',
341 
      'synth_reg_w_init.vhd',
342 
    ],
343 
    'vsimtime' => '6875000275.000000 ns',
344 
    'xilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
345 
    'xilinx_device' => 'xc6vlx240t-1ff1156',
346 
    'xilinx_family' => 'virtex6',
347 
    'xilinx_package' => 'ff1156',
348 
    'xilinx_part' => 'xc6vlx240t',
349 
    'xilinxdevice' => 'xc6vlx240t-1ff1156',
350 
    'xilinxfamily' => 'virtex6',
351 
    'xilinxpart' => 'xc6vlx240t',
352 
  },
353 
  'entityName' => '',
354 
  'nets' => {
355 
    'ce_1_sg' => {
356 
      'hdlType' => 'std_logic',
357 
      'width' => 1,
358 
    },
359 
    'clk_1_sg' => {
360 
      'hdlType' => 'std_logic',
361 
      'width' => 1,
362 
    },
363 
    'constant1_op_net_x0' => {
364 
      'hdlType' => 'std_logic',
365 
      'width' => 1,
366 
    },
367 
    'constant1_op_net_x1' => {
368 
      'hdlType' => 'std_logic',
369 
      'width' => 1,
370 
    },
371 
    'constant1_op_net_x10' => {
372 
      'hdlType' => 'std_logic',
373 
      'width' => 1,
374 
    },
375 
    'constant1_op_net_x11' => {
376 
      'hdlType' => 'std_logic',
377 
      'width' => 1,
378 
    },
379 
    'constant1_op_net_x12' => {
380 
      'hdlType' => 'std_logic',
381 
      'width' => 1,
382 
    },
383 
    'constant1_op_net_x13' => {
384 
      'hdlType' => 'std_logic',
385 
      'width' => 1,
386 
    },
387 
    'constant1_op_net_x2' => {
388 
      'hdlType' => 'std_logic',
389 
      'width' => 1,
390 
    },
391 
    'constant1_op_net_x3' => {
392 
      'hdlType' => 'std_logic',
393 
      'width' => 1,
394 
    },
395 
    'constant1_op_net_x4' => {
396 
      'hdlType' => 'std_logic',
397 
      'width' => 1,
398 
    },
399 
    'constant1_op_net_x5' => {
400 
      'hdlType' => 'std_logic',
401 
      'width' => 1,
402 
    },
403 
    'constant1_op_net_x6' => {
404 
      'hdlType' => 'std_logic',
405 
      'width' => 1,
406 
    },
407 
    'constant1_op_net_x7' => {
408 
      'hdlType' => 'std_logic',
409 
      'width' => 1,
410 
    },
411 
    'constant1_op_net_x8' => {
412 
      'hdlType' => 'std_logic',
413 
      'width' => 1,
414 
    },
415 
    'constant1_op_net_x9' => {
416 
      'hdlType' => 'std_logic',
417 
      'width' => 1,
418 
    },
419 
    'constant5_op_net_x0' => {
420 
      'hdlType' => 'std_logic',
421 
      'width' => 1,
422 
    },
423 
    'constant5_op_net_x1' => {
424 
      'hdlType' => 'std_logic',
425 
      'width' => 1,
426 
    },
427 
    'constant5_op_net_x10' => {
428 
      'hdlType' => 'std_logic',
429 
      'width' => 1,
430 
    },
431 
    'constant5_op_net_x11' => {
432 
      'hdlType' => 'std_logic',
433 
      'width' => 1,
434 
    },
435 
    'constant5_op_net_x12' => {
436 
      'hdlType' => 'std_logic',
437 
      'width' => 1,
438 
    },
439 
    'constant5_op_net_x13' => {
440 
      'hdlType' => 'std_logic',
441 
      'width' => 1,
442 
    },
443 
    'constant5_op_net_x14' => {
444 
      'hdlType' => 'std_logic',
445 
      'width' => 1,
446 
    },
447 
    'constant5_op_net_x15' => {
448 
      'hdlType' => 'std_logic',
449 
      'width' => 1,
450 
    },
451 
    'constant5_op_net_x16' => {
452 
      'hdlType' => 'std_logic',
453 
      'width' => 1,
454 
    },
455 
    'constant5_op_net_x17' => {
456 
      'hdlType' => 'std_logic',
457 
      'width' => 1,
458 
    },
459 
    'constant5_op_net_x18' => {
460 
      'hdlType' => 'std_logic',
461 
      'width' => 1,
462 
    },
463 
    'constant5_op_net_x19' => {
464 
      'hdlType' => 'std_logic',
465 
      'width' => 1,
466 
    },
467 
    'constant5_op_net_x2' => {
468 
      'hdlType' => 'std_logic',
469 
      'width' => 1,
470 
    },
471 
    'constant5_op_net_x3' => {
472 
      'hdlType' => 'std_logic',
473 
      'width' => 1,
474 
    },
475 
    'constant5_op_net_x4' => {
476 
      'hdlType' => 'std_logic',
477 
      'width' => 1,
478 
    },
479 
    'constant5_op_net_x5' => {
480 
      'hdlType' => 'std_logic',
481 
      'width' => 1,
482 
    },
483 
    'constant5_op_net_x6' => {
484 
      'hdlType' => 'std_logic',
485 
      'width' => 1,
486 
    },
487 
    'constant5_op_net_x7' => {
488 
      'hdlType' => 'std_logic',
489 
      'width' => 1,
490 
    },
491 
    'constant5_op_net_x8' => {
492 
      'hdlType' => 'std_logic',
493 
      'width' => 1,
494 
    },
495 
    'constant5_op_net_x9' => {
496 
      'hdlType' => 'std_logic',
497 
      'width' => 1,
498 
    },
499 
    'debug_in_1i_net' => {
500 
      'hdlType' => 'std_logic_vector(31 downto 0)',
501 
      'width' => 32,
502 
    },
503 
    'debug_in_1i_net_x0' => {
504 
      'hdlType' => 'std_logic_vector(31 downto 0)',
505 
      'width' => 32,
506 
    },
507 
    'debug_in_2i_net' => {
508 
      'hdlType' => 'std_logic_vector(31 downto 0)',
509 
      'width' => 32,
510 
    },
511 
    'debug_in_2i_net_x0' => {
512 
      'hdlType' => 'std_logic_vector(31 downto 0)',
513 
      'width' => 32,
514 
    },
515 
    'debug_in_3i_net' => {
516 
      'hdlType' => 'std_logic_vector(31 downto 0)',
517 
      'width' => 32,
518 
    },
519 
    'debug_in_3i_net_x0' => {
520 
      'hdlType' => 'std_logic_vector(31 downto 0)',
521 
      'width' => 32,
522 
    },
523 
    'debug_in_4i_net' => {
524 
      'hdlType' => 'std_logic_vector(31 downto 0)',
525 
      'width' => 32,
526 
    },
527 
    'debug_in_4i_net_x0' => {
528 
      'hdlType' => 'std_logic_vector(31 downto 0)',
529 
      'width' => 32,
530 
    },
531 
    'dma_host2board_busy_net' => {
532 
      'hdlType' => 'std_logic',
533 
      'width' => 1,
534 
    },
535 
    'dma_host2board_busy_net_x0' => {
536 
      'hdlType' => 'std_logic',
537 
      'width' => 1,
538 
    },
539 
    'dma_host2board_done_net' => {
540 
      'hdlType' => 'std_logic',
541 
      'width' => 1,
542 
    },
543 
    'dma_host2board_done_net_x0' => {
544 
      'hdlType' => 'std_logic',
545 
      'width' => 1,
546 
    },
547 
    'from_register10_data_out_net' => {
548 
      'hdlType' => 'std_logic_vector(31 downto 0)',
549 
      'width' => 32,
550 
    },
551 
    'from_register10_data_out_net_x0' => {
552 
      'hdlType' => 'std_logic_vector(31 downto 0)',
553 
      'width' => 32,
554 
    },
555 
    'from_register11_data_out_net' => {
556 
      'hdlType' => 'std_logic_vector(31 downto 0)',
557 
      'width' => 32,
558 
    },
559 
    'from_register11_data_out_net_x0' => {
560 
      'hdlType' => 'std_logic_vector(31 downto 0)',
561 
      'width' => 32,
562 
    },
563 
    'from_register12_data_out_net' => {
564 
      'hdlType' => 'std_logic',
565 
      'width' => 1,
566 
    },
567 
    'from_register12_data_out_net_x0' => {
568 
      'hdlType' => 'std_logic',
569 
      'width' => 1,
570 
    },
571 
    'from_register13_data_out_net' => {
572 
      'hdlType' => 'std_logic_vector(31 downto 0)',
573 
      'width' => 32,
574 
    },
575 
    'from_register13_data_out_net_x0' => {
576 
      'hdlType' => 'std_logic_vector(31 downto 0)',
577 
      'width' => 32,
578 
    },
579 
    'from_register14_data_out_net' => {
580 
      'hdlType' => 'std_logic',
581 
      'width' => 1,
582 
    },
583 
    'from_register14_data_out_net_x0' => {
584 
      'hdlType' => 'std_logic',
585 
      'width' => 1,
586 
    },
587 
    'from_register15_data_out_net' => {
588 
      'hdlType' => 'std_logic_vector(31 downto 0)',
589 
      'width' => 32,
590 
    },
591 
    'from_register15_data_out_net_x0' => {
592 
      'hdlType' => 'std_logic_vector(31 downto 0)',
593 
      'width' => 32,
594 
    },
595 
    'from_register16_data_out_net' => {
596 
      'hdlType' => 'std_logic',
597 
      'width' => 1,
598 
    },
599 
    'from_register16_data_out_net_x0' => {
600 
      'hdlType' => 'std_logic',
601 
      'width' => 1,
602 
    },
603 
    'from_register17_data_out_net' => {
604 
      'hdlType' => 'std_logic_vector(31 downto 0)',
605 
      'width' => 32,
606 
    },
607 
    'from_register17_data_out_net_x0' => {
608 
      'hdlType' => 'std_logic_vector(31 downto 0)',
609 
      'width' => 32,
610 
    },
611 
    'from_register18_data_out_net' => {
612 
      'hdlType' => 'std_logic',
613 
      'width' => 1,
614 
    },
615 
    'from_register18_data_out_net_x0' => {
616 
      'hdlType' => 'std_logic',
617 
      'width' => 1,
618 
    },
619 
    'from_register19_data_out_net' => {
620 
      'hdlType' => 'std_logic_vector(31 downto 0)',
621 
      'width' => 32,
622 
    },
623 
    'from_register19_data_out_net_x0' => {
624 
      'hdlType' => 'std_logic_vector(31 downto 0)',
625 
      'width' => 32,
626 
    },
627 
    'from_register1_data_out_net' => {
628 
      'hdlType' => 'std_logic',
629 
      'width' => 1,
630 
    },
631 
    'from_register1_data_out_net_x0' => {
632 
      'hdlType' => 'std_logic',
633 
      'width' => 1,
634 
    },
635 
    'from_register20_data_out_net' => {
636 
      'hdlType' => 'std_logic',
637 
      'width' => 1,
638 
    },
639 
    'from_register20_data_out_net_x0' => {
640 
      'hdlType' => 'std_logic',
641 
      'width' => 1,
642 
    },
643 
    'from_register21_data_out_net' => {
644 
      'hdlType' => 'std_logic_vector(31 downto 0)',
645 
      'width' => 32,
646 
    },
647 
    'from_register21_data_out_net_x0' => {
648 
      'hdlType' => 'std_logic_vector(31 downto 0)',
649 
      'width' => 32,
650 
    },
651 
    'from_register22_data_out_net' => {
652 
      'hdlType' => 'std_logic',
653 
      'width' => 1,
654 
    },
655 
    'from_register22_data_out_net_x0' => {
656 
      'hdlType' => 'std_logic',
657 
      'width' => 1,
658 
    },
659 
    'from_register23_data_out_net' => {
660 
      'hdlType' => 'std_logic_vector(31 downto 0)',
661 
      'width' => 32,
662 
    },
663 
    'from_register23_data_out_net_x0' => {
664 
      'hdlType' => 'std_logic_vector(31 downto 0)',
665 
      'width' => 32,
666 
    },
667 
    'from_register24_data_out_net' => {
668 
      'hdlType' => 'std_logic',
669 
      'width' => 1,
670 
    },
671 
    'from_register24_data_out_net_x0' => {
672 
      'hdlType' => 'std_logic',
673 
      'width' => 1,
674 
    },
675 
    'from_register25_data_out_net' => {
676 
      'hdlType' => 'std_logic_vector(31 downto 0)',
677 
      'width' => 32,
678 
    },
679 
    'from_register25_data_out_net_x0' => {
680 
      'hdlType' => 'std_logic_vector(31 downto 0)',
681 
      'width' => 32,
682 
    },
683 
    'from_register26_data_out_net' => {
684 
      'hdlType' => 'std_logic',
685 
      'width' => 1,
686 
    },
687 
    'from_register26_data_out_net_x0' => {
688 
      'hdlType' => 'std_logic',
689 
      'width' => 1,
690 
    },
691 
    'from_register27_data_out_net' => {
692 
      'hdlType' => 'std_logic_vector(31 downto 0)',
693 
      'width' => 32,
694 
    },
695 
    'from_register27_data_out_net_x0' => {
696 
      'hdlType' => 'std_logic_vector(31 downto 0)',
697 
      'width' => 32,
698 
    },
699 
    'from_register28_data_out_net' => {
700 
      'hdlType' => 'std_logic',
701 
      'width' => 1,
702 
    },
703 
    'from_register28_data_out_net_x0' => {
704 
      'hdlType' => 'std_logic',
705 
      'width' => 1,
706 
    },
707 
    'from_register2_data_out_net' => {
708 
      'hdlType' => 'std_logic',
709 
      'width' => 1,
710 
    },
711 
    'from_register2_data_out_net_x0' => {
712 
      'hdlType' => 'std_logic',
713 
      'width' => 1,
714 
    },
715 
    'from_register3_data_out_net' => {
716 
      'hdlType' => 'std_logic_vector(31 downto 0)',
717 
      'width' => 32,
718 
    },
719 
    'from_register3_data_out_net_x0' => {
720 
      'hdlType' => 'std_logic_vector(31 downto 0)',
721 
      'width' => 32,
722 
    },
723 
    'from_register4_data_out_net' => {
724 
      'hdlType' => 'std_logic',
725 
      'width' => 1,
726 
    },
727 
    'from_register4_data_out_net_x0' => {
728 
      'hdlType' => 'std_logic',
729 
      'width' => 1,
730 
    },
731 
    'from_register5_data_out_net' => {
732 
      'hdlType' => 'std_logic_vector(31 downto 0)',
733 
      'width' => 32,
734 
    },
735 
    'from_register5_data_out_net_x0' => {
736 
      'hdlType' => 'std_logic_vector(31 downto 0)',
737 
      'width' => 32,
738 
    },
739 
    'from_register6_data_out_net' => {
740 
      'hdlType' => 'std_logic',
741 
      'width' => 1,
742 
    },
743 
    'from_register6_data_out_net_x0' => {
744 
      'hdlType' => 'std_logic',
745 
      'width' => 1,
746 
    },
747 
    'from_register7_data_out_net' => {
748 
      'hdlType' => 'std_logic_vector(31 downto 0)',
749 
      'width' => 32,
750 
    },
751 
    'from_register7_data_out_net_x0' => {
752 
      'hdlType' => 'std_logic_vector(31 downto 0)',
753 
      'width' => 32,
754 
    },
755 
    'from_register8_data_out_net' => {
756 
      'hdlType' => 'std_logic_vector(31 downto 0)',
757 
      'width' => 32,
758 
    },
759 
    'from_register8_data_out_net_x0' => {
760 
      'hdlType' => 'std_logic_vector(31 downto 0)',
761 
      'width' => 32,
762 
    },
763 
    'from_register9_data_out_net' => {
764 
      'hdlType' => 'std_logic',
765 
      'width' => 1,
766 
    },
767 
    'from_register9_data_out_net_x0' => {
768 
      'hdlType' => 'std_logic',
769 
      'width' => 1,
770 
    },
771 
    'reg01_td_net' => {
772 
      'hdlType' => 'std_logic_vector(31 downto 0)',
773 
      'width' => 32,
774 
    },
775 
    'reg01_td_net_x0' => {
776 
      'hdlType' => 'std_logic_vector(31 downto 0)',
777 
      'width' => 32,
778 
    },
779 
    'reg01_tv_net' => {
780 
      'hdlType' => 'std_logic',
781 
      'width' => 1,
782 
    },
783 
    'reg01_tv_net_x0' => {
784 
      'hdlType' => 'std_logic',
785 
      'width' => 1,
786 
    },
787 
    'reg02_td_net' => {
788 
      'hdlType' => 'std_logic_vector(31 downto 0)',
789 
      'width' => 32,
790 
    },
791 
    'reg02_td_net_x0' => {
792 
      'hdlType' => 'std_logic_vector(31 downto 0)',
793 
      'width' => 32,
794 
    },
795 
    'reg02_tv_net' => {
796 
      'hdlType' => 'std_logic',
797 
      'width' => 1,
798 
    },
799 
    'reg02_tv_net_x0' => {
800 
      'hdlType' => 'std_logic',
801 
      'width' => 1,
802 
    },
803 
    'reg03_td_net' => {
804 
      'hdlType' => 'std_logic_vector(31 downto 0)',
805 
      'width' => 32,
806 
    },
807 
    'reg03_td_net_x0' => {
808 
      'hdlType' => 'std_logic_vector(31 downto 0)',
809 
      'width' => 32,
810 
    },
811 
    'reg03_tv_net' => {
812 
      'hdlType' => 'std_logic',
813 
      'width' => 1,
814 
    },
815 
    'reg03_tv_net_x0' => {
816 
      'hdlType' => 'std_logic',
817 
      'width' => 1,
818 
    },
819 
    'reg04_td_net' => {
820 
      'hdlType' => 'std_logic_vector(31 downto 0)',
821 
      'width' => 32,
822 
    },
823 
    'reg04_td_net_x0' => {
824 
      'hdlType' => 'std_logic_vector(31 downto 0)',
825 
      'width' => 32,
826 
    },
827 
    'reg04_tv_net' => {
828 
      'hdlType' => 'std_logic',
829 
      'width' => 1,
830 
    },
831 
    'reg04_tv_net_x0' => {
832 
      'hdlType' => 'std_logic',
833 
      'width' => 1,
834 
    },
835 
    'reg05_td_net' => {
836 
      'hdlType' => 'std_logic_vector(31 downto 0)',
837 
      'width' => 32,
838 
    },
839 
    'reg05_td_net_x0' => {
840 
      'hdlType' => 'std_logic_vector(31 downto 0)',
841 
      'width' => 32,
842 
    },
843 
    'reg05_tv_net' => {
844 
      'hdlType' => 'std_logic',
845 
      'width' => 1,
846 
    },
847 
    'reg05_tv_net_x0' => {
848 
      'hdlType' => 'std_logic',
849 
      'width' => 1,
850 
    },
851 
    'reg06_td_net' => {
852 
      'hdlType' => 'std_logic_vector(31 downto 0)',
853 
      'width' => 32,
854 
    },
855 
    'reg06_td_net_x0' => {
856 
      'hdlType' => 'std_logic_vector(31 downto 0)',
857 
      'width' => 32,
858 
    },
859 
    'reg06_tv_net' => {
860 
      'hdlType' => 'std_logic',
861 
      'width' => 1,
862 
    },
863 
    'reg06_tv_net_x0' => {
864 
      'hdlType' => 'std_logic',
865 
      'width' => 1,
866 
    },
867 
    'reg07_td_net' => {
868 
      'hdlType' => 'std_logic_vector(31 downto 0)',
869 
      'width' => 32,
870 
    },
871 
    'reg07_td_net_x0' => {
872 
      'hdlType' => 'std_logic_vector(31 downto 0)',
873 
      'width' => 32,
874 
    },
875 
    'reg07_tv_net' => {
876 
      'hdlType' => 'std_logic',
877 
      'width' => 1,
878 
    },
879 
    'reg07_tv_net_x0' => {
880 
      'hdlType' => 'std_logic',
881 
      'width' => 1,
882 
    },
883 
    'reg08_td_net' => {
884 
      'hdlType' => 'std_logic_vector(31 downto 0)',
885 
      'width' => 32,
886 
    },
887 
    'reg08_td_net_x0' => {
888 
      'hdlType' => 'std_logic_vector(31 downto 0)',
889 
      'width' => 32,
890 
    },
891 
    'reg08_tv_net' => {
892 
      'hdlType' => 'std_logic',
893 
      'width' => 1,
894 
    },
895 
    'reg08_tv_net_x0' => {
896 
      'hdlType' => 'std_logic',
897 
      'width' => 1,
898 
    },
899 
    'reg09_td_net' => {
900 
      'hdlType' => 'std_logic_vector(31 downto 0)',
901 
      'width' => 32,
902 
    },
903 
    'reg09_td_net_x0' => {
904 
      'hdlType' => 'std_logic_vector(31 downto 0)',
905 
      'width' => 32,
906 
    },
907 
    'reg09_tv_net' => {
908 
      'hdlType' => 'std_logic',
909 
      'width' => 1,
910 
    },
911 
    'reg09_tv_net_x0' => {
912 
      'hdlType' => 'std_logic',
913 
      'width' => 1,
914 
    },
915 
    'reg10_td_net' => {
916 
      'hdlType' => 'std_logic_vector(31 downto 0)',
917 
      'width' => 32,
918 
    },
919 
    'reg10_td_net_x0' => {
920 
      'hdlType' => 'std_logic_vector(31 downto 0)',
921 
      'width' => 32,
922 
    },
923 
    'reg10_tv_net' => {
924 
      'hdlType' => 'std_logic',
925 
      'width' => 1,
926 
    },
927 
    'reg10_tv_net_x0' => {
928 
      'hdlType' => 'std_logic',
929 
      'width' => 1,
930 
    },
931 
    'reg11_td_net' => {
932 
      'hdlType' => 'std_logic_vector(31 downto 0)',
933 
      'width' => 32,
934 
    },
935 
    'reg11_td_net_x0' => {
936 
      'hdlType' => 'std_logic_vector(31 downto 0)',
937 
      'width' => 32,
938 
    },
939 
    'reg11_tv_net' => {
940 
      'hdlType' => 'std_logic',
941 
      'width' => 1,
942 
    },
943 
    'reg11_tv_net_x0' => {
944 
      'hdlType' => 'std_logic',
945 
      'width' => 1,
946 
    },
947 
    'reg12_td_net' => {
948 
      'hdlType' => 'std_logic_vector(31 downto 0)',
949 
      'width' => 32,
950 
    },
951 
    'reg12_td_net_x0' => {
952 
      'hdlType' => 'std_logic_vector(31 downto 0)',
953 
      'width' => 32,
954 
    },
955 
    'reg12_tv_net' => {
956 
      'hdlType' => 'std_logic',
957 
      'width' => 1,
958 
    },
959 
    'reg12_tv_net_x0' => {
960 
      'hdlType' => 'std_logic',
961 
      'width' => 1,
962 
    },
963 
    'reg13_td_net' => {
964 
      'hdlType' => 'std_logic_vector(31 downto 0)',
965 
      'width' => 32,
966 
    },
967 
    'reg13_td_net_x0' => {
968 
      'hdlType' => 'std_logic_vector(31 downto 0)',
969 
      'width' => 32,
970 
    },
971 
    'reg13_tv_net' => {
972 
      'hdlType' => 'std_logic',
973 
      'width' => 1,
974 
    },
975 
    'reg13_tv_net_x0' => {
976 
      'hdlType' => 'std_logic',
977 
      'width' => 1,
978 
    },
979 
    'reg14_td_net' => {
980 
      'hdlType' => 'std_logic_vector(31 downto 0)',
981 
      'width' => 32,
982 
    },
983 
    'reg14_td_net_x0' => {
984 
      'hdlType' => 'std_logic_vector(31 downto 0)',
985 
      'width' => 32,
986 
    },
987 
    'reg14_tv_net' => {
988 
      'hdlType' => 'std_logic',
989 
      'width' => 1,
990 
    },
991 
    'reg14_tv_net_x0' => {
992 
      'hdlType' => 'std_logic',
993 
      'width' => 1,
994 
    },
995 
    'to_register10_dout_net' => {
996 
      'hdlType' => 'std_logic',
997 
      'width' => 1,
998 
    },
999 
    'to_register11_dout_net' => {
1000 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1001 
      'width' => 32,
1002 
    },
1003 
    'to_register12_dout_net' => {
1004 
      'hdlType' => 'std_logic',
1005 
      'width' => 1,
1006 
    },
1007 
    'to_register13_dout_net' => {
1008 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1009 
      'width' => 32,
1010 
    },
1011 
    'to_register14_dout_net' => {
1012 
      'hdlType' => 'std_logic',
1013 
      'width' => 1,
1014 
    },
1015 
    'to_register15_dout_net' => {
1016 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1017 
      'width' => 32,
1018 
    },
1019 
    'to_register16_dout_net' => {
1020 
      'hdlType' => 'std_logic',
1021 
      'width' => 1,
1022 
    },
1023 
    'to_register17_dout_net' => {
1024 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1025 
      'width' => 32,
1026 
    },
1027 
    'to_register18_dout_net' => {
1028 
      'hdlType' => 'std_logic',
1029 
      'width' => 1,
1030 
    },
1031 
    'to_register19_dout_net' => {
1032 
      'hdlType' => 'std_logic',
1033 
      'width' => 1,
1034 
    },
1035 
    'to_register1_dout_net' => {
1036 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1037 
      'width' => 32,
1038 
    },
1039 
    'to_register20_dout_net' => {
1040 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1041 
      'width' => 32,
1042 
    },
1043 
    'to_register21_dout_net' => {
1044 
      'hdlType' => 'std_logic',
1045 
      'width' => 1,
1046 
    },
1047 
    'to_register22_dout_net' => {
1048 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1049 
      'width' => 32,
1050 
    },
1051 
    'to_register23_dout_net' => {
1052 
      'hdlType' => 'std_logic',
1053 
      'width' => 1,
1054 
    },
1055 
    'to_register24_dout_net' => {
1056 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1057 
      'width' => 32,
1058 
    },
1059 
    'to_register25_dout_net' => {
1060 
      'hdlType' => 'std_logic',
1061 
      'width' => 1,
1062 
    },
1063 
    'to_register26_dout_net' => {
1064 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1065 
      'width' => 32,
1066 
    },
1067 
    'to_register27_dout_net' => {
1068 
      'hdlType' => 'std_logic',
1069 
      'width' => 1,
1070 
    },
1071 
    'to_register28_dout_net' => {
1072 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1073 
      'width' => 32,
1074 
    },
1075 
    'to_register29_dout_net' => {
1076 
      'hdlType' => 'std_logic',
1077 
      'width' => 1,
1078 
    },
1079 
    'to_register2_dout_net' => {
1080 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1081 
      'width' => 32,
1082 
    },
1083 
    'to_register30_dout_net' => {
1084 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1085 
      'width' => 32,
1086 
    },
1087 
    'to_register31_dout_net' => {
1088 
      'hdlType' => 'std_logic',
1089 
      'width' => 1,
1090 
    },
1091 
    'to_register32_dout_net' => {
1092 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1093 
      'width' => 32,
1094 
    },
1095 
    'to_register33_dout_net' => {
1096 
      'hdlType' => 'std_logic',
1097 
      'width' => 1,
1098 
    },
1099 
    'to_register34_dout_net' => {
1100 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1101 
      'width' => 32,
1102 
    },
1103 
    'to_register3_dout_net' => {
1104 
      'hdlType' => 'std_logic',
1105 
      'width' => 1,
1106 
    },
1107 
    'to_register4_dout_net' => {
1108 
      'hdlType' => 'std_logic',
1109 
      'width' => 1,
1110 
    },
1111 
    'to_register5_dout_net' => {
1112 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1113 
      'width' => 32,
1114 
    },
1115 
    'to_register6_dout_net' => {
1116 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1117 
      'width' => 32,
1118 
    },
1119 
    'to_register7_dout_net' => {
1120 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1121 
      'width' => 32,
1122 
    },
1123 
    'to_register8_dout_net' => {
1124 
      'hdlType' => 'std_logic',
1125 
      'width' => 1,
1126 
    },
1127 
    'to_register9_dout_net' => {
1128 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1129 
      'width' => 32,
1130 
    },
1131 
  },
1132 
  'subblocks' => {
1133 
    'debug_in_1i' => {
1134 
      'connections' => { 'debug_in_1i' => 'debug_in_1i_net', },
1135 
      'entity' => {
1136 
        'attributes' => {
1137 
          'isGateway' => 1,
1138 
          'is_floating_block' => 1,
1139 
        },
1140 
        'entityName' => 'debug_in_1i',
1141 
        'ports' => {
1142 
          'debug_in_1i' => {
1143 
            'attributes' => {
1144 
              'bin_pt' => 0,
1145 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
1146 
              'is_floating_block' => 1,
1147 
              'is_gateway_port' => 1,
1148 
              'must_be_hdl_vector' => 1,
1149 
              'period' => 1.0,
1150 
              'port_id' => '0',
1151 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
1152 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
1153 
              'timingConstraint' => 'none',
1154 
              'type' => 'UFix_32_0',
1155 
            },
1156 
            'direction' => 'out',
1157 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1158 
            'width' => 32,
1159 
          },
1160 
        },
1161 
      },
1162 
      'entityName' => 'debug_in_1i',
1163 
    },
1164 
    'debug_in_2i' => {
1165 
      'connections' => { 'debug_in_2i' => 'debug_in_2i_net', },
1166 
      'entity' => {
1167 
        'attributes' => {
1168 
          'isGateway' => 1,
1169 
          'is_floating_block' => 1,
1170 
        },
1171 
        'entityName' => 'debug_in_2i',
1172 
        'ports' => {
1173 
          'debug_in_2i' => {
1174 
            'attributes' => {
1175 
              'bin_pt' => 0,
1176 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
1177 
              'is_floating_block' => 1,
1178 
              'is_gateway_port' => 1,
1179 
              'must_be_hdl_vector' => 1,
1180 
              'period' => 1.0,
1181 
              'port_id' => '0',
1182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
1183 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
1184 
              'timingConstraint' => 'none',
1185 
              'type' => 'UFix_32_0',
1186 
            },
1187 
            'direction' => 'out',
1188 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1189 
            'width' => 32,
1190 
          },
1191 
        },
1192 
      },
1193 
      'entityName' => 'debug_in_2i',
1194 
    },
1195 
    'debug_in_3i' => {
1196 
      'connections' => { 'debug_in_3i' => 'debug_in_3i_net', },
1197 
      'entity' => {
1198 
        'attributes' => {
1199 
          'isGateway' => 1,
1200 
          'is_floating_block' => 1,
1201 
        },
1202 
        'entityName' => 'debug_in_3i',
1203 
        'ports' => {
1204 
          'debug_in_3i' => {
1205 
            'attributes' => {
1206 
              'bin_pt' => 0,
1207 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
1208 
              'is_floating_block' => 1,
1209 
              'is_gateway_port' => 1,
1210 
              'must_be_hdl_vector' => 1,
1211 
              'period' => 1.0,
1212 
              'port_id' => '0',
1213 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
1214 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
1215 
              'timingConstraint' => 'none',
1216 
              'type' => 'UFix_32_0',
1217 
            },
1218 
            'direction' => 'out',
1219 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1220 
            'width' => 32,
1221 
          },
1222 
        },
1223 
      },
1224 
      'entityName' => 'debug_in_3i',
1225 
    },
1226 
    'debug_in_4i' => {
1227 
      'connections' => { 'debug_in_4i' => 'debug_in_4i_net', },
1228 
      'entity' => {
1229 
        'attributes' => {
1230 
          'isGateway' => 1,
1231 
          'is_floating_block' => 1,
1232 
        },
1233 
        'entityName' => 'debug_in_4i',
1234 
        'ports' => {
1235 
          'debug_in_4i' => {
1236 
            'attributes' => {
1237 
              'bin_pt' => 0,
1238 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
1239 
              'is_floating_block' => 1,
1240 
              'is_gateway_port' => 1,
1241 
              'must_be_hdl_vector' => 1,
1242 
              'period' => 1.0,
1243 
              'port_id' => '0',
1244 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
1245 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
1246 
              'timingConstraint' => 'none',
1247 
              'type' => 'UFix_32_0',
1248 
            },
1249 
            'direction' => 'out',
1250 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1251 
            'width' => 32,
1252 
          },
1253 
        },
1254 
      },
1255 
      'entityName' => 'debug_in_4i',
1256 
    },
1257 
    'default_clock_driver' => {
1258 
      'connections' => {
1259 
        'ce_1' => 'ce_1_sg',
1260 
        'clk_1' => 'clk_1_sg',
1261 
      },
1262 
      'entity' => {
1263 
        'attributes' => {
1264 
          'domain' => 'default',
1265 
          'isClkDriver' => 1,
1266 
        },
1267 
        'entityName' => 'default_clock_driver',
1268 
        'ports' => {
1269 
          'ce_1' => {
1270 
            'attributes' => {
1271 
              'domain' => 'default',
1272 
              'group' => 1,
1273 
              'isCe' => 1,
1274 
              'period' => 1.0,
1275 
              'type' => 'logic',
1276 
            },
1277 
            'direction' => 'out',
1278 
            'hdlType' => 'std_logic',
1279 
            'width' => 1,
1280 
          },
1281 
          'clk_1' => {
1282 
            'attributes' => {
1283 
              'domain' => 'default',
1284 
              'group' => 1,
1285 
              'isClk' => 1,
1286 
              'period' => 1.0,
1287 
              'type' => 'logic',
1288 
            },
1289 
            'direction' => 'out',
1290 
            'hdlType' => 'std_logic',
1291 
            'width' => 1,
1292 
          },
1293 
        },
1294 
      },
1295 
      'entityName' => 'default_clock_driver',
1296 
    },
1297 
    'dma_host2board_busy' => {
1298 
      'connections' => { 'dma_host2board_busy' => 'dma_host2board_busy_net', },
1299 
      'entity' => {
1300 
        'attributes' => {
1301 
          'isGateway' => 1,
1302 
          'is_floating_block' => 1,
1303 
        },
1304 
        'entityName' => 'dma_host2board_busy',
1305 
        'ports' => {
1306 
          'dma_host2board_busy' => {
1307 
            'attributes' => {
1308 
              'bin_pt' => 0,
1309 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
1310 
              'is_floating_block' => 1,
1311 
              'is_gateway_port' => 1,
1312 
              'must_be_hdl_vector' => 1,
1313 
              'period' => 1.0,
1314 
              'port_id' => '0',
1315 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
1316 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
1317 
              'timingConstraint' => 'none',
1318 
              'type' => 'UFix_1_0',
1319 
            },
1320 
            'direction' => 'out',
1321 
            'hdlType' => 'std_logic',
1322 
            'width' => 1,
1323 
          },
1324 
        },
1325 
      },
1326 
      'entityName' => 'dma_host2board_busy',
1327 
    },
1328 
    'dma_host2board_done' => {
1329 
      'connections' => { 'dma_host2board_done' => 'dma_host2board_done_net', },
1330 
      'entity' => {
1331 
        'attributes' => {
1332 
          'isGateway' => 1,
1333 
          'is_floating_block' => 1,
1334 
        },
1335 
        'entityName' => 'dma_host2board_done',
1336 
        'ports' => {
1337 
          'dma_host2board_done' => {
1338 
            'attributes' => {
1339 
              'bin_pt' => 0,
1340 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
1341 
              'is_floating_block' => 1,
1342 
              'is_gateway_port' => 1,
1343 
              'must_be_hdl_vector' => 1,
1344 
              'period' => 1.0,
1345 
              'port_id' => '0',
1346 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
1347 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
1348 
              'timingConstraint' => 'none',
1349 
              'type' => 'UFix_1_0',
1350 
            },
1351 
            'direction' => 'out',
1352 
            'hdlType' => 'std_logic',
1353 
            'width' => 1,
1354 
          },
1355 
        },
1356 
      },
1357 
      'entityName' => 'dma_host2board_done',
1358 
    },
1359 
    'from_register1' => {
1360 
      'connections' => { 'data_out' => 'from_register1_data_out_net', },
1361 
      'entity' => {
1362 
        'attributes' => {
1363 
          'generics' => [],
1364 
          'is_floating_block' => 1,
1365 
          'mask' => {
1366 
            'Block_Handle' => 2090.00048828125,
1367 
            'Block_handle' => 2090.00048828125,
1368 
            'MDL_Handle' => 2083.00048828125,
1369 
            'MDL_handle' => 2083.00048828125,
1370 
            'arith_type' => 2,
1371 
            'bin_pt' => 0,
1372 
            'block_config' => 'sysgen_blockset:fromreg_config',
1373 
            'block_handle' => 2090.00048828125,
1374 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1375 
            'block_type' => 'fromreg',
1376 
            'dbl_ovrd' => 0,
1377 
            'gui_display_data_type' => 1,
1378 
            'init' => 0.0,
1379 
            'init_bit_vector' => '\'b0',
1380 
            'mdl_handle' => 2083.00048828125,
1381 
            'model_handle' => 2083.00048828125,
1382 
            'n_bits' => 1,
1383 
            'ownership' => 2,
1384 
            'period' => 8.0E-9,
1385 
            'preci_type' => 1,
1386 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1387 
            'shared_memory_name' => 'register01rv',
1388 
          },
1389 
          'needs_vhdl_wrapper' => 0,
1390 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1391 
        },
1392 
        'entityName' => 'x_x61',
1393 
        'ports' => {
1394 
          'data_out' => {
1395 
            'attributes' => {
1396 
              'bin_pt' => 0,
1397 
              'is_floating_block' => 1,
1398 
              'must_be_hdl_vector' => 1,
1399 
              'period' => 1.0,
1400 
              'port_id' => '0',
1401 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
1402 
              'type' => 'UFix_1_0',
1403 
            },
1404 
            'direction' => 'out',
1405 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1406 
            'width' => 1,
1407 
          },
1408 
        },
1409 
      },
1410 
      'entityName' => 'x_x61',
1411 
    },
1412 
    'from_register10' => {
1413 
      'connections' => { 'data_out' => 'from_register10_data_out_net', },
1414 
      'entity' => {
1415 
        'attributes' => {
1416 
          'generics' => [],
1417 
          'is_floating_block' => 1,
1418 
          'mask' => {
1419 
            'Block_Handle' => 2091.00048828125,
1420 
            'Block_handle' => 2091.00048828125,
1421 
            'MDL_Handle' => 2083.00048828125,
1422 
            'MDL_handle' => 2083.00048828125,
1423 
            'arith_type' => 2,
1424 
            'bin_pt' => 0,
1425 
            'block_config' => 'sysgen_blockset:fromreg_config',
1426 
            'block_handle' => 2091.00048828125,
1427 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1428 
            'block_type' => 'fromreg',
1429 
            'dbl_ovrd' => 0,
1430 
            'gui_display_data_type' => 1,
1431 
            'init' => 0.0,
1432 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1433 
            'mdl_handle' => 2083.00048828125,
1434 
            'model_handle' => 2083.00048828125,
1435 
            'n_bits' => 32,
1436 
            'ownership' => 2,
1437 
            'period' => 8.0E-9,
1438 
            'preci_type' => 1,
1439 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1440 
            'shared_memory_name' => 'register05rd',
1441 
          },
1442 
          'needs_vhdl_wrapper' => 0,
1443 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1444 
        },
1445 
        'entityName' => 'x_x62',
1446 
        'ports' => {
1447 
          'data_out' => {
1448 
            'attributes' => {
1449 
              'bin_pt' => 0,
1450 
              'is_floating_block' => 1,
1451 
              'must_be_hdl_vector' => 1,
1452 
              'period' => 1.0,
1453 
              'port_id' => '0',
1454 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
1455 
              'type' => 'UFix_32_0',
1456 
            },
1457 
            'direction' => 'out',
1458 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1459 
            'width' => 32,
1460 
          },
1461 
        },
1462 
      },
1463 
      'entityName' => 'x_x62',
1464 
    },
1465 
    'from_register11' => {
1466 
      'connections' => { 'data_out' => 'from_register11_data_out_net', },
1467 
      'entity' => {
1468 
        'attributes' => {
1469 
          'generics' => [],
1470 
          'is_floating_block' => 1,
1471 
          'mask' => {
1472 
            'Block_Handle' => 2092.00048828125,
1473 
            'Block_handle' => 2092.00048828125,
1474 
            'MDL_Handle' => 2083.00048828125,
1475 
            'MDL_handle' => 2083.00048828125,
1476 
            'arith_type' => 2,
1477 
            'bin_pt' => 0,
1478 
            'block_config' => 'sysgen_blockset:fromreg_config',
1479 
            'block_handle' => 2092.00048828125,
1480 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1481 
            'block_type' => 'fromreg',
1482 
            'dbl_ovrd' => 0,
1483 
            'gui_display_data_type' => 1,
1484 
            'init' => 0.0,
1485 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1486 
            'mdl_handle' => 2083.00048828125,
1487 
            'model_handle' => 2083.00048828125,
1488 
            'n_bits' => 32,
1489 
            'ownership' => 2,
1490 
            'period' => 8.0E-9,
1491 
            'preci_type' => 1,
1492 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1493 
            'shared_memory_name' => 'register06rd',
1494 
          },
1495 
          'needs_vhdl_wrapper' => 0,
1496 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1497 
        },
1498 
        'entityName' => 'x_x63',
1499 
        'ports' => {
1500 
          'data_out' => {
1501 
            'attributes' => {
1502 
              'bin_pt' => 0,
1503 
              'is_floating_block' => 1,
1504 
              'must_be_hdl_vector' => 1,
1505 
              'period' => 1.0,
1506 
              'port_id' => '0',
1507 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
1508 
              'type' => 'UFix_32_0',
1509 
            },
1510 
            'direction' => 'out',
1511 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1512 
            'width' => 32,
1513 
          },
1514 
        },
1515 
      },
1516 
      'entityName' => 'x_x63',
1517 
    },
1518 
    'from_register12' => {
1519 
      'connections' => { 'data_out' => 'from_register12_data_out_net', },
1520 
      'entity' => {
1521 
        'attributes' => {
1522 
          'generics' => [],
1523 
          'is_floating_block' => 1,
1524 
          'mask' => {
1525 
            'Block_Handle' => 2093.00048828125,
1526 
            'Block_handle' => 2093.00048828125,
1527 
            'MDL_Handle' => 2083.00048828125,
1528 
            'MDL_handle' => 2083.00048828125,
1529 
            'arith_type' => 2,
1530 
            'bin_pt' => 0,
1531 
            'block_config' => 'sysgen_blockset:fromreg_config',
1532 
            'block_handle' => 2093.00048828125,
1533 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1534 
            'block_type' => 'fromreg',
1535 
            'dbl_ovrd' => 0,
1536 
            'gui_display_data_type' => 1,
1537 
            'init' => 0.0,
1538 
            'init_bit_vector' => '\'b0',
1539 
            'mdl_handle' => 2083.00048828125,
1540 
            'model_handle' => 2083.00048828125,
1541 
            'n_bits' => 1,
1542 
            'ownership' => 2,
1543 
            'period' => 8.0E-9,
1544 
            'preci_type' => 1,
1545 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1546 
            'shared_memory_name' => 'register06rv',
1547 
          },
1548 
          'needs_vhdl_wrapper' => 0,
1549 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1550 
        },
1551 
        'entityName' => 'x_x64',
1552 
        'ports' => {
1553 
          'data_out' => {
1554 
            'attributes' => {
1555 
              'bin_pt' => 0,
1556 
              'is_floating_block' => 1,
1557 
              'must_be_hdl_vector' => 1,
1558 
              'period' => 1.0,
1559 
              'port_id' => '0',
1560 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
1561 
              'type' => 'UFix_1_0',
1562 
            },
1563 
            'direction' => 'out',
1564 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1565 
            'width' => 1,
1566 
          },
1567 
        },
1568 
      },
1569 
      'entityName' => 'x_x64',
1570 
    },
1571 
    'from_register13' => {
1572 
      'connections' => { 'data_out' => 'from_register13_data_out_net', },
1573 
      'entity' => {
1574 
        'attributes' => {
1575 
          'generics' => [],
1576 
          'is_floating_block' => 1,
1577 
          'mask' => {
1578 
            'Block_Handle' => 2094.00048828125,
1579 
            'Block_handle' => 2094.00048828125,
1580 
            'MDL_Handle' => 2083.00048828125,
1581 
            'MDL_handle' => 2083.00048828125,
1582 
            'arith_type' => 2,
1583 
            'bin_pt' => 0,
1584 
            'block_config' => 'sysgen_blockset:fromreg_config',
1585 
            'block_handle' => 2094.00048828125,
1586 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
1587 
            'block_type' => 'fromreg',
1588 
            'dbl_ovrd' => 0,
1589 
            'gui_display_data_type' => 1,
1590 
            'init' => 0.0,
1591 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1592 
            'mdl_handle' => 2083.00048828125,
1593 
            'model_handle' => 2083.00048828125,
1594 
            'n_bits' => 32,
1595 
            'ownership' => 2,
1596 
            'period' => 8.0E-9,
1597 
            'preci_type' => 1,
1598 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1599 
            'shared_memory_name' => 'register07rd',
1600 
          },
1601 
          'needs_vhdl_wrapper' => 0,
1602 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
1603 
        },
1604 
        'entityName' => 'x_x65',
1605 
        'ports' => {
1606 
          'data_out' => {
1607 
            'attributes' => {
1608 
              'bin_pt' => 0,
1609 
              'is_floating_block' => 1,
1610 
              'must_be_hdl_vector' => 1,
1611 
              'period' => 1.0,
1612 
              'port_id' => '0',
1613 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
1614 
              'type' => 'UFix_32_0',
1615 
            },
1616 
            'direction' => 'out',
1617 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1618 
            'width' => 32,
1619 
          },
1620 
        },
1621 
      },
1622 
      'entityName' => 'x_x65',
1623 
    },
1624 
    'from_register14' => {
1625 
      'connections' => { 'data_out' => 'from_register14_data_out_net', },
1626 
      'entity' => {
1627 
        'attributes' => {
1628 
          'generics' => [],
1629 
          'is_floating_block' => 1,
1630 
          'mask' => {
1631 
            'Block_Handle' => 2095.00048828125,
1632 
            'Block_handle' => 2095.00048828125,
1633 
            'MDL_Handle' => 2083.00048828125,
1634 
            'MDL_handle' => 2083.00048828125,
1635 
            'arith_type' => 2,
1636 
            'bin_pt' => 0,
1637 
            'block_config' => 'sysgen_blockset:fromreg_config',
1638 
            'block_handle' => 2095.00048828125,
1639 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
1640 
            'block_type' => 'fromreg',
1641 
            'dbl_ovrd' => 0,
1642 
            'gui_display_data_type' => 1,
1643 
            'init' => 0.0,
1644 
            'init_bit_vector' => '\'b0',
1645 
            'mdl_handle' => 2083.00048828125,
1646 
            'model_handle' => 2083.00048828125,
1647 
            'n_bits' => 1,
1648 
            'ownership' => 2,
1649 
            'period' => 8.0E-9,
1650 
            'preci_type' => 1,
1651 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1652 
            'shared_memory_name' => 'register07rv',
1653 
          },
1654 
          'needs_vhdl_wrapper' => 0,
1655 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
1656 
        },
1657 
        'entityName' => 'x_x66',
1658 
        'ports' => {
1659 
          'data_out' => {
1660 
            'attributes' => {
1661 
              'bin_pt' => 0,
1662 
              'is_floating_block' => 1,
1663 
              'must_be_hdl_vector' => 1,
1664 
              'period' => 1.0,
1665 
              'port_id' => '0',
1666 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
1667 
              'type' => 'UFix_1_0',
1668 
            },
1669 
            'direction' => 'out',
1670 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1671 
            'width' => 1,
1672 
          },
1673 
        },
1674 
      },
1675 
      'entityName' => 'x_x66',
1676 
    },
1677 
    'from_register15' => {
1678 
      'connections' => { 'data_out' => 'from_register15_data_out_net', },
1679 
      'entity' => {
1680 
        'attributes' => {
1681 
          'generics' => [],
1682 
          'is_floating_block' => 1,
1683 
          'mask' => {
1684 
            'Block_Handle' => 2096.00048828125,
1685 
            'Block_handle' => 2096.00048828125,
1686 
            'MDL_Handle' => 2083.00048828125,
1687 
            'MDL_handle' => 2083.00048828125,
1688 
            'arith_type' => 2,
1689 
            'bin_pt' => 0,
1690 
            'block_config' => 'sysgen_blockset:fromreg_config',
1691 
            'block_handle' => 2096.00048828125,
1692 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
1693 
            'block_type' => 'fromreg',
1694 
            'dbl_ovrd' => 0,
1695 
            'gui_display_data_type' => 1,
1696 
            'init' => 0.0,
1697 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1698 
            'mdl_handle' => 2083.00048828125,
1699 
            'model_handle' => 2083.00048828125,
1700 
            'n_bits' => 32,
1701 
            'ownership' => 2,
1702 
            'period' => 8.0E-9,
1703 
            'preci_type' => 1,
1704 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1705 
            'shared_memory_name' => 'register08rd',
1706 
          },
1707 
          'needs_vhdl_wrapper' => 0,
1708 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
1709 
        },
1710 
        'entityName' => 'x_x67',
1711 
        'ports' => {
1712 
          'data_out' => {
1713 
            'attributes' => {
1714 
              'bin_pt' => 0,
1715 
              'is_floating_block' => 1,
1716 
              'must_be_hdl_vector' => 1,
1717 
              'period' => 1.0,
1718 
              'port_id' => '0',
1719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
1720 
              'type' => 'UFix_32_0',
1721 
            },
1722 
            'direction' => 'out',
1723 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1724 
            'width' => 32,
1725 
          },
1726 
        },
1727 
      },
1728 
      'entityName' => 'x_x67',
1729 
    },
1730 
    'from_register16' => {
1731 
      'connections' => { 'data_out' => 'from_register16_data_out_net', },
1732 
      'entity' => {
1733 
        'attributes' => {
1734 
          'generics' => [],
1735 
          'is_floating_block' => 1,
1736 
          'mask' => {
1737 
            'Block_Handle' => 2097.00048828125,
1738 
            'Block_handle' => 2097.00048828125,
1739 
            'MDL_Handle' => 2083.00048828125,
1740 
            'MDL_handle' => 2083.00048828125,
1741 
            'arith_type' => 2,
1742 
            'bin_pt' => 0,
1743 
            'block_config' => 'sysgen_blockset:fromreg_config',
1744 
            'block_handle' => 2097.00048828125,
1745 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
1746 
            'block_type' => 'fromreg',
1747 
            'dbl_ovrd' => 0,
1748 
            'gui_display_data_type' => 1,
1749 
            'init' => 0.0,
1750 
            'init_bit_vector' => '\'b0',
1751 
            'mdl_handle' => 2083.00048828125,
1752 
            'model_handle' => 2083.00048828125,
1753 
            'n_bits' => 1,
1754 
            'ownership' => 2,
1755 
            'period' => 8.0E-9,
1756 
            'preci_type' => 1,
1757 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1758 
            'shared_memory_name' => 'register08rv',
1759 
          },
1760 
          'needs_vhdl_wrapper' => 0,
1761 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
1762 
        },
1763 
        'entityName' => 'x_x68',
1764 
        'ports' => {
1765 
          'data_out' => {
1766 
            'attributes' => {
1767 
              'bin_pt' => 0,
1768 
              'is_floating_block' => 1,
1769 
              'must_be_hdl_vector' => 1,
1770 
              'period' => 1.0,
1771 
              'port_id' => '0',
1772 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
1773 
              'type' => 'UFix_1_0',
1774 
            },
1775 
            'direction' => 'out',
1776 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1777 
            'width' => 1,
1778 
          },
1779 
        },
1780 
      },
1781 
      'entityName' => 'x_x68',
1782 
    },
1783 
    'from_register17' => {
1784 
      'connections' => { 'data_out' => 'from_register17_data_out_net', },
1785 
      'entity' => {
1786 
        'attributes' => {
1787 
          'generics' => [],
1788 
          'is_floating_block' => 1,
1789 
          'mask' => {
1790 
            'Block_Handle' => 2098.00048828125,
1791 
            'Block_handle' => 2098.00048828125,
1792 
            'MDL_Handle' => 2083.00048828125,
1793 
            'MDL_handle' => 2083.00048828125,
1794 
            'arith_type' => 2,
1795 
            'bin_pt' => 0,
1796 
            'block_config' => 'sysgen_blockset:fromreg_config',
1797 
            'block_handle' => 2098.00048828125,
1798 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
1799 
            'block_type' => 'fromreg',
1800 
            'dbl_ovrd' => 0,
1801 
            'gui_display_data_type' => 1,
1802 
            'init' => 0.0,
1803 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1804 
            'mdl_handle' => 2083.00048828125,
1805 
            'model_handle' => 2083.00048828125,
1806 
            'n_bits' => 32,
1807 
            'ownership' => 2,
1808 
            'period' => 8.0E-9,
1809 
            'preci_type' => 1,
1810 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1811 
            'shared_memory_name' => 'register09rd',
1812 
          },
1813 
          'needs_vhdl_wrapper' => 0,
1814 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
1815 
        },
1816 
        'entityName' => 'x_x69',
1817 
        'ports' => {
1818 
          'data_out' => {
1819 
            'attributes' => {
1820 
              'bin_pt' => 0,
1821 
              'is_floating_block' => 1,
1822 
              'must_be_hdl_vector' => 1,
1823 
              'period' => 1.0,
1824 
              'port_id' => '0',
1825 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
1826 
              'type' => 'UFix_32_0',
1827 
            },
1828 
            'direction' => 'out',
1829 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1830 
            'width' => 32,
1831 
          },
1832 
        },
1833 
      },
1834 
      'entityName' => 'x_x69',
1835 
    },
1836 
    'from_register18' => {
1837 
      'connections' => { 'data_out' => 'from_register18_data_out_net', },
1838 
      'entity' => {
1839 
        'attributes' => {
1840 
          'generics' => [],
1841 
          'is_floating_block' => 1,
1842 
          'mask' => {
1843 
            'Block_Handle' => 2099.00048828125,
1844 
            'Block_handle' => 2099.00048828125,
1845 
            'MDL_Handle' => 2083.00048828125,
1846 
            'MDL_handle' => 2083.00048828125,
1847 
            'arith_type' => 2,
1848 
            'bin_pt' => 0,
1849 
            'block_config' => 'sysgen_blockset:fromreg_config',
1850 
            'block_handle' => 2099.00048828125,
1851 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
1852 
            'block_type' => 'fromreg',
1853 
            'dbl_ovrd' => 0,
1854 
            'gui_display_data_type' => 1,
1855 
            'init' => 0.0,
1856 
            'init_bit_vector' => '\'b0',
1857 
            'mdl_handle' => 2083.00048828125,
1858 
            'model_handle' => 2083.00048828125,
1859 
            'n_bits' => 1,
1860 
            'ownership' => 2,
1861 
            'period' => 8.0E-9,
1862 
            'preci_type' => 1,
1863 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1864 
            'shared_memory_name' => 'register09rv',
1865 
          },
1866 
          'needs_vhdl_wrapper' => 0,
1867 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
1868 
        },
1869 
        'entityName' => 'x_x70',
1870 
        'ports' => {
1871 
          'data_out' => {
1872 
            'attributes' => {
1873 
              'bin_pt' => 0,
1874 
              'is_floating_block' => 1,
1875 
              'must_be_hdl_vector' => 1,
1876 
              'period' => 1.0,
1877 
              'port_id' => '0',
1878 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
1879 
              'type' => 'UFix_1_0',
1880 
            },
1881 
            'direction' => 'out',
1882 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1883 
            'width' => 1,
1884 
          },
1885 
        },
1886 
      },
1887 
      'entityName' => 'x_x70',
1888 
    },
1889 
    'from_register19' => {
1890 
      'connections' => { 'data_out' => 'from_register19_data_out_net', },
1891 
      'entity' => {
1892 
        'attributes' => {
1893 
          'generics' => [],
1894 
          'is_floating_block' => 1,
1895 
          'mask' => {
1896 
            'Block_Handle' => 2100.00048828125,
1897 
            'Block_handle' => 2100.00048828125,
1898 
            'MDL_Handle' => 2083.00048828125,
1899 
            'MDL_handle' => 2083.00048828125,
1900 
            'arith_type' => 2,
1901 
            'bin_pt' => 0,
1902 
            'block_config' => 'sysgen_blockset:fromreg_config',
1903 
            'block_handle' => 2100.00048828125,
1904 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
1905 
            'block_type' => 'fromreg',
1906 
            'dbl_ovrd' => 0,
1907 
            'gui_display_data_type' => 1,
1908 
            'init' => 0.0,
1909 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1910 
            'mdl_handle' => 2083.00048828125,
1911 
            'model_handle' => 2083.00048828125,
1912 
            'n_bits' => 32,
1913 
            'ownership' => 2,
1914 
            'period' => 8.0E-9,
1915 
            'preci_type' => 1,
1916 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1917 
            'shared_memory_name' => 'register10rd',
1918 
          },
1919 
          'needs_vhdl_wrapper' => 0,
1920 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
1921 
        },
1922 
        'entityName' => 'x_x71',
1923 
        'ports' => {
1924 
          'data_out' => {
1925 
            'attributes' => {
1926 
              'bin_pt' => 0,
1927 
              'is_floating_block' => 1,
1928 
              'must_be_hdl_vector' => 1,
1929 
              'period' => 1.0,
1930 
              'port_id' => '0',
1931 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
1932 
              'type' => 'UFix_32_0',
1933 
            },
1934 
            'direction' => 'out',
1935 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1936 
            'width' => 32,
1937 
          },
1938 
        },
1939 
      },
1940 
      'entityName' => 'x_x71',
1941 
    },
1942 
    'from_register2' => {
1943 
      'connections' => { 'data_out' => 'from_register2_data_out_net', },
1944 
      'entity' => {
1945 
        'attributes' => {
1946 
          'generics' => [],
1947 
          'is_floating_block' => 1,
1948 
          'mask' => {
1949 
            'Block_Handle' => 2101.00048828125,
1950 
            'Block_handle' => 2101.00048828125,
1951 
            'MDL_Handle' => 2083.00048828125,
1952 
            'MDL_handle' => 2083.00048828125,
1953 
            'arith_type' => 2,
1954 
            'bin_pt' => 0,
1955 
            'block_config' => 'sysgen_blockset:fromreg_config',
1956 
            'block_handle' => 2101.00048828125,
1957 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
1958 
            'block_type' => 'fromreg',
1959 
            'dbl_ovrd' => 0,
1960 
            'gui_display_data_type' => 1,
1961 
            'init' => 0.0,
1962 
            'init_bit_vector' => '\'b0',
1963 
            'mdl_handle' => 2083.00048828125,
1964 
            'model_handle' => 2083.00048828125,
1965 
            'n_bits' => 1,
1966 
            'ownership' => 2,
1967 
            'period' => 8.0E-9,
1968 
            'preci_type' => 1,
1969 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1970 
            'shared_memory_name' => 'register02rv',
1971 
          },
1972 
          'needs_vhdl_wrapper' => 0,
1973 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
1974 
        },
1975 
        'entityName' => 'x_x72',
1976 
        'ports' => {
1977 
          'data_out' => {
1978 
            'attributes' => {
1979 
              'bin_pt' => 0,
1980 
              'is_floating_block' => 1,
1981 
              'must_be_hdl_vector' => 1,
1982 
              'period' => 1.0,
1983 
              'port_id' => '0',
1984 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
1985 
              'type' => 'UFix_1_0',
1986 
            },
1987 
            'direction' => 'out',
1988 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1989 
            'width' => 1,
1990 
          },
1991 
        },
1992 
      },
1993 
      'entityName' => 'x_x72',
1994 
    },
1995 
    'from_register20' => {
1996 
      'connections' => { 'data_out' => 'from_register20_data_out_net', },
1997 
      'entity' => {
1998 
        'attributes' => {
1999 
          'generics' => [],
2000 
          'is_floating_block' => 1,
2001 
          'mask' => {
2002 
            'Block_Handle' => 2102.00048828125,
2003 
            'Block_handle' => 2102.00048828125,
2004 
            'MDL_Handle' => 2083.00048828125,
2005 
            'MDL_handle' => 2083.00048828125,
2006 
            'arith_type' => 2,
2007 
            'bin_pt' => 0,
2008 
            'block_config' => 'sysgen_blockset:fromreg_config',
2009 
            'block_handle' => 2102.00048828125,
2010 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2011 
            'block_type' => 'fromreg',
2012 
            'dbl_ovrd' => 0,
2013 
            'gui_display_data_type' => 1,
2014 
            'init' => 0.0,
2015 
            'init_bit_vector' => '\'b0',
2016 
            'mdl_handle' => 2083.00048828125,
2017 
            'model_handle' => 2083.00048828125,
2018 
            'n_bits' => 1,
2019 
            'ownership' => 2,
2020 
            'period' => 8.0E-9,
2021 
            'preci_type' => 1,
2022 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2023 
            'shared_memory_name' => 'register10rv',
2024 
          },
2025 
          'needs_vhdl_wrapper' => 0,
2026 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2027 
        },
2028 
        'entityName' => 'x_x73',
2029 
        'ports' => {
2030 
          'data_out' => {
2031 
            'attributes' => {
2032 
              'bin_pt' => 0,
2033 
              'is_floating_block' => 1,
2034 
              'must_be_hdl_vector' => 1,
2035 
              'period' => 1.0,
2036 
              'port_id' => '0',
2037 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
2038 
              'type' => 'UFix_1_0',
2039 
            },
2040 
            'direction' => 'out',
2041 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2042 
            'width' => 1,
2043 
          },
2044 
        },
2045 
      },
2046 
      'entityName' => 'x_x73',
2047 
    },
2048 
    'from_register21' => {
2049 
      'connections' => { 'data_out' => 'from_register21_data_out_net', },
2050 
      'entity' => {
2051 
        'attributes' => {
2052 
          'generics' => [],
2053 
          'is_floating_block' => 1,
2054 
          'mask' => {
2055 
            'Block_Handle' => 2103.00048828125,
2056 
            'Block_handle' => 2103.00048828125,
2057 
            'MDL_Handle' => 2083.00048828125,
2058 
            'MDL_handle' => 2083.00048828125,
2059 
            'arith_type' => 2,
2060 
            'bin_pt' => 0,
2061 
            'block_config' => 'sysgen_blockset:fromreg_config',
2062 
            'block_handle' => 2103.00048828125,
2063 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2064 
            'block_type' => 'fromreg',
2065 
            'dbl_ovrd' => 0,
2066 
            'gui_display_data_type' => 1,
2067 
            'init' => 0.0,
2068 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2069 
            'mdl_handle' => 2083.00048828125,
2070 
            'model_handle' => 2083.00048828125,
2071 
            'n_bits' => 32,
2072 
            'ownership' => 2,
2073 
            'period' => 8.0E-9,
2074 
            'preci_type' => 1,
2075 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2076 
            'shared_memory_name' => 'register11rd',
2077 
          },
2078 
          'needs_vhdl_wrapper' => 0,
2079 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2080 
        },
2081 
        'entityName' => 'x_x74',
2082 
        'ports' => {
2083 
          'data_out' => {
2084 
            'attributes' => {
2085 
              'bin_pt' => 0,
2086 
              'is_floating_block' => 1,
2087 
              'must_be_hdl_vector' => 1,
2088 
              'period' => 1.0,
2089 
              'port_id' => '0',
2090 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
2091 
              'type' => 'UFix_32_0',
2092 
            },
2093 
            'direction' => 'out',
2094 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2095 
            'width' => 32,
2096 
          },
2097 
        },
2098 
      },
2099 
      'entityName' => 'x_x74',
2100 
    },
2101 
    'from_register22' => {
2102 
      'connections' => { 'data_out' => 'from_register22_data_out_net', },
2103 
      'entity' => {
2104 
        'attributes' => {
2105 
          'generics' => [],
2106 
          'is_floating_block' => 1,
2107 
          'mask' => {
2108 
            'Block_Handle' => 2104.00048828125,
2109 
            'Block_handle' => 2104.00048828125,
2110 
            'MDL_Handle' => 2083.00048828125,
2111 
            'MDL_handle' => 2083.00048828125,
2112 
            'arith_type' => 2,
2113 
            'bin_pt' => 0,
2114 
            'block_config' => 'sysgen_blockset:fromreg_config',
2115 
            'block_handle' => 2104.00048828125,
2116 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2117 
            'block_type' => 'fromreg',
2118 
            'dbl_ovrd' => 0,
2119 
            'gui_display_data_type' => 1,
2120 
            'init' => 0.0,
2121 
            'init_bit_vector' => '\'b0',
2122 
            'mdl_handle' => 2083.00048828125,
2123 
            'model_handle' => 2083.00048828125,
2124 
            'n_bits' => 1,
2125 
            'ownership' => 2,
2126 
            'period' => 8.0E-9,
2127 
            'preci_type' => 1,
2128 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2129 
            'shared_memory_name' => 'register11rv',
2130 
          },
2131 
          'needs_vhdl_wrapper' => 0,
2132 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2133 
        },
2134 
        'entityName' => 'x_x75',
2135 
        'ports' => {
2136 
          'data_out' => {
2137 
            'attributes' => {
2138 
              'bin_pt' => 0,
2139 
              'is_floating_block' => 1,
2140 
              'must_be_hdl_vector' => 1,
2141 
              'period' => 1.0,
2142 
              'port_id' => '0',
2143 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
2144 
              'type' => 'UFix_1_0',
2145 
            },
2146 
            'direction' => 'out',
2147 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2148 
            'width' => 1,
2149 
          },
2150 
        },
2151 
      },
2152 
      'entityName' => 'x_x75',
2153 
    },
2154 
    'from_register23' => {
2155 
      'connections' => { 'data_out' => 'from_register23_data_out_net', },
2156 
      'entity' => {
2157 
        'attributes' => {
2158 
          'generics' => [],
2159 
          'is_floating_block' => 1,
2160 
          'mask' => {
2161 
            'Block_Handle' => 2105.00048828125,
2162 
            'Block_handle' => 2105.00048828125,
2163 
            'MDL_Handle' => 2083.00048828125,
2164 
            'MDL_handle' => 2083.00048828125,
2165 
            'arith_type' => 2,
2166 
            'bin_pt' => 0,
2167 
            'block_config' => 'sysgen_blockset:fromreg_config',
2168 
            'block_handle' => 2105.00048828125,
2169 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2170 
            'block_type' => 'fromreg',
2171 
            'dbl_ovrd' => 0,
2172 
            'gui_display_data_type' => 1,
2173 
            'init' => 0.0,
2174 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2175 
            'mdl_handle' => 2083.00048828125,
2176 
            'model_handle' => 2083.00048828125,
2177 
            'n_bits' => 32,
2178 
            'ownership' => 2,
2179 
            'period' => 8.0E-9,
2180 
            'preci_type' => 1,
2181 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2182 
            'shared_memory_name' => 'register12rd',
2183 
          },
2184 
          'needs_vhdl_wrapper' => 0,
2185 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2186 
        },
2187 
        'entityName' => 'x_x76',
2188 
        'ports' => {
2189 
          'data_out' => {
2190 
            'attributes' => {
2191 
              'bin_pt' => 0,
2192 
              'is_floating_block' => 1,
2193 
              'must_be_hdl_vector' => 1,
2194 
              'period' => 1.0,
2195 
              'port_id' => '0',
2196 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
2197 
              'type' => 'UFix_32_0',
2198 
            },
2199 
            'direction' => 'out',
2200 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2201 
            'width' => 32,
2202 
          },
2203 
        },
2204 
      },
2205 
      'entityName' => 'x_x76',
2206 
    },
2207 
    'from_register24' => {
2208 
      'connections' => { 'data_out' => 'from_register24_data_out_net', },
2209 
      'entity' => {
2210 
        'attributes' => {
2211 
          'generics' => [],
2212 
          'is_floating_block' => 1,
2213 
          'mask' => {
2214 
            'Block_Handle' => 2106.00048828125,
2215 
            'Block_handle' => 2106.00048828125,
2216 
            'MDL_Handle' => 2083.00048828125,
2217 
            'MDL_handle' => 2083.00048828125,
2218 
            'arith_type' => 2,
2219 
            'bin_pt' => 0,
2220 
            'block_config' => 'sysgen_blockset:fromreg_config',
2221 
            'block_handle' => 2106.00048828125,
2222 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2223 
            'block_type' => 'fromreg',
2224 
            'dbl_ovrd' => 0,
2225 
            'gui_display_data_type' => 1,
2226 
            'init' => 0.0,
2227 
            'init_bit_vector' => '\'b0',
2228 
            'mdl_handle' => 2083.00048828125,
2229 
            'model_handle' => 2083.00048828125,
2230 
            'n_bits' => 1,
2231 
            'ownership' => 2,
2232 
            'period' => 8.0E-9,
2233 
            'preci_type' => 1,
2234 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2235 
            'shared_memory_name' => 'register12rv',
2236 
          },
2237 
          'needs_vhdl_wrapper' => 0,
2238 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2239 
        },
2240 
        'entityName' => 'x_x77',
2241 
        'ports' => {
2242 
          'data_out' => {
2243 
            'attributes' => {
2244 
              'bin_pt' => 0,
2245 
              'is_floating_block' => 1,
2246 
              'must_be_hdl_vector' => 1,
2247 
              'period' => 1.0,
2248 
              'port_id' => '0',
2249 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
2250 
              'type' => 'UFix_1_0',
2251 
            },
2252 
            'direction' => 'out',
2253 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2254 
            'width' => 1,
2255 
          },
2256 
        },
2257 
      },
2258 
      'entityName' => 'x_x77',
2259 
    },
2260 
    'from_register25' => {
2261 
      'connections' => { 'data_out' => 'from_register25_data_out_net', },
2262 
      'entity' => {
2263 
        'attributes' => {
2264 
          'generics' => [],
2265 
          'is_floating_block' => 1,
2266 
          'mask' => {
2267 
            'Block_Handle' => 2107.00048828125,
2268 
            'Block_handle' => 2107.00048828125,
2269 
            'MDL_Handle' => 2083.00048828125,
2270 
            'MDL_handle' => 2083.00048828125,
2271 
            'arith_type' => 2,
2272 
            'bin_pt' => 0,
2273 
            'block_config' => 'sysgen_blockset:fromreg_config',
2274 
            'block_handle' => 2107.00048828125,
2275 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2276 
            'block_type' => 'fromreg',
2277 
            'dbl_ovrd' => 0,
2278 
            'gui_display_data_type' => 1,
2279 
            'init' => 0.0,
2280 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2281 
            'mdl_handle' => 2083.00048828125,
2282 
            'model_handle' => 2083.00048828125,
2283 
            'n_bits' => 32,
2284 
            'ownership' => 2,
2285 
            'period' => 8.0E-9,
2286 
            'preci_type' => 1,
2287 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2288 
            'shared_memory_name' => 'register13rd',
2289 
          },
2290 
          'needs_vhdl_wrapper' => 0,
2291 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2292 
        },
2293 
        'entityName' => 'x_x78',
2294 
        'ports' => {
2295 
          'data_out' => {
2296 
            'attributes' => {
2297 
              'bin_pt' => 0,
2298 
              'is_floating_block' => 1,
2299 
              'must_be_hdl_vector' => 1,
2300 
              'period' => 1.0,
2301 
              'port_id' => '0',
2302 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
2303 
              'type' => 'UFix_32_0',
2304 
            },
2305 
            'direction' => 'out',
2306 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2307 
            'width' => 32,
2308 
          },
2309 
        },
2310 
      },
2311 
      'entityName' => 'x_x78',
2312 
    },
2313 
    'from_register26' => {
2314 
      'connections' => { 'data_out' => 'from_register26_data_out_net', },
2315 
      'entity' => {
2316 
        'attributes' => {
2317 
          'generics' => [],
2318 
          'is_floating_block' => 1,
2319 
          'mask' => {
2320 
            'Block_Handle' => 2108.00048828125,
2321 
            'Block_handle' => 2108.00048828125,
2322 
            'MDL_Handle' => 2083.00048828125,
2323 
            'MDL_handle' => 2083.00048828125,
2324 
            'arith_type' => 2,
2325 
            'bin_pt' => 0,
2326 
            'block_config' => 'sysgen_blockset:fromreg_config',
2327 
            'block_handle' => 2108.00048828125,
2328 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2329 
            'block_type' => 'fromreg',
2330 
            'dbl_ovrd' => 0,
2331 
            'gui_display_data_type' => 1,
2332 
            'init' => 0.0,
2333 
            'init_bit_vector' => '\'b0',
2334 
            'mdl_handle' => 2083.00048828125,
2335 
            'model_handle' => 2083.00048828125,
2336 
            'n_bits' => 1,
2337 
            'ownership' => 2,
2338 
            'period' => 8.0E-9,
2339 
            'preci_type' => 1,
2340 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2341 
            'shared_memory_name' => 'register13rv',
2342 
          },
2343 
          'needs_vhdl_wrapper' => 0,
2344 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2345 
        },
2346 
        'entityName' => 'x_x79',
2347 
        'ports' => {
2348 
          'data_out' => {
2349 
            'attributes' => {
2350 
              'bin_pt' => 0,
2351 
              'is_floating_block' => 1,
2352 
              'must_be_hdl_vector' => 1,
2353 
              'period' => 1.0,
2354 
              'port_id' => '0',
2355 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
2356 
              'type' => 'UFix_1_0',
2357 
            },
2358 
            'direction' => 'out',
2359 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2360 
            'width' => 1,
2361 
          },
2362 
        },
2363 
      },
2364 
      'entityName' => 'x_x79',
2365 
    },
2366 
    'from_register27' => {
2367 
      'connections' => { 'data_out' => 'from_register27_data_out_net', },
2368 
      'entity' => {
2369 
        'attributes' => {
2370 
          'generics' => [],
2371 
          'is_floating_block' => 1,
2372 
          'mask' => {
2373 
            'Block_Handle' => 2109.00048828125,
2374 
            'Block_handle' => 2109.00048828125,
2375 
            'MDL_Handle' => 2083.00048828125,
2376 
            'MDL_handle' => 2083.00048828125,
2377 
            'arith_type' => 2,
2378 
            'bin_pt' => 0,
2379 
            'block_config' => 'sysgen_blockset:fromreg_config',
2380 
            'block_handle' => 2109.00048828125,
2381 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2382 
            'block_type' => 'fromreg',
2383 
            'dbl_ovrd' => 0,
2384 
            'gui_display_data_type' => 1,
2385 
            'init' => 0.0,
2386 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2387 
            'mdl_handle' => 2083.00048828125,
2388 
            'model_handle' => 2083.00048828125,
2389 
            'n_bits' => 32,
2390 
            'ownership' => 2,
2391 
            'period' => 8.0E-9,
2392 
            'preci_type' => 1,
2393 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2394 
            'shared_memory_name' => 'register14rd',
2395 
          },
2396 
          'needs_vhdl_wrapper' => 0,
2397 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2398 
        },
2399 
        'entityName' => 'x_x80',
2400 
        'ports' => {
2401 
          'data_out' => {
2402 
            'attributes' => {
2403 
              'bin_pt' => 0,
2404 
              'is_floating_block' => 1,
2405 
              'must_be_hdl_vector' => 1,
2406 
              'period' => 1.0,
2407 
              'port_id' => '0',
2408 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
2409 
              'type' => 'UFix_32_0',
2410 
            },
2411 
            'direction' => 'out',
2412 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2413 
            'width' => 32,
2414 
          },
2415 
        },
2416 
      },
2417 
      'entityName' => 'x_x80',
2418 
    },
2419 
    'from_register28' => {
2420 
      'connections' => { 'data_out' => 'from_register28_data_out_net', },
2421 
      'entity' => {
2422 
        'attributes' => {
2423 
          'generics' => [],
2424 
          'is_floating_block' => 1,
2425 
          'mask' => {
2426 
            'Block_Handle' => 2110.00048828125,
2427 
            'Block_handle' => 2110.00048828125,
2428 
            'MDL_Handle' => 2083.00048828125,
2429 
            'MDL_handle' => 2083.00048828125,
2430 
            'arith_type' => 2,
2431 
            'bin_pt' => 0,
2432 
            'block_config' => 'sysgen_blockset:fromreg_config',
2433 
            'block_handle' => 2110.00048828125,
2434 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2435 
            'block_type' => 'fromreg',
2436 
            'dbl_ovrd' => 0,
2437 
            'gui_display_data_type' => 1,
2438 
            'init' => 0.0,
2439 
            'init_bit_vector' => '\'b0',
2440 
            'mdl_handle' => 2083.00048828125,
2441 
            'model_handle' => 2083.00048828125,
2442 
            'n_bits' => 1,
2443 
            'ownership' => 2,
2444 
            'period' => 8.0E-9,
2445 
            'preci_type' => 1,
2446 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2447 
            'shared_memory_name' => 'register14rv',
2448 
          },
2449 
          'needs_vhdl_wrapper' => 0,
2450 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2451 
        },
2452 
        'entityName' => 'x_x81',
2453 
        'ports' => {
2454 
          'data_out' => {
2455 
            'attributes' => {
2456 
              'bin_pt' => 0,
2457 
              'is_floating_block' => 1,
2458 
              'must_be_hdl_vector' => 1,
2459 
              'period' => 1.0,
2460 
              'port_id' => '0',
2461 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
2462 
              'type' => 'UFix_1_0',
2463 
            },
2464 
            'direction' => 'out',
2465 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2466 
            'width' => 1,
2467 
          },
2468 
        },
2469 
      },
2470 
      'entityName' => 'x_x81',
2471 
    },
2472 
    'from_register3' => {
2473 
      'connections' => { 'data_out' => 'from_register3_data_out_net', },
2474 
      'entity' => {
2475 
        'attributes' => {
2476 
          'generics' => [],
2477 
          'is_floating_block' => 1,
2478 
          'mask' => {
2479 
            'Block_Handle' => 2111.00048828125,
2480 
            'Block_handle' => 2111.00048828125,
2481 
            'MDL_Handle' => 2083.00048828125,
2482 
            'MDL_handle' => 2083.00048828125,
2483 
            'arith_type' => 2,
2484 
            'bin_pt' => 0,
2485 
            'block_config' => 'sysgen_blockset:fromreg_config',
2486 
            'block_handle' => 2111.00048828125,
2487 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2488 
            'block_type' => 'fromreg',
2489 
            'dbl_ovrd' => 0,
2490 
            'gui_display_data_type' => 1,
2491 
            'init' => 0.0,
2492 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2493 
            'mdl_handle' => 2083.00048828125,
2494 
            'model_handle' => 2083.00048828125,
2495 
            'n_bits' => 32,
2496 
            'ownership' => 2,
2497 
            'period' => 8.0E-9,
2498 
            'preci_type' => 1,
2499 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2500 
            'shared_memory_name' => 'register01rd',
2501 
          },
2502 
          'needs_vhdl_wrapper' => 0,
2503 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2504 
        },
2505 
        'entityName' => 'x_x82',
2506 
        'ports' => {
2507 
          'data_out' => {
2508 
            'attributes' => {
2509 
              'bin_pt' => 0,
2510 
              'is_floating_block' => 1,
2511 
              'must_be_hdl_vector' => 1,
2512 
              'period' => 1.0,
2513 
              'port_id' => '0',
2514 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
2515 
              'type' => 'UFix_32_0',
2516 
            },
2517 
            'direction' => 'out',
2518 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2519 
            'width' => 32,
2520 
          },
2521 
        },
2522 
      },
2523 
      'entityName' => 'x_x82',
2524 
    },
2525 
    'from_register4' => {
2526 
      'connections' => { 'data_out' => 'from_register4_data_out_net', },
2527 
      'entity' => {
2528 
        'attributes' => {
2529 
          'generics' => [],
2530 
          'is_floating_block' => 1,
2531 
          'mask' => {
2532 
            'Block_Handle' => 2112.00048828125,
2533 
            'Block_handle' => 2112.00048828125,
2534 
            'MDL_Handle' => 2083.00048828125,
2535 
            'MDL_handle' => 2083.00048828125,
2536 
            'arith_type' => 2,
2537 
            'bin_pt' => 0,
2538 
            'block_config' => 'sysgen_blockset:fromreg_config',
2539 
            'block_handle' => 2112.00048828125,
2540 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2541 
            'block_type' => 'fromreg',
2542 
            'dbl_ovrd' => 0,
2543 
            'gui_display_data_type' => 1,
2544 
            'init' => 0.0,
2545 
            'init_bit_vector' => '\'b0',
2546 
            'mdl_handle' => 2083.00048828125,
2547 
            'model_handle' => 2083.00048828125,
2548 
            'n_bits' => 1,
2549 
            'ownership' => 2,
2550 
            'period' => 8.0E-9,
2551 
            'preci_type' => 1,
2552 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2553 
            'shared_memory_name' => 'register04rv',
2554 
          },
2555 
          'needs_vhdl_wrapper' => 0,
2556 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2557 
        },
2558 
        'entityName' => 'x_x83',
2559 
        'ports' => {
2560 
          'data_out' => {
2561 
            'attributes' => {
2562 
              'bin_pt' => 0,
2563 
              'is_floating_block' => 1,
2564 
              'must_be_hdl_vector' => 1,
2565 
              'period' => 1.0,
2566 
              'port_id' => '0',
2567 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
2568 
              'type' => 'UFix_1_0',
2569 
            },
2570 
            'direction' => 'out',
2571 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2572 
            'width' => 1,
2573 
          },
2574 
        },
2575 
      },
2576 
      'entityName' => 'x_x83',
2577 
    },
2578 
    'from_register5' => {
2579 
      'connections' => { 'data_out' => 'from_register5_data_out_net', },
2580 
      'entity' => {
2581 
        'attributes' => {
2582 
          'generics' => [],
2583 
          'is_floating_block' => 1,
2584 
          'mask' => {
2585 
            'Block_Handle' => 2113.00048828125,
2586 
            'Block_handle' => 2113.00048828125,
2587 
            'MDL_Handle' => 2083.00048828125,
2588 
            'MDL_handle' => 2083.00048828125,
2589 
            'arith_type' => 2,
2590 
            'bin_pt' => 0,
2591 
            'block_config' => 'sysgen_blockset:fromreg_config',
2592 
            'block_handle' => 2113.00048828125,
2593 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
2594 
            'block_type' => 'fromreg',
2595 
            'dbl_ovrd' => 0,
2596 
            'gui_display_data_type' => 1,
2597 
            'init' => 0.0,
2598 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2599 
            'mdl_handle' => 2083.00048828125,
2600 
            'model_handle' => 2083.00048828125,
2601 
            'n_bits' => 32,
2602 
            'ownership' => 2,
2603 
            'period' => 8.0E-9,
2604 
            'preci_type' => 1,
2605 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2606 
            'shared_memory_name' => 'register02rd',
2607 
          },
2608 
          'needs_vhdl_wrapper' => 0,
2609 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
2610 
        },
2611 
        'entityName' => 'x_x84',
2612 
        'ports' => {
2613 
          'data_out' => {
2614 
            'attributes' => {
2615 
              'bin_pt' => 0,
2616 
              'is_floating_block' => 1,
2617 
              'must_be_hdl_vector' => 1,
2618 
              'period' => 1.0,
2619 
              'port_id' => '0',
2620 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
2621 
              'type' => 'UFix_32_0',
2622 
            },
2623 
            'direction' => 'out',
2624 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2625 
            'width' => 32,
2626 
          },
2627 
        },
2628 
      },
2629 
      'entityName' => 'x_x84',
2630 
    },
2631 
    'from_register6' => {
2632 
      'connections' => { 'data_out' => 'from_register6_data_out_net', },
2633 
      'entity' => {
2634 
        'attributes' => {
2635 
          'generics' => [],
2636 
          'is_floating_block' => 1,
2637 
          'mask' => {
2638 
            'Block_Handle' => 2114.00048828125,
2639 
            'Block_handle' => 2114.00048828125,
2640 
            'MDL_Handle' => 2083.00048828125,
2641 
            'MDL_handle' => 2083.00048828125,
2642 
            'arith_type' => 2,
2643 
            'bin_pt' => 0,
2644 
            'block_config' => 'sysgen_blockset:fromreg_config',
2645 
            'block_handle' => 2114.00048828125,
2646 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
2647 
            'block_type' => 'fromreg',
2648 
            'dbl_ovrd' => 0,
2649 
            'gui_display_data_type' => 1,
2650 
            'init' => 0.0,
2651 
            'init_bit_vector' => '\'b0',
2652 
            'mdl_handle' => 2083.00048828125,
2653 
            'model_handle' => 2083.00048828125,
2654 
            'n_bits' => 1,
2655 
            'ownership' => 2,
2656 
            'period' => 8.0E-9,
2657 
            'preci_type' => 1,
2658 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2659 
            'shared_memory_name' => 'register03rv',
2660 
          },
2661 
          'needs_vhdl_wrapper' => 0,
2662 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
2663 
        },
2664 
        'entityName' => 'x_x85',
2665 
        'ports' => {
2666 
          'data_out' => {
2667 
            'attributes' => {
2668 
              'bin_pt' => 0,
2669 
              'is_floating_block' => 1,
2670 
              'must_be_hdl_vector' => 1,
2671 
              'period' => 1.0,
2672 
              'port_id' => '0',
2673 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
2674 
              'type' => 'UFix_1_0',
2675 
            },
2676 
            'direction' => 'out',
2677 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2678 
            'width' => 1,
2679 
          },
2680 
        },
2681 
      },
2682 
      'entityName' => 'x_x85',
2683 
    },
2684 
    'from_register7' => {
2685 
      'connections' => { 'data_out' => 'from_register7_data_out_net', },
2686 
      'entity' => {
2687 
        'attributes' => {
2688 
          'generics' => [],
2689 
          'is_floating_block' => 1,
2690 
          'mask' => {
2691 
            'Block_Handle' => 2115.00048828125,
2692 
            'Block_handle' => 2115.00048828125,
2693 
            'MDL_Handle' => 2083.00048828125,
2694 
            'MDL_handle' => 2083.00048828125,
2695 
            'arith_type' => 2,
2696 
            'bin_pt' => 0,
2697 
            'block_config' => 'sysgen_blockset:fromreg_config',
2698 
            'block_handle' => 2115.00048828125,
2699 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
2700 
            'block_type' => 'fromreg',
2701 
            'dbl_ovrd' => 0,
2702 
            'gui_display_data_type' => 1,
2703 
            'init' => 0.0,
2704 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2705 
            'mdl_handle' => 2083.00048828125,
2706 
            'model_handle' => 2083.00048828125,
2707 
            'n_bits' => 32,
2708 
            'ownership' => 2,
2709 
            'period' => 8.0E-9,
2710 
            'preci_type' => 1,
2711 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2712 
            'shared_memory_name' => 'register03rd',
2713 
          },
2714 
          'needs_vhdl_wrapper' => 0,
2715 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
2716 
        },
2717 
        'entityName' => 'x_x86',
2718 
        'ports' => {
2719 
          'data_out' => {
2720 
            'attributes' => {
2721 
              'bin_pt' => 0,
2722 
              'is_floating_block' => 1,
2723 
              'must_be_hdl_vector' => 1,
2724 
              'period' => 1.0,
2725 
              'port_id' => '0',
2726 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
2727 
              'type' => 'UFix_32_0',
2728 
            },
2729 
            'direction' => 'out',
2730 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2731 
            'width' => 32,
2732 
          },
2733 
        },
2734 
      },
2735 
      'entityName' => 'x_x86',
2736 
    },
2737 
    'from_register8' => {
2738 
      'connections' => { 'data_out' => 'from_register8_data_out_net', },
2739 
      'entity' => {
2740 
        'attributes' => {
2741 
          'generics' => [],
2742 
          'is_floating_block' => 1,
2743 
          'mask' => {
2744 
            'Block_Handle' => 2116.00048828125,
2745 
            'Block_handle' => 2116.00048828125,
2746 
            'MDL_Handle' => 2083.00048828125,
2747 
            'MDL_handle' => 2083.00048828125,
2748 
            'arith_type' => 2,
2749 
            'bin_pt' => 0,
2750 
            'block_config' => 'sysgen_blockset:fromreg_config',
2751 
            'block_handle' => 2116.00048828125,
2752 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
2753 
            'block_type' => 'fromreg',
2754 
            'dbl_ovrd' => 0,
2755 
            'gui_display_data_type' => 1,
2756 
            'init' => 0.0,
2757 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2758 
            'mdl_handle' => 2083.00048828125,
2759 
            'model_handle' => 2083.00048828125,
2760 
            'n_bits' => 32,
2761 
            'ownership' => 2,
2762 
            'period' => 8.0E-9,
2763 
            'preci_type' => 1,
2764 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2765 
            'shared_memory_name' => 'register04rd',
2766 
          },
2767 
          'needs_vhdl_wrapper' => 0,
2768 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
2769 
        },
2770 
        'entityName' => 'x_x87',
2771 
        'ports' => {
2772 
          'data_out' => {
2773 
            'attributes' => {
2774 
              'bin_pt' => 0,
2775 
              'is_floating_block' => 1,
2776 
              'must_be_hdl_vector' => 1,
2777 
              'period' => 1.0,
2778 
              'port_id' => '0',
2779 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
2780 
              'type' => 'UFix_32_0',
2781 
            },
2782 
            'direction' => 'out',
2783 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2784 
            'width' => 32,
2785 
          },
2786 
        },
2787 
      },
2788 
      'entityName' => 'x_x87',
2789 
    },
2790 
    'from_register9' => {
2791 
      'connections' => { 'data_out' => 'from_register9_data_out_net', },
2792 
      'entity' => {
2793 
        'attributes' => {
2794 
          'generics' => [],
2795 
          'is_floating_block' => 1,
2796 
          'mask' => {
2797 
            'Block_Handle' => 2117.00048828125,
2798 
            'Block_handle' => 2117.00048828125,
2799 
            'MDL_Handle' => 2083.00048828125,
2800 
            'MDL_handle' => 2083.00048828125,
2801 
            'arith_type' => 2,
2802 
            'bin_pt' => 0,
2803 
            'block_config' => 'sysgen_blockset:fromreg_config',
2804 
            'block_handle' => 2117.00048828125,
2805 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
2806 
            'block_type' => 'fromreg',
2807 
            'dbl_ovrd' => 0,
2808 
            'gui_display_data_type' => 1,
2809 
            'init' => 0.0,
2810 
            'init_bit_vector' => '\'b0',
2811 
            'mdl_handle' => 2083.00048828125,
2812 
            'model_handle' => 2083.00048828125,
2813 
            'n_bits' => 1,
2814 
            'ownership' => 2,
2815 
            'period' => 8.0E-9,
2816 
            'preci_type' => 1,
2817 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2818 
            'shared_memory_name' => 'register05rv',
2819 
          },
2820 
          'needs_vhdl_wrapper' => 0,
2821 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
2822 
        },
2823 
        'entityName' => 'x_x88',
2824 
        'ports' => {
2825 
          'data_out' => {
2826 
            'attributes' => {
2827 
              'bin_pt' => 0,
2828 
              'is_floating_block' => 1,
2829 
              'must_be_hdl_vector' => 1,
2830 
              'period' => 1.0,
2831 
              'port_id' => '0',
2832 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
2833 
              'type' => 'UFix_1_0',
2834 
            },
2835 
            'direction' => 'out',
2836 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2837 
            'width' => 1,
2838 
          },
2839 
        },
2840 
      },
2841 
      'entityName' => 'x_x88',
2842 
    },
2843 
    'inout_logic' => {
2844 
      'connections' => {
2845 
        'data_in' => 'debug_in_2i_net_x0',
2846 
        'data_in_x0' => 'reg04_tv_net_x0',
2847 
        'data_in_x1' => 'reg04_td_net_x0',
2848 
        'data_in_x10' => 'debug_in_3i_net_x0',
2849 
        'data_in_x11' => 'debug_in_4i_net_x0',
2850 
        'data_in_x12' => 'reg09_tv_net_x0',
2851 
        'data_in_x13' => 'reg09_td_net_x0',
2852 
        'data_in_x14' => 'reg10_tv_net_x0',
2853 
        'data_in_x15' => 'reg10_td_net_x0',
2854 
        'data_in_x16' => 'reg08_tv_net_x0',
2855 
        'data_in_x17' => 'reg08_td_net_x0',
2856 
        'data_in_x18' => 'reg11_tv_net_x0',
2857 
        'data_in_x19' => 'reg11_td_net_x0',
2858 
        'data_in_x2' => 'reg05_tv_net_x0',
2859 
        'data_in_x20' => 'reg12_tv_net_x0',
2860 
        'data_in_x21' => 'reg01_tv_net_x0',
2861 
        'data_in_x22' => 'reg12_td_net_x0',
2862 
        'data_in_x23' => 'reg13_tv_net_x0',
2863 
        'data_in_x24' => 'reg13_td_net_x0',
2864 
        'data_in_x25' => 'reg14_tv_net_x0',
2865 
        'data_in_x26' => 'reg14_td_net_x0',
2866 
        'data_in_x27' => 'reg02_tv_net_x0',
2867 
        'data_in_x28' => 'reg02_td_net_x0',
2868 
        'data_in_x29' => 'debug_in_1i_net_x0',
2869 
        'data_in_x3' => 'reg05_td_net_x0',
2870 
        'data_in_x30' => 'reg01_td_net_x0',
2871 
        'data_in_x31' => 'reg03_tv_net_x0',
2872 
        'data_in_x32' => 'reg03_td_net_x0',
2873 
        'data_in_x4' => 'reg06_tv_net_x0',
2874 
        'data_in_x5' => 'reg06_td_net_x0',
2875 
        'data_in_x6' => 'reg07_tv_net_x0',
2876 
        'data_in_x7' => 'reg07_td_net_x0',
2877 
        'data_in_x8' => 'dma_host2board_busy_net_x0',
2878 
        'data_in_x9' => 'dma_host2board_done_net_x0',
2879 
        'data_out' => 'from_register1_data_out_net',
2880 
        'data_out_x0' => 'from_register10_data_out_net',
2881 
        'data_out_x1' => 'from_register11_data_out_net',
2882 
        'data_out_x10' => 'from_register2_data_out_net',
2883 
        'data_out_x11' => 'from_register20_data_out_net',
2884 
        'data_out_x12' => 'from_register21_data_out_net',
2885 
        'data_out_x13' => 'from_register22_data_out_net',
2886 
        'data_out_x14' => 'from_register23_data_out_net',
2887 
        'data_out_x15' => 'from_register24_data_out_net',
2888 
        'data_out_x16' => 'from_register25_data_out_net',
2889 
        'data_out_x17' => 'from_register26_data_out_net',
2890 
        'data_out_x18' => 'from_register27_data_out_net',
2891 
        'data_out_x19' => 'from_register28_data_out_net',
2892 
        'data_out_x2' => 'from_register12_data_out_net',
2893 
        'data_out_x20' => 'from_register3_data_out_net',
2894 
        'data_out_x21' => 'from_register4_data_out_net',
2895 
        'data_out_x22' => 'from_register5_data_out_net',
2896 
        'data_out_x23' => 'from_register6_data_out_net',
2897 
        'data_out_x24' => 'from_register7_data_out_net',
2898 
        'data_out_x25' => 'from_register8_data_out_net',
2899 
        'data_out_x26' => 'from_register9_data_out_net',
2900 
        'data_out_x3' => 'from_register13_data_out_net',
2901 
        'data_out_x4' => 'from_register14_data_out_net',
2902 
        'data_out_x5' => 'from_register15_data_out_net',
2903 
        'data_out_x6' => 'from_register16_data_out_net',
2904 
        'data_out_x7' => 'from_register17_data_out_net',
2905 
        'data_out_x8' => 'from_register18_data_out_net',
2906 
        'data_out_x9' => 'from_register19_data_out_net',
2907 
        'debug_in_1i' => 'debug_in_1i_net',
2908 
        'debug_in_2i' => 'debug_in_2i_net',
2909 
        'debug_in_3i' => 'debug_in_3i_net',
2910 
        'debug_in_4i' => 'debug_in_4i_net',
2911 
        'dma_host2board_busy' => 'dma_host2board_busy_net',
2912 
        'dma_host2board_done' => 'dma_host2board_done_net',
2913 
        'en' => 'constant5_op_net_x0',
2914 
        'en_x0' => 'constant5_op_net_x1',
2915 
        'en_x1' => 'constant5_op_net_x2',
2916 
        'en_x10' => 'constant5_op_net_x11',
2917 
        'en_x11' => 'constant5_op_net_x12',
2918 
        'en_x12' => 'constant1_op_net_x0',
2919 
        'en_x13' => 'constant1_op_net_x1',
2920 
        'en_x14' => 'constant1_op_net_x2',
2921 
        'en_x15' => 'constant1_op_net_x3',
2922 
        'en_x16' => 'constant1_op_net_x4',
2923 
        'en_x17' => 'constant1_op_net_x5',
2924 
        'en_x18' => 'constant1_op_net_x6',
2925 
        'en_x19' => 'constant1_op_net_x7',
2926 
        'en_x2' => 'constant5_op_net_x3',
2927 
        'en_x20' => 'constant1_op_net_x8',
2928 
        'en_x21' => 'constant5_op_net_x13',
2929 
        'en_x22' => 'constant1_op_net_x9',
2930 
        'en_x23' => 'constant1_op_net_x10',
2931 
        'en_x24' => 'constant1_op_net_x11',
2932 
        'en_x25' => 'constant1_op_net_x12',
2933 
        'en_x26' => 'constant1_op_net_x13',
2934 
        'en_x27' => 'constant5_op_net_x14',
2935 
        'en_x28' => 'constant5_op_net_x15',
2936 
        'en_x29' => 'constant5_op_net_x16',
2937 
        'en_x3' => 'constant5_op_net_x4',
2938 
        'en_x30' => 'constant5_op_net_x17',
2939 
        'en_x31' => 'constant5_op_net_x18',
2940 
        'en_x32' => 'constant5_op_net_x19',
2941 
        'en_x4' => 'constant5_op_net_x5',
2942 
        'en_x5' => 'constant5_op_net_x6',
2943 
        'en_x6' => 'constant5_op_net_x7',
2944 
        'en_x7' => 'constant5_op_net_x8',
2945 
        'en_x8' => 'constant5_op_net_x9',
2946 
        'en_x9' => 'constant5_op_net_x10',
2947 
        'reg01_rd' => 'from_register3_data_out_net_x0',
2948 
        'reg01_rv' => 'from_register1_data_out_net_x0',
2949 
        'reg01_td' => 'reg01_td_net',
2950 
        'reg01_tv' => 'reg01_tv_net',
2951 
        'reg02_rd' => 'from_register5_data_out_net_x0',
2952 
        'reg02_rv' => 'from_register2_data_out_net_x0',
2953 
        'reg02_td' => 'reg02_td_net',
2954 
        'reg02_tv' => 'reg02_tv_net',
2955 
        'reg03_rd' => 'from_register7_data_out_net_x0',
2956 
        'reg03_rv' => 'from_register6_data_out_net_x0',
2957 
        'reg03_td' => 'reg03_td_net',
2958 
        'reg03_tv' => 'reg03_tv_net',
2959 
        'reg04_rd' => 'from_register8_data_out_net_x0',
2960 
        'reg04_rv' => 'from_register4_data_out_net_x0',
2961 
        'reg04_td' => 'reg04_td_net',
2962 
        'reg04_tv' => 'reg04_tv_net',
2963 
        'reg05_rd' => 'from_register10_data_out_net_x0',
2964 
        'reg05_rv' => 'from_register9_data_out_net_x0',
2965 
        'reg05_td' => 'reg05_td_net',
2966 
        'reg05_tv' => 'reg05_tv_net',
2967 
        'reg06_rd' => 'from_register11_data_out_net_x0',
2968 
        'reg06_rv' => 'from_register12_data_out_net_x0',
2969 
        'reg06_td' => 'reg06_td_net',
2970 
        'reg06_tv' => 'reg06_tv_net',
2971 
        'reg07_rd' => 'from_register13_data_out_net_x0',
2972 
        'reg07_rv' => 'from_register14_data_out_net_x0',
2973 
        'reg07_td' => 'reg07_td_net',
2974 
        'reg07_tv' => 'reg07_tv_net',
2975 
        'reg08_rd' => 'from_register15_data_out_net_x0',
2976 
        'reg08_rv' => 'from_register16_data_out_net_x0',
2977 
        'reg08_td' => 'reg08_td_net',
2978 
        'reg08_tv' => 'reg08_tv_net',
2979 
        'reg09_rd' => 'from_register17_data_out_net_x0',
2980 
        'reg09_rv' => 'from_register18_data_out_net_x0',
2981 
        'reg09_td' => 'reg09_td_net',
2982 
        'reg09_tv' => 'reg09_tv_net',
2983 
        'reg10_rd' => 'from_register19_data_out_net_x0',
2984 
        'reg10_rv' => 'from_register20_data_out_net_x0',
2985 
        'reg10_td' => 'reg10_td_net',
2986 
        'reg10_tv' => 'reg10_tv_net',
2987 
        'reg11_rd' => 'from_register21_data_out_net_x0',
2988 
        'reg11_rv' => 'from_register22_data_out_net_x0',
2989 
        'reg11_td' => 'reg11_td_net',
2990 
        'reg11_tv' => 'reg11_tv_net',
2991 
        'reg12_rd' => 'from_register23_data_out_net_x0',
2992 
        'reg12_rv' => 'from_register24_data_out_net_x0',
2993 
        'reg12_td' => 'reg12_td_net',
2994 
        'reg12_tv' => 'reg12_tv_net',
2995 
        'reg13_rd' => 'from_register25_data_out_net_x0',
2996 
        'reg13_rv' => 'from_register26_data_out_net_x0',
2997 
        'reg13_td' => 'reg13_td_net',
2998 
        'reg13_tv' => 'reg13_tv_net',
2999 
        'reg14_rd' => 'from_register27_data_out_net_x0',
3000 
        'reg14_rv' => 'from_register28_data_out_net_x0',
3001 
        'reg14_td' => 'reg14_td_net',
3002 
        'reg14_tv' => 'reg14_tv_net',
3003 
      },
3004 
      'entity' => {
3005 
        'attributes' => {
3006 
          'entityAlreadyNetlisted' => 1,
3007 
          'hdlKind' => 'vhdl',
3008 
          'isDesign' => 1,
3009 
          'simulinkName' => 'INOUT_LOGIC',
3010 
        },
3011 
        'entityName' => 'inout_logic',
3012 
        'ports' => {
3013 
          'data_in' => {
3014 
            'attributes' => {
3015 
              'bin_pt' => 0,
3016 
              'is_floating_block' => 1,
3017 
              'must_be_hdl_vector' => 1,
3018 
              'period' => 1.0,
3019 
              'port_id' => '0',
3020 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3021 
              'type' => 'UFix_32_0',
3022 
            },
3023 
            'direction' => 'out',
3024 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3025 
            'width' => 32,
3026 
          },
3027 
          'data_in_x0' => {
3028 
            'attributes' => {
3029 
              'bin_pt' => 0,
3030 
              'is_floating_block' => 1,
3031 
              'must_be_hdl_vector' => 1,
3032 
              'period' => 1.0,
3033 
              'port_id' => '0',
3034 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3035 
              'type' => 'Bool',
3036 
            },
3037 
            'direction' => 'out',
3038 
            'hdlType' => 'std_logic',
3039 
            'width' => 1,
3040 
          },
3041 
          'data_in_x1' => {
3042 
            'attributes' => {
3043 
              'bin_pt' => 0,
3044 
              'is_floating_block' => 1,
3045 
              'must_be_hdl_vector' => 1,
3046 
              'period' => 1.0,
3047 
              'port_id' => '0',
3048 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3049 
              'type' => 'UFix_32_0',
3050 
            },
3051 
            'direction' => 'out',
3052 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3053 
            'width' => 32,
3054 
          },
3055 
          'data_in_x10' => {
3056 
            'attributes' => {
3057 
              'bin_pt' => 0,
3058 
              'is_floating_block' => 1,
3059 
              'must_be_hdl_vector' => 1,
3060 
              'period' => 1.0,
3061 
              'port_id' => '0',
3062 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3063 
              'type' => 'UFix_32_0',
3064 
            },
3065 
            'direction' => 'out',
3066 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3067 
            'width' => 32,
3068 
          },
3069 
          'data_in_x11' => {
3070 
            'attributes' => {
3071 
              'bin_pt' => 0,
3072 
              'is_floating_block' => 1,
3073 
              'must_be_hdl_vector' => 1,
3074 
              'period' => 1.0,
3075 
              'port_id' => '0',
3076 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3077 
              'type' => 'UFix_32_0',
3078 
            },
3079 
            'direction' => 'out',
3080 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3081 
            'width' => 32,
3082 
          },
3083 
          'data_in_x12' => {
3084 
            'attributes' => {
3085 
              'bin_pt' => 0,
3086 
              'is_floating_block' => 1,
3087 
              'must_be_hdl_vector' => 1,
3088 
              'period' => 1.0,
3089 
              'port_id' => '0',
3090 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3091 
              'type' => 'Bool',
3092 
            },
3093 
            'direction' => 'out',
3094 
            'hdlType' => 'std_logic',
3095 
            'width' => 1,
3096 
          },
3097 
          'data_in_x13' => {
3098 
            'attributes' => {
3099 
              'bin_pt' => 0,
3100 
              'is_floating_block' => 1,
3101 
              'must_be_hdl_vector' => 1,
3102 
              'period' => 1.0,
3103 
              'port_id' => '0',
3104 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3105 
              'type' => 'UFix_32_0',
3106 
            },
3107 
            'direction' => 'out',
3108 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3109 
            'width' => 32,
3110 
          },
3111 
          'data_in_x14' => {
3112 
            'attributes' => {
3113 
              'bin_pt' => 0,
3114 
              'is_floating_block' => 1,
3115 
              'must_be_hdl_vector' => 1,
3116 
              'period' => 1.0,
3117 
              'port_id' => '0',
3118 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3119 
              'type' => 'Bool',
3120 
            },
3121 
            'direction' => 'out',
3122 
            'hdlType' => 'std_logic',
3123 
            'width' => 1,
3124 
          },
3125 
          'data_in_x15' => {
3126 
            'attributes' => {
3127 
              'bin_pt' => 0,
3128 
              'is_floating_block' => 1,
3129 
              'must_be_hdl_vector' => 1,
3130 
              'period' => 1.0,
3131 
              'port_id' => '0',
3132 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3133 
              'type' => 'UFix_32_0',
3134 
            },
3135 
            'direction' => 'out',
3136 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3137 
            'width' => 32,
3138 
          },
3139 
          'data_in_x16' => {
3140 
            'attributes' => {
3141 
              'bin_pt' => 0,
3142 
              'is_floating_block' => 1,
3143 
              'must_be_hdl_vector' => 1,
3144 
              'period' => 1.0,
3145 
              'port_id' => '0',
3146 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3147 
              'type' => 'Bool',
3148 
            },
3149 
            'direction' => 'out',
3150 
            'hdlType' => 'std_logic',
3151 
            'width' => 1,
3152 
          },
3153 
          'data_in_x17' => {
3154 
            'attributes' => {
3155 
              'bin_pt' => 0,
3156 
              'is_floating_block' => 1,
3157 
              'must_be_hdl_vector' => 1,
3158 
              'period' => 1.0,
3159 
              'port_id' => '0',
3160 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3161 
              'type' => 'UFix_32_0',
3162 
            },
3163 
            'direction' => 'out',
3164 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3165 
            'width' => 32,
3166 
          },
3167 
          'data_in_x18' => {
3168 
            'attributes' => {
3169 
              'bin_pt' => 0,
3170 
              'is_floating_block' => 1,
3171 
              'must_be_hdl_vector' => 1,
3172 
              'period' => 1.0,
3173 
              'port_id' => '0',
3174 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3175 
              'type' => 'Bool',
3176 
            },
3177 
            'direction' => 'out',
3178 
            'hdlType' => 'std_logic',
3179 
            'width' => 1,
3180 
          },
3181 
          'data_in_x19' => {
3182 
            'attributes' => {
3183 
              'bin_pt' => 0,
3184 
              'is_floating_block' => 1,
3185 
              'must_be_hdl_vector' => 1,
3186 
              'period' => 1.0,
3187 
              'port_id' => '0',
3188 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3189 
              'type' => 'UFix_32_0',
3190 
            },
3191 
            'direction' => 'out',
3192 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3193 
            'width' => 32,
3194 
          },
3195 
          'data_in_x2' => {
3196 
            'attributes' => {
3197 
              'bin_pt' => 0,
3198 
              'is_floating_block' => 1,
3199 
              'must_be_hdl_vector' => 1,
3200 
              'period' => 1.0,
3201 
              'port_id' => '0',
3202 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3203 
              'type' => 'Bool',
3204 
            },
3205 
            'direction' => 'out',
3206 
            'hdlType' => 'std_logic',
3207 
            'width' => 1,
3208 
          },
3209 
          'data_in_x20' => {
3210 
            'attributes' => {
3211 
              'bin_pt' => 0,
3212 
              'is_floating_block' => 1,
3213 
              'must_be_hdl_vector' => 1,
3214 
              'period' => 1.0,
3215 
              'port_id' => '0',
3216 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3217 
              'type' => 'Bool',
3218 
            },
3219 
            'direction' => 'out',
3220 
            'hdlType' => 'std_logic',
3221 
            'width' => 1,
3222 
          },
3223 
          'data_in_x21' => {
3224 
            'attributes' => {
3225 
              'bin_pt' => 0,
3226 
              'is_floating_block' => 1,
3227 
              'must_be_hdl_vector' => 1,
3228 
              'period' => 1.0,
3229 
              'port_id' => '0',
3230 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3231 
              'type' => 'Bool',
3232 
            },
3233 
            'direction' => 'out',
3234 
            'hdlType' => 'std_logic',
3235 
            'width' => 1,
3236 
          },
3237 
          'data_in_x22' => {
3238 
            'attributes' => {
3239 
              'bin_pt' => 0,
3240 
              'is_floating_block' => 1,
3241 
              'must_be_hdl_vector' => 1,
3242 
              'period' => 1.0,
3243 
              'port_id' => '0',
3244 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3245 
              'type' => 'UFix_32_0',
3246 
            },
3247 
            'direction' => 'out',
3248 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3249 
            'width' => 32,
3250 
          },
3251 
          'data_in_x23' => {
3252 
            'attributes' => {
3253 
              'bin_pt' => 0,
3254 
              'is_floating_block' => 1,
3255 
              'must_be_hdl_vector' => 1,
3256 
              'period' => 1.0,
3257 
              'port_id' => '0',
3258 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3259 
              'type' => 'Bool',
3260 
            },
3261 
            'direction' => 'out',
3262 
            'hdlType' => 'std_logic',
3263 
            'width' => 1,
3264 
          },
3265 
          'data_in_x24' => {
3266 
            'attributes' => {
3267 
              'bin_pt' => 0,
3268 
              'is_floating_block' => 1,
3269 
              'must_be_hdl_vector' => 1,
3270 
              'period' => 1.0,
3271 
              'port_id' => '0',
3272 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3273 
              'type' => 'UFix_32_0',
3274 
            },
3275 
            'direction' => 'out',
3276 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3277 
            'width' => 32,
3278 
          },
3279 
          'data_in_x25' => {
3280 
            'attributes' => {
3281 
              'bin_pt' => 0,
3282 
              'is_floating_block' => 1,
3283 
              'must_be_hdl_vector' => 1,
3284 
              'period' => 1.0,
3285 
              'port_id' => '0',
3286 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3287 
              'type' => 'Bool',
3288 
            },
3289 
            'direction' => 'out',
3290 
            'hdlType' => 'std_logic',
3291 
            'width' => 1,
3292 
          },
3293 
          'data_in_x26' => {
3294 
            'attributes' => {
3295 
              'bin_pt' => 0,
3296 
              'is_floating_block' => 1,
3297 
              'must_be_hdl_vector' => 1,
3298 
              'period' => 1.0,
3299 
              'port_id' => '0',
3300 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3301 
              'type' => 'UFix_32_0',
3302 
            },
3303 
            'direction' => 'out',
3304 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3305 
            'width' => 32,
3306 
          },
3307 
          'data_in_x27' => {
3308 
            'attributes' => {
3309 
              'bin_pt' => 0,
3310 
              'is_floating_block' => 1,
3311 
              'must_be_hdl_vector' => 1,
3312 
              'period' => 1.0,
3313 
              'port_id' => '0',
3314 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3315 
              'type' => 'Bool',
3316 
            },
3317 
            'direction' => 'out',
3318 
            'hdlType' => 'std_logic',
3319 
            'width' => 1,
3320 
          },
3321 
          'data_in_x28' => {
3322 
            'attributes' => {
3323 
              'bin_pt' => 0,
3324 
              'is_floating_block' => 1,
3325 
              'must_be_hdl_vector' => 1,
3326 
              'period' => 1.0,
3327 
              'port_id' => '0',
3328 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3329 
              'type' => 'UFix_32_0',
3330 
            },
3331 
            'direction' => 'out',
3332 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3333 
            'width' => 32,
3334 
          },
3335 
          'data_in_x29' => {
3336 
            'attributes' => {
3337 
              'bin_pt' => 0,
3338 
              'is_floating_block' => 1,
3339 
              'must_be_hdl_vector' => 1,
3340 
              'period' => 1.0,
3341 
              'port_id' => '0',
3342 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3343 
              'type' => 'UFix_32_0',
3344 
            },
3345 
            'direction' => 'out',
3346 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3347 
            'width' => 32,
3348 
          },
3349 
          'data_in_x3' => {
3350 
            'attributes' => {
3351 
              'bin_pt' => 0,
3352 
              'is_floating_block' => 1,
3353 
              'must_be_hdl_vector' => 1,
3354 
              'period' => 1.0,
3355 
              'port_id' => '0',
3356 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3357 
              'type' => 'UFix_32_0',
3358 
            },
3359 
            'direction' => 'out',
3360 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3361 
            'width' => 32,
3362 
          },
3363 
          'data_in_x30' => {
3364 
            'attributes' => {
3365 
              'bin_pt' => 0,
3366 
              'is_floating_block' => 1,
3367 
              'must_be_hdl_vector' => 1,
3368 
              'period' => 1.0,
3369 
              'port_id' => '0',
3370 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3371 
              'type' => 'UFix_32_0',
3372 
            },
3373 
            'direction' => 'out',
3374 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3375 
            'width' => 32,
3376 
          },
3377 
          'data_in_x31' => {
3378 
            'attributes' => {
3379 
              'bin_pt' => 0,
3380 
              'is_floating_block' => 1,
3381 
              'must_be_hdl_vector' => 1,
3382 
              'period' => 1.0,
3383 
              'port_id' => '0',
3384 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3385 
              'type' => 'Bool',
3386 
            },
3387 
            'direction' => 'out',
3388 
            'hdlType' => 'std_logic',
3389 
            'width' => 1,
3390 
          },
3391 
          'data_in_x32' => {
3392 
            'attributes' => {
3393 
              'bin_pt' => 0,
3394 
              'is_floating_block' => 1,
3395 
              'must_be_hdl_vector' => 1,
3396 
              'period' => 1.0,
3397 
              'port_id' => '0',
3398 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3399 
              'type' => 'UFix_32_0',
3400 
            },
3401 
            'direction' => 'out',
3402 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3403 
            'width' => 32,
3404 
          },
3405 
          'data_in_x4' => {
3406 
            'attributes' => {
3407 
              'bin_pt' => 0,
3408 
              'is_floating_block' => 1,
3409 
              'must_be_hdl_vector' => 1,
3410 
              'period' => 1.0,
3411 
              'port_id' => '0',
3412 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3413 
              'type' => 'Bool',
3414 
            },
3415 
            'direction' => 'out',
3416 
            'hdlType' => 'std_logic',
3417 
            'width' => 1,
3418 
          },
3419 
          'data_in_x5' => {
3420 
            'attributes' => {
3421 
              'bin_pt' => 0,
3422 
              'is_floating_block' => 1,
3423 
              'must_be_hdl_vector' => 1,
3424 
              'period' => 1.0,
3425 
              'port_id' => '0',
3426 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3427 
              'type' => 'UFix_32_0',
3428 
            },
3429 
            'direction' => 'out',
3430 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3431 
            'width' => 32,
3432 
          },
3433 
          'data_in_x6' => {
3434 
            'attributes' => {
3435 
              'bin_pt' => 0,
3436 
              'is_floating_block' => 1,
3437 
              'must_be_hdl_vector' => 1,
3438 
              'period' => 1.0,
3439 
              'port_id' => '0',
3440 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3441 
              'type' => 'Bool',
3442 
            },
3443 
            'direction' => 'out',
3444 
            'hdlType' => 'std_logic',
3445 
            'width' => 1,
3446 
          },
3447 
          'data_in_x7' => {
3448 
            'attributes' => {
3449 
              'bin_pt' => 0,
3450 
              'is_floating_block' => 1,
3451 
              'must_be_hdl_vector' => 1,
3452 
              'period' => 1.0,
3453 
              'port_id' => '0',
3454 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3455 
              'type' => 'UFix_32_0',
3456 
            },
3457 
            'direction' => 'out',
3458 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3459 
            'width' => 32,
3460 
          },
3461 
          'data_in_x8' => {
3462 
            'attributes' => {
3463 
              'bin_pt' => 0,
3464 
              'is_floating_block' => 1,
3465 
              'must_be_hdl_vector' => 1,
3466 
              'period' => 1.0,
3467 
              'port_id' => '0',
3468 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3469 
              'type' => 'UFix_1_0',
3470 
            },
3471 
            'direction' => 'out',
3472 
            'hdlType' => 'std_logic',
3473 
            'width' => 1,
3474 
          },
3475 
          'data_in_x9' => {
3476 
            'attributes' => {
3477 
              'bin_pt' => 0,
3478 
              'is_floating_block' => 1,
3479 
              'must_be_hdl_vector' => 1,
3480 
              'period' => 1.0,
3481 
              'port_id' => '0',
3482 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3483 
              'type' => 'UFix_1_0',
3484 
            },
3485 
            'direction' => 'out',
3486 
            'hdlType' => 'std_logic',
3487 
            'width' => 1,
3488 
          },
3489 
          'data_out' => {
3490 
            'attributes' => {
3491 
              'bin_pt' => 0,
3492 
              'is_floating_block' => 1,
3493 
              'must_be_hdl_vector' => 1,
3494 
              'period' => 1.0,
3495 
              'port_id' => '0',
3496 
              'simulinkName' => 'INOUT_LOGIC/From Register1',
3497 
              'type' => 'UFix_1_0',
3498 
            },
3499 
            'direction' => 'in',
3500 
            'hdlType' => 'std_logic',
3501 
            'width' => 1,
3502 
          },
3503 
          'data_out_x0' => {
3504 
            'attributes' => {
3505 
              'bin_pt' => 0,
3506 
              'is_floating_block' => 1,
3507 
              'must_be_hdl_vector' => 1,
3508 
              'period' => 1.0,
3509 
              'port_id' => '0',
3510 
              'simulinkName' => 'INOUT_LOGIC/From Register10',
3511 
              'type' => 'UFix_32_0',
3512 
            },
3513 
            'direction' => 'in',
3514 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3515 
            'width' => 32,
3516 
          },
3517 
          'data_out_x1' => {
3518 
            'attributes' => {
3519 
              'bin_pt' => 0,
3520 
              'is_floating_block' => 1,
3521 
              'must_be_hdl_vector' => 1,
3522 
              'period' => 1.0,
3523 
              'port_id' => '0',
3524 
              'simulinkName' => 'INOUT_LOGIC/From Register11',
3525 
              'type' => 'UFix_32_0',
3526 
            },
3527 
            'direction' => 'in',
3528 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3529 
            'width' => 32,
3530 
          },
3531 
          'data_out_x10' => {
3532 
            'attributes' => {
3533 
              'bin_pt' => 0,
3534 
              'is_floating_block' => 1,
3535 
              'must_be_hdl_vector' => 1,
3536 
              'period' => 1.0,
3537 
              'port_id' => '0',
3538 
              'simulinkName' => 'INOUT_LOGIC/From Register2',
3539 
              'type' => 'UFix_1_0',
3540 
            },
3541 
            'direction' => 'in',
3542 
            'hdlType' => 'std_logic',
3543 
            'width' => 1,
3544 
          },
3545 
          'data_out_x11' => {
3546 
            'attributes' => {
3547 
              'bin_pt' => 0,
3548 
              'is_floating_block' => 1,
3549 
              'must_be_hdl_vector' => 1,
3550 
              'period' => 1.0,
3551 
              'port_id' => '0',
3552 
              'simulinkName' => 'INOUT_LOGIC/From Register20',
3553 
              'type' => 'UFix_1_0',
3554 
            },
3555 
            'direction' => 'in',
3556 
            'hdlType' => 'std_logic',
3557 
            'width' => 1,
3558 
          },
3559 
          'data_out_x12' => {
3560 
            'attributes' => {
3561 
              'bin_pt' => 0,
3562 
              'is_floating_block' => 1,
3563 
              'must_be_hdl_vector' => 1,
3564 
              'period' => 1.0,
3565 
              'port_id' => '0',
3566 
              'simulinkName' => 'INOUT_LOGIC/From Register21',
3567 
              'type' => 'UFix_32_0',
3568 
            },
3569 
            'direction' => 'in',
3570 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3571 
            'width' => 32,
3572 
          },
3573 
          'data_out_x13' => {
3574 
            'attributes' => {
3575 
              'bin_pt' => 0,
3576 
              'is_floating_block' => 1,
3577 
              'must_be_hdl_vector' => 1,
3578 
              'period' => 1.0,
3579 
              'port_id' => '0',
3580 
              'simulinkName' => 'INOUT_LOGIC/From Register22',
3581 
              'type' => 'UFix_1_0',
3582 
            },
3583 
            'direction' => 'in',
3584 
            'hdlType' => 'std_logic',
3585 
            'width' => 1,
3586 
          },
3587 
          'data_out_x14' => {
3588 
            'attributes' => {
3589 
              'bin_pt' => 0,
3590 
              'is_floating_block' => 1,
3591 
              'must_be_hdl_vector' => 1,
3592 
              'period' => 1.0,
3593 
              'port_id' => '0',
3594 
              'simulinkName' => 'INOUT_LOGIC/From Register23',
3595 
              'type' => 'UFix_32_0',
3596 
            },
3597 
            'direction' => 'in',
3598 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3599 
            'width' => 32,
3600 
          },
3601 
          'data_out_x15' => {
3602 
            'attributes' => {
3603 
              'bin_pt' => 0,
3604 
              'is_floating_block' => 1,
3605 
              'must_be_hdl_vector' => 1,
3606 
              'period' => 1.0,
3607 
              'port_id' => '0',
3608 
              'simulinkName' => 'INOUT_LOGIC/From Register24',
3609 
              'type' => 'UFix_1_0',
3610 
            },
3611 
            'direction' => 'in',
3612 
            'hdlType' => 'std_logic',
3613 
            'width' => 1,
3614 
          },
3615 
          'data_out_x16' => {
3616 
            'attributes' => {
3617 
              'bin_pt' => 0,
3618 
              'is_floating_block' => 1,
3619 
              'must_be_hdl_vector' => 1,
3620 
              'period' => 1.0,
3621 
              'port_id' => '0',
3622 
              'simulinkName' => 'INOUT_LOGIC/From Register25',
3623 
              'type' => 'UFix_32_0',
3624 
            },
3625 
            'direction' => 'in',
3626 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3627 
            'width' => 32,
3628 
          },
3629 
          'data_out_x17' => {
3630 
            'attributes' => {
3631 
              'bin_pt' => 0,
3632 
              'is_floating_block' => 1,
3633 
              'must_be_hdl_vector' => 1,
3634 
              'period' => 1.0,
3635 
              'port_id' => '0',
3636 
              'simulinkName' => 'INOUT_LOGIC/From Register26',
3637 
              'type' => 'UFix_1_0',
3638 
            },
3639 
            'direction' => 'in',
3640 
            'hdlType' => 'std_logic',
3641 
            'width' => 1,
3642 
          },
3643 
          'data_out_x18' => {
3644 
            'attributes' => {
3645 
              'bin_pt' => 0,
3646 
              'is_floating_block' => 1,
3647 
              'must_be_hdl_vector' => 1,
3648 
              'period' => 1.0,
3649 
              'port_id' => '0',
3650 
              'simulinkName' => 'INOUT_LOGIC/From Register27',
3651 
              'type' => 'UFix_32_0',
3652 
            },
3653 
            'direction' => 'in',
3654 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3655 
            'width' => 32,
3656 
          },
3657 
          'data_out_x19' => {
3658 
            'attributes' => {
3659 
              'bin_pt' => 0,
3660 
              'is_floating_block' => 1,
3661 
              'must_be_hdl_vector' => 1,
3662 
              'period' => 1.0,
3663 
              'port_id' => '0',
3664 
              'simulinkName' => 'INOUT_LOGIC/From Register28',
3665 
              'type' => 'UFix_1_0',
3666 
            },
3667 
            'direction' => 'in',
3668 
            'hdlType' => 'std_logic',
3669 
            'width' => 1,
3670 
          },
3671 
          'data_out_x2' => {
3672 
            'attributes' => {
3673 
              'bin_pt' => 0,
3674 
              'is_floating_block' => 1,
3675 
              'must_be_hdl_vector' => 1,
3676 
              'period' => 1.0,
3677 
              'port_id' => '0',
3678 
              'simulinkName' => 'INOUT_LOGIC/From Register12',
3679 
              'type' => 'UFix_1_0',
3680 
            },
3681 
            'direction' => 'in',
3682 
            'hdlType' => 'std_logic',
3683 
            'width' => 1,
3684 
          },
3685 
          'data_out_x20' => {
3686 
            'attributes' => {
3687 
              'bin_pt' => 0,
3688 
              'is_floating_block' => 1,
3689 
              'must_be_hdl_vector' => 1,
3690 
              'period' => 1.0,
3691 
              'port_id' => '0',
3692 
              'simulinkName' => 'INOUT_LOGIC/From Register3',
3693 
              'type' => 'UFix_32_0',
3694 
            },
3695 
            'direction' => 'in',
3696 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3697 
            'width' => 32,
3698 
          },
3699 
          'data_out_x21' => {
3700 
            'attributes' => {
3701 
              'bin_pt' => 0,
3702 
              'is_floating_block' => 1,
3703 
              'must_be_hdl_vector' => 1,
3704 
              'period' => 1.0,
3705 
              'port_id' => '0',
3706 
              'simulinkName' => 'INOUT_LOGIC/From Register4',
3707 
              'type' => 'UFix_1_0',
3708 
            },
3709 
            'direction' => 'in',
3710 
            'hdlType' => 'std_logic',
3711 
            'width' => 1,
3712 
          },
3713 
          'data_out_x22' => {
3714 
            'attributes' => {
3715 
              'bin_pt' => 0,
3716 
              'is_floating_block' => 1,
3717 
              'must_be_hdl_vector' => 1,
3718 
              'period' => 1.0,
3719 
              'port_id' => '0',
3720 
              'simulinkName' => 'INOUT_LOGIC/From Register5',
3721 
              'type' => 'UFix_32_0',
3722 
            },
3723 
            'direction' => 'in',
3724 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3725 
            'width' => 32,
3726 
          },
3727 
          'data_out_x23' => {
3728 
            'attributes' => {
3729 
              'bin_pt' => 0,
3730 
              'is_floating_block' => 1,
3731 
              'must_be_hdl_vector' => 1,
3732 
              'period' => 1.0,
3733 
              'port_id' => '0',
3734 
              'simulinkName' => 'INOUT_LOGIC/From Register6',
3735 
              'type' => 'UFix_1_0',
3736 
            },
3737 
            'direction' => 'in',
3738 
            'hdlType' => 'std_logic',
3739 
            'width' => 1,
3740 
          },
3741 
          'data_out_x24' => {
3742 
            'attributes' => {
3743 
              'bin_pt' => 0,
3744 
              'is_floating_block' => 1,
3745 
              'must_be_hdl_vector' => 1,
3746 
              'period' => 1.0,
3747 
              'port_id' => '0',
3748 
              'simulinkName' => 'INOUT_LOGIC/From Register7',
3749 
              'type' => 'UFix_32_0',
3750 
            },
3751 
            'direction' => 'in',
3752 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3753 
            'width' => 32,
3754 
          },
3755 
          'data_out_x25' => {
3756 
            'attributes' => {
3757 
              'bin_pt' => 0,
3758 
              'is_floating_block' => 1,
3759 
              'must_be_hdl_vector' => 1,
3760 
              'period' => 1.0,
3761 
              'port_id' => '0',
3762 
              'simulinkName' => 'INOUT_LOGIC/From Register8',
3763 
              'type' => 'UFix_32_0',
3764 
            },
3765 
            'direction' => 'in',
3766 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3767 
            'width' => 32,
3768 
          },
3769 
          'data_out_x26' => {
3770 
            'attributes' => {
3771 
              'bin_pt' => 0,
3772 
              'is_floating_block' => 1,
3773 
              'must_be_hdl_vector' => 1,
3774 
              'period' => 1.0,
3775 
              'port_id' => '0',
3776 
              'simulinkName' => 'INOUT_LOGIC/From Register9',
3777 
              'type' => 'UFix_1_0',
3778 
            },
3779 
            'direction' => 'in',
3780 
            'hdlType' => 'std_logic',
3781 
            'width' => 1,
3782 
          },
3783 
          'data_out_x3' => {
3784 
            'attributes' => {
3785 
              'bin_pt' => 0,
3786 
              'is_floating_block' => 1,
3787 
              'must_be_hdl_vector' => 1,
3788 
              'period' => 1.0,
3789 
              'port_id' => '0',
3790 
              'simulinkName' => 'INOUT_LOGIC/From Register13',
3791 
              'type' => 'UFix_32_0',
3792 
            },
3793 
            'direction' => 'in',
3794 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3795 
            'width' => 32,
3796 
          },
3797 
          'data_out_x4' => {
3798 
            'attributes' => {
3799 
              'bin_pt' => 0,
3800 
              'is_floating_block' => 1,
3801 
              'must_be_hdl_vector' => 1,
3802 
              'period' => 1.0,
3803 
              'port_id' => '0',
3804 
              'simulinkName' => 'INOUT_LOGIC/From Register14',
3805 
              'type' => 'UFix_1_0',
3806 
            },
3807 
            'direction' => 'in',
3808 
            'hdlType' => 'std_logic',
3809 
            'width' => 1,
3810 
          },
3811 
          'data_out_x5' => {
3812 
            'attributes' => {
3813 
              'bin_pt' => 0,
3814 
              'is_floating_block' => 1,
3815 
              'must_be_hdl_vector' => 1,
3816 
              'period' => 1.0,
3817 
              'port_id' => '0',
3818 
              'simulinkName' => 'INOUT_LOGIC/From Register15',
3819 
              'type' => 'UFix_32_0',
3820 
            },
3821 
            'direction' => 'in',
3822 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3823 
            'width' => 32,
3824 
          },
3825 
          'data_out_x6' => {
3826 
            'attributes' => {
3827 
              'bin_pt' => 0,
3828 
              'is_floating_block' => 1,
3829 
              'must_be_hdl_vector' => 1,
3830 
              'period' => 1.0,
3831 
              'port_id' => '0',
3832 
              'simulinkName' => 'INOUT_LOGIC/From Register16',
3833 
              'type' => 'UFix_1_0',
3834 
            },
3835 
            'direction' => 'in',
3836 
            'hdlType' => 'std_logic',
3837 
            'width' => 1,
3838 
          },
3839 
          'data_out_x7' => {
3840 
            'attributes' => {
3841 
              'bin_pt' => 0,
3842 
              'is_floating_block' => 1,
3843 
              'must_be_hdl_vector' => 1,
3844 
              'period' => 1.0,
3845 
              'port_id' => '0',
3846 
              'simulinkName' => 'INOUT_LOGIC/From Register17',
3847 
              'type' => 'UFix_32_0',
3848 
            },
3849 
            'direction' => 'in',
3850 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3851 
            'width' => 32,
3852 
          },
3853 
          'data_out_x8' => {
3854 
            'attributes' => {
3855 
              'bin_pt' => 0,
3856 
              'is_floating_block' => 1,
3857 
              'must_be_hdl_vector' => 1,
3858 
              'period' => 1.0,
3859 
              'port_id' => '0',
3860 
              'simulinkName' => 'INOUT_LOGIC/From Register18',
3861 
              'type' => 'UFix_1_0',
3862 
            },
3863 
            'direction' => 'in',
3864 
            'hdlType' => 'std_logic',
3865 
            'width' => 1,
3866 
          },
3867 
          'data_out_x9' => {
3868 
            'attributes' => {
3869 
              'bin_pt' => 0,
3870 
              'is_floating_block' => 1,
3871 
              'must_be_hdl_vector' => 1,
3872 
              'period' => 1.0,
3873 
              'port_id' => '0',
3874 
              'simulinkName' => 'INOUT_LOGIC/From Register19',
3875 
              'type' => 'UFix_32_0',
3876 
            },
3877 
            'direction' => 'in',
3878 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3879 
            'width' => 32,
3880 
          },
3881 
          'debug_in_1i' => {
3882 
            'attributes' => {
3883 
              'bin_pt' => 0,
3884 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
3885 
              'is_floating_block' => 1,
3886 
              'is_gateway_port' => 1,
3887 
              'must_be_hdl_vector' => 1,
3888 
              'period' => 1.0,
3889 
              'port_id' => '0',
3890 
              'simulinkName' => 'INOUT_LOGIC/debug_in_1i',
3891 
              'source_block' => 'INOUT_LOGIC',
3892 
              'timingConstraint' => 'none',
3893 
              'type' => 'UFix_32_0',
3894 
            },
3895 
            'direction' => 'in',
3896 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3897 
            'width' => 32,
3898 
          },
3899 
          'debug_in_2i' => {
3900 
            'attributes' => {
3901 
              'bin_pt' => 0,
3902 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
3903 
              'is_floating_block' => 1,
3904 
              'is_gateway_port' => 1,
3905 
              'must_be_hdl_vector' => 1,
3906 
              'period' => 1.0,
3907 
              'port_id' => '0',
3908 
              'simulinkName' => 'INOUT_LOGIC/debug_in_2i',
3909 
              'source_block' => 'INOUT_LOGIC',
3910 
              'timingConstraint' => 'none',
3911 
              'type' => 'UFix_32_0',
3912 
            },
3913 
            'direction' => 'in',
3914 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3915 
            'width' => 32,
3916 
          },
3917 
          'debug_in_3i' => {
3918 
            'attributes' => {
3919 
              'bin_pt' => 0,
3920 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
3921 
              'is_floating_block' => 1,
3922 
              'is_gateway_port' => 1,
3923 
              'must_be_hdl_vector' => 1,
3924 
              'period' => 1.0,
3925 
              'port_id' => '0',
3926 
              'simulinkName' => 'INOUT_LOGIC/debug_in_3i',
3927 
              'source_block' => 'INOUT_LOGIC',
3928 
              'timingConstraint' => 'none',
3929 
              'type' => 'UFix_32_0',
3930 
            },
3931 
            'direction' => 'in',
3932 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3933 
            'width' => 32,
3934 
          },
3935 
          'debug_in_4i' => {
3936 
            'attributes' => {
3937 
              'bin_pt' => 0,
3938 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
3939 
              'is_floating_block' => 1,
3940 
              'is_gateway_port' => 1,
3941 
              'must_be_hdl_vector' => 1,
3942 
              'period' => 1.0,
3943 
              'port_id' => '0',
3944 
              'simulinkName' => 'INOUT_LOGIC/debug_in_4i',
3945 
              'source_block' => 'INOUT_LOGIC',
3946 
              'timingConstraint' => 'none',
3947 
              'type' => 'UFix_32_0',
3948 
            },
3949 
            'direction' => 'in',
3950 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3951 
            'width' => 32,
3952 
          },
3953 
          'dma_host2board_busy' => {
3954 
            'attributes' => {
3955 
              'bin_pt' => 0,
3956 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
3957 
              'is_floating_block' => 1,
3958 
              'is_gateway_port' => 1,
3959 
              'must_be_hdl_vector' => 1,
3960 
              'period' => 1.0,
3961 
              'port_id' => '0',
3962 
              'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Busy',
3963 
              'source_block' => 'INOUT_LOGIC',
3964 
              'timingConstraint' => 'none',
3965 
              'type' => 'UFix_1_0',
3966 
            },
3967 
            'direction' => 'in',
3968 
            'hdlType' => 'std_logic',
3969 
            'width' => 1,
3970 
          },
3971 
          'dma_host2board_done' => {
3972 
            'attributes' => {
3973 
              'bin_pt' => 0,
3974 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
3975 
              'is_floating_block' => 1,
3976 
              'is_gateway_port' => 1,
3977 
              'must_be_hdl_vector' => 1,
3978 
              'period' => 1.0,
3979 
              'port_id' => '0',
3980 
              'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Done',
3981 
              'source_block' => 'INOUT_LOGIC',
3982 
              'timingConstraint' => 'none',
3983 
              'type' => 'UFix_1_0',
3984 
            },
3985 
            'direction' => 'in',
3986 
            'hdlType' => 'std_logic',
3987 
            'width' => 1,
3988 
          },
3989 
          'en' => {
3990 
            'attributes' => {
3991 
              'bin_pt' => 0,
3992 
              'is_floating_block' => 1,
3993 
              'must_be_hdl_vector' => 1,
3994 
              'period' => 1.0,
3995 
              'port_id' => '0',
3996 
              'simulinkName' => 'INOUT_LOGIC/en',
3997 
              'type' => 'Bool',
3998 
            },
3999 
            'direction' => 'out',
4000 
            'hdlType' => 'std_logic',
4001 
            'width' => 1,
4002 
          },
4003 
          'en_x0' => {
4004 
            'attributes' => {
4005 
              'bin_pt' => 0,
4006 
              'is_floating_block' => 1,
4007 
              'must_be_hdl_vector' => 1,
4008 
              'period' => 1.0,
4009 
              'port_id' => '0',
4010 
              'simulinkName' => 'INOUT_LOGIC/en',
4011 
              'type' => 'Bool',
4012 
            },
4013 
            'direction' => 'out',
4014 
            'hdlType' => 'std_logic',
4015 
            'width' => 1,
4016 
          },
4017 
          'en_x1' => {
4018 
            'attributes' => {
4019 
              'bin_pt' => 0,
4020 
              'is_floating_block' => 1,
4021 
              'must_be_hdl_vector' => 1,
4022 
              'period' => 1.0,
4023 
              'port_id' => '0',
4024 
              'simulinkName' => 'INOUT_LOGIC/en',
4025 
              'type' => 'Bool',
4026 
            },
4027 
            'direction' => 'out',
4028 
            'hdlType' => 'std_logic',
4029 
            'width' => 1,
4030 
          },
4031 
          'en_x10' => {
4032 
            'attributes' => {
4033 
              'bin_pt' => 0,
4034 
              'is_floating_block' => 1,
4035 
              'must_be_hdl_vector' => 1,
4036 
              'period' => 1.0,
4037 
              'port_id' => '0',
4038 
              'simulinkName' => 'INOUT_LOGIC/en',
4039 
              'type' => 'Bool',
4040 
            },
4041 
            'direction' => 'out',
4042 
            'hdlType' => 'std_logic',
4043 
            'width' => 1,
4044 
          },
4045 
          'en_x11' => {
4046 
            'attributes' => {
4047 
              'bin_pt' => 0,
4048 
              'is_floating_block' => 1,
4049 
              'must_be_hdl_vector' => 1,
4050 
              'period' => 1.0,
4051 
              'port_id' => '0',
4052 
              'simulinkName' => 'INOUT_LOGIC/en',
4053 
              'type' => 'Bool',
4054 
            },
4055 
            'direction' => 'out',
4056 
            'hdlType' => 'std_logic',
4057 
            'width' => 1,
4058 
          },
4059 
          'en_x12' => {
4060 
            'attributes' => {
4061 
              'bin_pt' => 0,
4062 
              'is_floating_block' => 1,
4063 
              'must_be_hdl_vector' => 1,
4064 
              'period' => 1.0,
4065 
              'port_id' => '0',
4066 
              'simulinkName' => 'INOUT_LOGIC/en',
4067 
              'type' => 'Bool',
4068 
            },
4069 
            'direction' => 'out',
4070 
            'hdlType' => 'std_logic',
4071 
            'width' => 1,
4072 
          },
4073 
          'en_x13' => {
4074 
            'attributes' => {
4075 
              'bin_pt' => 0,
4076 
              'is_floating_block' => 1,
4077 
              'must_be_hdl_vector' => 1,
4078 
              'period' => 1.0,
4079 
              'port_id' => '0',
4080 
              'simulinkName' => 'INOUT_LOGIC/en',
4081 
              'type' => 'Bool',
4082 
            },
4083 
            'direction' => 'out',
4084 
            'hdlType' => 'std_logic',
4085 
            'width' => 1,
4086 
          },
4087 
          'en_x14' => {
4088 
            'attributes' => {
4089 
              'bin_pt' => 0,
4090 
              'is_floating_block' => 1,
4091 
              'must_be_hdl_vector' => 1,
4092 
              'period' => 1.0,
4093 
              'port_id' => '0',
4094 
              'simulinkName' => 'INOUT_LOGIC/en',
4095 
              'type' => 'Bool',
4096 
            },
4097 
            'direction' => 'out',
4098 
            'hdlType' => 'std_logic',
4099 
            'width' => 1,
4100 
          },
4101 
          'en_x15' => {
4102 
            'attributes' => {
4103 
              'bin_pt' => 0,
4104 
              'is_floating_block' => 1,
4105 
              'must_be_hdl_vector' => 1,
4106 
              'period' => 1.0,
4107 
              'port_id' => '0',
4108 
              'simulinkName' => 'INOUT_LOGIC/en',
4109 
              'type' => 'Bool',
4110 
            },
4111 
            'direction' => 'out',
4112 
            'hdlType' => 'std_logic',
4113 
            'width' => 1,
4114 
          },
4115 
          'en_x16' => {
4116 
            'attributes' => {
4117 
              'bin_pt' => 0,
4118 
              'is_floating_block' => 1,
4119 
              'must_be_hdl_vector' => 1,
4120 
              'period' => 1.0,
4121 
              'port_id' => '0',
4122 
              'simulinkName' => 'INOUT_LOGIC/en',
4123 
              'type' => 'Bool',
4124 
            },
4125 
            'direction' => 'out',
4126 
            'hdlType' => 'std_logic',
4127 
            'width' => 1,
4128 
          },
4129 
          'en_x17' => {
4130 
            'attributes' => {
4131 
              'bin_pt' => 0,
4132 
              'is_floating_block' => 1,
4133 
              'must_be_hdl_vector' => 1,
4134 
              'period' => 1.0,
4135 
              'port_id' => '0',
4136 
              'simulinkName' => 'INOUT_LOGIC/en',
4137 
              'type' => 'Bool',
4138 
            },
4139 
            'direction' => 'out',
4140 
            'hdlType' => 'std_logic',
4141 
            'width' => 1,
4142 
          },
4143 
          'en_x18' => {
4144 
            'attributes' => {
4145 
              'bin_pt' => 0,
4146 
              'is_floating_block' => 1,
4147 
              'must_be_hdl_vector' => 1,
4148 
              'period' => 1.0,
4149 
              'port_id' => '0',
4150 
              'simulinkName' => 'INOUT_LOGIC/en',
4151 
              'type' => 'Bool',
4152 
            },
4153 
            'direction' => 'out',
4154 
            'hdlType' => 'std_logic',
4155 
            'width' => 1,
4156 
          },
4157 
          'en_x19' => {
4158 
            'attributes' => {
4159 
              'bin_pt' => 0,
4160 
              'is_floating_block' => 1,
4161 
              'must_be_hdl_vector' => 1,
4162 
              'period' => 1.0,
4163 
              'port_id' => '0',
4164 
              'simulinkName' => 'INOUT_LOGIC/en',
4165 
              'type' => 'Bool',
4166 
            },
4167 
            'direction' => 'out',
4168 
            'hdlType' => 'std_logic',
4169 
            'width' => 1,
4170 
          },
4171 
          'en_x2' => {
4172 
            'attributes' => {
4173 
              'bin_pt' => 0,
4174 
              'is_floating_block' => 1,
4175 
              'must_be_hdl_vector' => 1,
4176 
              'period' => 1.0,
4177 
              'port_id' => '0',
4178 
              'simulinkName' => 'INOUT_LOGIC/en',
4179 
              'type' => 'Bool',
4180 
            },
4181 
            'direction' => 'out',
4182 
            'hdlType' => 'std_logic',
4183 
            'width' => 1,
4184 
          },
4185 
          'en_x20' => {
4186 
            'attributes' => {
4187 
              'bin_pt' => 0,
4188 
              'is_floating_block' => 1,
4189 
              'must_be_hdl_vector' => 1,
4190 
              'period' => 1.0,
4191 
              'port_id' => '0',
4192 
              'simulinkName' => 'INOUT_LOGIC/en',
4193 
              'type' => 'Bool',
4194 
            },
4195 
            'direction' => 'out',
4196 
            'hdlType' => 'std_logic',
4197 
            'width' => 1,
4198 
          },
4199 
          'en_x21' => {
4200 
            'attributes' => {
4201 
              'bin_pt' => 0,
4202 
              'is_floating_block' => 1,
4203 
              'must_be_hdl_vector' => 1,
4204 
              'period' => 1.0,
4205 
              'port_id' => '0',
4206 
              'simulinkName' => 'INOUT_LOGIC/en',
4207 
              'type' => 'Bool',
4208 
            },
4209 
            'direction' => 'out',
4210 
            'hdlType' => 'std_logic',
4211 
            'width' => 1,
4212 
          },
4213 
          'en_x22' => {
4214 
            'attributes' => {
4215 
              'bin_pt' => 0,
4216 
              'is_floating_block' => 1,
4217 
              'must_be_hdl_vector' => 1,
4218 
              'period' => 1.0,
4219 
              'port_id' => '0',
4220 
              'simulinkName' => 'INOUT_LOGIC/en',
4221 
              'type' => 'Bool',
4222 
            },
4223 
            'direction' => 'out',
4224 
            'hdlType' => 'std_logic',
4225 
            'width' => 1,
4226 
          },
4227 
          'en_x23' => {
4228 
            'attributes' => {
4229 
              'bin_pt' => 0,
4230 
              'is_floating_block' => 1,
4231 
              'must_be_hdl_vector' => 1,
4232 
              'period' => 1.0,
4233 
              'port_id' => '0',
4234 
              'simulinkName' => 'INOUT_LOGIC/en',
4235 
              'type' => 'Bool',
4236 
            },
4237 
            'direction' => 'out',
4238 
            'hdlType' => 'std_logic',
4239 
            'width' => 1,
4240 
          },
4241 
          'en_x24' => {
4242 
            'attributes' => {
4243 
              'bin_pt' => 0,
4244 
              'is_floating_block' => 1,
4245 
              'must_be_hdl_vector' => 1,
4246 
              'period' => 1.0,
4247 
              'port_id' => '0',
4248 
              'simulinkName' => 'INOUT_LOGIC/en',
4249 
              'type' => 'Bool',
4250 
            },
4251 
            'direction' => 'out',
4252 
            'hdlType' => 'std_logic',
4253 
            'width' => 1,
4254 
          },
4255 
          'en_x25' => {
4256 
            'attributes' => {
4257 
              'bin_pt' => 0,
4258 
              'is_floating_block' => 1,
4259 
              'must_be_hdl_vector' => 1,
4260 
              'period' => 1.0,
4261 
              'port_id' => '0',
4262 
              'simulinkName' => 'INOUT_LOGIC/en',
4263 
              'type' => 'Bool',
4264 
            },
4265 
            'direction' => 'out',
4266 
            'hdlType' => 'std_logic',
4267 
            'width' => 1,
4268 
          },
4269 
          'en_x26' => {
4270 
            'attributes' => {
4271 
              'bin_pt' => 0,
4272 
              'is_floating_block' => 1,
4273 
              'must_be_hdl_vector' => 1,
4274 
              'period' => 1.0,
4275 
              'port_id' => '0',
4276 
              'simulinkName' => 'INOUT_LOGIC/en',
4277 
              'type' => 'Bool',
4278 
            },
4279 
            'direction' => 'out',
4280 
            'hdlType' => 'std_logic',
4281 
            'width' => 1,
4282 
          },
4283 
          'en_x27' => {
4284 
            'attributes' => {
4285 
              'bin_pt' => 0,
4286 
              'is_floating_block' => 1,
4287 
              'must_be_hdl_vector' => 1,
4288 
              'period' => 1.0,
4289 
              'port_id' => '0',
4290 
              'simulinkName' => 'INOUT_LOGIC/en',
4291 
              'type' => 'Bool',
4292 
            },
4293 
            'direction' => 'out',
4294 
            'hdlType' => 'std_logic',
4295 
            'width' => 1,
4296 
          },
4297 
          'en_x28' => {
4298 
            'attributes' => {
4299 
              'bin_pt' => 0,
4300 
              'is_floating_block' => 1,
4301 
              'must_be_hdl_vector' => 1,
4302 
              'period' => 1.0,
4303 
              'port_id' => '0',
4304 
              'simulinkName' => 'INOUT_LOGIC/en',
4305 
              'type' => 'Bool',
4306 
            },
4307 
            'direction' => 'out',
4308 
            'hdlType' => 'std_logic',
4309 
            'width' => 1,
4310 
          },
4311 
          'en_x29' => {
4312 
            'attributes' => {
4313 
              'bin_pt' => 0,
4314 
              'is_floating_block' => 1,
4315 
              'must_be_hdl_vector' => 1,
4316 
              'period' => 1.0,
4317 
              'port_id' => '0',
4318 
              'simulinkName' => 'INOUT_LOGIC/en',
4319 
              'type' => 'Bool',
4320 
            },
4321 
            'direction' => 'out',
4322 
            'hdlType' => 'std_logic',
4323 
            'width' => 1,
4324 
          },
4325 
          'en_x3' => {
4326 
            'attributes' => {
4327 
              'bin_pt' => 0,
4328 
              'is_floating_block' => 1,
4329 
              'must_be_hdl_vector' => 1,
4330 
              'period' => 1.0,
4331 
              'port_id' => '0',
4332 
              'simulinkName' => 'INOUT_LOGIC/en',
4333 
              'type' => 'Bool',
4334 
            },
4335 
            'direction' => 'out',
4336 
            'hdlType' => 'std_logic',
4337 
            'width' => 1,
4338 
          },
4339 
          'en_x30' => {
4340 
            'attributes' => {
4341 
              'bin_pt' => 0,
4342 
              'is_floating_block' => 1,
4343 
              'must_be_hdl_vector' => 1,
4344 
              'period' => 1.0,
4345 
              'port_id' => '0',
4346 
              'simulinkName' => 'INOUT_LOGIC/en',
4347 
              'type' => 'Bool',
4348 
            },
4349 
            'direction' => 'out',
4350 
            'hdlType' => 'std_logic',
4351 
            'width' => 1,
4352 
          },
4353 
          'en_x31' => {
4354 
            'attributes' => {
4355 
              'bin_pt' => 0,
4356 
              'is_floating_block' => 1,
4357 
              'must_be_hdl_vector' => 1,
4358 
              'period' => 1.0,
4359 
              'port_id' => '0',
4360 
              'simulinkName' => 'INOUT_LOGIC/en',
4361 
              'type' => 'Bool',
4362 
            },
4363 
            'direction' => 'out',
4364 
            'hdlType' => 'std_logic',
4365 
            'width' => 1,
4366 
          },
4367 
          'en_x32' => {
4368 
            'attributes' => {
4369 
              'bin_pt' => 0,
4370 
              'is_floating_block' => 1,
4371 
              'must_be_hdl_vector' => 1,
4372 
              'period' => 1.0,
4373 
              'port_id' => '0',
4374 
              'simulinkName' => 'INOUT_LOGIC/en',
4375 
              'type' => 'Bool',
4376 
            },
4377 
            'direction' => 'out',
4378 
            'hdlType' => 'std_logic',
4379 
            'width' => 1,
4380 
          },
4381 
          'en_x4' => {
4382 
            'attributes' => {
4383 
              'bin_pt' => 0,
4384 
              'is_floating_block' => 1,
4385 
              'must_be_hdl_vector' => 1,
4386 
              'period' => 1.0,
4387 
              'port_id' => '0',
4388 
              'simulinkName' => 'INOUT_LOGIC/en',
4389 
              'type' => 'Bool',
4390 
            },
4391 
            'direction' => 'out',
4392 
            'hdlType' => 'std_logic',
4393 
            'width' => 1,
4394 
          },
4395 
          'en_x5' => {
4396 
            'attributes' => {
4397 
              'bin_pt' => 0,
4398 
              'is_floating_block' => 1,
4399 
              'must_be_hdl_vector' => 1,
4400 
              'period' => 1.0,
4401 
              'port_id' => '0',
4402 
              'simulinkName' => 'INOUT_LOGIC/en',
4403 
              'type' => 'Bool',
4404 
            },
4405 
            'direction' => 'out',
4406 
            'hdlType' => 'std_logic',
4407 
            'width' => 1,
4408 
          },
4409 
          'en_x6' => {
4410 
            'attributes' => {
4411 
              'bin_pt' => 0,
4412 
              'is_floating_block' => 1,
4413 
              'must_be_hdl_vector' => 1,
4414 
              'period' => 1.0,
4415 
              'port_id' => '0',
4416 
              'simulinkName' => 'INOUT_LOGIC/en',
4417 
              'type' => 'Bool',
4418 
            },
4419 
            'direction' => 'out',
4420 
            'hdlType' => 'std_logic',
4421 
            'width' => 1,
4422 
          },
4423 
          'en_x7' => {
4424 
            'attributes' => {
4425 
              'bin_pt' => 0,
4426 
              'is_floating_block' => 1,
4427 
              'must_be_hdl_vector' => 1,
4428 
              'period' => 1.0,
4429 
              'port_id' => '0',
4430 
              'simulinkName' => 'INOUT_LOGIC/en',
4431 
              'type' => 'Bool',
4432 
            },
4433 
            'direction' => 'out',
4434 
            'hdlType' => 'std_logic',
4435 
            'width' => 1,
4436 
          },
4437 
          'en_x8' => {
4438 
            'attributes' => {
4439 
              'bin_pt' => 0,
4440 
              'is_floating_block' => 1,
4441 
              'must_be_hdl_vector' => 1,
4442 
              'period' => 1.0,
4443 
              'port_id' => '0',
4444 
              'simulinkName' => 'INOUT_LOGIC/en',
4445 
              'type' => 'Bool',
4446 
            },
4447 
            'direction' => 'out',
4448 
            'hdlType' => 'std_logic',
4449 
            'width' => 1,
4450 
          },
4451 
          'en_x9' => {
4452 
            'attributes' => {
4453 
              'bin_pt' => 0,
4454 
              'is_floating_block' => 1,
4455 
              'must_be_hdl_vector' => 1,
4456 
              'period' => 1.0,
4457 
              'port_id' => '0',
4458 
              'simulinkName' => 'INOUT_LOGIC/en',
4459 
              'type' => 'Bool',
4460 
            },
4461 
            'direction' => 'out',
4462 
            'hdlType' => 'std_logic',
4463 
            'width' => 1,
4464 
          },
4465 
          'reg01_rd' => {
4466 
            'attributes' => {
4467 
              'bin_pt' => 0,
4468 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
4469 
              'is_floating_block' => 1,
4470 
              'is_gateway_port' => 1,
4471 
              'must_be_hdl_vector' => 1,
4472 
              'period' => 1.0,
4473 
              'port_id' => '0',
4474 
              'simulinkName' => 'INOUT_LOGIC/reg01_rd',
4475 
              'source_block' => 'INOUT_LOGIC',
4476 
              'timingConstraint' => 'none',
4477 
              'type' => 'UFix_32_0',
4478 
            },
4479 
            'direction' => 'out',
4480 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4481 
            'width' => 32,
4482 
          },
4483 
          'reg01_rv' => {
4484 
            'attributes' => {
4485 
              'bin_pt' => 0,
4486 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
4487 
              'is_floating_block' => 1,
4488 
              'is_gateway_port' => 1,
4489 
              'must_be_hdl_vector' => 1,
4490 
              'period' => 1.0,
4491 
              'port_id' => '0',
4492 
              'simulinkName' => 'INOUT_LOGIC/reg01_rv',
4493 
              'source_block' => 'INOUT_LOGIC',
4494 
              'timingConstraint' => 'none',
4495 
              'type' => 'UFix_1_0',
4496 
            },
4497 
            'direction' => 'out',
4498 
            'hdlType' => 'std_logic',
4499 
            'width' => 1,
4500 
          },
4501 
          'reg01_td' => {
4502 
            'attributes' => {
4503 
              'bin_pt' => 0,
4504 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
4505 
              'is_floating_block' => 1,
4506 
              'is_gateway_port' => 1,
4507 
              'must_be_hdl_vector' => 1,
4508 
              'period' => 1.0,
4509 
              'port_id' => '0',
4510 
              'simulinkName' => 'INOUT_LOGIC/reg01_td',
4511 
              'source_block' => 'INOUT_LOGIC',
4512 
              'timingConstraint' => 'none',
4513 
              'type' => 'UFix_32_0',
4514 
            },
4515 
            'direction' => 'in',
4516 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4517 
            'width' => 32,
4518 
          },
4519 
          'reg01_tv' => {
4520 
            'attributes' => {
4521 
              'bin_pt' => 0,
4522 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
4523 
              'is_floating_block' => 1,
4524 
              'is_gateway_port' => 1,
4525 
              'must_be_hdl_vector' => 1,
4526 
              'period' => 1.0,
4527 
              'port_id' => '0',
4528 
              'simulinkName' => 'INOUT_LOGIC/reg01_tv',
4529 
              'source_block' => 'INOUT_LOGIC',
4530 
              'timingConstraint' => 'none',
4531 
              'type' => 'Bool',
4532 
            },
4533 
            'direction' => 'in',
4534 
            'hdlType' => 'std_logic',
4535 
            'width' => 1,
4536 
          },
4537 
          'reg02_rd' => {
4538 
            'attributes' => {
4539 
              'bin_pt' => 0,
4540 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
4541 
              'is_floating_block' => 1,
4542 
              'is_gateway_port' => 1,
4543 
              'must_be_hdl_vector' => 1,
4544 
              'period' => 1.0,
4545 
              'port_id' => '0',
4546 
              'simulinkName' => 'INOUT_LOGIC/reg02_rd',
4547 
              'source_block' => 'INOUT_LOGIC',
4548 
              'timingConstraint' => 'none',
4549 
              'type' => 'UFix_32_0',
4550 
            },
4551 
            'direction' => 'out',
4552 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4553 
            'width' => 32,
4554 
          },
4555 
          'reg02_rv' => {
4556 
            'attributes' => {
4557 
              'bin_pt' => 0,
4558 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
4559 
              'is_floating_block' => 1,
4560 
              'is_gateway_port' => 1,
4561 
              'must_be_hdl_vector' => 1,
4562 
              'period' => 1.0,
4563 
              'port_id' => '0',
4564 
              'simulinkName' => 'INOUT_LOGIC/reg02_rv',
4565 
              'source_block' => 'INOUT_LOGIC',
4566 
              'timingConstraint' => 'none',
4567 
              'type' => 'UFix_1_0',
4568 
            },
4569 
            'direction' => 'out',
4570 
            'hdlType' => 'std_logic',
4571 
            'width' => 1,
4572 
          },
4573 
          'reg02_td' => {
4574 
            'attributes' => {
4575 
              'bin_pt' => 0,
4576 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
4577 
              'is_floating_block' => 1,
4578 
              'is_gateway_port' => 1,
4579 
              'must_be_hdl_vector' => 1,
4580 
              'period' => 1.0,
4581 
              'port_id' => '0',
4582 
              'simulinkName' => 'INOUT_LOGIC/reg02_td',
4583 
              'source_block' => 'INOUT_LOGIC',
4584 
              'timingConstraint' => 'none',
4585 
              'type' => 'UFix_32_0',
4586 
            },
4587 
            'direction' => 'in',
4588 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4589 
            'width' => 32,
4590 
          },
4591 
          'reg02_tv' => {
4592 
            'attributes' => {
4593 
              'bin_pt' => 0,
4594 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
4595 
              'is_floating_block' => 1,
4596 
              'is_gateway_port' => 1,
4597 
              'must_be_hdl_vector' => 1,
4598 
              'period' => 1.0,
4599 
              'port_id' => '0',
4600 
              'simulinkName' => 'INOUT_LOGIC/reg02_tv',
4601 
              'source_block' => 'INOUT_LOGIC',
4602 
              'timingConstraint' => 'none',
4603 
              'type' => 'Bool',
4604 
            },
4605 
            'direction' => 'in',
4606 
            'hdlType' => 'std_logic',
4607 
            'width' => 1,
4608 
          },
4609 
          'reg03_rd' => {
4610 
            'attributes' => {
4611 
              'bin_pt' => 0,
4612 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
4613 
              'is_floating_block' => 1,
4614 
              'is_gateway_port' => 1,
4615 
              'must_be_hdl_vector' => 1,
4616 
              'period' => 1.0,
4617 
              'port_id' => '0',
4618 
              'simulinkName' => 'INOUT_LOGIC/reg03_rd',
4619 
              'source_block' => 'INOUT_LOGIC',
4620 
              'timingConstraint' => 'none',
4621 
              'type' => 'UFix_32_0',
4622 
            },
4623 
            'direction' => 'out',
4624 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4625 
            'width' => 32,
4626 
          },
4627 
          'reg03_rv' => {
4628 
            'attributes' => {
4629 
              'bin_pt' => 0,
4630 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
4631 
              'is_floating_block' => 1,
4632 
              'is_gateway_port' => 1,
4633 
              'must_be_hdl_vector' => 1,
4634 
              'period' => 1.0,
4635 
              'port_id' => '0',
4636 
              'simulinkName' => 'INOUT_LOGIC/reg03_rv',
4637 
              'source_block' => 'INOUT_LOGIC',
4638 
              'timingConstraint' => 'none',
4639 
              'type' => 'UFix_1_0',
4640 
            },
4641 
            'direction' => 'out',
4642 
            'hdlType' => 'std_logic',
4643 
            'width' => 1,
4644 
          },
4645 
          'reg03_td' => {
4646 
            'attributes' => {
4647 
              'bin_pt' => 0,
4648 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
4649 
              'is_floating_block' => 1,
4650 
              'is_gateway_port' => 1,
4651 
              'must_be_hdl_vector' => 1,
4652 
              'period' => 1.0,
4653 
              'port_id' => '0',
4654 
              'simulinkName' => 'INOUT_LOGIC/reg03_td',
4655 
              'source_block' => 'INOUT_LOGIC',
4656 
              'timingConstraint' => 'none',
4657 
              'type' => 'UFix_32_0',
4658 
            },
4659 
            'direction' => 'in',
4660 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4661 
            'width' => 32,
4662 
          },
4663 
          'reg03_tv' => {
4664 
            'attributes' => {
4665 
              'bin_pt' => 0,
4666 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
4667 
              'is_floating_block' => 1,
4668 
              'is_gateway_port' => 1,
4669 
              'must_be_hdl_vector' => 1,
4670 
              'period' => 1.0,
4671 
              'port_id' => '0',
4672 
              'simulinkName' => 'INOUT_LOGIC/reg03_tv',
4673 
              'source_block' => 'INOUT_LOGIC',
4674 
              'timingConstraint' => 'none',
4675 
              'type' => 'Bool',
4676 
            },
4677 
            'direction' => 'in',
4678 
            'hdlType' => 'std_logic',
4679 
            'width' => 1,
4680 
          },
4681 
          'reg04_rd' => {
4682 
            'attributes' => {
4683 
              'bin_pt' => 0,
4684 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
4685 
              'is_floating_block' => 1,
4686 
              'is_gateway_port' => 1,
4687 
              'must_be_hdl_vector' => 1,
4688 
              'period' => 1.0,
4689 
              'port_id' => '0',
4690 
              'simulinkName' => 'INOUT_LOGIC/reg04_rd',
4691 
              'source_block' => 'INOUT_LOGIC',
4692 
              'timingConstraint' => 'none',
4693 
              'type' => 'UFix_32_0',
4694 
            },
4695 
            'direction' => 'out',
4696 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4697 
            'width' => 32,
4698 
          },
4699 
          'reg04_rv' => {
4700 
            'attributes' => {
4701 
              'bin_pt' => 0,
4702 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
4703 
              'is_floating_block' => 1,
4704 
              'is_gateway_port' => 1,
4705 
              'must_be_hdl_vector' => 1,
4706 
              'period' => 1.0,
4707 
              'port_id' => '0',
4708 
              'simulinkName' => 'INOUT_LOGIC/reg04_rv',
4709 
              'source_block' => 'INOUT_LOGIC',
4710 
              'timingConstraint' => 'none',
4711 
              'type' => 'UFix_1_0',
4712 
            },
4713 
            'direction' => 'out',
4714 
            'hdlType' => 'std_logic',
4715 
            'width' => 1,
4716 
          },
4717 
          'reg04_td' => {
4718 
            'attributes' => {
4719 
              'bin_pt' => 0,
4720 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
4721 
              'is_floating_block' => 1,
4722 
              'is_gateway_port' => 1,
4723 
              'must_be_hdl_vector' => 1,
4724 
              'period' => 1.0,
4725 
              'port_id' => '0',
4726 
              'simulinkName' => 'INOUT_LOGIC/reg04_td',
4727 
              'source_block' => 'INOUT_LOGIC',
4728 
              'timingConstraint' => 'none',
4729 
              'type' => 'UFix_32_0',
4730 
            },
4731 
            'direction' => 'in',
4732 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4733 
            'width' => 32,
4734 
          },
4735 
          'reg04_tv' => {
4736 
            'attributes' => {
4737 
              'bin_pt' => 0,
4738 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
4739 
              'is_floating_block' => 1,
4740 
              'is_gateway_port' => 1,
4741 
              'must_be_hdl_vector' => 1,
4742 
              'period' => 1.0,
4743 
              'port_id' => '0',
4744 
              'simulinkName' => 'INOUT_LOGIC/reg04_tv',
4745 
              'source_block' => 'INOUT_LOGIC',
4746 
              'timingConstraint' => 'none',
4747 
              'type' => 'Bool',
4748 
            },
4749 
            'direction' => 'in',
4750 
            'hdlType' => 'std_logic',
4751 
            'width' => 1,
4752 
          },
4753 
          'reg05_rd' => {
4754 
            'attributes' => {
4755 
              'bin_pt' => 0,
4756 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
4757 
              'is_floating_block' => 1,
4758 
              'is_gateway_port' => 1,
4759 
              'must_be_hdl_vector' => 1,
4760 
              'period' => 1.0,
4761 
              'port_id' => '0',
4762 
              'simulinkName' => 'INOUT_LOGIC/reg05_rd',
4763 
              'source_block' => 'INOUT_LOGIC',
4764 
              'timingConstraint' => 'none',
4765 
              'type' => 'UFix_32_0',
4766 
            },
4767 
            'direction' => 'out',
4768 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4769 
            'width' => 32,
4770 
          },
4771 
          'reg05_rv' => {
4772 
            'attributes' => {
4773 
              'bin_pt' => 0,
4774 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
4775 
              'is_floating_block' => 1,
4776 
              'is_gateway_port' => 1,
4777 
              'must_be_hdl_vector' => 1,
4778 
              'period' => 1.0,
4779 
              'port_id' => '0',
4780 
              'simulinkName' => 'INOUT_LOGIC/reg05_rv',
4781 
              'source_block' => 'INOUT_LOGIC',
4782 
              'timingConstraint' => 'none',
4783 
              'type' => 'UFix_1_0',
4784 
            },
4785 
            'direction' => 'out',
4786 
            'hdlType' => 'std_logic',
4787 
            'width' => 1,
4788 
          },
4789 
          'reg05_td' => {
4790 
            'attributes' => {
4791 
              'bin_pt' => 0,
4792 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
4793 
              'is_floating_block' => 1,
4794 
              'is_gateway_port' => 1,
4795 
              'must_be_hdl_vector' => 1,
4796 
              'period' => 1.0,
4797 
              'port_id' => '0',
4798 
              'simulinkName' => 'INOUT_LOGIC/reg05_td',
4799 
              'source_block' => 'INOUT_LOGIC',
4800 
              'timingConstraint' => 'none',
4801 
              'type' => 'UFix_32_0',
4802 
            },
4803 
            'direction' => 'in',
4804 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4805 
            'width' => 32,
4806 
          },
4807 
          'reg05_tv' => {
4808 
            'attributes' => {
4809 
              'bin_pt' => 0,
4810 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
4811 
              'is_floating_block' => 1,
4812 
              'is_gateway_port' => 1,
4813 
              'must_be_hdl_vector' => 1,
4814 
              'period' => 1.0,
4815 
              'port_id' => '0',
4816 
              'simulinkName' => 'INOUT_LOGIC/reg05_tv',
4817 
              'source_block' => 'INOUT_LOGIC',
4818 
              'timingConstraint' => 'none',
4819 
              'type' => 'Bool',
4820 
            },
4821 
            'direction' => 'in',
4822 
            'hdlType' => 'std_logic',
4823 
            'width' => 1,
4824 
          },
4825 
          'reg06_rd' => {
4826 
            'attributes' => {
4827 
              'bin_pt' => 0,
4828 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
4829 
              'is_floating_block' => 1,
4830 
              'is_gateway_port' => 1,
4831 
              'must_be_hdl_vector' => 1,
4832 
              'period' => 1.0,
4833 
              'port_id' => '0',
4834 
              'simulinkName' => 'INOUT_LOGIC/reg06_rd',
4835 
              'source_block' => 'INOUT_LOGIC',
4836 
              'timingConstraint' => 'none',
4837 
              'type' => 'UFix_32_0',
4838 
            },
4839 
            'direction' => 'out',
4840 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4841 
            'width' => 32,
4842 
          },
4843 
          'reg06_rv' => {
4844 
            'attributes' => {
4845 
              'bin_pt' => 0,
4846 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
4847 
              'is_floating_block' => 1,
4848 
              'is_gateway_port' => 1,
4849 
              'must_be_hdl_vector' => 1,
4850 
              'period' => 1.0,
4851 
              'port_id' => '0',
4852 
              'simulinkName' => 'INOUT_LOGIC/reg06_rv',
4853 
              'source_block' => 'INOUT_LOGIC',
4854 
              'timingConstraint' => 'none',
4855 
              'type' => 'UFix_1_0',
4856 
            },
4857 
            'direction' => 'out',
4858 
            'hdlType' => 'std_logic',
4859 
            'width' => 1,
4860 
          },
4861 
          'reg06_td' => {
4862 
            'attributes' => {
4863 
              'bin_pt' => 0,
4864 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
4865 
              'is_floating_block' => 1,
4866 
              'is_gateway_port' => 1,
4867 
              'must_be_hdl_vector' => 1,
4868 
              'period' => 1.0,
4869 
              'port_id' => '0',
4870 
              'simulinkName' => 'INOUT_LOGIC/reg06_td',
4871 
              'source_block' => 'INOUT_LOGIC',
4872 
              'timingConstraint' => 'none',
4873 
              'type' => 'UFix_32_0',
4874 
            },
4875 
            'direction' => 'in',
4876 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4877 
            'width' => 32,
4878 
          },
4879 
          'reg06_tv' => {
4880 
            'attributes' => {
4881 
              'bin_pt' => 0,
4882 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
4883 
              'is_floating_block' => 1,
4884 
              'is_gateway_port' => 1,
4885 
              'must_be_hdl_vector' => 1,
4886 
              'period' => 1.0,
4887 
              'port_id' => '0',
4888 
              'simulinkName' => 'INOUT_LOGIC/reg06_tv',
4889 
              'source_block' => 'INOUT_LOGIC',
4890 
              'timingConstraint' => 'none',
4891 
              'type' => 'Bool',
4892 
            },
4893 
            'direction' => 'in',
4894 
            'hdlType' => 'std_logic',
4895 
            'width' => 1,
4896 
          },
4897 
          'reg07_rd' => {
4898 
            'attributes' => {
4899 
              'bin_pt' => 0,
4900 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
4901 
              'is_floating_block' => 1,
4902 
              'is_gateway_port' => 1,
4903 
              'must_be_hdl_vector' => 1,
4904 
              'period' => 1.0,
4905 
              'port_id' => '0',
4906 
              'simulinkName' => 'INOUT_LOGIC/reg07_rd',
4907 
              'source_block' => 'INOUT_LOGIC',
4908 
              'timingConstraint' => 'none',
4909 
              'type' => 'UFix_32_0',
4910 
            },
4911 
            'direction' => 'out',
4912 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4913 
            'width' => 32,
4914 
          },
4915 
          'reg07_rv' => {
4916 
            'attributes' => {
4917 
              'bin_pt' => 0,
4918 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
4919 
              'is_floating_block' => 1,
4920 
              'is_gateway_port' => 1,
4921 
              'must_be_hdl_vector' => 1,
4922 
              'period' => 1.0,
4923 
              'port_id' => '0',
4924 
              'simulinkName' => 'INOUT_LOGIC/reg07_rv',
4925 
              'source_block' => 'INOUT_LOGIC',
4926 
              'timingConstraint' => 'none',
4927 
              'type' => 'UFix_1_0',
4928 
            },
4929 
            'direction' => 'out',
4930 
            'hdlType' => 'std_logic',
4931 
            'width' => 1,
4932 
          },
4933 
          'reg07_td' => {
4934 
            'attributes' => {
4935 
              'bin_pt' => 0,
4936 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
4937 
              'is_floating_block' => 1,
4938 
              'is_gateway_port' => 1,
4939 
              'must_be_hdl_vector' => 1,
4940 
              'period' => 1.0,
4941 
              'port_id' => '0',
4942 
              'simulinkName' => 'INOUT_LOGIC/reg07_td',
4943 
              'source_block' => 'INOUT_LOGIC',
4944 
              'timingConstraint' => 'none',
4945 
              'type' => 'UFix_32_0',
4946 
            },
4947 
            'direction' => 'in',
4948 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4949 
            'width' => 32,
4950 
          },
4951 
          'reg07_tv' => {
4952 
            'attributes' => {
4953 
              'bin_pt' => 0,
4954 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
4955 
              'is_floating_block' => 1,
4956 
              'is_gateway_port' => 1,
4957 
              'must_be_hdl_vector' => 1,
4958 
              'period' => 1.0,
4959 
              'port_id' => '0',
4960 
              'simulinkName' => 'INOUT_LOGIC/reg07_tv',
4961 
              'source_block' => 'INOUT_LOGIC',
4962 
              'timingConstraint' => 'none',
4963 
              'type' => 'Bool',
4964 
            },
4965 
            'direction' => 'in',
4966 
            'hdlType' => 'std_logic',
4967 
            'width' => 1,
4968 
          },
4969 
          'reg08_rd' => {
4970 
            'attributes' => {
4971 
              'bin_pt' => 0,
4972 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
4973 
              'is_floating_block' => 1,
4974 
              'is_gateway_port' => 1,
4975 
              'must_be_hdl_vector' => 1,
4976 
              'period' => 1.0,
4977 
              'port_id' => '0',
4978 
              'simulinkName' => 'INOUT_LOGIC/reg08_rd',
4979 
              'source_block' => 'INOUT_LOGIC',
4980 
              'timingConstraint' => 'none',
4981 
              'type' => 'UFix_32_0',
4982 
            },
4983 
            'direction' => 'out',
4984 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4985 
            'width' => 32,
4986 
          },
4987 
          'reg08_rv' => {
4988 
            'attributes' => {
4989 
              'bin_pt' => 0,
4990 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
4991 
              'is_floating_block' => 1,
4992 
              'is_gateway_port' => 1,
4993 
              'must_be_hdl_vector' => 1,
4994 
              'period' => 1.0,
4995 
              'port_id' => '0',
4996 
              'simulinkName' => 'INOUT_LOGIC/reg08_rv',
4997 
              'source_block' => 'INOUT_LOGIC',
4998 
              'timingConstraint' => 'none',
4999 
              'type' => 'UFix_1_0',
5000 
            },
5001 
            'direction' => 'out',
5002 
            'hdlType' => 'std_logic',
5003 
            'width' => 1,
5004 
          },
5005 
          'reg08_td' => {
5006 
            'attributes' => {
5007 
              'bin_pt' => 0,
5008 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
5009 
              'is_floating_block' => 1,
5010 
              'is_gateway_port' => 1,
5011 
              'must_be_hdl_vector' => 1,
5012 
              'period' => 1.0,
5013 
              'port_id' => '0',
5014 
              'simulinkName' => 'INOUT_LOGIC/reg08_td',
5015 
              'source_block' => 'INOUT_LOGIC',
5016 
              'timingConstraint' => 'none',
5017 
              'type' => 'UFix_32_0',
5018 
            },
5019 
            'direction' => 'in',
5020 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5021 
            'width' => 32,
5022 
          },
5023 
          'reg08_tv' => {
5024 
            'attributes' => {
5025 
              'bin_pt' => 0,
5026 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
5027 
              'is_floating_block' => 1,
5028 
              'is_gateway_port' => 1,
5029 
              'must_be_hdl_vector' => 1,
5030 
              'period' => 1.0,
5031 
              'port_id' => '0',
5032 
              'simulinkName' => 'INOUT_LOGIC/reg08_tv',
5033 
              'source_block' => 'INOUT_LOGIC',
5034 
              'timingConstraint' => 'none',
5035 
              'type' => 'Bool',
5036 
            },
5037 
            'direction' => 'in',
5038 
            'hdlType' => 'std_logic',
5039 
            'width' => 1,
5040 
          },
5041 
          'reg09_rd' => {
5042 
            'attributes' => {
5043 
              'bin_pt' => 0,
5044 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
5045 
              'is_floating_block' => 1,
5046 
              'is_gateway_port' => 1,
5047 
              'must_be_hdl_vector' => 1,
5048 
              'period' => 1.0,
5049 
              'port_id' => '0',
5050 
              'simulinkName' => 'INOUT_LOGIC/reg09_rd',
5051 
              'source_block' => 'INOUT_LOGIC',
5052 
              'timingConstraint' => 'none',
5053 
              'type' => 'UFix_32_0',
5054 
            },
5055 
            'direction' => 'out',
5056 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5057 
            'width' => 32,
5058 
          },
5059 
          'reg09_rv' => {
5060 
            'attributes' => {
5061 
              'bin_pt' => 0,
5062 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
5063 
              'is_floating_block' => 1,
5064 
              'is_gateway_port' => 1,
5065 
              'must_be_hdl_vector' => 1,
5066 
              'period' => 1.0,
5067 
              'port_id' => '0',
5068 
              'simulinkName' => 'INOUT_LOGIC/reg09_rv',
5069 
              'source_block' => 'INOUT_LOGIC',
5070 
              'timingConstraint' => 'none',
5071 
              'type' => 'UFix_1_0',
5072 
            },
5073 
            'direction' => 'out',
5074 
            'hdlType' => 'std_logic',
5075 
            'width' => 1,
5076 
          },
5077 
          'reg09_td' => {
5078 
            'attributes' => {
5079 
              'bin_pt' => 0,
5080 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
5081 
              'is_floating_block' => 1,
5082 
              'is_gateway_port' => 1,
5083 
              'must_be_hdl_vector' => 1,
5084 
              'period' => 1.0,
5085 
              'port_id' => '0',
5086 
              'simulinkName' => 'INOUT_LOGIC/reg09_td',
5087 
              'source_block' => 'INOUT_LOGIC',
5088 
              'timingConstraint' => 'none',
5089 
              'type' => 'UFix_32_0',
5090 
            },
5091 
            'direction' => 'in',
5092 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5093 
            'width' => 32,
5094 
          },
5095 
          'reg09_tv' => {
5096 
            'attributes' => {
5097 
              'bin_pt' => 0,
5098 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
5099 
              'is_floating_block' => 1,
5100 
              'is_gateway_port' => 1,
5101 
              'must_be_hdl_vector' => 1,
5102 
              'period' => 1.0,
5103 
              'port_id' => '0',
5104 
              'simulinkName' => 'INOUT_LOGIC/reg09_tv',
5105 
              'source_block' => 'INOUT_LOGIC',
5106 
              'timingConstraint' => 'none',
5107 
              'type' => 'Bool',
5108 
            },
5109 
            'direction' => 'in',
5110 
            'hdlType' => 'std_logic',
5111 
            'width' => 1,
5112 
          },
5113 
          'reg10_rd' => {
5114 
            'attributes' => {
5115 
              'bin_pt' => 0,
5116 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
5117 
              'is_floating_block' => 1,
5118 
              'is_gateway_port' => 1,
5119 
              'must_be_hdl_vector' => 1,
5120 
              'period' => 1.0,
5121 
              'port_id' => '0',
5122 
              'simulinkName' => 'INOUT_LOGIC/reg10_rd',
5123 
              'source_block' => 'INOUT_LOGIC',
5124 
              'timingConstraint' => 'none',
5125 
              'type' => 'UFix_32_0',
5126 
            },
5127 
            'direction' => 'out',
5128 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5129 
            'width' => 32,
5130 
          },
5131 
          'reg10_rv' => {
5132 
            'attributes' => {
5133 
              'bin_pt' => 0,
5134 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
5135 
              'is_floating_block' => 1,
5136 
              'is_gateway_port' => 1,
5137 
              'must_be_hdl_vector' => 1,
5138 
              'period' => 1.0,
5139 
              'port_id' => '0',
5140 
              'simulinkName' => 'INOUT_LOGIC/reg10_rv',
5141 
              'source_block' => 'INOUT_LOGIC',
5142 
              'timingConstraint' => 'none',
5143 
              'type' => 'UFix_1_0',
5144 
            },
5145 
            'direction' => 'out',
5146 
            'hdlType' => 'std_logic',
5147 
            'width' => 1,
5148 
          },
5149 
          'reg10_td' => {
5150 
            'attributes' => {
5151 
              'bin_pt' => 0,
5152 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
5153 
              'is_floating_block' => 1,
5154 
              'is_gateway_port' => 1,
5155 
              'must_be_hdl_vector' => 1,
5156 
              'period' => 1.0,
5157 
              'port_id' => '0',
5158 
              'simulinkName' => 'INOUT_LOGIC/reg10_td',
5159 
              'source_block' => 'INOUT_LOGIC',
5160 
              'timingConstraint' => 'none',
5161 
              'type' => 'UFix_32_0',
5162 
            },
5163 
            'direction' => 'in',
5164 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5165 
            'width' => 32,
5166 
          },
5167 
          'reg10_tv' => {
5168 
            'attributes' => {
5169 
              'bin_pt' => 0,
5170 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
5171 
              'is_floating_block' => 1,
5172 
              'is_gateway_port' => 1,
5173 
              'must_be_hdl_vector' => 1,
5174 
              'period' => 1.0,
5175 
              'port_id' => '0',
5176 
              'simulinkName' => 'INOUT_LOGIC/reg10_tv',
5177 
              'source_block' => 'INOUT_LOGIC',
5178 
              'timingConstraint' => 'none',
5179 
              'type' => 'Bool',
5180 
            },
5181 
            'direction' => 'in',
5182 
            'hdlType' => 'std_logic',
5183 
            'width' => 1,
5184 
          },
5185 
          'reg11_rd' => {
5186 
            'attributes' => {
5187 
              'bin_pt' => 0,
5188 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
5189 
              'is_floating_block' => 1,
5190 
              'is_gateway_port' => 1,
5191 
              'must_be_hdl_vector' => 1,
5192 
              'period' => 1.0,
5193 
              'port_id' => '0',
5194 
              'simulinkName' => 'INOUT_LOGIC/reg11_rd',
5195 
              'source_block' => 'INOUT_LOGIC',
5196 
              'timingConstraint' => 'none',
5197 
              'type' => 'UFix_32_0',
5198 
            },
5199 
            'direction' => 'out',
5200 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5201 
            'width' => 32,
5202 
          },
5203 
          'reg11_rv' => {
5204 
            'attributes' => {
5205 
              'bin_pt' => 0,
5206 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
5207 
              'is_floating_block' => 1,
5208 
              'is_gateway_port' => 1,
5209 
              'must_be_hdl_vector' => 1,
5210 
              'period' => 1.0,
5211 
              'port_id' => '0',
5212 
              'simulinkName' => 'INOUT_LOGIC/reg11_rv',
5213 
              'source_block' => 'INOUT_LOGIC',
5214 
              'timingConstraint' => 'none',
5215 
              'type' => 'UFix_1_0',
5216 
            },
5217 
            'direction' => 'out',
5218 
            'hdlType' => 'std_logic',
5219 
            'width' => 1,
5220 
          },
5221 
          'reg11_td' => {
5222 
            'attributes' => {
5223 
              'bin_pt' => 0,
5224 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
5225 
              'is_floating_block' => 1,
5226 
              'is_gateway_port' => 1,
5227 
              'must_be_hdl_vector' => 1,
5228 
              'period' => 1.0,
5229 
              'port_id' => '0',
5230 
              'simulinkName' => 'INOUT_LOGIC/reg11_td',
5231 
              'source_block' => 'INOUT_LOGIC',
5232 
              'timingConstraint' => 'none',
5233 
              'type' => 'UFix_32_0',
5234 
            },
5235 
            'direction' => 'in',
5236 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5237 
            'width' => 32,
5238 
          },
5239 
          'reg11_tv' => {
5240 
            'attributes' => {
5241 
              'bin_pt' => 0,
5242 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
5243 
              'is_floating_block' => 1,
5244 
              'is_gateway_port' => 1,
5245 
              'must_be_hdl_vector' => 1,
5246 
              'period' => 1.0,
5247 
              'port_id' => '0',
5248 
              'simulinkName' => 'INOUT_LOGIC/reg11_tv',
5249 
              'source_block' => 'INOUT_LOGIC',
5250 
              'timingConstraint' => 'none',
5251 
              'type' => 'Bool',
5252 
            },
5253 
            'direction' => 'in',
5254 
            'hdlType' => 'std_logic',
5255 
            'width' => 1,
5256 
          },
5257 
          'reg12_rd' => {
5258 
            'attributes' => {
5259 
              'bin_pt' => 0,
5260 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
5261 
              'is_floating_block' => 1,
5262 
              'is_gateway_port' => 1,
5263 
              'must_be_hdl_vector' => 1,
5264 
              'period' => 1.0,
5265 
              'port_id' => '0',
5266 
              'simulinkName' => 'INOUT_LOGIC/reg12_rd',
5267 
              'source_block' => 'INOUT_LOGIC',
5268 
              'timingConstraint' => 'none',
5269 
              'type' => 'UFix_32_0',
5270 
            },
5271 
            'direction' => 'out',
5272 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5273 
            'width' => 32,
5274 
          },
5275 
          'reg12_rv' => {
5276 
            'attributes' => {
5277 
              'bin_pt' => 0,
5278 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
5279 
              'is_floating_block' => 1,
5280 
              'is_gateway_port' => 1,
5281 
              'must_be_hdl_vector' => 1,
5282 
              'period' => 1.0,
5283 
              'port_id' => '0',
5284 
              'simulinkName' => 'INOUT_LOGIC/reg12_rv',
5285 
              'source_block' => 'INOUT_LOGIC',
5286 
              'timingConstraint' => 'none',
5287 
              'type' => 'UFix_1_0',
5288 
            },
5289 
            'direction' => 'out',
5290 
            'hdlType' => 'std_logic',
5291 
            'width' => 1,
5292 
          },
5293 
          'reg12_td' => {
5294 
            'attributes' => {
5295 
              'bin_pt' => 0,
5296 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
5297 
              'is_floating_block' => 1,
5298 
              'is_gateway_port' => 1,
5299 
              'must_be_hdl_vector' => 1,
5300 
              'period' => 1.0,
5301 
              'port_id' => '0',
5302 
              'simulinkName' => 'INOUT_LOGIC/reg12_td',
5303 
              'source_block' => 'INOUT_LOGIC',
5304 
              'timingConstraint' => 'none',
5305 
              'type' => 'UFix_32_0',
5306 
            },
5307 
            'direction' => 'in',
5308 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5309 
            'width' => 32,
5310 
          },
5311 
          'reg12_tv' => {
5312 
            'attributes' => {
5313 
              'bin_pt' => 0,
5314 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
5315 
              'is_floating_block' => 1,
5316 
              'is_gateway_port' => 1,
5317 
              'must_be_hdl_vector' => 1,
5318 
              'period' => 1.0,
5319 
              'port_id' => '0',
5320 
              'simulinkName' => 'INOUT_LOGIC/reg12_tv',
5321 
              'source_block' => 'INOUT_LOGIC',
5322 
              'timingConstraint' => 'none',
5323 
              'type' => 'Bool',
5324 
            },
5325 
            'direction' => 'in',
5326 
            'hdlType' => 'std_logic',
5327 
            'width' => 1,
5328 
          },
5329 
          'reg13_rd' => {
5330 
            'attributes' => {
5331 
              'bin_pt' => 0,
5332 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
5333 
              'is_floating_block' => 1,
5334 
              'is_gateway_port' => 1,
5335 
              'must_be_hdl_vector' => 1,
5336 
              'period' => 1.0,
5337 
              'port_id' => '0',
5338 
              'simulinkName' => 'INOUT_LOGIC/reg13_rd',
5339 
              'source_block' => 'INOUT_LOGIC',
5340 
              'timingConstraint' => 'none',
5341 
              'type' => 'UFix_32_0',
5342 
            },
5343 
            'direction' => 'out',
5344 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5345 
            'width' => 32,
5346 
          },
5347 
          'reg13_rv' => {
5348 
            'attributes' => {
5349 
              'bin_pt' => 0,
5350 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
5351 
              'is_floating_block' => 1,
5352 
              'is_gateway_port' => 1,
5353 
              'must_be_hdl_vector' => 1,
5354 
              'period' => 1.0,
5355 
              'port_id' => '0',
5356 
              'simulinkName' => 'INOUT_LOGIC/reg13_rv',
5357 
              'source_block' => 'INOUT_LOGIC',
5358 
              'timingConstraint' => 'none',
5359 
              'type' => 'UFix_1_0',
5360 
            },
5361 
            'direction' => 'out',
5362 
            'hdlType' => 'std_logic',
5363 
            'width' => 1,
5364 
          },
5365 
          'reg13_td' => {
5366 
            'attributes' => {
5367 
              'bin_pt' => 0,
5368 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5369 
              'is_floating_block' => 1,
5370 
              'is_gateway_port' => 1,
5371 
              'must_be_hdl_vector' => 1,
5372 
              'period' => 1.0,
5373 
              'port_id' => '0',
5374 
              'simulinkName' => 'INOUT_LOGIC/reg13_td',
5375 
              'source_block' => 'INOUT_LOGIC',
5376 
              'timingConstraint' => 'none',
5377 
              'type' => 'UFix_32_0',
5378 
            },
5379 
            'direction' => 'in',
5380 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5381 
            'width' => 32,
5382 
          },
5383 
          'reg13_tv' => {
5384 
            'attributes' => {
5385 
              'bin_pt' => 0,
5386 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
5387 
              'is_floating_block' => 1,
5388 
              'is_gateway_port' => 1,
5389 
              'must_be_hdl_vector' => 1,
5390 
              'period' => 1.0,
5391 
              'port_id' => '0',
5392 
              'simulinkName' => 'INOUT_LOGIC/reg13_tv',
5393 
              'source_block' => 'INOUT_LOGIC',
5394 
              'timingConstraint' => 'none',
5395 
              'type' => 'Bool',
5396 
            },
5397 
            'direction' => 'in',
5398 
            'hdlType' => 'std_logic',
5399 
            'width' => 1,
5400 
          },
5401 
          'reg14_rd' => {
5402 
            'attributes' => {
5403 
              'bin_pt' => 0,
5404 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
5405 
              'is_floating_block' => 1,
5406 
              'is_gateway_port' => 1,
5407 
              'must_be_hdl_vector' => 1,
5408 
              'period' => 1.0,
5409 
              'port_id' => '0',
5410 
              'simulinkName' => 'INOUT_LOGIC/reg14_rd',
5411 
              'source_block' => 'INOUT_LOGIC',
5412 
              'timingConstraint' => 'none',
5413 
              'type' => 'UFix_32_0',
5414 
            },
5415 
            'direction' => 'out',
5416 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5417 
            'width' => 32,
5418 
          },
5419 
          'reg14_rv' => {
5420 
            'attributes' => {
5421 
              'bin_pt' => 0,
5422 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
5423 
              'is_floating_block' => 1,
5424 
              'is_gateway_port' => 1,
5425 
              'must_be_hdl_vector' => 1,
5426 
              'period' => 1.0,
5427 
              'port_id' => '0',
5428 
              'simulinkName' => 'INOUT_LOGIC/reg14_rv',
5429 
              'source_block' => 'INOUT_LOGIC',
5430 
              'timingConstraint' => 'none',
5431 
              'type' => 'UFix_1_0',
5432 
            },
5433 
            'direction' => 'out',
5434 
            'hdlType' => 'std_logic',
5435 
            'width' => 1,
5436 
          },
5437 
          'reg14_td' => {
5438 
            'attributes' => {
5439 
              'bin_pt' => 0,
5440 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
5441 
              'is_floating_block' => 1,
5442 
              'is_gateway_port' => 1,
5443 
              'must_be_hdl_vector' => 1,
5444 
              'period' => 1.0,
5445 
              'port_id' => '0',
5446 
              'simulinkName' => 'INOUT_LOGIC/reg14_td',
5447 
              'source_block' => 'INOUT_LOGIC',
5448 
              'timingConstraint' => 'none',
5449 
              'type' => 'UFix_32_0',
5450 
            },
5451 
            'direction' => 'in',
5452 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5453 
            'width' => 32,
5454 
          },
5455 
          'reg14_tv' => {
5456 
            'attributes' => {
5457 
              'bin_pt' => 0,
5458 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5459 
              'is_floating_block' => 1,
5460 
              'is_gateway_port' => 1,
5461 
              'must_be_hdl_vector' => 1,
5462 
              'period' => 1.0,
5463 
              'port_id' => '0',
5464 
              'simulinkName' => 'INOUT_LOGIC/reg14_tv',
5465 
              'source_block' => 'INOUT_LOGIC',
5466 
              'timingConstraint' => 'none',
5467 
              'type' => 'Bool',
5468 
            },
5469 
            'direction' => 'in',
5470 
            'hdlType' => 'std_logic',
5471 
            'width' => 1,
5472 
          },
5473 
        },
5474 
      },
5475 
      'entityName' => 'inout_logic',
5476 
    },
5477 
    'reg01_rd' => {
5478 
      'connections' => { 'reg01_rd' => 'from_register3_data_out_net_x0', },
5479 
      'entity' => {
5480 
        'attributes' => {
5481 
          'isGateway' => 1,
5482 
          'is_floating_block' => 1,
5483 
        },
5484 
        'entityName' => 'reg01_rd',
5485 
        'ports' => {
5486 
          'reg01_rd' => {
5487 
            'attributes' => {
5488 
              'bin_pt' => 0,
5489 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
5490 
              'is_floating_block' => 1,
5491 
              'is_gateway_port' => 1,
5492 
              'must_be_hdl_vector' => 1,
5493 
              'period' => 1.0,
5494 
              'port_id' => '0',
5495 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
5496 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
5497 
              'timingConstraint' => 'none',
5498 
              'type' => 'UFix_32_0',
5499 
            },
5500 
            'direction' => 'in',
5501 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5502 
            'width' => 32,
5503 
          },
5504 
        },
5505 
      },
5506 
      'entityName' => 'reg01_rd',
5507 
    },
5508 
    'reg01_rv' => {
5509 
      'connections' => { 'reg01_rv' => 'from_register1_data_out_net_x0', },
5510 
      'entity' => {
5511 
        'attributes' => {
5512 
          'isGateway' => 1,
5513 
          'is_floating_block' => 1,
5514 
        },
5515 
        'entityName' => 'reg01_rv',
5516 
        'ports' => {
5517 
          'reg01_rv' => {
5518 
            'attributes' => {
5519 
              'bin_pt' => 0,
5520 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
5521 
              'is_floating_block' => 1,
5522 
              'is_gateway_port' => 1,
5523 
              'must_be_hdl_vector' => 1,
5524 
              'period' => 1.0,
5525 
              'port_id' => '0',
5526 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
5527 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
5528 
              'timingConstraint' => 'none',
5529 
              'type' => 'UFix_1_0',
5530 
            },
5531 
            'direction' => 'in',
5532 
            'hdlType' => 'std_logic',
5533 
            'width' => 1,
5534 
          },
5535 
        },
5536 
      },
5537 
      'entityName' => 'reg01_rv',
5538 
    },
5539 
    'reg01_td' => {
5540 
      'connections' => { 'reg01_td' => 'reg01_td_net', },
5541 
      'entity' => {
5542 
        'attributes' => {
5543 
          'isGateway' => 1,
5544 
          'is_floating_block' => 1,
5545 
        },
5546 
        'entityName' => 'reg01_td',
5547 
        'ports' => {
5548 
          'reg01_td' => {
5549 
            'attributes' => {
5550 
              'bin_pt' => 0,
5551 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
5552 
              'is_floating_block' => 1,
5553 
              'is_gateway_port' => 1,
5554 
              'must_be_hdl_vector' => 1,
5555 
              'period' => 1.0,
5556 
              'port_id' => '0',
5557 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
5558 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
5559 
              'timingConstraint' => 'none',
5560 
              'type' => 'UFix_32_0',
5561 
            },
5562 
            'direction' => 'out',
5563 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5564 
            'width' => 32,
5565 
          },
5566 
        },
5567 
      },
5568 
      'entityName' => 'reg01_td',
5569 
    },
5570 
    'reg01_tv' => {
5571 
      'connections' => { 'reg01_tv' => 'reg01_tv_net', },
5572 
      'entity' => {
5573 
        'attributes' => {
5574 
          'isGateway' => 1,
5575 
          'is_floating_block' => 1,
5576 
        },
5577 
        'entityName' => 'reg01_tv',
5578 
        'ports' => {
5579 
          'reg01_tv' => {
5580 
            'attributes' => {
5581 
              'bin_pt' => 0,
5582 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
5583 
              'is_floating_block' => 1,
5584 
              'is_gateway_port' => 1,
5585 
              'must_be_hdl_vector' => 1,
5586 
              'period' => 1.0,
5587 
              'port_id' => '0',
5588 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
5589 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
5590 
              'timingConstraint' => 'none',
5591 
              'type' => 'Bool',
5592 
            },
5593 
            'direction' => 'out',
5594 
            'hdlType' => 'std_logic',
5595 
            'width' => 1,
5596 
          },
5597 
        },
5598 
      },
5599 
      'entityName' => 'reg01_tv',
5600 
    },
5601 
    'reg02_rd' => {
5602 
      'connections' => { 'reg02_rd' => 'from_register5_data_out_net_x0', },
5603 
      'entity' => {
5604 
        'attributes' => {
5605 
          'isGateway' => 1,
5606 
          'is_floating_block' => 1,
5607 
        },
5608 
        'entityName' => 'reg02_rd',
5609 
        'ports' => {
5610 
          'reg02_rd' => {
5611 
            'attributes' => {
5612 
              'bin_pt' => 0,
5613 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
5614 
              'is_floating_block' => 1,
5615 
              'is_gateway_port' => 1,
5616 
              'must_be_hdl_vector' => 1,
5617 
              'period' => 1.0,
5618 
              'port_id' => '0',
5619 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
5620 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
5621 
              'timingConstraint' => 'none',
5622 
              'type' => 'UFix_32_0',
5623 
            },
5624 
            'direction' => 'in',
5625 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5626 
            'width' => 32,
5627 
          },
5628 
        },
5629 
      },
5630 
      'entityName' => 'reg02_rd',
5631 
    },
5632 
    'reg02_rv' => {
5633 
      'connections' => { 'reg02_rv' => 'from_register2_data_out_net_x0', },
5634 
      'entity' => {
5635 
        'attributes' => {
5636 
          'isGateway' => 1,
5637 
          'is_floating_block' => 1,
5638 
        },
5639 
        'entityName' => 'reg02_rv',
5640 
        'ports' => {
5641 
          'reg02_rv' => {
5642 
            'attributes' => {
5643 
              'bin_pt' => 0,
5644 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
5645 
              'is_floating_block' => 1,
5646 
              'is_gateway_port' => 1,
5647 
              'must_be_hdl_vector' => 1,
5648 
              'period' => 1.0,
5649 
              'port_id' => '0',
5650 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
5651 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
5652 
              'timingConstraint' => 'none',
5653 
              'type' => 'UFix_1_0',
5654 
            },
5655 
            'direction' => 'in',
5656 
            'hdlType' => 'std_logic',
5657 
            'width' => 1,
5658 
          },
5659 
        },
5660 
      },
5661 
      'entityName' => 'reg02_rv',
5662 
    },
5663 
    'reg02_td' => {
5664 
      'connections' => { 'reg02_td' => 'reg02_td_net', },
5665 
      'entity' => {
5666 
        'attributes' => {
5667 
          'isGateway' => 1,
5668 
          'is_floating_block' => 1,
5669 
        },
5670 
        'entityName' => 'reg02_td',
5671 
        'ports' => {
5672 
          'reg02_td' => {
5673 
            'attributes' => {
5674 
              'bin_pt' => 0,
5675 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
5676 
              'is_floating_block' => 1,
5677 
              'is_gateway_port' => 1,
5678 
              'must_be_hdl_vector' => 1,
5679 
              'period' => 1.0,
5680 
              'port_id' => '0',
5681 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
5682 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
5683 
              'timingConstraint' => 'none',
5684 
              'type' => 'UFix_32_0',
5685 
            },
5686 
            'direction' => 'out',
5687 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5688 
            'width' => 32,
5689 
          },
5690 
        },
5691 
      },
5692 
      'entityName' => 'reg02_td',
5693 
    },
5694 
    'reg02_tv' => {
5695 
      'connections' => { 'reg02_tv' => 'reg02_tv_net', },
5696 
      'entity' => {
5697 
        'attributes' => {
5698 
          'isGateway' => 1,
5699 
          'is_floating_block' => 1,
5700 
        },
5701 
        'entityName' => 'reg02_tv',
5702 
        'ports' => {
5703 
          'reg02_tv' => {
5704 
            'attributes' => {
5705 
              'bin_pt' => 0,
5706 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
5707 
              'is_floating_block' => 1,
5708 
              'is_gateway_port' => 1,
5709 
              'must_be_hdl_vector' => 1,
5710 
              'period' => 1.0,
5711 
              'port_id' => '0',
5712 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
5713 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
5714 
              'timingConstraint' => 'none',
5715 
              'type' => 'Bool',
5716 
            },
5717 
            'direction' => 'out',
5718 
            'hdlType' => 'std_logic',
5719 
            'width' => 1,
5720 
          },
5721 
        },
5722 
      },
5723 
      'entityName' => 'reg02_tv',
5724 
    },
5725 
    'reg03_rd' => {
5726 
      'connections' => { 'reg03_rd' => 'from_register7_data_out_net_x0', },
5727 
      'entity' => {
5728 
        'attributes' => {
5729 
          'isGateway' => 1,
5730 
          'is_floating_block' => 1,
5731 
        },
5732 
        'entityName' => 'reg03_rd',
5733 
        'ports' => {
5734 
          'reg03_rd' => {
5735 
            'attributes' => {
5736 
              'bin_pt' => 0,
5737 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
5738 
              'is_floating_block' => 1,
5739 
              'is_gateway_port' => 1,
5740 
              'must_be_hdl_vector' => 1,
5741 
              'period' => 1.0,
5742 
              'port_id' => '0',
5743 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
5744 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
5745 
              'timingConstraint' => 'none',
5746 
              'type' => 'UFix_32_0',
5747 
            },
5748 
            'direction' => 'in',
5749 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5750 
            'width' => 32,
5751 
          },
5752 
        },
5753 
      },
5754 
      'entityName' => 'reg03_rd',
5755 
    },
5756 
    'reg03_rv' => {
5757 
      'connections' => { 'reg03_rv' => 'from_register6_data_out_net_x0', },
5758 
      'entity' => {
5759 
        'attributes' => {
5760 
          'isGateway' => 1,
5761 
          'is_floating_block' => 1,
5762 
        },
5763 
        'entityName' => 'reg03_rv',
5764 
        'ports' => {
5765 
          'reg03_rv' => {
5766 
            'attributes' => {
5767 
              'bin_pt' => 0,
5768 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
5769 
              'is_floating_block' => 1,
5770 
              'is_gateway_port' => 1,
5771 
              'must_be_hdl_vector' => 1,
5772 
              'period' => 1.0,
5773 
              'port_id' => '0',
5774 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
5775 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
5776 
              'timingConstraint' => 'none',
5777 
              'type' => 'UFix_1_0',
5778 
            },
5779 
            'direction' => 'in',
5780 
            'hdlType' => 'std_logic',
5781 
            'width' => 1,
5782 
          },
5783 
        },
5784 
      },
5785 
      'entityName' => 'reg03_rv',
5786 
    },
5787 
    'reg03_td' => {
5788 
      'connections' => { 'reg03_td' => 'reg03_td_net', },
5789 
      'entity' => {
5790 
        'attributes' => {
5791 
          'isGateway' => 1,
5792 
          'is_floating_block' => 1,
5793 
        },
5794 
        'entityName' => 'reg03_td',
5795 
        'ports' => {
5796 
          'reg03_td' => {
5797 
            'attributes' => {
5798 
              'bin_pt' => 0,
5799 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
5800 
              'is_floating_block' => 1,
5801 
              'is_gateway_port' => 1,
5802 
              'must_be_hdl_vector' => 1,
5803 
              'period' => 1.0,
5804 
              'port_id' => '0',
5805 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
5806 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
5807 
              'timingConstraint' => 'none',
5808 
              'type' => 'UFix_32_0',
5809 
            },
5810 
            'direction' => 'out',
5811 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5812 
            'width' => 32,
5813 
          },
5814 
        },
5815 
      },
5816 
      'entityName' => 'reg03_td',
5817 
    },
5818 
    'reg03_tv' => {
5819 
      'connections' => { 'reg03_tv' => 'reg03_tv_net', },
5820 
      'entity' => {
5821 
        'attributes' => {
5822 
          'isGateway' => 1,
5823 
          'is_floating_block' => 1,
5824 
        },
5825 
        'entityName' => 'reg03_tv',
5826 
        'ports' => {
5827 
          'reg03_tv' => {
5828 
            'attributes' => {
5829 
              'bin_pt' => 0,
5830 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
5831 
              'is_floating_block' => 1,
5832 
              'is_gateway_port' => 1,
5833 
              'must_be_hdl_vector' => 1,
5834 
              'period' => 1.0,
5835 
              'port_id' => '0',
5836 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
5837 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
5838 
              'timingConstraint' => 'none',
5839 
              'type' => 'Bool',
5840 
            },
5841 
            'direction' => 'out',
5842 
            'hdlType' => 'std_logic',
5843 
            'width' => 1,
5844 
          },
5845 
        },
5846 
      },
5847 
      'entityName' => 'reg03_tv',
5848 
    },
5849 
    'reg04_rd' => {
5850 
      'connections' => { 'reg04_rd' => 'from_register8_data_out_net_x0', },
5851 
      'entity' => {
5852 
        'attributes' => {
5853 
          'isGateway' => 1,
5854 
          'is_floating_block' => 1,
5855 
        },
5856 
        'entityName' => 'reg04_rd',
5857 
        'ports' => {
5858 
          'reg04_rd' => {
5859 
            'attributes' => {
5860 
              'bin_pt' => 0,
5861 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
5862 
              'is_floating_block' => 1,
5863 
              'is_gateway_port' => 1,
5864 
              'must_be_hdl_vector' => 1,
5865 
              'period' => 1.0,
5866 
              'port_id' => '0',
5867 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
5868 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
5869 
              'timingConstraint' => 'none',
5870 
              'type' => 'UFix_32_0',
5871 
            },
5872 
            'direction' => 'in',
5873 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5874 
            'width' => 32,
5875 
          },
5876 
        },
5877 
      },
5878 
      'entityName' => 'reg04_rd',
5879 
    },
5880 
    'reg04_rv' => {
5881 
      'connections' => { 'reg04_rv' => 'from_register4_data_out_net_x0', },
5882 
      'entity' => {
5883 
        'attributes' => {
5884 
          'isGateway' => 1,
5885 
          'is_floating_block' => 1,
5886 
        },
5887 
        'entityName' => 'reg04_rv',
5888 
        'ports' => {
5889 
          'reg04_rv' => {
5890 
            'attributes' => {
5891 
              'bin_pt' => 0,
5892 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
5893 
              'is_floating_block' => 1,
5894 
              'is_gateway_port' => 1,
5895 
              'must_be_hdl_vector' => 1,
5896 
              'period' => 1.0,
5897 
              'port_id' => '0',
5898 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
5899 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
5900 
              'timingConstraint' => 'none',
5901 
              'type' => 'UFix_1_0',
5902 
            },
5903 
            'direction' => 'in',
5904 
            'hdlType' => 'std_logic',
5905 
            'width' => 1,
5906 
          },
5907 
        },
5908 
      },
5909 
      'entityName' => 'reg04_rv',
5910 
    },
5911 
    'reg04_td' => {
5912 
      'connections' => { 'reg04_td' => 'reg04_td_net', },
5913 
      'entity' => {
5914 
        'attributes' => {
5915 
          'isGateway' => 1,
5916 
          'is_floating_block' => 1,
5917 
        },
5918 
        'entityName' => 'reg04_td',
5919 
        'ports' => {
5920 
          'reg04_td' => {
5921 
            'attributes' => {
5922 
              'bin_pt' => 0,
5923 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
5924 
              'is_floating_block' => 1,
5925 
              'is_gateway_port' => 1,
5926 
              'must_be_hdl_vector' => 1,
5927 
              'period' => 1.0,
5928 
              'port_id' => '0',
5929 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
5930 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
5931 
              'timingConstraint' => 'none',
5932 
              'type' => 'UFix_32_0',
5933 
            },
5934 
            'direction' => 'out',
5935 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5936 
            'width' => 32,
5937 
          },
5938 
        },
5939 
      },
5940 
      'entityName' => 'reg04_td',
5941 
    },
5942 
    'reg04_tv' => {
5943 
      'connections' => { 'reg04_tv' => 'reg04_tv_net', },
5944 
      'entity' => {
5945 
        'attributes' => {
5946 
          'isGateway' => 1,
5947 
          'is_floating_block' => 1,
5948 
        },
5949 
        'entityName' => 'reg04_tv',
5950 
        'ports' => {
5951 
          'reg04_tv' => {
5952 
            'attributes' => {
5953 
              'bin_pt' => 0,
5954 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
5955 
              'is_floating_block' => 1,
5956 
              'is_gateway_port' => 1,
5957 
              'must_be_hdl_vector' => 1,
5958 
              'period' => 1.0,
5959 
              'port_id' => '0',
5960 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
5961 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
5962 
              'timingConstraint' => 'none',
5963 
              'type' => 'Bool',
5964 
            },
5965 
            'direction' => 'out',
5966 
            'hdlType' => 'std_logic',
5967 
            'width' => 1,
5968 
          },
5969 
        },
5970 
      },
5971 
      'entityName' => 'reg04_tv',
5972 
    },
5973 
    'reg05_rd' => {
5974 
      'connections' => { 'reg05_rd' => 'from_register10_data_out_net_x0', },
5975 
      'entity' => {
5976 
        'attributes' => {
5977 
          'isGateway' => 1,
5978 
          'is_floating_block' => 1,
5979 
        },
5980 
        'entityName' => 'reg05_rd',
5981 
        'ports' => {
5982 
          'reg05_rd' => {
5983 
            'attributes' => {
5984 
              'bin_pt' => 0,
5985 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
5986 
              'is_floating_block' => 1,
5987 
              'is_gateway_port' => 1,
5988 
              'must_be_hdl_vector' => 1,
5989 
              'period' => 1.0,
5990 
              'port_id' => '0',
5991 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
5992 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
5993 
              'timingConstraint' => 'none',
5994 
              'type' => 'UFix_32_0',
5995 
            },
5996 
            'direction' => 'in',
5997 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5998 
            'width' => 32,
5999 
          },
6000 
        },
6001 
      },
6002 
      'entityName' => 'reg05_rd',
6003 
    },
6004 
    'reg05_rv' => {
6005 
      'connections' => { 'reg05_rv' => 'from_register9_data_out_net_x0', },
6006 
      'entity' => {
6007 
        'attributes' => {
6008 
          'isGateway' => 1,
6009 
          'is_floating_block' => 1,
6010 
        },
6011 
        'entityName' => 'reg05_rv',
6012 
        'ports' => {
6013 
          'reg05_rv' => {
6014 
            'attributes' => {
6015 
              'bin_pt' => 0,
6016 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
6017 
              'is_floating_block' => 1,
6018 
              'is_gateway_port' => 1,
6019 
              'must_be_hdl_vector' => 1,
6020 
              'period' => 1.0,
6021 
              'port_id' => '0',
6022 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
6023 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
6024 
              'timingConstraint' => 'none',
6025 
              'type' => 'UFix_1_0',
6026 
            },
6027 
            'direction' => 'in',
6028 
            'hdlType' => 'std_logic',
6029 
            'width' => 1,
6030 
          },
6031 
        },
6032 
      },
6033 
      'entityName' => 'reg05_rv',
6034 
    },
6035 
    'reg05_td' => {
6036 
      'connections' => { 'reg05_td' => 'reg05_td_net', },
6037 
      'entity' => {
6038 
        'attributes' => {
6039 
          'isGateway' => 1,
6040 
          'is_floating_block' => 1,
6041 
        },
6042 
        'entityName' => 'reg05_td',
6043 
        'ports' => {
6044 
          'reg05_td' => {
6045 
            'attributes' => {
6046 
              'bin_pt' => 0,
6047 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
6048 
              'is_floating_block' => 1,
6049 
              'is_gateway_port' => 1,
6050 
              'must_be_hdl_vector' => 1,
6051 
              'period' => 1.0,
6052 
              'port_id' => '0',
6053 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
6054 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
6055 
              'timingConstraint' => 'none',
6056 
              'type' => 'UFix_32_0',
6057 
            },
6058 
            'direction' => 'out',
6059 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6060 
            'width' => 32,
6061 
          },
6062 
        },
6063 
      },
6064 
      'entityName' => 'reg05_td',
6065 
    },
6066 
    'reg05_tv' => {
6067 
      'connections' => { 'reg05_tv' => 'reg05_tv_net', },
6068 
      'entity' => {
6069 
        'attributes' => {
6070 
          'isGateway' => 1,
6071 
          'is_floating_block' => 1,
6072 
        },
6073 
        'entityName' => 'reg05_tv',
6074 
        'ports' => {
6075 
          'reg05_tv' => {
6076 
            'attributes' => {
6077 
              'bin_pt' => 0,
6078 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
6079 
              'is_floating_block' => 1,
6080 
              'is_gateway_port' => 1,
6081 
              'must_be_hdl_vector' => 1,
6082 
              'period' => 1.0,
6083 
              'port_id' => '0',
6084 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
6085 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
6086 
              'timingConstraint' => 'none',
6087 
              'type' => 'Bool',
6088 
            },
6089 
            'direction' => 'out',
6090 
            'hdlType' => 'std_logic',
6091 
            'width' => 1,
6092 
          },
6093 
        },
6094 
      },
6095 
      'entityName' => 'reg05_tv',
6096 
    },
6097 
    'reg06_rd' => {
6098 
      'connections' => { 'reg06_rd' => 'from_register11_data_out_net_x0', },
6099 
      'entity' => {
6100 
        'attributes' => {
6101 
          'isGateway' => 1,
6102 
          'is_floating_block' => 1,
6103 
        },
6104 
        'entityName' => 'reg06_rd',
6105 
        'ports' => {
6106 
          'reg06_rd' => {
6107 
            'attributes' => {
6108 
              'bin_pt' => 0,
6109 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
6110 
              'is_floating_block' => 1,
6111 
              'is_gateway_port' => 1,
6112 
              'must_be_hdl_vector' => 1,
6113 
              'period' => 1.0,
6114 
              'port_id' => '0',
6115 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
6116 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
6117 
              'timingConstraint' => 'none',
6118 
              'type' => 'UFix_32_0',
6119 
            },
6120 
            'direction' => 'in',
6121 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6122 
            'width' => 32,
6123 
          },
6124 
        },
6125 
      },
6126 
      'entityName' => 'reg06_rd',
6127 
    },
6128 
    'reg06_rv' => {
6129 
      'connections' => { 'reg06_rv' => 'from_register12_data_out_net_x0', },
6130 
      'entity' => {
6131 
        'attributes' => {
6132 
          'isGateway' => 1,
6133 
          'is_floating_block' => 1,
6134 
        },
6135 
        'entityName' => 'reg06_rv',
6136 
        'ports' => {
6137 
          'reg06_rv' => {
6138 
            'attributes' => {
6139 
              'bin_pt' => 0,
6140 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
6141 
              'is_floating_block' => 1,
6142 
              'is_gateway_port' => 1,
6143 
              'must_be_hdl_vector' => 1,
6144 
              'period' => 1.0,
6145 
              'port_id' => '0',
6146 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
6147 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
6148 
              'timingConstraint' => 'none',
6149 
              'type' => 'UFix_1_0',
6150 
            },
6151 
            'direction' => 'in',
6152 
            'hdlType' => 'std_logic',
6153 
            'width' => 1,
6154 
          },
6155 
        },
6156 
      },
6157 
      'entityName' => 'reg06_rv',
6158 
    },
6159 
    'reg06_td' => {
6160 
      'connections' => { 'reg06_td' => 'reg06_td_net', },
6161 
      'entity' => {
6162 
        'attributes' => {
6163 
          'isGateway' => 1,
6164 
          'is_floating_block' => 1,
6165 
        },
6166 
        'entityName' => 'reg06_td',
6167 
        'ports' => {
6168 
          'reg06_td' => {
6169 
            'attributes' => {
6170 
              'bin_pt' => 0,
6171 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
6172 
              'is_floating_block' => 1,
6173 
              'is_gateway_port' => 1,
6174 
              'must_be_hdl_vector' => 1,
6175 
              'period' => 1.0,
6176 
              'port_id' => '0',
6177 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
6178 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
6179 
              'timingConstraint' => 'none',
6180 
              'type' => 'UFix_32_0',
6181 
            },
6182 
            'direction' => 'out',
6183 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6184 
            'width' => 32,
6185 
          },
6186 
        },
6187 
      },
6188 
      'entityName' => 'reg06_td',
6189 
    },
6190 
    'reg06_tv' => {
6191 
      'connections' => { 'reg06_tv' => 'reg06_tv_net', },
6192 
      'entity' => {
6193 
        'attributes' => {
6194 
          'isGateway' => 1,
6195 
          'is_floating_block' => 1,
6196 
        },
6197 
        'entityName' => 'reg06_tv',
6198 
        'ports' => {
6199 
          'reg06_tv' => {
6200 
            'attributes' => {
6201 
              'bin_pt' => 0,
6202 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
6203 
              'is_floating_block' => 1,
6204 
              'is_gateway_port' => 1,
6205 
              'must_be_hdl_vector' => 1,
6206 
              'period' => 1.0,
6207 
              'port_id' => '0',
6208 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
6209 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
6210 
              'timingConstraint' => 'none',
6211 
              'type' => 'Bool',
6212 
            },
6213 
            'direction' => 'out',
6214 
            'hdlType' => 'std_logic',
6215 
            'width' => 1,
6216 
          },
6217 
        },
6218 
      },
6219 
      'entityName' => 'reg06_tv',
6220 
    },
6221 
    'reg07_rd' => {
6222 
      'connections' => { 'reg07_rd' => 'from_register13_data_out_net_x0', },
6223 
      'entity' => {
6224 
        'attributes' => {
6225 
          'isGateway' => 1,
6226 
          'is_floating_block' => 1,
6227 
        },
6228 
        'entityName' => 'reg07_rd',
6229 
        'ports' => {
6230 
          'reg07_rd' => {
6231 
            'attributes' => {
6232 
              'bin_pt' => 0,
6233 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
6234 
              'is_floating_block' => 1,
6235 
              'is_gateway_port' => 1,
6236 
              'must_be_hdl_vector' => 1,
6237 
              'period' => 1.0,
6238 
              'port_id' => '0',
6239 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
6240 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
6241 
              'timingConstraint' => 'none',
6242 
              'type' => 'UFix_32_0',
6243 
            },
6244 
            'direction' => 'in',
6245 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6246 
            'width' => 32,
6247 
          },
6248 
        },
6249 
      },
6250 
      'entityName' => 'reg07_rd',
6251 
    },
6252 
    'reg07_rv' => {
6253 
      'connections' => { 'reg07_rv' => 'from_register14_data_out_net_x0', },
6254 
      'entity' => {
6255 
        'attributes' => {
6256 
          'isGateway' => 1,
6257 
          'is_floating_block' => 1,
6258 
        },
6259 
        'entityName' => 'reg07_rv',
6260 
        'ports' => {
6261 
          'reg07_rv' => {
6262 
            'attributes' => {
6263 
              'bin_pt' => 0,
6264 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
6265 
              'is_floating_block' => 1,
6266 
              'is_gateway_port' => 1,
6267 
              'must_be_hdl_vector' => 1,
6268 
              'period' => 1.0,
6269 
              'port_id' => '0',
6270 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
6271 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
6272 
              'timingConstraint' => 'none',
6273 
              'type' => 'UFix_1_0',
6274 
            },
6275 
            'direction' => 'in',
6276 
            'hdlType' => 'std_logic',
6277 
            'width' => 1,
6278 
          },
6279 
        },
6280 
      },
6281 
      'entityName' => 'reg07_rv',
6282 
    },
6283 
    'reg07_td' => {
6284 
      'connections' => { 'reg07_td' => 'reg07_td_net', },
6285 
      'entity' => {
6286 
        'attributes' => {
6287 
          'isGateway' => 1,
6288 
          'is_floating_block' => 1,
6289 
        },
6290 
        'entityName' => 'reg07_td',
6291 
        'ports' => {
6292 
          'reg07_td' => {
6293 
            'attributes' => {
6294 
              'bin_pt' => 0,
6295 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
6296 
              'is_floating_block' => 1,
6297 
              'is_gateway_port' => 1,
6298 
              'must_be_hdl_vector' => 1,
6299 
              'period' => 1.0,
6300 
              'port_id' => '0',
6301 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
6302 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
6303 
              'timingConstraint' => 'none',
6304 
              'type' => 'UFix_32_0',
6305 
            },
6306 
            'direction' => 'out',
6307 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6308 
            'width' => 32,
6309 
          },
6310 
        },
6311 
      },
6312 
      'entityName' => 'reg07_td',
6313 
    },
6314 
    'reg07_tv' => {
6315 
      'connections' => { 'reg07_tv' => 'reg07_tv_net', },
6316 
      'entity' => {
6317 
        'attributes' => {
6318 
          'isGateway' => 1,
6319 
          'is_floating_block' => 1,
6320 
        },
6321 
        'entityName' => 'reg07_tv',
6322 
        'ports' => {
6323 
          'reg07_tv' => {
6324 
            'attributes' => {
6325 
              'bin_pt' => 0,
6326 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
6327 
              'is_floating_block' => 1,
6328 
              'is_gateway_port' => 1,
6329 
              'must_be_hdl_vector' => 1,
6330 
              'period' => 1.0,
6331 
              'port_id' => '0',
6332 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
6333 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
6334 
              'timingConstraint' => 'none',
6335 
              'type' => 'Bool',
6336 
            },
6337 
            'direction' => 'out',
6338 
            'hdlType' => 'std_logic',
6339 
            'width' => 1,
6340 
          },
6341 
        },
6342 
      },
6343 
      'entityName' => 'reg07_tv',
6344 
    },
6345 
    'reg08_rd' => {
6346 
      'connections' => { 'reg08_rd' => 'from_register15_data_out_net_x0', },
6347 
      'entity' => {
6348 
        'attributes' => {
6349 
          'isGateway' => 1,
6350 
          'is_floating_block' => 1,
6351 
        },
6352 
        'entityName' => 'reg08_rd',
6353 
        'ports' => {
6354 
          'reg08_rd' => {
6355 
            'attributes' => {
6356 
              'bin_pt' => 0,
6357 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
6358 
              'is_floating_block' => 1,
6359 
              'is_gateway_port' => 1,
6360 
              'must_be_hdl_vector' => 1,
6361 
              'period' => 1.0,
6362 
              'port_id' => '0',
6363 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
6364 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
6365 
              'timingConstraint' => 'none',
6366 
              'type' => 'UFix_32_0',
6367 
            },
6368 
            'direction' => 'in',
6369 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6370 
            'width' => 32,
6371 
          },
6372 
        },
6373 
      },
6374 
      'entityName' => 'reg08_rd',
6375 
    },
6376 
    'reg08_rv' => {
6377 
      'connections' => { 'reg08_rv' => 'from_register16_data_out_net_x0', },
6378 
      'entity' => {
6379 
        'attributes' => {
6380 
          'isGateway' => 1,
6381 
          'is_floating_block' => 1,
6382 
        },
6383 
        'entityName' => 'reg08_rv',
6384 
        'ports' => {
6385 
          'reg08_rv' => {
6386 
            'attributes' => {
6387 
              'bin_pt' => 0,
6388 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
6389 
              'is_floating_block' => 1,
6390 
              'is_gateway_port' => 1,
6391 
              'must_be_hdl_vector' => 1,
6392 
              'period' => 1.0,
6393 
              'port_id' => '0',
6394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
6395 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
6396 
              'timingConstraint' => 'none',
6397 
              'type' => 'UFix_1_0',
6398 
            },
6399 
            'direction' => 'in',
6400 
            'hdlType' => 'std_logic',
6401 
            'width' => 1,
6402 
          },
6403 
        },
6404 
      },
6405 
      'entityName' => 'reg08_rv',
6406 
    },
6407 
    'reg08_td' => {
6408 
      'connections' => { 'reg08_td' => 'reg08_td_net', },
6409 
      'entity' => {
6410 
        'attributes' => {
6411 
          'isGateway' => 1,
6412 
          'is_floating_block' => 1,
6413 
        },
6414 
        'entityName' => 'reg08_td',
6415 
        'ports' => {
6416 
          'reg08_td' => {
6417 
            'attributes' => {
6418 
              'bin_pt' => 0,
6419 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
6420 
              'is_floating_block' => 1,
6421 
              'is_gateway_port' => 1,
6422 
              'must_be_hdl_vector' => 1,
6423 
              'period' => 1.0,
6424 
              'port_id' => '0',
6425 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
6426 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
6427 
              'timingConstraint' => 'none',
6428 
              'type' => 'UFix_32_0',
6429 
            },
6430 
            'direction' => 'out',
6431 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6432 
            'width' => 32,
6433 
          },
6434 
        },
6435 
      },
6436 
      'entityName' => 'reg08_td',
6437 
    },
6438 
    'reg08_tv' => {
6439 
      'connections' => { 'reg08_tv' => 'reg08_tv_net', },
6440 
      'entity' => {
6441 
        'attributes' => {
6442 
          'isGateway' => 1,
6443 
          'is_floating_block' => 1,
6444 
        },
6445 
        'entityName' => 'reg08_tv',
6446 
        'ports' => {
6447 
          'reg08_tv' => {
6448 
            'attributes' => {
6449 
              'bin_pt' => 0,
6450 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
6451 
              'is_floating_block' => 1,
6452 
              'is_gateway_port' => 1,
6453 
              'must_be_hdl_vector' => 1,
6454 
              'period' => 1.0,
6455 
              'port_id' => '0',
6456 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
6457 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
6458 
              'timingConstraint' => 'none',
6459 
              'type' => 'Bool',
6460 
            },
6461 
            'direction' => 'out',
6462 
            'hdlType' => 'std_logic',
6463 
            'width' => 1,
6464 
          },
6465 
        },
6466 
      },
6467 
      'entityName' => 'reg08_tv',
6468 
    },
6469 
    'reg09_rd' => {
6470 
      'connections' => { 'reg09_rd' => 'from_register17_data_out_net_x0', },
6471 
      'entity' => {
6472 
        'attributes' => {
6473 
          'isGateway' => 1,
6474 
          'is_floating_block' => 1,
6475 
        },
6476 
        'entityName' => 'reg09_rd',
6477 
        'ports' => {
6478 
          'reg09_rd' => {
6479 
            'attributes' => {
6480 
              'bin_pt' => 0,
6481 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
6482 
              'is_floating_block' => 1,
6483 
              'is_gateway_port' => 1,
6484 
              'must_be_hdl_vector' => 1,
6485 
              'period' => 1.0,
6486 
              'port_id' => '0',
6487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
6488 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
6489 
              'timingConstraint' => 'none',
6490 
              'type' => 'UFix_32_0',
6491 
            },
6492 
            'direction' => 'in',
6493 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6494 
            'width' => 32,
6495 
          },
6496 
        },
6497 
      },
6498 
      'entityName' => 'reg09_rd',
6499 
    },
6500 
    'reg09_rv' => {
6501 
      'connections' => { 'reg09_rv' => 'from_register18_data_out_net_x0', },
6502 
      'entity' => {
6503 
        'attributes' => {
6504 
          'isGateway' => 1,
6505 
          'is_floating_block' => 1,
6506 
        },
6507 
        'entityName' => 'reg09_rv',
6508 
        'ports' => {
6509 
          'reg09_rv' => {
6510 
            'attributes' => {
6511 
              'bin_pt' => 0,
6512 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
6513 
              'is_floating_block' => 1,
6514 
              'is_gateway_port' => 1,
6515 
              'must_be_hdl_vector' => 1,
6516 
              'period' => 1.0,
6517 
              'port_id' => '0',
6518 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
6519 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
6520 
              'timingConstraint' => 'none',
6521 
              'type' => 'UFix_1_0',
6522 
            },
6523 
            'direction' => 'in',
6524 
            'hdlType' => 'std_logic',
6525 
            'width' => 1,
6526 
          },
6527 
        },
6528 
      },
6529 
      'entityName' => 'reg09_rv',
6530 
    },
6531 
    'reg09_td' => {
6532 
      'connections' => { 'reg09_td' => 'reg09_td_net', },
6533 
      'entity' => {
6534 
        'attributes' => {
6535 
          'isGateway' => 1,
6536 
          'is_floating_block' => 1,
6537 
        },
6538 
        'entityName' => 'reg09_td',
6539 
        'ports' => {
6540 
          'reg09_td' => {
6541 
            'attributes' => {
6542 
              'bin_pt' => 0,
6543 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
6544 
              'is_floating_block' => 1,
6545 
              'is_gateway_port' => 1,
6546 
              'must_be_hdl_vector' => 1,
6547 
              'period' => 1.0,
6548 
              'port_id' => '0',
6549 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
6550 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
6551 
              'timingConstraint' => 'none',
6552 
              'type' => 'UFix_32_0',
6553 
            },
6554 
            'direction' => 'out',
6555 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6556 
            'width' => 32,
6557 
          },
6558 
        },
6559 
      },
6560 
      'entityName' => 'reg09_td',
6561 
    },
6562 
    'reg09_tv' => {
6563 
      'connections' => { 'reg09_tv' => 'reg09_tv_net', },
6564 
      'entity' => {
6565 
        'attributes' => {
6566 
          'isGateway' => 1,
6567 
          'is_floating_block' => 1,
6568 
        },
6569 
        'entityName' => 'reg09_tv',
6570 
        'ports' => {
6571 
          'reg09_tv' => {
6572 
            'attributes' => {
6573 
              'bin_pt' => 0,
6574 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
6575 
              'is_floating_block' => 1,
6576 
              'is_gateway_port' => 1,
6577 
              'must_be_hdl_vector' => 1,
6578 
              'period' => 1.0,
6579 
              'port_id' => '0',
6580 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
6581 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
6582 
              'timingConstraint' => 'none',
6583 
              'type' => 'Bool',
6584 
            },
6585 
            'direction' => 'out',
6586 
            'hdlType' => 'std_logic',
6587 
            'width' => 1,
6588 
          },
6589 
        },
6590 
      },
6591 
      'entityName' => 'reg09_tv',
6592 
    },
6593 
    'reg10_rd' => {
6594 
      'connections' => { 'reg10_rd' => 'from_register19_data_out_net_x0', },
6595 
      'entity' => {
6596 
        'attributes' => {
6597 
          'isGateway' => 1,
6598 
          'is_floating_block' => 1,
6599 
        },
6600 
        'entityName' => 'reg10_rd',
6601 
        'ports' => {
6602 
          'reg10_rd' => {
6603 
            'attributes' => {
6604 
              'bin_pt' => 0,
6605 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
6606 
              'is_floating_block' => 1,
6607 
              'is_gateway_port' => 1,
6608 
              'must_be_hdl_vector' => 1,
6609 
              'period' => 1.0,
6610 
              'port_id' => '0',
6611 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
6612 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
6613 
              'timingConstraint' => 'none',
6614 
              'type' => 'UFix_32_0',
6615 
            },
6616 
            'direction' => 'in',
6617 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6618 
            'width' => 32,
6619 
          },
6620 
        },
6621 
      },
6622 
      'entityName' => 'reg10_rd',
6623 
    },
6624 
    'reg10_rv' => {
6625 
      'connections' => { 'reg10_rv' => 'from_register20_data_out_net_x0', },
6626 
      'entity' => {
6627 
        'attributes' => {
6628 
          'isGateway' => 1,
6629 
          'is_floating_block' => 1,
6630 
        },
6631 
        'entityName' => 'reg10_rv',
6632 
        'ports' => {
6633 
          'reg10_rv' => {
6634 
            'attributes' => {
6635 
              'bin_pt' => 0,
6636 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
6637 
              'is_floating_block' => 1,
6638 
              'is_gateway_port' => 1,
6639 
              'must_be_hdl_vector' => 1,
6640 
              'period' => 1.0,
6641 
              'port_id' => '0',
6642 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
6643 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
6644 
              'timingConstraint' => 'none',
6645 
              'type' => 'UFix_1_0',
6646 
            },
6647 
            'direction' => 'in',
6648 
            'hdlType' => 'std_logic',
6649 
            'width' => 1,
6650 
          },
6651 
        },
6652 
      },
6653 
      'entityName' => 'reg10_rv',
6654 
    },
6655 
    'reg10_td' => {
6656 
      'connections' => { 'reg10_td' => 'reg10_td_net', },
6657 
      'entity' => {
6658 
        'attributes' => {
6659 
          'isGateway' => 1,
6660 
          'is_floating_block' => 1,
6661 
        },
6662 
        'entityName' => 'reg10_td',
6663 
        'ports' => {
6664 
          'reg10_td' => {
6665 
            'attributes' => {
6666 
              'bin_pt' => 0,
6667 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
6668 
              'is_floating_block' => 1,
6669 
              'is_gateway_port' => 1,
6670 
              'must_be_hdl_vector' => 1,
6671 
              'period' => 1.0,
6672 
              'port_id' => '0',
6673 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
6674 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
6675 
              'timingConstraint' => 'none',
6676 
              'type' => 'UFix_32_0',
6677 
            },
6678 
            'direction' => 'out',
6679 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6680 
            'width' => 32,
6681 
          },
6682 
        },
6683 
      },
6684 
      'entityName' => 'reg10_td',
6685 
    },
6686 
    'reg10_tv' => {
6687 
      'connections' => { 'reg10_tv' => 'reg10_tv_net', },
6688 
      'entity' => {
6689 
        'attributes' => {
6690 
          'isGateway' => 1,
6691 
          'is_floating_block' => 1,
6692 
        },
6693 
        'entityName' => 'reg10_tv',
6694 
        'ports' => {
6695 
          'reg10_tv' => {
6696 
            'attributes' => {
6697 
              'bin_pt' => 0,
6698 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
6699 
              'is_floating_block' => 1,
6700 
              'is_gateway_port' => 1,
6701 
              'must_be_hdl_vector' => 1,
6702 
              'period' => 1.0,
6703 
              'port_id' => '0',
6704 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
6705 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
6706 
              'timingConstraint' => 'none',
6707 
              'type' => 'Bool',
6708 
            },
6709 
            'direction' => 'out',
6710 
            'hdlType' => 'std_logic',
6711 
            'width' => 1,
6712 
          },
6713 
        },
6714 
      },
6715 
      'entityName' => 'reg10_tv',
6716 
    },
6717 
    'reg11_rd' => {
6718 
      'connections' => { 'reg11_rd' => 'from_register21_data_out_net_x0', },
6719 
      'entity' => {
6720 
        'attributes' => {
6721 
          'isGateway' => 1,
6722 
          'is_floating_block' => 1,
6723 
        },
6724 
        'entityName' => 'reg11_rd',
6725 
        'ports' => {
6726 
          'reg11_rd' => {
6727 
            'attributes' => {
6728 
              'bin_pt' => 0,
6729 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
6730 
              'is_floating_block' => 1,
6731 
              'is_gateway_port' => 1,
6732 
              'must_be_hdl_vector' => 1,
6733 
              'period' => 1.0,
6734 
              'port_id' => '0',
6735 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
6736 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
6737 
              'timingConstraint' => 'none',
6738 
              'type' => 'UFix_32_0',
6739 
            },
6740 
            'direction' => 'in',
6741 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6742 
            'width' => 32,
6743 
          },
6744 
        },
6745 
      },
6746 
      'entityName' => 'reg11_rd',
6747 
    },
6748 
    'reg11_rv' => {
6749 
      'connections' => { 'reg11_rv' => 'from_register22_data_out_net_x0', },
6750 
      'entity' => {
6751 
        'attributes' => {
6752 
          'isGateway' => 1,
6753 
          'is_floating_block' => 1,
6754 
        },
6755 
        'entityName' => 'reg11_rv',
6756 
        'ports' => {
6757 
          'reg11_rv' => {
6758 
            'attributes' => {
6759 
              'bin_pt' => 0,
6760 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
6761 
              'is_floating_block' => 1,
6762 
              'is_gateway_port' => 1,
6763 
              'must_be_hdl_vector' => 1,
6764 
              'period' => 1.0,
6765 
              'port_id' => '0',
6766 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
6767 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
6768 
              'timingConstraint' => 'none',
6769 
              'type' => 'UFix_1_0',
6770 
            },
6771 
            'direction' => 'in',
6772 
            'hdlType' => 'std_logic',
6773 
            'width' => 1,
6774 
          },
6775 
        },
6776 
      },
6777 
      'entityName' => 'reg11_rv',
6778 
    },
6779 
    'reg11_td' => {
6780 
      'connections' => { 'reg11_td' => 'reg11_td_net', },
6781 
      'entity' => {
6782 
        'attributes' => {
6783 
          'isGateway' => 1,
6784 
          'is_floating_block' => 1,
6785 
        },
6786 
        'entityName' => 'reg11_td',
6787 
        'ports' => {
6788 
          'reg11_td' => {
6789 
            'attributes' => {
6790 
              'bin_pt' => 0,
6791 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
6792 
              'is_floating_block' => 1,
6793 
              'is_gateway_port' => 1,
6794 
              'must_be_hdl_vector' => 1,
6795 
              'period' => 1.0,
6796 
              'port_id' => '0',
6797 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
6798 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
6799 
              'timingConstraint' => 'none',
6800 
              'type' => 'UFix_32_0',
6801 
            },
6802 
            'direction' => 'out',
6803 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6804 
            'width' => 32,
6805 
          },
6806 
        },
6807 
      },
6808 
      'entityName' => 'reg11_td',
6809 
    },
6810 
    'reg11_tv' => {
6811 
      'connections' => { 'reg11_tv' => 'reg11_tv_net', },
6812 
      'entity' => {
6813 
        'attributes' => {
6814 
          'isGateway' => 1,
6815 
          'is_floating_block' => 1,
6816 
        },
6817 
        'entityName' => 'reg11_tv',
6818 
        'ports' => {
6819 
          'reg11_tv' => {
6820 
            'attributes' => {
6821 
              'bin_pt' => 0,
6822 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
6823 
              'is_floating_block' => 1,
6824 
              'is_gateway_port' => 1,
6825 
              'must_be_hdl_vector' => 1,
6826 
              'period' => 1.0,
6827 
              'port_id' => '0',
6828 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
6829 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
6830 
              'timingConstraint' => 'none',
6831 
              'type' => 'Bool',
6832 
            },
6833 
            'direction' => 'out',
6834 
            'hdlType' => 'std_logic',
6835 
            'width' => 1,
6836 
          },
6837 
        },
6838 
      },
6839 
      'entityName' => 'reg11_tv',
6840 
    },
6841 
    'reg12_rd' => {
6842 
      'connections' => { 'reg12_rd' => 'from_register23_data_out_net_x0', },
6843 
      'entity' => {
6844 
        'attributes' => {
6845 
          'isGateway' => 1,
6846 
          'is_floating_block' => 1,
6847 
        },
6848 
        'entityName' => 'reg12_rd',
6849 
        'ports' => {
6850 
          'reg12_rd' => {
6851 
            'attributes' => {
6852 
              'bin_pt' => 0,
6853 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
6854 
              'is_floating_block' => 1,
6855 
              'is_gateway_port' => 1,
6856 
              'must_be_hdl_vector' => 1,
6857 
              'period' => 1.0,
6858 
              'port_id' => '0',
6859 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
6860 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
6861 
              'timingConstraint' => 'none',
6862 
              'type' => 'UFix_32_0',
6863 
            },
6864 
            'direction' => 'in',
6865 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6866 
            'width' => 32,
6867 
          },
6868 
        },
6869 
      },
6870 
      'entityName' => 'reg12_rd',
6871 
    },
6872 
    'reg12_rv' => {
6873 
      'connections' => { 'reg12_rv' => 'from_register24_data_out_net_x0', },
6874 
      'entity' => {
6875 
        'attributes' => {
6876 
          'isGateway' => 1,
6877 
          'is_floating_block' => 1,
6878 
        },
6879 
        'entityName' => 'reg12_rv',
6880 
        'ports' => {
6881 
          'reg12_rv' => {
6882 
            'attributes' => {
6883 
              'bin_pt' => 0,
6884 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
6885 
              'is_floating_block' => 1,
6886 
              'is_gateway_port' => 1,
6887 
              'must_be_hdl_vector' => 1,
6888 
              'period' => 1.0,
6889 
              'port_id' => '0',
6890 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
6891 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
6892 
              'timingConstraint' => 'none',
6893 
              'type' => 'UFix_1_0',
6894 
            },
6895 
            'direction' => 'in',
6896 
            'hdlType' => 'std_logic',
6897 
            'width' => 1,
6898 
          },
6899 
        },
6900 
      },
6901 
      'entityName' => 'reg12_rv',
6902 
    },
6903 
    'reg12_td' => {
6904 
      'connections' => { 'reg12_td' => 'reg12_td_net', },
6905 
      'entity' => {
6906 
        'attributes' => {
6907 
          'isGateway' => 1,
6908 
          'is_floating_block' => 1,
6909 
        },
6910 
        'entityName' => 'reg12_td',
6911 
        'ports' => {
6912 
          'reg12_td' => {
6913 
            'attributes' => {
6914 
              'bin_pt' => 0,
6915 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
6916 
              'is_floating_block' => 1,
6917 
              'is_gateway_port' => 1,
6918 
              'must_be_hdl_vector' => 1,
6919 
              'period' => 1.0,
6920 
              'port_id' => '0',
6921 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
6922 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
6923 
              'timingConstraint' => 'none',
6924 
              'type' => 'UFix_32_0',
6925 
            },
6926 
            'direction' => 'out',
6927 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6928 
            'width' => 32,
6929 
          },
6930 
        },
6931 
      },
6932 
      'entityName' => 'reg12_td',
6933 
    },
6934 
    'reg12_tv' => {
6935 
      'connections' => { 'reg12_tv' => 'reg12_tv_net', },
6936 
      'entity' => {
6937 
        'attributes' => {
6938 
          'isGateway' => 1,
6939 
          'is_floating_block' => 1,
6940 
        },
6941 
        'entityName' => 'reg12_tv',
6942 
        'ports' => {
6943 
          'reg12_tv' => {
6944 
            'attributes' => {
6945 
              'bin_pt' => 0,
6946 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
6947 
              'is_floating_block' => 1,
6948 
              'is_gateway_port' => 1,
6949 
              'must_be_hdl_vector' => 1,
6950 
              'period' => 1.0,
6951 
              'port_id' => '0',
6952 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
6953 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
6954 
              'timingConstraint' => 'none',
6955 
              'type' => 'Bool',
6956 
            },
6957 
            'direction' => 'out',
6958 
            'hdlType' => 'std_logic',
6959 
            'width' => 1,
6960 
          },
6961 
        },
6962 
      },
6963 
      'entityName' => 'reg12_tv',
6964 
    },
6965 
    'reg13_rd' => {
6966 
      'connections' => { 'reg13_rd' => 'from_register25_data_out_net_x0', },
6967 
      'entity' => {
6968 
        'attributes' => {
6969 
          'isGateway' => 1,
6970 
          'is_floating_block' => 1,
6971 
        },
6972 
        'entityName' => 'reg13_rd',
6973 
        'ports' => {
6974 
          'reg13_rd' => {
6975 
            'attributes' => {
6976 
              'bin_pt' => 0,
6977 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
6978 
              'is_floating_block' => 1,
6979 
              'is_gateway_port' => 1,
6980 
              'must_be_hdl_vector' => 1,
6981 
              'period' => 1.0,
6982 
              'port_id' => '0',
6983 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
6984 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
6985 
              'timingConstraint' => 'none',
6986 
              'type' => 'UFix_32_0',
6987 
            },
6988 
            'direction' => 'in',
6989 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6990 
            'width' => 32,
6991 
          },
6992 
        },
6993 
      },
6994 
      'entityName' => 'reg13_rd',
6995 
    },
6996 
    'reg13_rv' => {
6997 
      'connections' => { 'reg13_rv' => 'from_register26_data_out_net_x0', },
6998 
      'entity' => {
6999 
        'attributes' => {
7000 
          'isGateway' => 1,
7001 
          'is_floating_block' => 1,
7002 
        },
7003 
        'entityName' => 'reg13_rv',
7004 
        'ports' => {
7005 
          'reg13_rv' => {
7006 
            'attributes' => {
7007 
              'bin_pt' => 0,
7008 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
7009 
              'is_floating_block' => 1,
7010 
              'is_gateway_port' => 1,
7011 
              'must_be_hdl_vector' => 1,
7012 
              'period' => 1.0,
7013 
              'port_id' => '0',
7014 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
7015 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
7016 
              'timingConstraint' => 'none',
7017 
              'type' => 'UFix_1_0',
7018 
            },
7019 
            'direction' => 'in',
7020 
            'hdlType' => 'std_logic',
7021 
            'width' => 1,
7022 
          },
7023 
        },
7024 
      },
7025 
      'entityName' => 'reg13_rv',
7026 
    },
7027 
    'reg13_td' => {
7028 
      'connections' => { 'reg13_td' => 'reg13_td_net', },
7029 
      'entity' => {
7030 
        'attributes' => {
7031 
          'isGateway' => 1,
7032 
          'is_floating_block' => 1,
7033 
        },
7034 
        'entityName' => 'reg13_td',
7035 
        'ports' => {
7036 
          'reg13_td' => {
7037 
            'attributes' => {
7038 
              'bin_pt' => 0,
7039 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
7040 
              'is_floating_block' => 1,
7041 
              'is_gateway_port' => 1,
7042 
              'must_be_hdl_vector' => 1,
7043 
              'period' => 1.0,
7044 
              'port_id' => '0',
7045 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
7046 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
7047 
              'timingConstraint' => 'none',
7048 
              'type' => 'UFix_32_0',
7049 
            },
7050 
            'direction' => 'out',
7051 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7052 
            'width' => 32,
7053 
          },
7054 
        },
7055 
      },
7056 
      'entityName' => 'reg13_td',
7057 
    },
7058 
    'reg13_tv' => {
7059 
      'connections' => { 'reg13_tv' => 'reg13_tv_net', },
7060 
      'entity' => {
7061 
        'attributes' => {
7062 
          'isGateway' => 1,
7063 
          'is_floating_block' => 1,
7064 
        },
7065 
        'entityName' => 'reg13_tv',
7066 
        'ports' => {
7067 
          'reg13_tv' => {
7068 
            'attributes' => {
7069 
              'bin_pt' => 0,
7070 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
7071 
              'is_floating_block' => 1,
7072 
              'is_gateway_port' => 1,
7073 
              'must_be_hdl_vector' => 1,
7074 
              'period' => 1.0,
7075 
              'port_id' => '0',
7076 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
7077 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
7078 
              'timingConstraint' => 'none',
7079 
              'type' => 'Bool',
7080 
            },
7081 
            'direction' => 'out',
7082 
            'hdlType' => 'std_logic',
7083 
            'width' => 1,
7084 
          },
7085 
        },
7086 
      },
7087 
      'entityName' => 'reg13_tv',
7088 
    },
7089 
    'reg14_rd' => {
7090 
      'connections' => { 'reg14_rd' => 'from_register27_data_out_net_x0', },
7091 
      'entity' => {
7092 
        'attributes' => {
7093 
          'isGateway' => 1,
7094 
          'is_floating_block' => 1,
7095 
        },
7096 
        'entityName' => 'reg14_rd',
7097 
        'ports' => {
7098 
          'reg14_rd' => {
7099 
            'attributes' => {
7100 
              'bin_pt' => 0,
7101 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
7102 
              'is_floating_block' => 1,
7103 
              'is_gateway_port' => 1,
7104 
              'must_be_hdl_vector' => 1,
7105 
              'period' => 1.0,
7106 
              'port_id' => '0',
7107 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
7108 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
7109 
              'timingConstraint' => 'none',
7110 
              'type' => 'UFix_32_0',
7111 
            },
7112 
            'direction' => 'in',
7113 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7114 
            'width' => 32,
7115 
          },
7116 
        },
7117 
      },
7118 
      'entityName' => 'reg14_rd',
7119 
    },
7120 
    'reg14_rv' => {
7121 
      'connections' => { 'reg14_rv' => 'from_register28_data_out_net_x0', },
7122 
      'entity' => {
7123 
        'attributes' => {
7124 
          'isGateway' => 1,
7125 
          'is_floating_block' => 1,
7126 
        },
7127 
        'entityName' => 'reg14_rv',
7128 
        'ports' => {
7129 
          'reg14_rv' => {
7130 
            'attributes' => {
7131 
              'bin_pt' => 0,
7132 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
7133 
              'is_floating_block' => 1,
7134 
              'is_gateway_port' => 1,
7135 
              'must_be_hdl_vector' => 1,
7136 
              'period' => 1.0,
7137 
              'port_id' => '0',
7138 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
7139 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
7140 
              'timingConstraint' => 'none',
7141 
              'type' => 'UFix_1_0',
7142 
            },
7143 
            'direction' => 'in',
7144 
            'hdlType' => 'std_logic',
7145 
            'width' => 1,
7146 
          },
7147 
        },
7148 
      },
7149 
      'entityName' => 'reg14_rv',
7150 
    },
7151 
    'reg14_td' => {
7152 
      'connections' => { 'reg14_td' => 'reg14_td_net', },
7153 
      'entity' => {
7154 
        'attributes' => {
7155 
          'isGateway' => 1,
7156 
          'is_floating_block' => 1,
7157 
        },
7158 
        'entityName' => 'reg14_td',
7159 
        'ports' => {
7160 
          'reg14_td' => {
7161 
            'attributes' => {
7162 
              'bin_pt' => 0,
7163 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
7164 
              'is_floating_block' => 1,
7165 
              'is_gateway_port' => 1,
7166 
              'must_be_hdl_vector' => 1,
7167 
              'period' => 1.0,
7168 
              'port_id' => '0',
7169 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
7170 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
7171 
              'timingConstraint' => 'none',
7172 
              'type' => 'UFix_32_0',
7173 
            },
7174 
            'direction' => 'out',
7175 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7176 
            'width' => 32,
7177 
          },
7178 
        },
7179 
      },
7180 
      'entityName' => 'reg14_td',
7181 
    },
7182 
    'reg14_tv' => {
7183 
      'connections' => { 'reg14_tv' => 'reg14_tv_net', },
7184 
      'entity' => {
7185 
        'attributes' => {
7186 
          'isGateway' => 1,
7187 
          'is_floating_block' => 1,
7188 
        },
7189 
        'entityName' => 'reg14_tv',
7190 
        'ports' => {
7191 
          'reg14_tv' => {
7192 
            'attributes' => {
7193 
              'bin_pt' => 0,
7194 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
7195 
              'is_floating_block' => 1,
7196 
              'is_gateway_port' => 1,
7197 
              'must_be_hdl_vector' => 1,
7198 
              'period' => 1.0,
7199 
              'port_id' => '0',
7200 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
7201 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
7202 
              'timingConstraint' => 'none',
7203 
              'type' => 'Bool',
7204 
            },
7205 
            'direction' => 'out',
7206 
            'hdlType' => 'std_logic',
7207 
            'width' => 1,
7208 
          },
7209 
        },
7210 
      },
7211 
      'entityName' => 'reg14_tv',
7212 
    },
7213 
    'to_register1' => {
7214 
      'connections' => {
7215 
        'ce' => 'ce_1_sg',
7216 
        'clk' => 'clk_1_sg',
7217 
        'clr' => [
7218 
          'constant',
7219 
          '\'0\'',
7220 
        ],
7221 
        'data_in' => 'debug_in_2i_net_x0',
7222 
        'dout' => 'to_register1_dout_net',
7223 
        'en' => 'constant5_op_net_x0',
7224 
      },
7225 
      'entity' => {
7226 
        'attributes' => {
7227 
          'generics' => [],
7228 
          'is_floating_block' => 1,
7229 
          'mask' => {
7230 
            'Block_Handle' => 2118.00048828125,
7231 
            'Block_handle' => 2118.00048828125,
7232 
            'MDL_Handle' => 2083.00048828125,
7233 
            'MDL_handle' => 2083.00048828125,
7234 
            'arith_type' => 1,
7235 
            'bin_pt' => 14,
7236 
            'block_config' => 'sysgen_blockset:toreg_config',
7237 
            'block_handle' => 2118.00048828125,
7238 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
7239 
            'block_type' => 'toreg',
7240 
            'dbl_ovrd' => 0,
7241 
            'explicit_data_type' => 0,
7242 
            'gui_display_data_type' => 1,
7243 
            'init' => 0.0,
7244 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
7245 
            'mdl_handle' => 2083.00048828125,
7246 
            'model_handle' => 2083.00048828125,
7247 
            'n_bits' => 16,
7248 
            'ownership' => 1,
7249 
            'preci_type' => 1,
7250 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7251 
            'shared_memory_name' => 'debug2i',
7252 
          },
7253 
          'needs_vhdl_wrapper' => 0,
7254 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
7255 
        },
7256 
        'entityName' => 'x',
7257 
        'ports' => {
7258 
          'ce' => {
7259 
            'attributes' => {
7260 
              'domain' => '',
7261 
              'group' => 1,
7262 
              'isCe' => 1,
7263 
              'is_floating_block' => 1,
7264 
              'period' => 1.0,
7265 
              'type' => 'logic',
7266 
            },
7267 
            'direction' => 'in',
7268 
            'hdlType' => 'std_logic',
7269 
            'width' => 1,
7270 
          },
7271 
          'clk' => {
7272 
            'attributes' => {
7273 
              'domain' => '',
7274 
              'group' => 1,
7275 
              'isClk' => 1,
7276 
              'is_floating_block' => 1,
7277 
              'period' => 1.0,
7278 
              'type' => 'logic',
7279 
            },
7280 
            'direction' => 'in',
7281 
            'hdlType' => 'std_logic',
7282 
            'width' => 1,
7283 
          },
7284 
          'clr' => {
7285 
            'attributes' => {
7286 
              'domain' => '',
7287 
              'group' => 1,
7288 
              'isClr' => 1,
7289 
              'is_floating_block' => 1,
7290 
              'period' => 1,
7291 
              'type' => 'logic',
7292 
              'valid_bit_used' => 0,
7293 
            },
7294 
            'direction' => 'in',
7295 
            'hdlType' => 'std_logic',
7296 
            'width' => 1,
7297 
          },
7298 
          'data_in' => {
7299 
            'attributes' => {
7300 
              'bin_pt' => 0,
7301 
              'is_floating_block' => 1,
7302 
              'must_be_hdl_vector' => 1,
7303 
              'period' => 1.0,
7304 
              'port_id' => '0',
7305 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
7306 
              'type' => 'UFix_32_0',
7307 
            },
7308 
            'direction' => 'in',
7309 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7310 
            'width' => 32,
7311 
          },
7312 
          'dout' => {
7313 
            'attributes' => {
7314 
              'bin_pt' => 0,
7315 
              'is_floating_block' => 1,
7316 
              'must_be_hdl_vector' => 1,
7317 
              'period' => 1.0,
7318 
              'port_id' => '0',
7319 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
7320 
              'type' => 'UFix_32_0',
7321 
            },
7322 
            'direction' => 'out',
7323 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7324 
            'width' => 32,
7325 
          },
7326 
          'en' => {
7327 
            'attributes' => {
7328 
              'bin_pt' => 0,
7329 
              'is_floating_block' => 1,
7330 
              'must_be_hdl_vector' => 1,
7331 
              'period' => 1.0,
7332 
              'port_id' => '1',
7333 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
7334 
              'type' => 'Bool',
7335 
            },
7336 
            'direction' => 'in',
7337 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7338 
            'width' => 1,
7339 
          },
7340 
        },
7341 
      },
7342 
      'entityName' => 'x',
7343 
    },
7344 
    'to_register10' => {
7345 
      'connections' => {
7346 
        'ce' => 'ce_1_sg',
7347 
        'clk' => 'clk_1_sg',
7348 
        'clr' => [
7349 
          'constant',
7350 
          '\'0\'',
7351 
        ],
7352 
        'data_in' => 'reg04_tv_net_x0',
7353 
        'dout' => 'to_register10_dout_net',
7354 
        'en' => 'constant5_op_net_x1',
7355 
      },
7356 
      'entity' => {
7357 
        'attributes' => {
7358 
          'generics' => [],
7359 
          'is_floating_block' => 1,
7360 
          'mask' => {
7361 
            'Block_Handle' => 2119.00048828125,
7362 
            'Block_handle' => 2119.00048828125,
7363 
            'MDL_Handle' => 2083.00048828125,
7364 
            'MDL_handle' => 2083.00048828125,
7365 
            'arith_type' => 1,
7366 
            'bin_pt' => 14,
7367 
            'block_config' => 'sysgen_blockset:toreg_config',
7368 
            'block_handle' => 2119.00048828125,
7369 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
7370 
            'block_type' => 'toreg',
7371 
            'dbl_ovrd' => 0,
7372 
            'explicit_data_type' => 0,
7373 
            'gui_display_data_type' => 1,
7374 
            'init' => 0.0,
7375 
            'init_bit_vector' => '\'b0',
7376 
            'mdl_handle' => 2083.00048828125,
7377 
            'model_handle' => 2083.00048828125,
7378 
            'n_bits' => 16,
7379 
            'ownership' => 1,
7380 
            'preci_type' => 1,
7381 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7382 
            'shared_memory_name' => 'register04tv',
7383 
          },
7384 
          'needs_vhdl_wrapper' => 0,
7385 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
7386 
        },
7387 
        'entityName' => 'x_x0',
7388 
        'ports' => {
7389 
          'ce' => {
7390 
            'attributes' => {
7391 
              'domain' => '',
7392 
              'group' => 1,
7393 
              'isCe' => 1,
7394 
              'is_floating_block' => 1,
7395 
              'period' => 1.0,
7396 
              'type' => 'logic',
7397 
            },
7398 
            'direction' => 'in',
7399 
            'hdlType' => 'std_logic',
7400 
            'width' => 1,
7401 
          },
7402 
          'clk' => {
7403 
            'attributes' => {
7404 
              'domain' => '',
7405 
              'group' => 1,
7406 
              'isClk' => 1,
7407 
              'is_floating_block' => 1,
7408 
              'period' => 1.0,
7409 
              'type' => 'logic',
7410 
            },
7411 
            'direction' => 'in',
7412 
            'hdlType' => 'std_logic',
7413 
            'width' => 1,
7414 
          },
7415 
          'clr' => {
7416 
            'attributes' => {
7417 
              'domain' => '',
7418 
              'group' => 1,
7419 
              'isClr' => 1,
7420 
              'is_floating_block' => 1,
7421 
              'period' => 1,
7422 
              'type' => 'logic',
7423 
              'valid_bit_used' => 0,
7424 
            },
7425 
            'direction' => 'in',
7426 
            'hdlType' => 'std_logic',
7427 
            'width' => 1,
7428 
          },
7429 
          'data_in' => {
7430 
            'attributes' => {
7431 
              'bin_pt' => 0,
7432 
              'is_floating_block' => 1,
7433 
              'must_be_hdl_vector' => 1,
7434 
              'period' => 1.0,
7435 
              'port_id' => '0',
7436 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
7437 
              'type' => 'Bool',
7438 
            },
7439 
            'direction' => 'in',
7440 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7441 
            'width' => 1,
7442 
          },
7443 
          'dout' => {
7444 
            'attributes' => {
7445 
              'bin_pt' => 0,
7446 
              'is_floating_block' => 1,
7447 
              'must_be_hdl_vector' => 1,
7448 
              'period' => 1.0,
7449 
              'port_id' => '0',
7450 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
7451 
              'type' => 'Bool',
7452 
            },
7453 
            'direction' => 'out',
7454 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7455 
            'width' => 1,
7456 
          },
7457 
          'en' => {
7458 
            'attributes' => {
7459 
              'bin_pt' => 0,
7460 
              'is_floating_block' => 1,
7461 
              'must_be_hdl_vector' => 1,
7462 
              'period' => 1.0,
7463 
              'port_id' => '1',
7464 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
7465 
              'type' => 'Bool',
7466 
            },
7467 
            'direction' => 'in',
7468 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7469 
            'width' => 1,
7470 
          },
7471 
        },
7472 
      },
7473 
      'entityName' => 'x_x0',
7474 
    },
7475 
    'to_register11' => {
7476 
      'connections' => {
7477 
        'ce' => 'ce_1_sg',
7478 
        'clk' => 'clk_1_sg',
7479 
        'clr' => [
7480 
          'constant',
7481 
          '\'0\'',
7482 
        ],
7483 
        'data_in' => 'reg04_td_net_x0',
7484 
        'dout' => 'to_register11_dout_net',
7485 
        'en' => 'constant5_op_net_x2',
7486 
      },
7487 
      'entity' => {
7488 
        'attributes' => {
7489 
          'generics' => [],
7490 
          'is_floating_block' => 1,
7491 
          'mask' => {
7492 
            'Block_Handle' => 2120.00048828125,
7493 
            'Block_handle' => 2120.00048828125,
7494 
            'MDL_Handle' => 2083.00048828125,
7495 
            'MDL_handle' => 2083.00048828125,
7496 
            'arith_type' => 1,
7497 
            'bin_pt' => 14,
7498 
            'block_config' => 'sysgen_blockset:toreg_config',
7499 
            'block_handle' => 2120.00048828125,
7500 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
7501 
            'block_type' => 'toreg',
7502 
            'dbl_ovrd' => 0,
7503 
            'explicit_data_type' => 0,
7504 
            'gui_display_data_type' => 1,
7505 
            'init' => 0.0,
7506 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
7507 
            'mdl_handle' => 2083.00048828125,
7508 
            'model_handle' => 2083.00048828125,
7509 
            'n_bits' => 16,
7510 
            'ownership' => 1,
7511 
            'preci_type' => 1,
7512 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7513 
            'shared_memory_name' => 'register04td',
7514 
          },
7515 
          'needs_vhdl_wrapper' => 0,
7516 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
7517 
        },
7518 
        'entityName' => 'x_x1',
7519 
        'ports' => {
7520 
          'ce' => {
7521 
            'attributes' => {
7522 
              'domain' => '',
7523 
              'group' => 1,
7524 
              'isCe' => 1,
7525 
              'is_floating_block' => 1,
7526 
              'period' => 1.0,
7527 
              'type' => 'logic',
7528 
            },
7529 
            'direction' => 'in',
7530 
            'hdlType' => 'std_logic',
7531 
            'width' => 1,
7532 
          },
7533 
          'clk' => {
7534 
            'attributes' => {
7535 
              'domain' => '',
7536 
              'group' => 1,
7537 
              'isClk' => 1,
7538 
              'is_floating_block' => 1,
7539 
              'period' => 1.0,
7540 
              'type' => 'logic',
7541 
            },
7542 
            'direction' => 'in',
7543 
            'hdlType' => 'std_logic',
7544 
            'width' => 1,
7545 
          },
7546 
          'clr' => {
7547 
            'attributes' => {
7548 
              'domain' => '',
7549 
              'group' => 1,
7550 
              'isClr' => 1,
7551 
              'is_floating_block' => 1,
7552 
              'period' => 1,
7553 
              'type' => 'logic',
7554 
              'valid_bit_used' => 0,
7555 
            },
7556 
            'direction' => 'in',
7557 
            'hdlType' => 'std_logic',
7558 
            'width' => 1,
7559 
          },
7560 
          'data_in' => {
7561 
            'attributes' => {
7562 
              'bin_pt' => 0,
7563 
              'is_floating_block' => 1,
7564 
              'must_be_hdl_vector' => 1,
7565 
              'period' => 1.0,
7566 
              'port_id' => '0',
7567 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
7568 
              'type' => 'UFix_32_0',
7569 
            },
7570 
            'direction' => 'in',
7571 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7572 
            'width' => 32,
7573 
          },
7574 
          'dout' => {
7575 
            'attributes' => {
7576 
              'bin_pt' => 0,
7577 
              'is_floating_block' => 1,
7578 
              'must_be_hdl_vector' => 1,
7579 
              'period' => 1.0,
7580 
              'port_id' => '0',
7581 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
7582 
              'type' => 'UFix_32_0',
7583 
            },
7584 
            'direction' => 'out',
7585 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7586 
            'width' => 32,
7587 
          },
7588 
          'en' => {
7589 
            'attributes' => {
7590 
              'bin_pt' => 0,
7591 
              'is_floating_block' => 1,
7592 
              'must_be_hdl_vector' => 1,
7593 
              'period' => 1.0,
7594 
              'port_id' => '1',
7595 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
7596 
              'type' => 'Bool',
7597 
            },
7598 
            'direction' => 'in',
7599 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7600 
            'width' => 1,
7601 
          },
7602 
        },
7603 
      },
7604 
      'entityName' => 'x_x1',
7605 
    },
7606 
    'to_register12' => {
7607 
      'connections' => {
7608 
        'ce' => 'ce_1_sg',
7609 
        'clk' => 'clk_1_sg',
7610 
        'clr' => [
7611 
          'constant',
7612 
          '\'0\'',
7613 
        ],
7614 
        'data_in' => 'reg05_tv_net_x0',
7615 
        'dout' => 'to_register12_dout_net',
7616 
        'en' => 'constant5_op_net_x3',
7617 
      },
7618 
      'entity' => {
7619 
        'attributes' => {
7620 
          'generics' => [],
7621 
          'is_floating_block' => 1,
7622 
          'mask' => {
7623 
            'Block_Handle' => 2121.00048828125,
7624 
            'Block_handle' => 2121.00048828125,
7625 
            'MDL_Handle' => 2083.00048828125,
7626 
            'MDL_handle' => 2083.00048828125,
7627 
            'arith_type' => 1,
7628 
            'bin_pt' => 14,
7629 
            'block_config' => 'sysgen_blockset:toreg_config',
7630 
            'block_handle' => 2121.00048828125,
7631 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
7632 
            'block_type' => 'toreg',
7633 
            'dbl_ovrd' => 0,
7634 
            'explicit_data_type' => 0,
7635 
            'gui_display_data_type' => 1,
7636 
            'init' => 0.0,
7637 
            'init_bit_vector' => '\'b0',
7638 
            'mdl_handle' => 2083.00048828125,
7639 
            'model_handle' => 2083.00048828125,
7640 
            'n_bits' => 16,
7641 
            'ownership' => 1,
7642 
            'preci_type' => 1,
7643 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7644 
            'shared_memory_name' => 'register05tv',
7645 
          },
7646 
          'needs_vhdl_wrapper' => 0,
7647 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
7648 
        },
7649 
        'entityName' => 'x_x2',
7650 
        'ports' => {
7651 
          'ce' => {
7652 
            'attributes' => {
7653 
              'domain' => '',
7654 
              'group' => 1,
7655 
              'isCe' => 1,
7656 
              'is_floating_block' => 1,
7657 
              'period' => 1.0,
7658 
              'type' => 'logic',
7659 
            },
7660 
            'direction' => 'in',
7661 
            'hdlType' => 'std_logic',
7662 
            'width' => 1,
7663 
          },
7664 
          'clk' => {
7665 
            'attributes' => {
7666 
              'domain' => '',
7667 
              'group' => 1,
7668 
              'isClk' => 1,
7669 
              'is_floating_block' => 1,
7670 
              'period' => 1.0,
7671 
              'type' => 'logic',
7672 
            },
7673 
            'direction' => 'in',
7674 
            'hdlType' => 'std_logic',
7675 
            'width' => 1,
7676 
          },
7677 
          'clr' => {
7678 
            'attributes' => {
7679 
              'domain' => '',
7680 
              'group' => 1,
7681 
              'isClr' => 1,
7682 
              'is_floating_block' => 1,
7683 
              'period' => 1,
7684 
              'type' => 'logic',
7685 
              'valid_bit_used' => 0,
7686 
            },
7687 
            'direction' => 'in',
7688 
            'hdlType' => 'std_logic',
7689 
            'width' => 1,
7690 
          },
7691 
          'data_in' => {
7692 
            'attributes' => {
7693 
              'bin_pt' => 0,
7694 
              'is_floating_block' => 1,
7695 
              'must_be_hdl_vector' => 1,
7696 
              'period' => 1.0,
7697 
              'port_id' => '0',
7698 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
7699 
              'type' => 'Bool',
7700 
            },
7701 
            'direction' => 'in',
7702 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7703 
            'width' => 1,
7704 
          },
7705 
          'dout' => {
7706 
            'attributes' => {
7707 
              'bin_pt' => 0,
7708 
              'is_floating_block' => 1,
7709 
              'must_be_hdl_vector' => 1,
7710 
              'period' => 1.0,
7711 
              'port_id' => '0',
7712 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
7713 
              'type' => 'Bool',
7714 
            },
7715 
            'direction' => 'out',
7716 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7717 
            'width' => 1,
7718 
          },
7719 
          'en' => {
7720 
            'attributes' => {
7721 
              'bin_pt' => 0,
7722 
              'is_floating_block' => 1,
7723 
              'must_be_hdl_vector' => 1,
7724 
              'period' => 1.0,
7725 
              'port_id' => '1',
7726 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
7727 
              'type' => 'Bool',
7728 
            },
7729 
            'direction' => 'in',
7730 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7731 
            'width' => 1,
7732 
          },
7733 
        },
7734 
      },
7735 
      'entityName' => 'x_x2',
7736 
    },
7737 
    'to_register13' => {
7738 
      'connections' => {
7739 
        'ce' => 'ce_1_sg',
7740 
        'clk' => 'clk_1_sg',
7741 
        'clr' => [
7742 
          'constant',
7743 
          '\'0\'',
7744 
        ],
7745 
        'data_in' => 'reg05_td_net_x0',
7746 
        'dout' => 'to_register13_dout_net',
7747 
        'en' => 'constant5_op_net_x4',
7748 
      },
7749 
      'entity' => {
7750 
        'attributes' => {
7751 
          'generics' => [],
7752 
          'is_floating_block' => 1,
7753 
          'mask' => {
7754 
            'Block_Handle' => 2122.00048828125,
7755 
            'Block_handle' => 2122.00048828125,
7756 
            'MDL_Handle' => 2083.00048828125,
7757 
            'MDL_handle' => 2083.00048828125,
7758 
            'arith_type' => 1,
7759 
            'bin_pt' => 14,
7760 
            'block_config' => 'sysgen_blockset:toreg_config',
7761 
            'block_handle' => 2122.00048828125,
7762 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
7763 
            'block_type' => 'toreg',
7764 
            'dbl_ovrd' => 0,
7765 
            'explicit_data_type' => 0,
7766 
            'gui_display_data_type' => 1,
7767 
            'init' => 0.0,
7768 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
7769 
            'mdl_handle' => 2083.00048828125,
7770 
            'model_handle' => 2083.00048828125,
7771 
            'n_bits' => 16,
7772 
            'ownership' => 1,
7773 
            'preci_type' => 1,
7774 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7775 
            'shared_memory_name' => 'register05td',
7776 
          },
7777 
          'needs_vhdl_wrapper' => 0,
7778 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
7779 
        },
7780 
        'entityName' => 'x_x3',
7781 
        'ports' => {
7782 
          'ce' => {
7783 
            'attributes' => {
7784 
              'domain' => '',
7785 
              'group' => 1,
7786 
              'isCe' => 1,
7787 
              'is_floating_block' => 1,
7788 
              'period' => 1.0,
7789 
              'type' => 'logic',
7790 
            },
7791 
            'direction' => 'in',
7792 
            'hdlType' => 'std_logic',
7793 
            'width' => 1,
7794 
          },
7795 
          'clk' => {
7796 
            'attributes' => {
7797 
              'domain' => '',
7798 
              'group' => 1,
7799 
              'isClk' => 1,
7800 
              'is_floating_block' => 1,
7801 
              'period' => 1.0,
7802 
              'type' => 'logic',
7803 
            },
7804 
            'direction' => 'in',
7805 
            'hdlType' => 'std_logic',
7806 
            'width' => 1,
7807 
          },
7808 
          'clr' => {
7809 
            'attributes' => {
7810 
              'domain' => '',
7811 
              'group' => 1,
7812 
              'isClr' => 1,
7813 
              'is_floating_block' => 1,
7814 
              'period' => 1,
7815 
              'type' => 'logic',
7816 
              'valid_bit_used' => 0,
7817 
            },
7818 
            'direction' => 'in',
7819 
            'hdlType' => 'std_logic',
7820 
            'width' => 1,
7821 
          },
7822 
          'data_in' => {
7823 
            'attributes' => {
7824 
              'bin_pt' => 0,
7825 
              'is_floating_block' => 1,
7826 
              'must_be_hdl_vector' => 1,
7827 
              'period' => 1.0,
7828 
              'port_id' => '0',
7829 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
7830 
              'type' => 'UFix_32_0',
7831 
            },
7832 
            'direction' => 'in',
7833 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7834 
            'width' => 32,
7835 
          },
7836 
          'dout' => {
7837 
            'attributes' => {
7838 
              'bin_pt' => 0,
7839 
              'is_floating_block' => 1,
7840 
              'must_be_hdl_vector' => 1,
7841 
              'period' => 1.0,
7842 
              'port_id' => '0',
7843 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
7844 
              'type' => 'UFix_32_0',
7845 
            },
7846 
            'direction' => 'out',
7847 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7848 
            'width' => 32,
7849 
          },
7850 
          'en' => {
7851 
            'attributes' => {
7852 
              'bin_pt' => 0,
7853 
              'is_floating_block' => 1,
7854 
              'must_be_hdl_vector' => 1,
7855 
              'period' => 1.0,
7856 
              'port_id' => '1',
7857 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
7858 
              'type' => 'Bool',
7859 
            },
7860 
            'direction' => 'in',
7861 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7862 
            'width' => 1,
7863 
          },
7864 
        },
7865 
      },
7866 
      'entityName' => 'x_x3',
7867 
    },
7868 
    'to_register14' => {
7869 
      'connections' => {
7870 
        'ce' => 'ce_1_sg',
7871 
        'clk' => 'clk_1_sg',
7872 
        'clr' => [
7873 
          'constant',
7874 
          '\'0\'',
7875 
        ],
7876 
        'data_in' => 'reg06_tv_net_x0',
7877 
        'dout' => 'to_register14_dout_net',
7878 
        'en' => 'constant5_op_net_x5',
7879 
      },
7880 
      'entity' => {
7881 
        'attributes' => {
7882 
          'generics' => [],
7883 
          'is_floating_block' => 1,
7884 
          'mask' => {
7885 
            'Block_Handle' => 2123.00048828125,
7886 
            'Block_handle' => 2123.00048828125,
7887 
            'MDL_Handle' => 2083.00048828125,
7888 
            'MDL_handle' => 2083.00048828125,
7889 
            'arith_type' => 1,
7890 
            'bin_pt' => 14,
7891 
            'block_config' => 'sysgen_blockset:toreg_config',
7892 
            'block_handle' => 2123.00048828125,
7893 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
7894 
            'block_type' => 'toreg',
7895 
            'dbl_ovrd' => 0,
7896 
            'explicit_data_type' => 0,
7897 
            'gui_display_data_type' => 1,
7898 
            'init' => 0.0,
7899 
            'init_bit_vector' => '\'b0',
7900 
            'mdl_handle' => 2083.00048828125,
7901 
            'model_handle' => 2083.00048828125,
7902 
            'n_bits' => 16,
7903 
            'ownership' => 1,
7904 
            'preci_type' => 1,
7905 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
7906 
            'shared_memory_name' => 'register06tv',
7907 
          },
7908 
          'needs_vhdl_wrapper' => 0,
7909 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
7910 
        },
7911 
        'entityName' => 'x_x4',
7912 
        'ports' => {
7913 
          'ce' => {
7914 
            'attributes' => {
7915 
              'domain' => '',
7916 
              'group' => 1,
7917 
              'isCe' => 1,
7918 
              'is_floating_block' => 1,
7919 
              'period' => 1.0,
7920 
              'type' => 'logic',
7921 
            },
7922 
            'direction' => 'in',
7923 
            'hdlType' => 'std_logic',
7924 
            'width' => 1,
7925 
          },
7926 
          'clk' => {
7927 
            'attributes' => {
7928 
              'domain' => '',
7929 
              'group' => 1,
7930 
              'isClk' => 1,
7931 
              'is_floating_block' => 1,
7932 
              'period' => 1.0,
7933 
              'type' => 'logic',
7934 
            },
7935 
            'direction' => 'in',
7936 
            'hdlType' => 'std_logic',
7937 
            'width' => 1,
7938 
          },
7939 
          'clr' => {
7940 
            'attributes' => {
7941 
              'domain' => '',
7942 
              'group' => 1,
7943 
              'isClr' => 1,
7944 
              'is_floating_block' => 1,
7945 
              'period' => 1,
7946 
              'type' => 'logic',
7947 
              'valid_bit_used' => 0,
7948 
            },
7949 
            'direction' => 'in',
7950 
            'hdlType' => 'std_logic',
7951 
            'width' => 1,
7952 
          },
7953 
          'data_in' => {
7954 
            'attributes' => {
7955 
              'bin_pt' => 0,
7956 
              'is_floating_block' => 1,
7957 
              'must_be_hdl_vector' => 1,
7958 
              'period' => 1.0,
7959 
              'port_id' => '0',
7960 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
7961 
              'type' => 'Bool',
7962 
            },
7963 
            'direction' => 'in',
7964 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7965 
            'width' => 1,
7966 
          },
7967 
          'dout' => {
7968 
            'attributes' => {
7969 
              'bin_pt' => 0,
7970 
              'is_floating_block' => 1,
7971 
              'must_be_hdl_vector' => 1,
7972 
              'period' => 1.0,
7973 
              'port_id' => '0',
7974 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
7975 
              'type' => 'Bool',
7976 
            },
7977 
            'direction' => 'out',
7978 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7979 
            'width' => 1,
7980 
          },
7981 
          'en' => {
7982 
            'attributes' => {
7983 
              'bin_pt' => 0,
7984 
              'is_floating_block' => 1,
7985 
              'must_be_hdl_vector' => 1,
7986 
              'period' => 1.0,
7987 
              'port_id' => '1',
7988 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
7989 
              'type' => 'Bool',
7990 
            },
7991 
            'direction' => 'in',
7992 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7993 
            'width' => 1,
7994 
          },
7995 
        },
7996 
      },
7997 
      'entityName' => 'x_x4',
7998 
    },
7999 
    'to_register15' => {
8000 
      'connections' => {
8001 
        'ce' => 'ce_1_sg',
8002 
        'clk' => 'clk_1_sg',
8003 
        'clr' => [
8004 
          'constant',
8005 
          '\'0\'',
8006 
        ],
8007 
        'data_in' => 'reg06_td_net_x0',
8008 
        'dout' => 'to_register15_dout_net',
8009 
        'en' => 'constant5_op_net_x6',
8010 
      },
8011 
      'entity' => {
8012 
        'attributes' => {
8013 
          'generics' => [],
8014 
          'is_floating_block' => 1,
8015 
          'mask' => {
8016 
            'Block_Handle' => 2124.00048828125,
8017 
            'Block_handle' => 2124.00048828125,
8018 
            'MDL_Handle' => 2083.00048828125,
8019 
            'MDL_handle' => 2083.00048828125,
8020 
            'arith_type' => 1,
8021 
            'bin_pt' => 14,
8022 
            'block_config' => 'sysgen_blockset:toreg_config',
8023 
            'block_handle' => 2124.00048828125,
8024 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
8025 
            'block_type' => 'toreg',
8026 
            'dbl_ovrd' => 0,
8027 
            'explicit_data_type' => 0,
8028 
            'gui_display_data_type' => 1,
8029 
            'init' => 0.0,
8030 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
8031 
            'mdl_handle' => 2083.00048828125,
8032 
            'model_handle' => 2083.00048828125,
8033 
            'n_bits' => 16,
8034 
            'ownership' => 1,
8035 
            'preci_type' => 1,
8036 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8037 
            'shared_memory_name' => 'register06td',
8038 
          },
8039 
          'needs_vhdl_wrapper' => 0,
8040 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
8041 
        },
8042 
        'entityName' => 'x_x5',
8043 
        'ports' => {
8044 
          'ce' => {
8045 
            'attributes' => {
8046 
              'domain' => '',
8047 
              'group' => 1,
8048 
              'isCe' => 1,
8049 
              'is_floating_block' => 1,
8050 
              'period' => 1.0,
8051 
              'type' => 'logic',
8052 
            },
8053 
            'direction' => 'in',
8054 
            'hdlType' => 'std_logic',
8055 
            'width' => 1,
8056 
          },
8057 
          'clk' => {
8058 
            'attributes' => {
8059 
              'domain' => '',
8060 
              'group' => 1,
8061 
              'isClk' => 1,
8062 
              'is_floating_block' => 1,
8063 
              'period' => 1.0,
8064 
              'type' => 'logic',
8065 
            },
8066 
            'direction' => 'in',
8067 
            'hdlType' => 'std_logic',
8068 
            'width' => 1,
8069 
          },
8070 
          'clr' => {
8071 
            'attributes' => {
8072 
              'domain' => '',
8073 
              'group' => 1,
8074 
              'isClr' => 1,
8075 
              'is_floating_block' => 1,
8076 
              'period' => 1,
8077 
              'type' => 'logic',
8078 
              'valid_bit_used' => 0,
8079 
            },
8080 
            'direction' => 'in',
8081 
            'hdlType' => 'std_logic',
8082 
            'width' => 1,
8083 
          },
8084 
          'data_in' => {
8085 
            'attributes' => {
8086 
              'bin_pt' => 0,
8087 
              'is_floating_block' => 1,
8088 
              'must_be_hdl_vector' => 1,
8089 
              'period' => 1.0,
8090 
              'port_id' => '0',
8091 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
8092 
              'type' => 'UFix_32_0',
8093 
            },
8094 
            'direction' => 'in',
8095 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8096 
            'width' => 32,
8097 
          },
8098 
          'dout' => {
8099 
            'attributes' => {
8100 
              'bin_pt' => 0,
8101 
              'is_floating_block' => 1,
8102 
              'must_be_hdl_vector' => 1,
8103 
              'period' => 1.0,
8104 
              'port_id' => '0',
8105 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
8106 
              'type' => 'UFix_32_0',
8107 
            },
8108 
            'direction' => 'out',
8109 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8110 
            'width' => 32,
8111 
          },
8112 
          'en' => {
8113 
            'attributes' => {
8114 
              'bin_pt' => 0,
8115 
              'is_floating_block' => 1,
8116 
              'must_be_hdl_vector' => 1,
8117 
              'period' => 1.0,
8118 
              'port_id' => '1',
8119 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
8120 
              'type' => 'Bool',
8121 
            },
8122 
            'direction' => 'in',
8123 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8124 
            'width' => 1,
8125 
          },
8126 
        },
8127 
      },
8128 
      'entityName' => 'x_x5',
8129 
    },
8130 
    'to_register16' => {
8131 
      'connections' => {
8132 
        'ce' => 'ce_1_sg',
8133 
        'clk' => 'clk_1_sg',
8134 
        'clr' => [
8135 
          'constant',
8136 
          '\'0\'',
8137 
        ],
8138 
        'data_in' => 'reg07_tv_net_x0',
8139 
        'dout' => 'to_register16_dout_net',
8140 
        'en' => 'constant5_op_net_x7',
8141 
      },
8142 
      'entity' => {
8143 
        'attributes' => {
8144 
          'generics' => [],
8145 
          'is_floating_block' => 1,
8146 
          'mask' => {
8147 
            'Block_Handle' => 2125.00048828125,
8148 
            'Block_handle' => 2125.00048828125,
8149 
            'MDL_Handle' => 2083.00048828125,
8150 
            'MDL_handle' => 2083.00048828125,
8151 
            'arith_type' => 1,
8152 
            'bin_pt' => 14,
8153 
            'block_config' => 'sysgen_blockset:toreg_config',
8154 
            'block_handle' => 2125.00048828125,
8155 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
8156 
            'block_type' => 'toreg',
8157 
            'dbl_ovrd' => 0,
8158 
            'explicit_data_type' => 0,
8159 
            'gui_display_data_type' => 1,
8160 
            'init' => 0.0,
8161 
            'init_bit_vector' => '\'b0',
8162 
            'mdl_handle' => 2083.00048828125,
8163 
            'model_handle' => 2083.00048828125,
8164 
            'n_bits' => 16,
8165 
            'ownership' => 1,
8166 
            'preci_type' => 1,
8167 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8168 
            'shared_memory_name' => 'register07tv',
8169 
          },
8170 
          'needs_vhdl_wrapper' => 0,
8171 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
8172 
        },
8173 
        'entityName' => 'x_x6',
8174 
        'ports' => {
8175 
          'ce' => {
8176 
            'attributes' => {
8177 
              'domain' => '',
8178 
              'group' => 1,
8179 
              'isCe' => 1,
8180 
              'is_floating_block' => 1,
8181 
              'period' => 1.0,
8182 
              'type' => 'logic',
8183 
            },
8184 
            'direction' => 'in',
8185 
            'hdlType' => 'std_logic',
8186 
            'width' => 1,
8187 
          },
8188 
          'clk' => {
8189 
            'attributes' => {
8190 
              'domain' => '',
8191 
              'group' => 1,
8192 
              'isClk' => 1,
8193 
              'is_floating_block' => 1,
8194 
              'period' => 1.0,
8195 
              'type' => 'logic',
8196 
            },
8197 
            'direction' => 'in',
8198 
            'hdlType' => 'std_logic',
8199 
            'width' => 1,
8200 
          },
8201 
          'clr' => {
8202 
            'attributes' => {
8203 
              'domain' => '',
8204 
              'group' => 1,
8205 
              'isClr' => 1,
8206 
              'is_floating_block' => 1,
8207 
              'period' => 1,
8208 
              'type' => 'logic',
8209 
              'valid_bit_used' => 0,
8210 
            },
8211 
            'direction' => 'in',
8212 
            'hdlType' => 'std_logic',
8213 
            'width' => 1,
8214 
          },
8215 
          'data_in' => {
8216 
            'attributes' => {
8217 
              'bin_pt' => 0,
8218 
              'is_floating_block' => 1,
8219 
              'must_be_hdl_vector' => 1,
8220 
              'period' => 1.0,
8221 
              'port_id' => '0',
8222 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
8223 
              'type' => 'Bool',
8224 
            },
8225 
            'direction' => 'in',
8226 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8227 
            'width' => 1,
8228 
          },
8229 
          'dout' => {
8230 
            'attributes' => {
8231 
              'bin_pt' => 0,
8232 
              'is_floating_block' => 1,
8233 
              'must_be_hdl_vector' => 1,
8234 
              'period' => 1.0,
8235 
              'port_id' => '0',
8236 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
8237 
              'type' => 'Bool',
8238 
            },
8239 
            'direction' => 'out',
8240 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8241 
            'width' => 1,
8242 
          },
8243 
          'en' => {
8244 
            'attributes' => {
8245 
              'bin_pt' => 0,
8246 
              'is_floating_block' => 1,
8247 
              'must_be_hdl_vector' => 1,
8248 
              'period' => 1.0,
8249 
              'port_id' => '1',
8250 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
8251 
              'type' => 'Bool',
8252 
            },
8253 
            'direction' => 'in',
8254 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8255 
            'width' => 1,
8256 
          },
8257 
        },
8258 
      },
8259 
      'entityName' => 'x_x6',
8260 
    },
8261 
    'to_register17' => {
8262 
      'connections' => {
8263 
        'ce' => 'ce_1_sg',
8264 
        'clk' => 'clk_1_sg',
8265 
        'clr' => [
8266 
          'constant',
8267 
          '\'0\'',
8268 
        ],
8269 
        'data_in' => 'reg07_td_net_x0',
8270 
        'dout' => 'to_register17_dout_net',
8271 
        'en' => 'constant5_op_net_x8',
8272 
      },
8273 
      'entity' => {
8274 
        'attributes' => {
8275 
          'generics' => [],
8276 
          'is_floating_block' => 1,
8277 
          'mask' => {
8278 
            'Block_Handle' => 2126.00048828125,
8279 
            'Block_handle' => 2126.00048828125,
8280 
            'MDL_Handle' => 2083.00048828125,
8281 
            'MDL_handle' => 2083.00048828125,
8282 
            'arith_type' => 1,
8283 
            'bin_pt' => 14,
8284 
            'block_config' => 'sysgen_blockset:toreg_config',
8285 
            'block_handle' => 2126.00048828125,
8286 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
8287 
            'block_type' => 'toreg',
8288 
            'dbl_ovrd' => 0,
8289 
            'explicit_data_type' => 0,
8290 
            'gui_display_data_type' => 1,
8291 
            'init' => 0.0,
8292 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
8293 
            'mdl_handle' => 2083.00048828125,
8294 
            'model_handle' => 2083.00048828125,
8295 
            'n_bits' => 16,
8296 
            'ownership' => 1,
8297 
            'preci_type' => 1,
8298 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8299 
            'shared_memory_name' => 'register07td',
8300 
          },
8301 
          'needs_vhdl_wrapper' => 0,
8302 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
8303 
        },
8304 
        'entityName' => 'x_x7',
8305 
        'ports' => {
8306 
          'ce' => {
8307 
            'attributes' => {
8308 
              'domain' => '',
8309 
              'group' => 1,
8310 
              'isCe' => 1,
8311 
              'is_floating_block' => 1,
8312 
              'period' => 1.0,
8313 
              'type' => 'logic',
8314 
            },
8315 
            'direction' => 'in',
8316 
            'hdlType' => 'std_logic',
8317 
            'width' => 1,
8318 
          },
8319 
          'clk' => {
8320 
            'attributes' => {
8321 
              'domain' => '',
8322 
              'group' => 1,
8323 
              'isClk' => 1,
8324 
              'is_floating_block' => 1,
8325 
              'period' => 1.0,
8326 
              'type' => 'logic',
8327 
            },
8328 
            'direction' => 'in',
8329 
            'hdlType' => 'std_logic',
8330 
            'width' => 1,
8331 
          },
8332 
          'clr' => {
8333 
            'attributes' => {
8334 
              'domain' => '',
8335 
              'group' => 1,
8336 
              'isClr' => 1,
8337 
              'is_floating_block' => 1,
8338 
              'period' => 1,
8339 
              'type' => 'logic',
8340 
              'valid_bit_used' => 0,
8341 
            },
8342 
            'direction' => 'in',
8343 
            'hdlType' => 'std_logic',
8344 
            'width' => 1,
8345 
          },
8346 
          'data_in' => {
8347 
            'attributes' => {
8348 
              'bin_pt' => 0,
8349 
              'is_floating_block' => 1,
8350 
              'must_be_hdl_vector' => 1,
8351 
              'period' => 1.0,
8352 
              'port_id' => '0',
8353 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
8354 
              'type' => 'UFix_32_0',
8355 
            },
8356 
            'direction' => 'in',
8357 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8358 
            'width' => 32,
8359 
          },
8360 
          'dout' => {
8361 
            'attributes' => {
8362 
              'bin_pt' => 0,
8363 
              'is_floating_block' => 1,
8364 
              'must_be_hdl_vector' => 1,
8365 
              'period' => 1.0,
8366 
              'port_id' => '0',
8367 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
8368 
              'type' => 'UFix_32_0',
8369 
            },
8370 
            'direction' => 'out',
8371 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8372 
            'width' => 32,
8373 
          },
8374 
          'en' => {
8375 
            'attributes' => {
8376 
              'bin_pt' => 0,
8377 
              'is_floating_block' => 1,
8378 
              'must_be_hdl_vector' => 1,
8379 
              'period' => 1.0,
8380 
              'port_id' => '1',
8381 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
8382 
              'type' => 'Bool',
8383 
            },
8384 
            'direction' => 'in',
8385 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8386 
            'width' => 1,
8387 
          },
8388 
        },
8389 
      },
8390 
      'entityName' => 'x_x7',
8391 
    },
8392 
    'to_register18' => {
8393 
      'connections' => {
8394 
        'ce' => 'ce_1_sg',
8395 
        'clk' => 'clk_1_sg',
8396 
        'clr' => [
8397 
          'constant',
8398 
          '\'0\'',
8399 
        ],
8400 
        'data_in' => 'dma_host2board_busy_net_x0',
8401 
        'dout' => 'to_register18_dout_net',
8402 
        'en' => 'constant5_op_net_x9',
8403 
      },
8404 
      'entity' => {
8405 
        'attributes' => {
8406 
          'generics' => [],
8407 
          'is_floating_block' => 1,
8408 
          'mask' => {
8409 
            'Block_Handle' => 2127.00048828125,
8410 
            'Block_handle' => 2127.00048828125,
8411 
            'MDL_Handle' => 2083.00048828125,
8412 
            'MDL_handle' => 2083.00048828125,
8413 
            'arith_type' => 1,
8414 
            'bin_pt' => 14,
8415 
            'block_config' => 'sysgen_blockset:toreg_config',
8416 
            'block_handle' => 2127.00048828125,
8417 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
8418 
            'block_type' => 'toreg',
8419 
            'dbl_ovrd' => 0,
8420 
            'explicit_data_type' => 0,
8421 
            'gui_display_data_type' => 1,
8422 
            'init' => 0.0,
8423 
            'init_bit_vector' => '\'b0',
8424 
            'mdl_handle' => 2083.00048828125,
8425 
            'model_handle' => 2083.00048828125,
8426 
            'n_bits' => 16,
8427 
            'ownership' => 1,
8428 
            'preci_type' => 1,
8429 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8430 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
8431 
          },
8432 
          'needs_vhdl_wrapper' => 0,
8433 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
8434 
        },
8435 
        'entityName' => 'x_x8',
8436 
        'ports' => {
8437 
          'ce' => {
8438 
            'attributes' => {
8439 
              'domain' => '',
8440 
              'group' => 1,
8441 
              'isCe' => 1,
8442 
              'is_floating_block' => 1,
8443 
              'period' => 1.0,
8444 
              'type' => 'logic',
8445 
            },
8446 
            'direction' => 'in',
8447 
            'hdlType' => 'std_logic',
8448 
            'width' => 1,
8449 
          },
8450 
          'clk' => {
8451 
            'attributes' => {
8452 
              'domain' => '',
8453 
              'group' => 1,
8454 
              'isClk' => 1,
8455 
              'is_floating_block' => 1,
8456 
              'period' => 1.0,
8457 
              'type' => 'logic',
8458 
            },
8459 
            'direction' => 'in',
8460 
            'hdlType' => 'std_logic',
8461 
            'width' => 1,
8462 
          },
8463 
          'clr' => {
8464 
            'attributes' => {
8465 
              'domain' => '',
8466 
              'group' => 1,
8467 
              'isClr' => 1,
8468 
              'is_floating_block' => 1,
8469 
              'period' => 1,
8470 
              'type' => 'logic',
8471 
              'valid_bit_used' => 0,
8472 
            },
8473 
            'direction' => 'in',
8474 
            'hdlType' => 'std_logic',
8475 
            'width' => 1,
8476 
          },
8477 
          'data_in' => {
8478 
            'attributes' => {
8479 
              'bin_pt' => 0,
8480 
              'is_floating_block' => 1,
8481 
              'must_be_hdl_vector' => 1,
8482 
              'period' => 1.0,
8483 
              'port_id' => '0',
8484 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
8485 
              'type' => 'UFix_1_0',
8486 
            },
8487 
            'direction' => 'in',
8488 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8489 
            'width' => 1,
8490 
          },
8491 
          'dout' => {
8492 
            'attributes' => {
8493 
              'bin_pt' => 0,
8494 
              'is_floating_block' => 1,
8495 
              'must_be_hdl_vector' => 1,
8496 
              'period' => 1.0,
8497 
              'port_id' => '0',
8498 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
8499 
              'type' => 'UFix_1_0',
8500 
            },
8501 
            'direction' => 'out',
8502 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8503 
            'width' => 1,
8504 
          },
8505 
          'en' => {
8506 
            'attributes' => {
8507 
              'bin_pt' => 0,
8508 
              'is_floating_block' => 1,
8509 
              'must_be_hdl_vector' => 1,
8510 
              'period' => 1.0,
8511 
              'port_id' => '1',
8512 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
8513 
              'type' => 'Bool',
8514 
            },
8515 
            'direction' => 'in',
8516 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8517 
            'width' => 1,
8518 
          },
8519 
        },
8520 
      },
8521 
      'entityName' => 'x_x8',
8522 
    },
8523 
    'to_register19' => {
8524 
      'connections' => {
8525 
        'ce' => 'ce_1_sg',
8526 
        'clk' => 'clk_1_sg',
8527 
        'clr' => [
8528 
          'constant',
8529 
          '\'0\'',
8530 
        ],
8531 
        'data_in' => 'dma_host2board_done_net_x0',
8532 
        'dout' => 'to_register19_dout_net',
8533 
        'en' => 'constant5_op_net_x10',
8534 
      },
8535 
      'entity' => {
8536 
        'attributes' => {
8537 
          'generics' => [],
8538 
          'is_floating_block' => 1,
8539 
          'mask' => {
8540 
            'Block_Handle' => 2128.00048828125,
8541 
            'Block_handle' => 2128.00048828125,
8542 
            'MDL_Handle' => 2083.00048828125,
8543 
            'MDL_handle' => 2083.00048828125,
8544 
            'arith_type' => 1,
8545 
            'bin_pt' => 14,
8546 
            'block_config' => 'sysgen_blockset:toreg_config',
8547 
            'block_handle' => 2128.00048828125,
8548 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
8549 
            'block_type' => 'toreg',
8550 
            'dbl_ovrd' => 0,
8551 
            'explicit_data_type' => 0,
8552 
            'gui_display_data_type' => 1,
8553 
            'init' => 0.0,
8554 
            'init_bit_vector' => '\'b0',
8555 
            'mdl_handle' => 2083.00048828125,
8556 
            'model_handle' => 2083.00048828125,
8557 
            'n_bits' => 16,
8558 
            'ownership' => 1,
8559 
            'preci_type' => 1,
8560 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8561 
            'shared_memory_name' => 'DMA_Host2Board_Done',
8562 
          },
8563 
          'needs_vhdl_wrapper' => 0,
8564 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
8565 
        },
8566 
        'entityName' => 'x_x9',
8567 
        'ports' => {
8568 
          'ce' => {
8569 
            'attributes' => {
8570 
              'domain' => '',
8571 
              'group' => 1,
8572 
              'isCe' => 1,
8573 
              'is_floating_block' => 1,
8574 
              'period' => 1.0,
8575 
              'type' => 'logic',
8576 
            },
8577 
            'direction' => 'in',
8578 
            'hdlType' => 'std_logic',
8579 
            'width' => 1,
8580 
          },
8581 
          'clk' => {
8582 
            'attributes' => {
8583 
              'domain' => '',
8584 
              'group' => 1,
8585 
              'isClk' => 1,
8586 
              'is_floating_block' => 1,
8587 
              'period' => 1.0,
8588 
              'type' => 'logic',
8589 
            },
8590 
            'direction' => 'in',
8591 
            'hdlType' => 'std_logic',
8592 
            'width' => 1,
8593 
          },
8594 
          'clr' => {
8595 
            'attributes' => {
8596 
              'domain' => '',
8597 
              'group' => 1,
8598 
              'isClr' => 1,
8599 
              'is_floating_block' => 1,
8600 
              'period' => 1,
8601 
              'type' => 'logic',
8602 
              'valid_bit_used' => 0,
8603 
            },
8604 
            'direction' => 'in',
8605 
            'hdlType' => 'std_logic',
8606 
            'width' => 1,
8607 
          },
8608 
          'data_in' => {
8609 
            'attributes' => {
8610 
              'bin_pt' => 0,
8611 
              'is_floating_block' => 1,
8612 
              'must_be_hdl_vector' => 1,
8613 
              'period' => 1.0,
8614 
              'port_id' => '0',
8615 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
8616 
              'type' => 'UFix_1_0',
8617 
            },
8618 
            'direction' => 'in',
8619 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8620 
            'width' => 1,
8621 
          },
8622 
          'dout' => {
8623 
            'attributes' => {
8624 
              'bin_pt' => 0,
8625 
              'is_floating_block' => 1,
8626 
              'must_be_hdl_vector' => 1,
8627 
              'period' => 1.0,
8628 
              'port_id' => '0',
8629 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
8630 
              'type' => 'UFix_1_0',
8631 
            },
8632 
            'direction' => 'out',
8633 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8634 
            'width' => 1,
8635 
          },
8636 
          'en' => {
8637 
            'attributes' => {
8638 
              'bin_pt' => 0,
8639 
              'is_floating_block' => 1,
8640 
              'must_be_hdl_vector' => 1,
8641 
              'period' => 1.0,
8642 
              'port_id' => '1',
8643 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
8644 
              'type' => 'Bool',
8645 
            },
8646 
            'direction' => 'in',
8647 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8648 
            'width' => 1,
8649 
          },
8650 
        },
8651 
      },
8652 
      'entityName' => 'x_x9',
8653 
    },
8654 
    'to_register2' => {
8655 
      'connections' => {
8656 
        'ce' => 'ce_1_sg',
8657 
        'clk' => 'clk_1_sg',
8658 
        'clr' => [
8659 
          'constant',
8660 
          '\'0\'',
8661 
        ],
8662 
        'data_in' => 'debug_in_3i_net_x0',
8663 
        'dout' => 'to_register2_dout_net',
8664 
        'en' => 'constant5_op_net_x11',
8665 
      },
8666 
      'entity' => {
8667 
        'attributes' => {
8668 
          'generics' => [],
8669 
          'is_floating_block' => 1,
8670 
          'mask' => {
8671 
            'Block_Handle' => 2129.00048828125,
8672 
            'Block_handle' => 2129.00048828125,
8673 
            'MDL_Handle' => 2083.00048828125,
8674 
            'MDL_handle' => 2083.00048828125,
8675 
            'arith_type' => 1,
8676 
            'bin_pt' => 14,
8677 
            'block_config' => 'sysgen_blockset:toreg_config',
8678 
            'block_handle' => 2129.00048828125,
8679 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
8680 
            'block_type' => 'toreg',
8681 
            'dbl_ovrd' => 0,
8682 
            'explicit_data_type' => 0,
8683 
            'gui_display_data_type' => 1,
8684 
            'init' => 0.0,
8685 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
8686 
            'mdl_handle' => 2083.00048828125,
8687 
            'model_handle' => 2083.00048828125,
8688 
            'n_bits' => 16,
8689 
            'ownership' => 1,
8690 
            'preci_type' => 1,
8691 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8692 
            'shared_memory_name' => 'debug3i',
8693 
          },
8694 
          'needs_vhdl_wrapper' => 0,
8695 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
8696 
        },
8697 
        'entityName' => 'x_x10',
8698 
        'ports' => {
8699 
          'ce' => {
8700 
            'attributes' => {
8701 
              'domain' => '',
8702 
              'group' => 1,
8703 
              'isCe' => 1,
8704 
              'is_floating_block' => 1,
8705 
              'period' => 1.0,
8706 
              'type' => 'logic',
8707 
            },
8708 
            'direction' => 'in',
8709 
            'hdlType' => 'std_logic',
8710 
            'width' => 1,
8711 
          },
8712 
          'clk' => {
8713 
            'attributes' => {
8714 
              'domain' => '',
8715 
              'group' => 1,
8716 
              'isClk' => 1,
8717 
              'is_floating_block' => 1,
8718 
              'period' => 1.0,
8719 
              'type' => 'logic',
8720 
            },
8721 
            'direction' => 'in',
8722 
            'hdlType' => 'std_logic',
8723 
            'width' => 1,
8724 
          },
8725 
          'clr' => {
8726 
            'attributes' => {
8727 
              'domain' => '',
8728 
              'group' => 1,
8729 
              'isClr' => 1,
8730 
              'is_floating_block' => 1,
8731 
              'period' => 1,
8732 
              'type' => 'logic',
8733 
              'valid_bit_used' => 0,
8734 
            },
8735 
            'direction' => 'in',
8736 
            'hdlType' => 'std_logic',
8737 
            'width' => 1,
8738 
          },
8739 
          'data_in' => {
8740 
            'attributes' => {
8741 
              'bin_pt' => 0,
8742 
              'is_floating_block' => 1,
8743 
              'must_be_hdl_vector' => 1,
8744 
              'period' => 1.0,
8745 
              'port_id' => '0',
8746 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
8747 
              'type' => 'UFix_32_0',
8748 
            },
8749 
            'direction' => 'in',
8750 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8751 
            'width' => 32,
8752 
          },
8753 
          'dout' => {
8754 
            'attributes' => {
8755 
              'bin_pt' => 0,
8756 
              'is_floating_block' => 1,
8757 
              'must_be_hdl_vector' => 1,
8758 
              'period' => 1.0,
8759 
              'port_id' => '0',
8760 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
8761 
              'type' => 'UFix_32_0',
8762 
            },
8763 
            'direction' => 'out',
8764 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8765 
            'width' => 32,
8766 
          },
8767 
          'en' => {
8768 
            'attributes' => {
8769 
              'bin_pt' => 0,
8770 
              'is_floating_block' => 1,
8771 
              'must_be_hdl_vector' => 1,
8772 
              'period' => 1.0,
8773 
              'port_id' => '1',
8774 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
8775 
              'type' => 'Bool',
8776 
            },
8777 
            'direction' => 'in',
8778 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8779 
            'width' => 1,
8780 
          },
8781 
        },
8782 
      },
8783 
      'entityName' => 'x_x10',
8784 
    },
8785 
    'to_register20' => {
8786 
      'connections' => {
8787 
        'ce' => 'ce_1_sg',
8788 
        'clk' => 'clk_1_sg',
8789 
        'clr' => [
8790 
          'constant',
8791 
          '\'0\'',
8792 
        ],
8793 
        'data_in' => 'debug_in_4i_net_x0',
8794 
        'dout' => 'to_register20_dout_net',
8795 
        'en' => 'constant5_op_net_x12',
8796 
      },
8797 
      'entity' => {
8798 
        'attributes' => {
8799 
          'generics' => [],
8800 
          'is_floating_block' => 1,
8801 
          'mask' => {
8802 
            'Block_Handle' => 2130.00048828125,
8803 
            'Block_handle' => 2130.00048828125,
8804 
            'MDL_Handle' => 2083.00048828125,
8805 
            'MDL_handle' => 2083.00048828125,
8806 
            'arith_type' => 1,
8807 
            'bin_pt' => 14,
8808 
            'block_config' => 'sysgen_blockset:toreg_config',
8809 
            'block_handle' => 2130.00048828125,
8810 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
8811 
            'block_type' => 'toreg',
8812 
            'dbl_ovrd' => 0,
8813 
            'explicit_data_type' => 0,
8814 
            'gui_display_data_type' => 1,
8815 
            'init' => 0.0,
8816 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
8817 
            'mdl_handle' => 2083.00048828125,
8818 
            'model_handle' => 2083.00048828125,
8819 
            'n_bits' => 16,
8820 
            'ownership' => 1,
8821 
            'preci_type' => 1,
8822 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8823 
            'shared_memory_name' => 'debug4i',
8824 
          },
8825 
          'needs_vhdl_wrapper' => 0,
8826 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
8827 
        },
8828 
        'entityName' => 'x_x11',
8829 
        'ports' => {
8830 
          'ce' => {
8831 
            'attributes' => {
8832 
              'domain' => '',
8833 
              'group' => 1,
8834 
              'isCe' => 1,
8835 
              'is_floating_block' => 1,
8836 
              'period' => 1.0,
8837 
              'type' => 'logic',
8838 
            },
8839 
            'direction' => 'in',
8840 
            'hdlType' => 'std_logic',
8841 
            'width' => 1,
8842 
          },
8843 
          'clk' => {
8844 
            'attributes' => {
8845 
              'domain' => '',
8846 
              'group' => 1,
8847 
              'isClk' => 1,
8848 
              'is_floating_block' => 1,
8849 
              'period' => 1.0,
8850 
              'type' => 'logic',
8851 
            },
8852 
            'direction' => 'in',
8853 
            'hdlType' => 'std_logic',
8854 
            'width' => 1,
8855 
          },
8856 
          'clr' => {
8857 
            'attributes' => {
8858 
              'domain' => '',
8859 
              'group' => 1,
8860 
              'isClr' => 1,
8861 
              'is_floating_block' => 1,
8862 
              'period' => 1,
8863 
              'type' => 'logic',
8864 
              'valid_bit_used' => 0,
8865 
            },
8866 
            'direction' => 'in',
8867 
            'hdlType' => 'std_logic',
8868 
            'width' => 1,
8869 
          },
8870 
          'data_in' => {
8871 
            'attributes' => {
8872 
              'bin_pt' => 0,
8873 
              'is_floating_block' => 1,
8874 
              'must_be_hdl_vector' => 1,
8875 
              'period' => 1.0,
8876 
              'port_id' => '0',
8877 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
8878 
              'type' => 'UFix_32_0',
8879 
            },
8880 
            'direction' => 'in',
8881 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8882 
            'width' => 32,
8883 
          },
8884 
          'dout' => {
8885 
            'attributes' => {
8886 
              'bin_pt' => 0,
8887 
              'is_floating_block' => 1,
8888 
              'must_be_hdl_vector' => 1,
8889 
              'period' => 1.0,
8890 
              'port_id' => '0',
8891 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
8892 
              'type' => 'UFix_32_0',
8893 
            },
8894 
            'direction' => 'out',
8895 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8896 
            'width' => 32,
8897 
          },
8898 
          'en' => {
8899 
            'attributes' => {
8900 
              'bin_pt' => 0,
8901 
              'is_floating_block' => 1,
8902 
              'must_be_hdl_vector' => 1,
8903 
              'period' => 1.0,
8904 
              'port_id' => '1',
8905 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
8906 
              'type' => 'Bool',
8907 
            },
8908 
            'direction' => 'in',
8909 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8910 
            'width' => 1,
8911 
          },
8912 
        },
8913 
      },
8914 
      'entityName' => 'x_x11',
8915 
    },
8916 
    'to_register21' => {
8917 
      'connections' => {
8918 
        'ce' => 'ce_1_sg',
8919 
        'clk' => 'clk_1_sg',
8920 
        'clr' => [
8921 
          'constant',
8922 
          '\'0\'',
8923 
        ],
8924 
        'data_in' => 'reg09_tv_net_x0',
8925 
        'dout' => 'to_register21_dout_net',
8926 
        'en' => 'constant1_op_net_x0',
8927 
      },
8928 
      'entity' => {
8929 
        'attributes' => {
8930 
          'generics' => [],
8931 
          'is_floating_block' => 1,
8932 
          'mask' => {
8933 
            'Block_Handle' => 2131.00048828125,
8934 
            'Block_handle' => 2131.00048828125,
8935 
            'MDL_Handle' => 2083.00048828125,
8936 
            'MDL_handle' => 2083.00048828125,
8937 
            'arith_type' => 1,
8938 
            'bin_pt' => 14,
8939 
            'block_config' => 'sysgen_blockset:toreg_config',
8940 
            'block_handle' => 2131.00048828125,
8941 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
8942 
            'block_type' => 'toreg',
8943 
            'dbl_ovrd' => 0,
8944 
            'explicit_data_type' => 0,
8945 
            'gui_display_data_type' => 1,
8946 
            'init' => 0.0,
8947 
            'init_bit_vector' => '\'b0',
8948 
            'mdl_handle' => 2083.00048828125,
8949 
            'model_handle' => 2083.00048828125,
8950 
            'n_bits' => 16,
8951 
            'ownership' => 1,
8952 
            'preci_type' => 1,
8953 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
8954 
            'shared_memory_name' => 'register09tv',
8955 
          },
8956 
          'needs_vhdl_wrapper' => 0,
8957 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
8958 
        },
8959 
        'entityName' => 'x_x12',
8960 
        'ports' => {
8961 
          'ce' => {
8962 
            'attributes' => {
8963 
              'domain' => '',
8964 
              'group' => 1,
8965 
              'isCe' => 1,
8966 
              'is_floating_block' => 1,
8967 
              'period' => 1.0,
8968 
              'type' => 'logic',
8969 
            },
8970 
            'direction' => 'in',
8971 
            'hdlType' => 'std_logic',
8972 
            'width' => 1,
8973 
          },
8974 
          'clk' => {
8975 
            'attributes' => {
8976 
              'domain' => '',
8977 
              'group' => 1,
8978 
              'isClk' => 1,
8979 
              'is_floating_block' => 1,
8980 
              'period' => 1.0,
8981 
              'type' => 'logic',
8982 
            },
8983 
            'direction' => 'in',
8984 
            'hdlType' => 'std_logic',
8985 
            'width' => 1,
8986 
          },
8987 
          'clr' => {
8988 
            'attributes' => {
8989 
              'domain' => '',
8990 
              'group' => 1,
8991 
              'isClr' => 1,
8992 
              'is_floating_block' => 1,
8993 
              'period' => 1,
8994 
              'type' => 'logic',
8995 
              'valid_bit_used' => 0,
8996 
            },
8997 
            'direction' => 'in',
8998 
            'hdlType' => 'std_logic',
8999 
            'width' => 1,
9000 
          },
9001 
          'data_in' => {
9002 
            'attributes' => {
9003 
              'bin_pt' => 0,
9004 
              'is_floating_block' => 1,
9005 
              'must_be_hdl_vector' => 1,
9006 
              'period' => 1.0,
9007 
              'port_id' => '0',
9008 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
9009 
              'type' => 'Bool',
9010 
            },
9011 
            'direction' => 'in',
9012 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9013 
            'width' => 1,
9014 
          },
9015 
          'dout' => {
9016 
            'attributes' => {
9017 
              'bin_pt' => 0,
9018 
              'is_floating_block' => 1,
9019 
              'must_be_hdl_vector' => 1,
9020 
              'period' => 1.0,
9021 
              'port_id' => '0',
9022 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
9023 
              'type' => 'Bool',
9024 
            },
9025 
            'direction' => 'out',
9026 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9027 
            'width' => 1,
9028 
          },
9029 
          'en' => {
9030 
            'attributes' => {
9031 
              'bin_pt' => 0,
9032 
              'is_floating_block' => 1,
9033 
              'must_be_hdl_vector' => 1,
9034 
              'period' => 1.0,
9035 
              'port_id' => '1',
9036 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
9037 
              'type' => 'Bool',
9038 
            },
9039 
            'direction' => 'in',
9040 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9041 
            'width' => 1,
9042 
          },
9043 
        },
9044 
      },
9045 
      'entityName' => 'x_x12',
9046 
    },
9047 
    'to_register22' => {
9048 
      'connections' => {
9049 
        'ce' => 'ce_1_sg',
9050 
        'clk' => 'clk_1_sg',
9051 
        'clr' => [
9052 
          'constant',
9053 
          '\'0\'',
9054 
        ],
9055 
        'data_in' => 'reg09_td_net_x0',
9056 
        'dout' => 'to_register22_dout_net',
9057 
        'en' => 'constant1_op_net_x1',
9058 
      },
9059 
      'entity' => {
9060 
        'attributes' => {
9061 
          'generics' => [],
9062 
          'is_floating_block' => 1,
9063 
          'mask' => {
9064 
            'Block_Handle' => 2132.00048828125,
9065 
            'Block_handle' => 2132.00048828125,
9066 
            'MDL_Handle' => 2083.00048828125,
9067 
            'MDL_handle' => 2083.00048828125,
9068 
            'arith_type' => 1,
9069 
            'bin_pt' => 14,
9070 
            'block_config' => 'sysgen_blockset:toreg_config',
9071 
            'block_handle' => 2132.00048828125,
9072 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
9073 
            'block_type' => 'toreg',
9074 
            'dbl_ovrd' => 0,
9075 
            'explicit_data_type' => 0,
9076 
            'gui_display_data_type' => 1,
9077 
            'init' => 0.0,
9078 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
9079 
            'mdl_handle' => 2083.00048828125,
9080 
            'model_handle' => 2083.00048828125,
9081 
            'n_bits' => 16,
9082 
            'ownership' => 1,
9083 
            'preci_type' => 1,
9084 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9085 
            'shared_memory_name' => 'register09td',
9086 
          },
9087 
          'needs_vhdl_wrapper' => 0,
9088 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
9089 
        },
9090 
        'entityName' => 'x_x13',
9091 
        'ports' => {
9092 
          'ce' => {
9093 
            'attributes' => {
9094 
              'domain' => '',
9095 
              'group' => 1,
9096 
              'isCe' => 1,
9097 
              'is_floating_block' => 1,
9098 
              'period' => 1.0,
9099 
              'type' => 'logic',
9100 
            },
9101 
            'direction' => 'in',
9102 
            'hdlType' => 'std_logic',
9103 
            'width' => 1,
9104 
          },
9105 
          'clk' => {
9106 
            'attributes' => {
9107 
              'domain' => '',
9108 
              'group' => 1,
9109 
              'isClk' => 1,
9110 
              'is_floating_block' => 1,
9111 
              'period' => 1.0,
9112 
              'type' => 'logic',
9113 
            },
9114 
            'direction' => 'in',
9115 
            'hdlType' => 'std_logic',
9116 
            'width' => 1,
9117 
          },
9118 
          'clr' => {
9119 
            'attributes' => {
9120 
              'domain' => '',
9121 
              'group' => 1,
9122 
              'isClr' => 1,
9123 
              'is_floating_block' => 1,
9124 
              'period' => 1,
9125 
              'type' => 'logic',
9126 
              'valid_bit_used' => 0,
9127 
            },
9128 
            'direction' => 'in',
9129 
            'hdlType' => 'std_logic',
9130 
            'width' => 1,
9131 
          },
9132 
          'data_in' => {
9133 
            'attributes' => {
9134 
              'bin_pt' => 0,
9135 
              'is_floating_block' => 1,
9136 
              'must_be_hdl_vector' => 1,
9137 
              'period' => 1.0,
9138 
              'port_id' => '0',
9139 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
9140 
              'type' => 'UFix_32_0',
9141 
            },
9142 
            'direction' => 'in',
9143 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9144 
            'width' => 32,
9145 
          },
9146 
          'dout' => {
9147 
            'attributes' => {
9148 
              'bin_pt' => 0,
9149 
              'is_floating_block' => 1,
9150 
              'must_be_hdl_vector' => 1,
9151 
              'period' => 1.0,
9152 
              'port_id' => '0',
9153 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
9154 
              'type' => 'UFix_32_0',
9155 
            },
9156 
            'direction' => 'out',
9157 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9158 
            'width' => 32,
9159 
          },
9160 
          'en' => {
9161 
            'attributes' => {
9162 
              'bin_pt' => 0,
9163 
              'is_floating_block' => 1,
9164 
              'must_be_hdl_vector' => 1,
9165 
              'period' => 1.0,
9166 
              'port_id' => '1',
9167 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
9168 
              'type' => 'Bool',
9169 
            },
9170 
            'direction' => 'in',
9171 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9172 
            'width' => 1,
9173 
          },
9174 
        },
9175 
      },
9176 
      'entityName' => 'x_x13',
9177 
    },
9178 
    'to_register23' => {
9179 
      'connections' => {
9180 
        'ce' => 'ce_1_sg',
9181 
        'clk' => 'clk_1_sg',
9182 
        'clr' => [
9183 
          'constant',
9184 
          '\'0\'',
9185 
        ],
9186 
        'data_in' => 'reg10_tv_net_x0',
9187 
        'dout' => 'to_register23_dout_net',
9188 
        'en' => 'constant1_op_net_x2',
9189 
      },
9190 
      'entity' => {
9191 
        'attributes' => {
9192 
          'generics' => [],
9193 
          'is_floating_block' => 1,
9194 
          'mask' => {
9195 
            'Block_Handle' => 2133.00048828125,
9196 
            'Block_handle' => 2133.00048828125,
9197 
            'MDL_Handle' => 2083.00048828125,
9198 
            'MDL_handle' => 2083.00048828125,
9199 
            'arith_type' => 1,
9200 
            'bin_pt' => 14,
9201 
            'block_config' => 'sysgen_blockset:toreg_config',
9202 
            'block_handle' => 2133.00048828125,
9203 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
9204 
            'block_type' => 'toreg',
9205 
            'dbl_ovrd' => 0,
9206 
            'explicit_data_type' => 0,
9207 
            'gui_display_data_type' => 1,
9208 
            'init' => 0.0,
9209 
            'init_bit_vector' => '\'b0',
9210 
            'mdl_handle' => 2083.00048828125,
9211 
            'model_handle' => 2083.00048828125,
9212 
            'n_bits' => 16,
9213 
            'ownership' => 1,
9214 
            'preci_type' => 1,
9215 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9216 
            'shared_memory_name' => 'register10tv',
9217 
          },
9218 
          'needs_vhdl_wrapper' => 0,
9219 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
9220 
        },
9221 
        'entityName' => 'x_x14',
9222 
        'ports' => {
9223 
          'ce' => {
9224 
            'attributes' => {
9225 
              'domain' => '',
9226 
              'group' => 1,
9227 
              'isCe' => 1,
9228 
              'is_floating_block' => 1,
9229 
              'period' => 1.0,
9230 
              'type' => 'logic',
9231 
            },
9232 
            'direction' => 'in',
9233 
            'hdlType' => 'std_logic',
9234 
            'width' => 1,
9235 
          },
9236 
          'clk' => {
9237 
            'attributes' => {
9238 
              'domain' => '',
9239 
              'group' => 1,
9240 
              'isClk' => 1,
9241 
              'is_floating_block' => 1,
9242 
              'period' => 1.0,
9243 
              'type' => 'logic',
9244 
            },
9245 
            'direction' => 'in',
9246 
            'hdlType' => 'std_logic',
9247 
            'width' => 1,
9248 
          },
9249 
          'clr' => {
9250 
            'attributes' => {
9251 
              'domain' => '',
9252 
              'group' => 1,
9253 
              'isClr' => 1,
9254 
              'is_floating_block' => 1,
9255 
              'period' => 1,
9256 
              'type' => 'logic',
9257 
              'valid_bit_used' => 0,
9258 
            },
9259 
            'direction' => 'in',
9260 
            'hdlType' => 'std_logic',
9261 
            'width' => 1,
9262 
          },
9263 
          'data_in' => {
9264 
            'attributes' => {
9265 
              'bin_pt' => 0,
9266 
              'is_floating_block' => 1,
9267 
              'must_be_hdl_vector' => 1,
9268 
              'period' => 1.0,
9269 
              'port_id' => '0',
9270 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
9271 
              'type' => 'Bool',
9272 
            },
9273 
            'direction' => 'in',
9274 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9275 
            'width' => 1,
9276 
          },
9277 
          'dout' => {
9278 
            'attributes' => {
9279 
              'bin_pt' => 0,
9280 
              'is_floating_block' => 1,
9281 
              'must_be_hdl_vector' => 1,
9282 
              'period' => 1.0,
9283 
              'port_id' => '0',
9284 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
9285 
              'type' => 'Bool',
9286 
            },
9287 
            'direction' => 'out',
9288 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9289 
            'width' => 1,
9290 
          },
9291 
          'en' => {
9292 
            'attributes' => {
9293 
              'bin_pt' => 0,
9294 
              'is_floating_block' => 1,
9295 
              'must_be_hdl_vector' => 1,
9296 
              'period' => 1.0,
9297 
              'port_id' => '1',
9298 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
9299 
              'type' => 'Bool',
9300 
            },
9301 
            'direction' => 'in',
9302 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9303 
            'width' => 1,
9304 
          },
9305 
        },
9306 
      },
9307 
      'entityName' => 'x_x14',
9308 
    },
9309 
    'to_register24' => {
9310 
      'connections' => {
9311 
        'ce' => 'ce_1_sg',
9312 
        'clk' => 'clk_1_sg',
9313 
        'clr' => [
9314 
          'constant',
9315 
          '\'0\'',
9316 
        ],
9317 
        'data_in' => 'reg10_td_net_x0',
9318 
        'dout' => 'to_register24_dout_net',
9319 
        'en' => 'constant1_op_net_x3',
9320 
      },
9321 
      'entity' => {
9322 
        'attributes' => {
9323 
          'generics' => [],
9324 
          'is_floating_block' => 1,
9325 
          'mask' => {
9326 
            'Block_Handle' => 2134.00048828125,
9327 
            'Block_handle' => 2134.00048828125,
9328 
            'MDL_Handle' => 2083.00048828125,
9329 
            'MDL_handle' => 2083.00048828125,
9330 
            'arith_type' => 1,
9331 
            'bin_pt' => 14,
9332 
            'block_config' => 'sysgen_blockset:toreg_config',
9333 
            'block_handle' => 2134.00048828125,
9334 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
9335 
            'block_type' => 'toreg',
9336 
            'dbl_ovrd' => 0,
9337 
            'explicit_data_type' => 0,
9338 
            'gui_display_data_type' => 1,
9339 
            'init' => 0.0,
9340 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
9341 
            'mdl_handle' => 2083.00048828125,
9342 
            'model_handle' => 2083.00048828125,
9343 
            'n_bits' => 16,
9344 
            'ownership' => 1,
9345 
            'preci_type' => 1,
9346 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9347 
            'shared_memory_name' => 'register10td',
9348 
          },
9349 
          'needs_vhdl_wrapper' => 0,
9350 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
9351 
        },
9352 
        'entityName' => 'x_x15',
9353 
        'ports' => {
9354 
          'ce' => {
9355 
            'attributes' => {
9356 
              'domain' => '',
9357 
              'group' => 1,
9358 
              'isCe' => 1,
9359 
              'is_floating_block' => 1,
9360 
              'period' => 1.0,
9361 
              'type' => 'logic',
9362 
            },
9363 
            'direction' => 'in',
9364 
            'hdlType' => 'std_logic',
9365 
            'width' => 1,
9366 
          },
9367 
          'clk' => {
9368 
            'attributes' => {
9369 
              'domain' => '',
9370 
              'group' => 1,
9371 
              'isClk' => 1,
9372 
              'is_floating_block' => 1,
9373 
              'period' => 1.0,
9374 
              'type' => 'logic',
9375 
            },
9376 
            'direction' => 'in',
9377 
            'hdlType' => 'std_logic',
9378 
            'width' => 1,
9379 
          },
9380 
          'clr' => {
9381 
            'attributes' => {
9382 
              'domain' => '',
9383 
              'group' => 1,
9384 
              'isClr' => 1,
9385 
              'is_floating_block' => 1,
9386 
              'period' => 1,
9387 
              'type' => 'logic',
9388 
              'valid_bit_used' => 0,
9389 
            },
9390 
            'direction' => 'in',
9391 
            'hdlType' => 'std_logic',
9392 
            'width' => 1,
9393 
          },
9394 
          'data_in' => {
9395 
            'attributes' => {
9396 
              'bin_pt' => 0,
9397 
              'is_floating_block' => 1,
9398 
              'must_be_hdl_vector' => 1,
9399 
              'period' => 1.0,
9400 
              'port_id' => '0',
9401 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
9402 
              'type' => 'UFix_32_0',
9403 
            },
9404 
            'direction' => 'in',
9405 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9406 
            'width' => 32,
9407 
          },
9408 
          'dout' => {
9409 
            'attributes' => {
9410 
              'bin_pt' => 0,
9411 
              'is_floating_block' => 1,
9412 
              'must_be_hdl_vector' => 1,
9413 
              'period' => 1.0,
9414 
              'port_id' => '0',
9415 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
9416 
              'type' => 'UFix_32_0',
9417 
            },
9418 
            'direction' => 'out',
9419 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9420 
            'width' => 32,
9421 
          },
9422 
          'en' => {
9423 
            'attributes' => {
9424 
              'bin_pt' => 0,
9425 
              'is_floating_block' => 1,
9426 
              'must_be_hdl_vector' => 1,
9427 
              'period' => 1.0,
9428 
              'port_id' => '1',
9429 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
9430 
              'type' => 'Bool',
9431 
            },
9432 
            'direction' => 'in',
9433 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9434 
            'width' => 1,
9435 
          },
9436 
        },
9437 
      },
9438 
      'entityName' => 'x_x15',
9439 
    },
9440 
    'to_register25' => {
9441 
      'connections' => {
9442 
        'ce' => 'ce_1_sg',
9443 
        'clk' => 'clk_1_sg',
9444 
        'clr' => [
9445 
          'constant',
9446 
          '\'0\'',
9447 
        ],
9448 
        'data_in' => 'reg08_tv_net_x0',
9449 
        'dout' => 'to_register25_dout_net',
9450 
        'en' => 'constant1_op_net_x4',
9451 
      },
9452 
      'entity' => {
9453 
        'attributes' => {
9454 
          'generics' => [],
9455 
          'is_floating_block' => 1,
9456 
          'mask' => {
9457 
            'Block_Handle' => 2135.00048828125,
9458 
            'Block_handle' => 2135.00048828125,
9459 
            'MDL_Handle' => 2083.00048828125,
9460 
            'MDL_handle' => 2083.00048828125,
9461 
            'arith_type' => 1,
9462 
            'bin_pt' => 14,
9463 
            'block_config' => 'sysgen_blockset:toreg_config',
9464 
            'block_handle' => 2135.00048828125,
9465 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
9466 
            'block_type' => 'toreg',
9467 
            'dbl_ovrd' => 0,
9468 
            'explicit_data_type' => 0,
9469 
            'gui_display_data_type' => 1,
9470 
            'init' => 0.0,
9471 
            'init_bit_vector' => '\'b0',
9472 
            'mdl_handle' => 2083.00048828125,
9473 
            'model_handle' => 2083.00048828125,
9474 
            'n_bits' => 16,
9475 
            'ownership' => 1,
9476 
            'preci_type' => 1,
9477 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9478 
            'shared_memory_name' => 'register08tv',
9479 
          },
9480 
          'needs_vhdl_wrapper' => 0,
9481 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
9482 
        },
9483 
        'entityName' => 'x_x16',
9484 
        'ports' => {
9485 
          'ce' => {
9486 
            'attributes' => {
9487 
              'domain' => '',
9488 
              'group' => 1,
9489 
              'isCe' => 1,
9490 
              'is_floating_block' => 1,
9491 
              'period' => 1.0,
9492 
              'type' => 'logic',
9493 
            },
9494 
            'direction' => 'in',
9495 
            'hdlType' => 'std_logic',
9496 
            'width' => 1,
9497 
          },
9498 
          'clk' => {
9499 
            'attributes' => {
9500 
              'domain' => '',
9501 
              'group' => 1,
9502 
              'isClk' => 1,
9503 
              'is_floating_block' => 1,
9504 
              'period' => 1.0,
9505 
              'type' => 'logic',
9506 
            },
9507 
            'direction' => 'in',
9508 
            'hdlType' => 'std_logic',
9509 
            'width' => 1,
9510 
          },
9511 
          'clr' => {
9512 
            'attributes' => {
9513 
              'domain' => '',
9514 
              'group' => 1,
9515 
              'isClr' => 1,
9516 
              'is_floating_block' => 1,
9517 
              'period' => 1,
9518 
              'type' => 'logic',
9519 
              'valid_bit_used' => 0,
9520 
            },
9521 
            'direction' => 'in',
9522 
            'hdlType' => 'std_logic',
9523 
            'width' => 1,
9524 
          },
9525 
          'data_in' => {
9526 
            'attributes' => {
9527 
              'bin_pt' => 0,
9528 
              'is_floating_block' => 1,
9529 
              'must_be_hdl_vector' => 1,
9530 
              'period' => 1.0,
9531 
              'port_id' => '0',
9532 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
9533 
              'type' => 'Bool',
9534 
            },
9535 
            'direction' => 'in',
9536 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9537 
            'width' => 1,
9538 
          },
9539 
          'dout' => {
9540 
            'attributes' => {
9541 
              'bin_pt' => 0,
9542 
              'is_floating_block' => 1,
9543 
              'must_be_hdl_vector' => 1,
9544 
              'period' => 1.0,
9545 
              'port_id' => '0',
9546 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
9547 
              'type' => 'Bool',
9548 
            },
9549 
            'direction' => 'out',
9550 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9551 
            'width' => 1,
9552 
          },
9553 
          'en' => {
9554 
            'attributes' => {
9555 
              'bin_pt' => 0,
9556 
              'is_floating_block' => 1,
9557 
              'must_be_hdl_vector' => 1,
9558 
              'period' => 1.0,
9559 
              'port_id' => '1',
9560 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
9561 
              'type' => 'Bool',
9562 
            },
9563 
            'direction' => 'in',
9564 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9565 
            'width' => 1,
9566 
          },
9567 
        },
9568 
      },
9569 
      'entityName' => 'x_x16',
9570 
    },
9571 
    'to_register26' => {
9572 
      'connections' => {
9573 
        'ce' => 'ce_1_sg',
9574 
        'clk' => 'clk_1_sg',
9575 
        'clr' => [
9576 
          'constant',
9577 
          '\'0\'',
9578 
        ],
9579 
        'data_in' => 'reg08_td_net_x0',
9580 
        'dout' => 'to_register26_dout_net',
9581 
        'en' => 'constant1_op_net_x5',
9582 
      },
9583 
      'entity' => {
9584 
        'attributes' => {
9585 
          'generics' => [],
9586 
          'is_floating_block' => 1,
9587 
          'mask' => {
9588 
            'Block_Handle' => 2136.00048828125,
9589 
            'Block_handle' => 2136.00048828125,
9590 
            'MDL_Handle' => 2083.00048828125,
9591 
            'MDL_handle' => 2083.00048828125,
9592 
            'arith_type' => 1,
9593 
            'bin_pt' => 14,
9594 
            'block_config' => 'sysgen_blockset:toreg_config',
9595 
            'block_handle' => 2136.00048828125,
9596 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
9597 
            'block_type' => 'toreg',
9598 
            'dbl_ovrd' => 0,
9599 
            'explicit_data_type' => 0,
9600 
            'gui_display_data_type' => 1,
9601 
            'init' => 0.0,
9602 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
9603 
            'mdl_handle' => 2083.00048828125,
9604 
            'model_handle' => 2083.00048828125,
9605 
            'n_bits' => 16,
9606 
            'ownership' => 1,
9607 
            'preci_type' => 1,
9608 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9609 
            'shared_memory_name' => 'register08td',
9610 
          },
9611 
          'needs_vhdl_wrapper' => 0,
9612 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
9613 
        },
9614 
        'entityName' => 'x_x17',
9615 
        'ports' => {
9616 
          'ce' => {
9617 
            'attributes' => {
9618 
              'domain' => '',
9619 
              'group' => 1,
9620 
              'isCe' => 1,
9621 
              'is_floating_block' => 1,
9622 
              'period' => 1.0,
9623 
              'type' => 'logic',
9624 
            },
9625 
            'direction' => 'in',
9626 
            'hdlType' => 'std_logic',
9627 
            'width' => 1,
9628 
          },
9629 
          'clk' => {
9630 
            'attributes' => {
9631 
              'domain' => '',
9632 
              'group' => 1,
9633 
              'isClk' => 1,
9634 
              'is_floating_block' => 1,
9635 
              'period' => 1.0,
9636 
              'type' => 'logic',
9637 
            },
9638 
            'direction' => 'in',
9639 
            'hdlType' => 'std_logic',
9640 
            'width' => 1,
9641 
          },
9642 
          'clr' => {
9643 
            'attributes' => {
9644 
              'domain' => '',
9645 
              'group' => 1,
9646 
              'isClr' => 1,
9647 
              'is_floating_block' => 1,
9648 
              'period' => 1,
9649 
              'type' => 'logic',
9650 
              'valid_bit_used' => 0,
9651 
            },
9652 
            'direction' => 'in',
9653 
            'hdlType' => 'std_logic',
9654 
            'width' => 1,
9655 
          },
9656 
          'data_in' => {
9657 
            'attributes' => {
9658 
              'bin_pt' => 0,
9659 
              'is_floating_block' => 1,
9660 
              'must_be_hdl_vector' => 1,
9661 
              'period' => 1.0,
9662 
              'port_id' => '0',
9663 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
9664 
              'type' => 'UFix_32_0',
9665 
            },
9666 
            'direction' => 'in',
9667 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9668 
            'width' => 32,
9669 
          },
9670 
          'dout' => {
9671 
            'attributes' => {
9672 
              'bin_pt' => 0,
9673 
              'is_floating_block' => 1,
9674 
              'must_be_hdl_vector' => 1,
9675 
              'period' => 1.0,
9676 
              'port_id' => '0',
9677 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
9678 
              'type' => 'UFix_32_0',
9679 
            },
9680 
            'direction' => 'out',
9681 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9682 
            'width' => 32,
9683 
          },
9684 
          'en' => {
9685 
            'attributes' => {
9686 
              'bin_pt' => 0,
9687 
              'is_floating_block' => 1,
9688 
              'must_be_hdl_vector' => 1,
9689 
              'period' => 1.0,
9690 
              'port_id' => '1',
9691 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
9692 
              'type' => 'Bool',
9693 
            },
9694 
            'direction' => 'in',
9695 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9696 
            'width' => 1,
9697 
          },
9698 
        },
9699 
      },
9700 
      'entityName' => 'x_x17',
9701 
    },
9702 
    'to_register27' => {
9703 
      'connections' => {
9704 
        'ce' => 'ce_1_sg',
9705 
        'clk' => 'clk_1_sg',
9706 
        'clr' => [
9707 
          'constant',
9708 
          '\'0\'',
9709 
        ],
9710 
        'data_in' => 'reg11_tv_net_x0',
9711 
        'dout' => 'to_register27_dout_net',
9712 
        'en' => 'constant1_op_net_x6',
9713 
      },
9714 
      'entity' => {
9715 
        'attributes' => {
9716 
          'generics' => [],
9717 
          'is_floating_block' => 1,
9718 
          'mask' => {
9719 
            'Block_Handle' => 2137.00048828125,
9720 
            'Block_handle' => 2137.00048828125,
9721 
            'MDL_Handle' => 2083.00048828125,
9722 
            'MDL_handle' => 2083.00048828125,
9723 
            'arith_type' => 1,
9724 
            'bin_pt' => 14,
9725 
            'block_config' => 'sysgen_blockset:toreg_config',
9726 
            'block_handle' => 2137.00048828125,
9727 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
9728 
            'block_type' => 'toreg',
9729 
            'dbl_ovrd' => 0,
9730 
            'explicit_data_type' => 0,
9731 
            'gui_display_data_type' => 1,
9732 
            'init' => 0.0,
9733 
            'init_bit_vector' => '\'b0',
9734 
            'mdl_handle' => 2083.00048828125,
9735 
            'model_handle' => 2083.00048828125,
9736 
            'n_bits' => 16,
9737 
            'ownership' => 1,
9738 
            'preci_type' => 1,
9739 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9740 
            'shared_memory_name' => 'register11tv',
9741 
          },
9742 
          'needs_vhdl_wrapper' => 0,
9743 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
9744 
        },
9745 
        'entityName' => 'x_x18',
9746 
        'ports' => {
9747 
          'ce' => {
9748 
            'attributes' => {
9749 
              'domain' => '',
9750 
              'group' => 1,
9751 
              'isCe' => 1,
9752 
              'is_floating_block' => 1,
9753 
              'period' => 1.0,
9754 
              'type' => 'logic',
9755 
            },
9756 
            'direction' => 'in',
9757 
            'hdlType' => 'std_logic',
9758 
            'width' => 1,
9759 
          },
9760 
          'clk' => {
9761 
            'attributes' => {
9762 
              'domain' => '',
9763 
              'group' => 1,
9764 
              'isClk' => 1,
9765 
              'is_floating_block' => 1,
9766 
              'period' => 1.0,
9767 
              'type' => 'logic',
9768 
            },
9769 
            'direction' => 'in',
9770 
            'hdlType' => 'std_logic',
9771 
            'width' => 1,
9772 
          },
9773 
          'clr' => {
9774 
            'attributes' => {
9775 
              'domain' => '',
9776 
              'group' => 1,
9777 
              'isClr' => 1,
9778 
              'is_floating_block' => 1,
9779 
              'period' => 1,
9780 
              'type' => 'logic',
9781 
              'valid_bit_used' => 0,
9782 
            },
9783 
            'direction' => 'in',
9784 
            'hdlType' => 'std_logic',
9785 
            'width' => 1,
9786 
          },
9787 
          'data_in' => {
9788 
            'attributes' => {
9789 
              'bin_pt' => 0,
9790 
              'is_floating_block' => 1,
9791 
              'must_be_hdl_vector' => 1,
9792 
              'period' => 1.0,
9793 
              'port_id' => '0',
9794 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
9795 
              'type' => 'Bool',
9796 
            },
9797 
            'direction' => 'in',
9798 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9799 
            'width' => 1,
9800 
          },
9801 
          'dout' => {
9802 
            'attributes' => {
9803 
              'bin_pt' => 0,
9804 
              'is_floating_block' => 1,
9805 
              'must_be_hdl_vector' => 1,
9806 
              'period' => 1.0,
9807 
              'port_id' => '0',
9808 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
9809 
              'type' => 'Bool',
9810 
            },
9811 
            'direction' => 'out',
9812 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9813 
            'width' => 1,
9814 
          },
9815 
          'en' => {
9816 
            'attributes' => {
9817 
              'bin_pt' => 0,
9818 
              'is_floating_block' => 1,
9819 
              'must_be_hdl_vector' => 1,
9820 
              'period' => 1.0,
9821 
              'port_id' => '1',
9822 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
9823 
              'type' => 'Bool',
9824 
            },
9825 
            'direction' => 'in',
9826 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9827 
            'width' => 1,
9828 
          },
9829 
        },
9830 
      },
9831 
      'entityName' => 'x_x18',
9832 
    },
9833 
    'to_register28' => {
9834 
      'connections' => {
9835 
        'ce' => 'ce_1_sg',
9836 
        'clk' => 'clk_1_sg',
9837 
        'clr' => [
9838 
          'constant',
9839 
          '\'0\'',
9840 
        ],
9841 
        'data_in' => 'reg11_td_net_x0',
9842 
        'dout' => 'to_register28_dout_net',
9843 
        'en' => 'constant1_op_net_x7',
9844 
      },
9845 
      'entity' => {
9846 
        'attributes' => {
9847 
          'generics' => [],
9848 
          'is_floating_block' => 1,
9849 
          'mask' => {
9850 
            'Block_Handle' => 2138.00048828125,
9851 
            'Block_handle' => 2138.00048828125,
9852 
            'MDL_Handle' => 2083.00048828125,
9853 
            'MDL_handle' => 2083.00048828125,
9854 
            'arith_type' => 1,
9855 
            'bin_pt' => 14,
9856 
            'block_config' => 'sysgen_blockset:toreg_config',
9857 
            'block_handle' => 2138.00048828125,
9858 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
9859 
            'block_type' => 'toreg',
9860 
            'dbl_ovrd' => 0,
9861 
            'explicit_data_type' => 0,
9862 
            'gui_display_data_type' => 1,
9863 
            'init' => 0.0,
9864 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
9865 
            'mdl_handle' => 2083.00048828125,
9866 
            'model_handle' => 2083.00048828125,
9867 
            'n_bits' => 16,
9868 
            'ownership' => 1,
9869 
            'preci_type' => 1,
9870 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
9871 
            'shared_memory_name' => 'register11td',
9872 
          },
9873 
          'needs_vhdl_wrapper' => 0,
9874 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
9875 
        },
9876 
        'entityName' => 'x_x19',
9877 
        'ports' => {
9878 
          'ce' => {
9879 
            'attributes' => {
9880 
              'domain' => '',
9881 
              'group' => 1,
9882 
              'isCe' => 1,
9883 
              'is_floating_block' => 1,
9884 
              'period' => 1.0,
9885 
              'type' => 'logic',
9886 
            },
9887 
            'direction' => 'in',
9888 
            'hdlType' => 'std_logic',
9889 
            'width' => 1,
9890 
          },
9891 
          'clk' => {
9892 
            'attributes' => {
9893 
              'domain' => '',
9894 
              'group' => 1,
9895 
              'isClk' => 1,
9896 
              'is_floating_block' => 1,
9897 
              'period' => 1.0,
9898 
              'type' => 'logic',
9899 
            },
9900 
            'direction' => 'in',
9901 
            'hdlType' => 'std_logic',
9902 
            'width' => 1,
9903 
          },
9904 
          'clr' => {
9905 
            'attributes' => {
9906 
              'domain' => '',
9907 
              'group' => 1,
9908 
              'isClr' => 1,
9909 
              'is_floating_block' => 1,
9910 
              'period' => 1,
9911 
              'type' => 'logic',
9912 
              'valid_bit_used' => 0,
9913 
            },
9914 
            'direction' => 'in',
9915 
            'hdlType' => 'std_logic',
9916 
            'width' => 1,
9917 
          },
9918 
          'data_in' => {
9919 
            'attributes' => {
9920 
              'bin_pt' => 0,
9921 
              'is_floating_block' => 1,
9922 
              'must_be_hdl_vector' => 1,
9923 
              'period' => 1.0,
9924 
              'port_id' => '0',
9925 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
9926 
              'type' => 'UFix_32_0',
9927 
            },
9928 
            'direction' => 'in',
9929 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9930 
            'width' => 32,
9931 
          },
9932 
          'dout' => {
9933 
            'attributes' => {
9934 
              'bin_pt' => 0,
9935 
              'is_floating_block' => 1,
9936 
              'must_be_hdl_vector' => 1,
9937 
              'period' => 1.0,
9938 
              'port_id' => '0',
9939 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
9940 
              'type' => 'UFix_32_0',
9941 
            },
9942 
            'direction' => 'out',
9943 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9944 
            'width' => 32,
9945 
          },
9946 
          'en' => {
9947 
            'attributes' => {
9948 
              'bin_pt' => 0,
9949 
              'is_floating_block' => 1,
9950 
              'must_be_hdl_vector' => 1,
9951 
              'period' => 1.0,
9952 
              'port_id' => '1',
9953 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
9954 
              'type' => 'Bool',
9955 
            },
9956 
            'direction' => 'in',
9957 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9958 
            'width' => 1,
9959 
          },
9960 
        },
9961 
      },
9962 
      'entityName' => 'x_x19',
9963 
    },
9964 
    'to_register29' => {
9965 
      'connections' => {
9966 
        'ce' => 'ce_1_sg',
9967 
        'clk' => 'clk_1_sg',
9968 
        'clr' => [
9969 
          'constant',
9970 
          '\'0\'',
9971 
        ],
9972 
        'data_in' => 'reg12_tv_net_x0',
9973 
        'dout' => 'to_register29_dout_net',
9974 
        'en' => 'constant1_op_net_x8',
9975 
      },
9976 
      'entity' => {
9977 
        'attributes' => {
9978 
          'generics' => [],
9979 
          'is_floating_block' => 1,
9980 
          'mask' => {
9981 
            'Block_Handle' => 2139.00048828125,
9982 
            'Block_handle' => 2139.00048828125,
9983 
            'MDL_Handle' => 2083.00048828125,
9984 
            'MDL_handle' => 2083.00048828125,
9985 
            'arith_type' => 1,
9986 
            'bin_pt' => 14,
9987 
            'block_config' => 'sysgen_blockset:toreg_config',
9988 
            'block_handle' => 2139.00048828125,
9989 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
9990 
            'block_type' => 'toreg',
9991 
            'dbl_ovrd' => 0,
9992 
            'explicit_data_type' => 0,
9993 
            'gui_display_data_type' => 1,
9994 
            'init' => 0.0,
9995 
            'init_bit_vector' => '\'b0',
9996 
            'mdl_handle' => 2083.00048828125,
9997 
            'model_handle' => 2083.00048828125,
9998 
            'n_bits' => 16,
9999 
            'ownership' => 1,
10000 
            'preci_type' => 1,
10001 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10002 
            'shared_memory_name' => 'register12tv',
10003 
          },
10004 
          'needs_vhdl_wrapper' => 0,
10005 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
10006 
        },
10007 
        'entityName' => 'x_x20',
10008 
        'ports' => {
10009 
          'ce' => {
10010 
            'attributes' => {
10011 
              'domain' => '',
10012 
              'group' => 1,
10013 
              'isCe' => 1,
10014 
              'is_floating_block' => 1,
10015 
              'period' => 1.0,
10016 
              'type' => 'logic',
10017 
            },
10018 
            'direction' => 'in',
10019 
            'hdlType' => 'std_logic',
10020 
            'width' => 1,
10021 
          },
10022 
          'clk' => {
10023 
            'attributes' => {
10024 
              'domain' => '',
10025 
              'group' => 1,
10026 
              'isClk' => 1,
10027 
              'is_floating_block' => 1,
10028 
              'period' => 1.0,
10029 
              'type' => 'logic',
10030 
            },
10031 
            'direction' => 'in',
10032 
            'hdlType' => 'std_logic',
10033 
            'width' => 1,
10034 
          },
10035 
          'clr' => {
10036 
            'attributes' => {
10037 
              'domain' => '',
10038 
              'group' => 1,
10039 
              'isClr' => 1,
10040 
              'is_floating_block' => 1,
10041 
              'period' => 1,
10042 
              'type' => 'logic',
10043 
              'valid_bit_used' => 0,
10044 
            },
10045 
            'direction' => 'in',
10046 
            'hdlType' => 'std_logic',
10047 
            'width' => 1,
10048 
          },
10049 
          'data_in' => {
10050 
            'attributes' => {
10051 
              'bin_pt' => 0,
10052 
              'is_floating_block' => 1,
10053 
              'must_be_hdl_vector' => 1,
10054 
              'period' => 1.0,
10055 
              'port_id' => '0',
10056 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
10057 
              'type' => 'Bool',
10058 
            },
10059 
            'direction' => 'in',
10060 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10061 
            'width' => 1,
10062 
          },
10063 
          'dout' => {
10064 
            'attributes' => {
10065 
              'bin_pt' => 0,
10066 
              'is_floating_block' => 1,
10067 
              'must_be_hdl_vector' => 1,
10068 
              'period' => 1.0,
10069 
              'port_id' => '0',
10070 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
10071 
              'type' => 'Bool',
10072 
            },
10073 
            'direction' => 'out',
10074 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10075 
            'width' => 1,
10076 
          },
10077 
          'en' => {
10078 
            'attributes' => {
10079 
              'bin_pt' => 0,
10080 
              'is_floating_block' => 1,
10081 
              'must_be_hdl_vector' => 1,
10082 
              'period' => 1.0,
10083 
              'port_id' => '1',
10084 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
10085 
              'type' => 'Bool',
10086 
            },
10087 
            'direction' => 'in',
10088 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10089 
            'width' => 1,
10090 
          },
10091 
        },
10092 
      },
10093 
      'entityName' => 'x_x20',
10094 
    },
10095 
    'to_register3' => {
10096 
      'connections' => {
10097 
        'ce' => 'ce_1_sg',
10098 
        'clk' => 'clk_1_sg',
10099 
        'clr' => [
10100 
          'constant',
10101 
          '\'0\'',
10102 
        ],
10103 
        'data_in' => 'reg01_tv_net_x0',
10104 
        'dout' => 'to_register3_dout_net',
10105 
        'en' => 'constant5_op_net_x13',
10106 
      },
10107 
      'entity' => {
10108 
        'attributes' => {
10109 
          'generics' => [],
10110 
          'is_floating_block' => 1,
10111 
          'mask' => {
10112 
            'Block_Handle' => 2140.00048828125,
10113 
            'Block_handle' => 2140.00048828125,
10114 
            'MDL_Handle' => 2083.00048828125,
10115 
            'MDL_handle' => 2083.00048828125,
10116 
            'arith_type' => 1,
10117 
            'bin_pt' => 14,
10118 
            'block_config' => 'sysgen_blockset:toreg_config',
10119 
            'block_handle' => 2140.00048828125,
10120 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
10121 
            'block_type' => 'toreg',
10122 
            'dbl_ovrd' => 0,
10123 
            'explicit_data_type' => 0,
10124 
            'gui_display_data_type' => 1,
10125 
            'init' => 0.0,
10126 
            'init_bit_vector' => '\'b0',
10127 
            'mdl_handle' => 2083.00048828125,
10128 
            'model_handle' => 2083.00048828125,
10129 
            'n_bits' => 16,
10130 
            'ownership' => 1,
10131 
            'preci_type' => 1,
10132 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10133 
            'shared_memory_name' => 'register01tv',
10134 
          },
10135 
          'needs_vhdl_wrapper' => 0,
10136 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
10137 
        },
10138 
        'entityName' => 'x_x21',
10139 
        'ports' => {
10140 
          'ce' => {
10141 
            'attributes' => {
10142 
              'domain' => '',
10143 
              'group' => 1,
10144 
              'isCe' => 1,
10145 
              'is_floating_block' => 1,
10146 
              'period' => 1.0,
10147 
              'type' => 'logic',
10148 
            },
10149 
            'direction' => 'in',
10150 
            'hdlType' => 'std_logic',
10151 
            'width' => 1,
10152 
          },
10153 
          'clk' => {
10154 
            'attributes' => {
10155 
              'domain' => '',
10156 
              'group' => 1,
10157 
              'isClk' => 1,
10158 
              'is_floating_block' => 1,
10159 
              'period' => 1.0,
10160 
              'type' => 'logic',
10161 
            },
10162 
            'direction' => 'in',
10163 
            'hdlType' => 'std_logic',
10164 
            'width' => 1,
10165 
          },
10166 
          'clr' => {
10167 
            'attributes' => {
10168 
              'domain' => '',
10169 
              'group' => 1,
10170 
              'isClr' => 1,
10171 
              'is_floating_block' => 1,
10172 
              'period' => 1,
10173 
              'type' => 'logic',
10174 
              'valid_bit_used' => 0,
10175 
            },
10176 
            'direction' => 'in',
10177 
            'hdlType' => 'std_logic',
10178 
            'width' => 1,
10179 
          },
10180 
          'data_in' => {
10181 
            'attributes' => {
10182 
              'bin_pt' => 0,
10183 
              'is_floating_block' => 1,
10184 
              'must_be_hdl_vector' => 1,
10185 
              'period' => 1.0,
10186 
              'port_id' => '0',
10187 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
10188 
              'type' => 'Bool',
10189 
            },
10190 
            'direction' => 'in',
10191 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10192 
            'width' => 1,
10193 
          },
10194 
          'dout' => {
10195 
            'attributes' => {
10196 
              'bin_pt' => 0,
10197 
              'is_floating_block' => 1,
10198 
              'must_be_hdl_vector' => 1,
10199 
              'period' => 1.0,
10200 
              'port_id' => '0',
10201 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
10202 
              'type' => 'Bool',
10203 
            },
10204 
            'direction' => 'out',
10205 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10206 
            'width' => 1,
10207 
          },
10208 
          'en' => {
10209 
            'attributes' => {
10210 
              'bin_pt' => 0,
10211 
              'is_floating_block' => 1,
10212 
              'must_be_hdl_vector' => 1,
10213 
              'period' => 1.0,
10214 
              'port_id' => '1',
10215 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
10216 
              'type' => 'Bool',
10217 
            },
10218 
            'direction' => 'in',
10219 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10220 
            'width' => 1,
10221 
          },
10222 
        },
10223 
      },
10224 
      'entityName' => 'x_x21',
10225 
    },
10226 
    'to_register30' => {
10227 
      'connections' => {
10228 
        'ce' => 'ce_1_sg',
10229 
        'clk' => 'clk_1_sg',
10230 
        'clr' => [
10231 
          'constant',
10232 
          '\'0\'',
10233 
        ],
10234 
        'data_in' => 'reg12_td_net_x0',
10235 
        'dout' => 'to_register30_dout_net',
10236 
        'en' => 'constant1_op_net_x9',
10237 
      },
10238 
      'entity' => {
10239 
        'attributes' => {
10240 
          'generics' => [],
10241 
          'is_floating_block' => 1,
10242 
          'mask' => {
10243 
            'Block_Handle' => 2141.00048828125,
10244 
            'Block_handle' => 2141.00048828125,
10245 
            'MDL_Handle' => 2083.00048828125,
10246 
            'MDL_handle' => 2083.00048828125,
10247 
            'arith_type' => 1,
10248 
            'bin_pt' => 14,
10249 
            'block_config' => 'sysgen_blockset:toreg_config',
10250 
            'block_handle' => 2141.00048828125,
10251 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
10252 
            'block_type' => 'toreg',
10253 
            'dbl_ovrd' => 0,
10254 
            'explicit_data_type' => 0,
10255 
            'gui_display_data_type' => 1,
10256 
            'init' => 0.0,
10257 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
10258 
            'mdl_handle' => 2083.00048828125,
10259 
            'model_handle' => 2083.00048828125,
10260 
            'n_bits' => 16,
10261 
            'ownership' => 1,
10262 
            'preci_type' => 1,
10263 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10264 
            'shared_memory_name' => 'register12td',
10265 
          },
10266 
          'needs_vhdl_wrapper' => 0,
10267 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
10268 
        },
10269 
        'entityName' => 'x_x22',
10270 
        'ports' => {
10271 
          'ce' => {
10272 
            'attributes' => {
10273 
              'domain' => '',
10274 
              'group' => 1,
10275 
              'isCe' => 1,
10276 
              'is_floating_block' => 1,
10277 
              'period' => 1.0,
10278 
              'type' => 'logic',
10279 
            },
10280 
            'direction' => 'in',
10281 
            'hdlType' => 'std_logic',
10282 
            'width' => 1,
10283 
          },
10284 
          'clk' => {
10285 
            'attributes' => {
10286 
              'domain' => '',
10287 
              'group' => 1,
10288 
              'isClk' => 1,
10289 
              'is_floating_block' => 1,
10290 
              'period' => 1.0,
10291 
              'type' => 'logic',
10292 
            },
10293 
            'direction' => 'in',
10294 
            'hdlType' => 'std_logic',
10295 
            'width' => 1,
10296 
          },
10297 
          'clr' => {
10298 
            'attributes' => {
10299 
              'domain' => '',
10300 
              'group' => 1,
10301 
              'isClr' => 1,
10302 
              'is_floating_block' => 1,
10303 
              'period' => 1,
10304 
              'type' => 'logic',
10305 
              'valid_bit_used' => 0,
10306 
            },
10307 
            'direction' => 'in',
10308 
            'hdlType' => 'std_logic',
10309 
            'width' => 1,
10310 
          },
10311 
          'data_in' => {
10312 
            'attributes' => {
10313 
              'bin_pt' => 0,
10314 
              'is_floating_block' => 1,
10315 
              'must_be_hdl_vector' => 1,
10316 
              'period' => 1.0,
10317 
              'port_id' => '0',
10318 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
10319 
              'type' => 'UFix_32_0',
10320 
            },
10321 
            'direction' => 'in',
10322 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10323 
            'width' => 32,
10324 
          },
10325 
          'dout' => {
10326 
            'attributes' => {
10327 
              'bin_pt' => 0,
10328 
              'is_floating_block' => 1,
10329 
              'must_be_hdl_vector' => 1,
10330 
              'period' => 1.0,
10331 
              'port_id' => '0',
10332 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
10333 
              'type' => 'UFix_32_0',
10334 
            },
10335 
            'direction' => 'out',
10336 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10337 
            'width' => 32,
10338 
          },
10339 
          'en' => {
10340 
            'attributes' => {
10341 
              'bin_pt' => 0,
10342 
              'is_floating_block' => 1,
10343 
              'must_be_hdl_vector' => 1,
10344 
              'period' => 1.0,
10345 
              'port_id' => '1',
10346 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
10347 
              'type' => 'Bool',
10348 
            },
10349 
            'direction' => 'in',
10350 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10351 
            'width' => 1,
10352 
          },
10353 
        },
10354 
      },
10355 
      'entityName' => 'x_x22',
10356 
    },
10357 
    'to_register31' => {
10358 
      'connections' => {
10359 
        'ce' => 'ce_1_sg',
10360 
        'clk' => 'clk_1_sg',
10361 
        'clr' => [
10362 
          'constant',
10363 
          '\'0\'',
10364 
        ],
10365 
        'data_in' => 'reg13_tv_net_x0',
10366 
        'dout' => 'to_register31_dout_net',
10367 
        'en' => 'constant1_op_net_x10',
10368 
      },
10369 
      'entity' => {
10370 
        'attributes' => {
10371 
          'generics' => [],
10372 
          'is_floating_block' => 1,
10373 
          'mask' => {
10374 
            'Block_Handle' => 2142.00048828125,
10375 
            'Block_handle' => 2142.00048828125,
10376 
            'MDL_Handle' => 2083.00048828125,
10377 
            'MDL_handle' => 2083.00048828125,
10378 
            'arith_type' => 1,
10379 
            'bin_pt' => 14,
10380 
            'block_config' => 'sysgen_blockset:toreg_config',
10381 
            'block_handle' => 2142.00048828125,
10382 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
10383 
            'block_type' => 'toreg',
10384 
            'dbl_ovrd' => 0,
10385 
            'explicit_data_type' => 0,
10386 
            'gui_display_data_type' => 1,
10387 
            'init' => 0.0,
10388 
            'init_bit_vector' => '\'b0',
10389 
            'mdl_handle' => 2083.00048828125,
10390 
            'model_handle' => 2083.00048828125,
10391 
            'n_bits' => 16,
10392 
            'ownership' => 1,
10393 
            'preci_type' => 1,
10394 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10395 
            'shared_memory_name' => 'register13tv',
10396 
          },
10397 
          'needs_vhdl_wrapper' => 0,
10398 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
10399 
        },
10400 
        'entityName' => 'x_x23',
10401 
        'ports' => {
10402 
          'ce' => {
10403 
            'attributes' => {
10404 
              'domain' => '',
10405 
              'group' => 1,
10406 
              'isCe' => 1,
10407 
              'is_floating_block' => 1,
10408 
              'period' => 1.0,
10409 
              'type' => 'logic',
10410 
            },
10411 
            'direction' => 'in',
10412 
            'hdlType' => 'std_logic',
10413 
            'width' => 1,
10414 
          },
10415 
          'clk' => {
10416 
            'attributes' => {
10417 
              'domain' => '',
10418 
              'group' => 1,
10419 
              'isClk' => 1,
10420 
              'is_floating_block' => 1,
10421 
              'period' => 1.0,
10422 
              'type' => 'logic',
10423 
            },
10424 
            'direction' => 'in',
10425 
            'hdlType' => 'std_logic',
10426 
            'width' => 1,
10427 
          },
10428 
          'clr' => {
10429 
            'attributes' => {
10430 
              'domain' => '',
10431 
              'group' => 1,
10432 
              'isClr' => 1,
10433 
              'is_floating_block' => 1,
10434 
              'period' => 1,
10435 
              'type' => 'logic',
10436 
              'valid_bit_used' => 0,
10437 
            },
10438 
            'direction' => 'in',
10439 
            'hdlType' => 'std_logic',
10440 
            'width' => 1,
10441 
          },
10442 
          'data_in' => {
10443 
            'attributes' => {
10444 
              'bin_pt' => 0,
10445 
              'is_floating_block' => 1,
10446 
              'must_be_hdl_vector' => 1,
10447 
              'period' => 1.0,
10448 
              'port_id' => '0',
10449 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
10450 
              'type' => 'Bool',
10451 
            },
10452 
            'direction' => 'in',
10453 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10454 
            'width' => 1,
10455 
          },
10456 
          'dout' => {
10457 
            'attributes' => {
10458 
              'bin_pt' => 0,
10459 
              'is_floating_block' => 1,
10460 
              'must_be_hdl_vector' => 1,
10461 
              'period' => 1.0,
10462 
              'port_id' => '0',
10463 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
10464 
              'type' => 'Bool',
10465 
            },
10466 
            'direction' => 'out',
10467 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10468 
            'width' => 1,
10469 
          },
10470 
          'en' => {
10471 
            'attributes' => {
10472 
              'bin_pt' => 0,
10473 
              'is_floating_block' => 1,
10474 
              'must_be_hdl_vector' => 1,
10475 
              'period' => 1.0,
10476 
              'port_id' => '1',
10477 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
10478 
              'type' => 'Bool',
10479 
            },
10480 
            'direction' => 'in',
10481 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10482 
            'width' => 1,
10483 
          },
10484 
        },
10485 
      },
10486 
      'entityName' => 'x_x23',
10487 
    },
10488 
    'to_register32' => {
10489 
      'connections' => {
10490 
        'ce' => 'ce_1_sg',
10491 
        'clk' => 'clk_1_sg',
10492 
        'clr' => [
10493 
          'constant',
10494 
          '\'0\'',
10495 
        ],
10496 
        'data_in' => 'reg13_td_net_x0',
10497 
        'dout' => 'to_register32_dout_net',
10498 
        'en' => 'constant1_op_net_x11',
10499 
      },
10500 
      'entity' => {
10501 
        'attributes' => {
10502 
          'generics' => [],
10503 
          'is_floating_block' => 1,
10504 
          'mask' => {
10505 
            'Block_Handle' => 2143.00048828125,
10506 
            'Block_handle' => 2143.00048828125,
10507 
            'MDL_Handle' => 2083.00048828125,
10508 
            'MDL_handle' => 2083.00048828125,
10509 
            'arith_type' => 1,
10510 
            'bin_pt' => 14,
10511 
            'block_config' => 'sysgen_blockset:toreg_config',
10512 
            'block_handle' => 2143.00048828125,
10513 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
10514 
            'block_type' => 'toreg',
10515 
            'dbl_ovrd' => 0,
10516 
            'explicit_data_type' => 0,
10517 
            'gui_display_data_type' => 1,
10518 
            'init' => 0.0,
10519 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
10520 
            'mdl_handle' => 2083.00048828125,
10521 
            'model_handle' => 2083.00048828125,
10522 
            'n_bits' => 16,
10523 
            'ownership' => 1,
10524 
            'preci_type' => 1,
10525 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10526 
            'shared_memory_name' => 'register13td',
10527 
          },
10528 
          'needs_vhdl_wrapper' => 0,
10529 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
10530 
        },
10531 
        'entityName' => 'x_x24',
10532 
        'ports' => {
10533 
          'ce' => {
10534 
            'attributes' => {
10535 
              'domain' => '',
10536 
              'group' => 1,
10537 
              'isCe' => 1,
10538 
              'is_floating_block' => 1,
10539 
              'period' => 1.0,
10540 
              'type' => 'logic',
10541 
            },
10542 
            'direction' => 'in',
10543 
            'hdlType' => 'std_logic',
10544 
            'width' => 1,
10545 
          },
10546 
          'clk' => {
10547 
            'attributes' => {
10548 
              'domain' => '',
10549 
              'group' => 1,
10550 
              'isClk' => 1,
10551 
              'is_floating_block' => 1,
10552 
              'period' => 1.0,
10553 
              'type' => 'logic',
10554 
            },
10555 
            'direction' => 'in',
10556 
            'hdlType' => 'std_logic',
10557 
            'width' => 1,
10558 
          },
10559 
          'clr' => {
10560 
            'attributes' => {
10561 
              'domain' => '',
10562 
              'group' => 1,
10563 
              'isClr' => 1,
10564 
              'is_floating_block' => 1,
10565 
              'period' => 1,
10566 
              'type' => 'logic',
10567 
              'valid_bit_used' => 0,
10568 
            },
10569 
            'direction' => 'in',
10570 
            'hdlType' => 'std_logic',
10571 
            'width' => 1,
10572 
          },
10573 
          'data_in' => {
10574 
            'attributes' => {
10575 
              'bin_pt' => 0,
10576 
              'is_floating_block' => 1,
10577 
              'must_be_hdl_vector' => 1,
10578 
              'period' => 1.0,
10579 
              'port_id' => '0',
10580 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
10581 
              'type' => 'UFix_32_0',
10582 
            },
10583 
            'direction' => 'in',
10584 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10585 
            'width' => 32,
10586 
          },
10587 
          'dout' => {
10588 
            'attributes' => {
10589 
              'bin_pt' => 0,
10590 
              'is_floating_block' => 1,
10591 
              'must_be_hdl_vector' => 1,
10592 
              'period' => 1.0,
10593 
              'port_id' => '0',
10594 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
10595 
              'type' => 'UFix_32_0',
10596 
            },
10597 
            'direction' => 'out',
10598 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10599 
            'width' => 32,
10600 
          },
10601 
          'en' => {
10602 
            'attributes' => {
10603 
              'bin_pt' => 0,
10604 
              'is_floating_block' => 1,
10605 
              'must_be_hdl_vector' => 1,
10606 
              'period' => 1.0,
10607 
              'port_id' => '1',
10608 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
10609 
              'type' => 'Bool',
10610 
            },
10611 
            'direction' => 'in',
10612 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10613 
            'width' => 1,
10614 
          },
10615 
        },
10616 
      },
10617 
      'entityName' => 'x_x24',
10618 
    },
10619 
    'to_register33' => {
10620 
      'connections' => {
10621 
        'ce' => 'ce_1_sg',
10622 
        'clk' => 'clk_1_sg',
10623 
        'clr' => [
10624 
          'constant',
10625 
          '\'0\'',
10626 
        ],
10627 
        'data_in' => 'reg14_tv_net_x0',
10628 
        'dout' => 'to_register33_dout_net',
10629 
        'en' => 'constant1_op_net_x12',
10630 
      },
10631 
      'entity' => {
10632 
        'attributes' => {
10633 
          'generics' => [],
10634 
          'is_floating_block' => 1,
10635 
          'mask' => {
10636 
            'Block_Handle' => 2144.00048828125,
10637 
            'Block_handle' => 2144.00048828125,
10638 
            'MDL_Handle' => 2083.00048828125,
10639 
            'MDL_handle' => 2083.00048828125,
10640 
            'arith_type' => 1,
10641 
            'bin_pt' => 14,
10642 
            'block_config' => 'sysgen_blockset:toreg_config',
10643 
            'block_handle' => 2144.00048828125,
10644 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
10645 
            'block_type' => 'toreg',
10646 
            'dbl_ovrd' => 0,
10647 
            'explicit_data_type' => 0,
10648 
            'gui_display_data_type' => 1,
10649 
            'init' => 0.0,
10650 
            'init_bit_vector' => '\'b0',
10651 
            'mdl_handle' => 2083.00048828125,
10652 
            'model_handle' => 2083.00048828125,
10653 
            'n_bits' => 16,
10654 
            'ownership' => 1,
10655 
            'preci_type' => 1,
10656 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10657 
            'shared_memory_name' => 'register14tv',
10658 
          },
10659 
          'needs_vhdl_wrapper' => 0,
10660 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
10661 
        },
10662 
        'entityName' => 'x_x25',
10663 
        'ports' => {
10664 
          'ce' => {
10665 
            'attributes' => {
10666 
              'domain' => '',
10667 
              'group' => 1,
10668 
              'isCe' => 1,
10669 
              'is_floating_block' => 1,
10670 
              'period' => 1.0,
10671 
              'type' => 'logic',
10672 
            },
10673 
            'direction' => 'in',
10674 
            'hdlType' => 'std_logic',
10675 
            'width' => 1,
10676 
          },
10677 
          'clk' => {
10678 
            'attributes' => {
10679 
              'domain' => '',
10680 
              'group' => 1,
10681 
              'isClk' => 1,
10682 
              'is_floating_block' => 1,
10683 
              'period' => 1.0,
10684 
              'type' => 'logic',
10685 
            },
10686 
            'direction' => 'in',
10687 
            'hdlType' => 'std_logic',
10688 
            'width' => 1,
10689 
          },
10690 
          'clr' => {
10691 
            'attributes' => {
10692 
              'domain' => '',
10693 
              'group' => 1,
10694 
              'isClr' => 1,
10695 
              'is_floating_block' => 1,
10696 
              'period' => 1,
10697 
              'type' => 'logic',
10698 
              'valid_bit_used' => 0,
10699 
            },
10700 
            'direction' => 'in',
10701 
            'hdlType' => 'std_logic',
10702 
            'width' => 1,
10703 
          },
10704 
          'data_in' => {
10705 
            'attributes' => {
10706 
              'bin_pt' => 0,
10707 
              'is_floating_block' => 1,
10708 
              'must_be_hdl_vector' => 1,
10709 
              'period' => 1.0,
10710 
              'port_id' => '0',
10711 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
10712 
              'type' => 'Bool',
10713 
            },
10714 
            'direction' => 'in',
10715 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10716 
            'width' => 1,
10717 
          },
10718 
          'dout' => {
10719 
            'attributes' => {
10720 
              'bin_pt' => 0,
10721 
              'is_floating_block' => 1,
10722 
              'must_be_hdl_vector' => 1,
10723 
              'period' => 1.0,
10724 
              'port_id' => '0',
10725 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
10726 
              'type' => 'Bool',
10727 
            },
10728 
            'direction' => 'out',
10729 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10730 
            'width' => 1,
10731 
          },
10732 
          'en' => {
10733 
            'attributes' => {
10734 
              'bin_pt' => 0,
10735 
              'is_floating_block' => 1,
10736 
              'must_be_hdl_vector' => 1,
10737 
              'period' => 1.0,
10738 
              'port_id' => '1',
10739 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
10740 
              'type' => 'Bool',
10741 
            },
10742 
            'direction' => 'in',
10743 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10744 
            'width' => 1,
10745 
          },
10746 
        },
10747 
      },
10748 
      'entityName' => 'x_x25',
10749 
    },
10750 
    'to_register34' => {
10751 
      'connections' => {
10752 
        'ce' => 'ce_1_sg',
10753 
        'clk' => 'clk_1_sg',
10754 
        'clr' => [
10755 
          'constant',
10756 
          '\'0\'',
10757 
        ],
10758 
        'data_in' => 'reg14_td_net_x0',
10759 
        'dout' => 'to_register34_dout_net',
10760 
        'en' => 'constant1_op_net_x13',
10761 
      },
10762 
      'entity' => {
10763 
        'attributes' => {
10764 
          'generics' => [],
10765 
          'is_floating_block' => 1,
10766 
          'mask' => {
10767 
            'Block_Handle' => 2145.00048828125,
10768 
            'Block_handle' => 2145.00048828125,
10769 
            'MDL_Handle' => 2083.00048828125,
10770 
            'MDL_handle' => 2083.00048828125,
10771 
            'arith_type' => 1,
10772 
            'bin_pt' => 14,
10773 
            'block_config' => 'sysgen_blockset:toreg_config',
10774 
            'block_handle' => 2145.00048828125,
10775 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
10776 
            'block_type' => 'toreg',
10777 
            'dbl_ovrd' => 0,
10778 
            'explicit_data_type' => 0,
10779 
            'gui_display_data_type' => 1,
10780 
            'init' => 0.0,
10781 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
10782 
            'mdl_handle' => 2083.00048828125,
10783 
            'model_handle' => 2083.00048828125,
10784 
            'n_bits' => 16,
10785 
            'ownership' => 1,
10786 
            'preci_type' => 1,
10787 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10788 
            'shared_memory_name' => 'register14td',
10789 
          },
10790 
          'needs_vhdl_wrapper' => 0,
10791 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
10792 
        },
10793 
        'entityName' => 'x_x26',
10794 
        'ports' => {
10795 
          'ce' => {
10796 
            'attributes' => {
10797 
              'domain' => '',
10798 
              'group' => 1,
10799 
              'isCe' => 1,
10800 
              'is_floating_block' => 1,
10801 
              'period' => 1.0,
10802 
              'type' => 'logic',
10803 
            },
10804 
            'direction' => 'in',
10805 
            'hdlType' => 'std_logic',
10806 
            'width' => 1,
10807 
          },
10808 
          'clk' => {
10809 
            'attributes' => {
10810 
              'domain' => '',
10811 
              'group' => 1,
10812 
              'isClk' => 1,
10813 
              'is_floating_block' => 1,
10814 
              'period' => 1.0,
10815 
              'type' => 'logic',
10816 
            },
10817 
            'direction' => 'in',
10818 
            'hdlType' => 'std_logic',
10819 
            'width' => 1,
10820 
          },
10821 
          'clr' => {
10822 
            'attributes' => {
10823 
              'domain' => '',
10824 
              'group' => 1,
10825 
              'isClr' => 1,
10826 
              'is_floating_block' => 1,
10827 
              'period' => 1,
10828 
              'type' => 'logic',
10829 
              'valid_bit_used' => 0,
10830 
            },
10831 
            'direction' => 'in',
10832 
            'hdlType' => 'std_logic',
10833 
            'width' => 1,
10834 
          },
10835 
          'data_in' => {
10836 
            'attributes' => {
10837 
              'bin_pt' => 0,
10838 
              'is_floating_block' => 1,
10839 
              'must_be_hdl_vector' => 1,
10840 
              'period' => 1.0,
10841 
              'port_id' => '0',
10842 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
10843 
              'type' => 'UFix_32_0',
10844 
            },
10845 
            'direction' => 'in',
10846 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10847 
            'width' => 32,
10848 
          },
10849 
          'dout' => {
10850 
            'attributes' => {
10851 
              'bin_pt' => 0,
10852 
              'is_floating_block' => 1,
10853 
              'must_be_hdl_vector' => 1,
10854 
              'period' => 1.0,
10855 
              'port_id' => '0',
10856 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
10857 
              'type' => 'UFix_32_0',
10858 
            },
10859 
            'direction' => 'out',
10860 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10861 
            'width' => 32,
10862 
          },
10863 
          'en' => {
10864 
            'attributes' => {
10865 
              'bin_pt' => 0,
10866 
              'is_floating_block' => 1,
10867 
              'must_be_hdl_vector' => 1,
10868 
              'period' => 1.0,
10869 
              'port_id' => '1',
10870 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
10871 
              'type' => 'Bool',
10872 
            },
10873 
            'direction' => 'in',
10874 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10875 
            'width' => 1,
10876 
          },
10877 
        },
10878 
      },
10879 
      'entityName' => 'x_x26',
10880 
    },
10881 
    'to_register4' => {
10882 
      'connections' => {
10883 
        'ce' => 'ce_1_sg',
10884 
        'clk' => 'clk_1_sg',
10885 
        'clr' => [
10886 
          'constant',
10887 
          '\'0\'',
10888 
        ],
10889 
        'data_in' => 'reg02_tv_net_x0',
10890 
        'dout' => 'to_register4_dout_net',
10891 
        'en' => 'constant5_op_net_x14',
10892 
      },
10893 
      'entity' => {
10894 
        'attributes' => {
10895 
          'generics' => [],
10896 
          'is_floating_block' => 1,
10897 
          'mask' => {
10898 
            'Block_Handle' => 2146.00048828125,
10899 
            'Block_handle' => 2146.00048828125,
10900 
            'MDL_Handle' => 2083.00048828125,
10901 
            'MDL_handle' => 2083.00048828125,
10902 
            'arith_type' => 1,
10903 
            'bin_pt' => 14,
10904 
            'block_config' => 'sysgen_blockset:toreg_config',
10905 
            'block_handle' => 2146.00048828125,
10906 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
10907 
            'block_type' => 'toreg',
10908 
            'dbl_ovrd' => 0,
10909 
            'explicit_data_type' => 0,
10910 
            'gui_display_data_type' => 1,
10911 
            'init' => 0.0,
10912 
            'init_bit_vector' => '\'b0',
10913 
            'mdl_handle' => 2083.00048828125,
10914 
            'model_handle' => 2083.00048828125,
10915 
            'n_bits' => 16,
10916 
            'ownership' => 1,
10917 
            'preci_type' => 1,
10918 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
10919 
            'shared_memory_name' => 'register02tv',
10920 
          },
10921 
          'needs_vhdl_wrapper' => 0,
10922 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
10923 
        },
10924 
        'entityName' => 'x_x27',
10925 
        'ports' => {
10926 
          'ce' => {
10927 
            'attributes' => {
10928 
              'domain' => '',
10929 
              'group' => 1,
10930 
              'isCe' => 1,
10931 
              'is_floating_block' => 1,
10932 
              'period' => 1.0,
10933 
              'type' => 'logic',
10934 
            },
10935 
            'direction' => 'in',
10936 
            'hdlType' => 'std_logic',
10937 
            'width' => 1,
10938 
          },
10939 
          'clk' => {
10940 
            'attributes' => {
10941 
              'domain' => '',
10942 
              'group' => 1,
10943 
              'isClk' => 1,
10944 
              'is_floating_block' => 1,
10945 
              'period' => 1.0,
10946 
              'type' => 'logic',
10947 
            },
10948 
            'direction' => 'in',
10949 
            'hdlType' => 'std_logic',
10950 
            'width' => 1,
10951 
          },
10952 
          'clr' => {
10953 
            'attributes' => {
10954 
              'domain' => '',
10955 
              'group' => 1,
10956 
              'isClr' => 1,
10957 
              'is_floating_block' => 1,
10958 
              'period' => 1,
10959 
              'type' => 'logic',
10960 
              'valid_bit_used' => 0,
10961 
            },
10962 
            'direction' => 'in',
10963 
            'hdlType' => 'std_logic',
10964 
            'width' => 1,
10965 
          },
10966 
          'data_in' => {
10967 
            'attributes' => {
10968 
              'bin_pt' => 0,
10969 
              'is_floating_block' => 1,
10970 
              'must_be_hdl_vector' => 1,
10971 
              'period' => 1.0,
10972 
              'port_id' => '0',
10973 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
10974 
              'type' => 'Bool',
10975 
            },
10976 
            'direction' => 'in',
10977 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10978 
            'width' => 1,
10979 
          },
10980 
          'dout' => {
10981 
            'attributes' => {
10982 
              'bin_pt' => 0,
10983 
              'is_floating_block' => 1,
10984 
              'must_be_hdl_vector' => 1,
10985 
              'period' => 1.0,
10986 
              'port_id' => '0',
10987 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
10988 
              'type' => 'Bool',
10989 
            },
10990 
            'direction' => 'out',
10991 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10992 
            'width' => 1,
10993 
          },
10994 
          'en' => {
10995 
            'attributes' => {
10996 
              'bin_pt' => 0,
10997 
              'is_floating_block' => 1,
10998 
              'must_be_hdl_vector' => 1,
10999 
              'period' => 1.0,
11000 
              'port_id' => '1',
11001 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
11002 
              'type' => 'Bool',
11003 
            },
11004 
            'direction' => 'in',
11005 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11006 
            'width' => 1,
11007 
          },
11008 
        },
11009 
      },
11010 
      'entityName' => 'x_x27',
11011 
    },
11012 
    'to_register5' => {
11013 
      'connections' => {
11014 
        'ce' => 'ce_1_sg',
11015 
        'clk' => 'clk_1_sg',
11016 
        'clr' => [
11017 
          'constant',
11018 
          '\'0\'',
11019 
        ],
11020 
        'data_in' => 'reg02_td_net_x0',
11021 
        'dout' => 'to_register5_dout_net',
11022 
        'en' => 'constant5_op_net_x15',
11023 
      },
11024 
      'entity' => {
11025 
        'attributes' => {
11026 
          'generics' => [],
11027 
          'is_floating_block' => 1,
11028 
          'mask' => {
11029 
            'Block_Handle' => 2147.00048828125,
11030 
            'Block_handle' => 2147.00048828125,
11031 
            'MDL_Handle' => 2083.00048828125,
11032 
            'MDL_handle' => 2083.00048828125,
11033 
            'arith_type' => 1,
11034 
            'bin_pt' => 14,
11035 
            'block_config' => 'sysgen_blockset:toreg_config',
11036 
            'block_handle' => 2147.00048828125,
11037 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
11038 
            'block_type' => 'toreg',
11039 
            'dbl_ovrd' => 0,
11040 
            'explicit_data_type' => 0,
11041 
            'gui_display_data_type' => 1,
11042 
            'init' => 0.0,
11043 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
11044 
            'mdl_handle' => 2083.00048828125,
11045 
            'model_handle' => 2083.00048828125,
11046 
            'n_bits' => 16,
11047 
            'ownership' => 1,
11048 
            'preci_type' => 1,
11049 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
11050 
            'shared_memory_name' => 'register02td',
11051 
          },
11052 
          'needs_vhdl_wrapper' => 0,
11053 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
11054 
        },
11055 
        'entityName' => 'x_x28',
11056 
        'ports' => {
11057 
          'ce' => {
11058 
            'attributes' => {
11059 
              'domain' => '',
11060 
              'group' => 1,
11061 
              'isCe' => 1,
11062 
              'is_floating_block' => 1,
11063 
              'period' => 1.0,
11064 
              'type' => 'logic',
11065 
            },
11066 
            'direction' => 'in',
11067 
            'hdlType' => 'std_logic',
11068 
            'width' => 1,
11069 
          },
11070 
          'clk' => {
11071 
            'attributes' => {
11072 
              'domain' => '',
11073 
              'group' => 1,
11074 
              'isClk' => 1,
11075 
              'is_floating_block' => 1,
11076 
              'period' => 1.0,
11077 
              'type' => 'logic',
11078 
            },
11079 
            'direction' => 'in',
11080 
            'hdlType' => 'std_logic',
11081 
            'width' => 1,
11082 
          },
11083 
          'clr' => {
11084 
            'attributes' => {
11085 
              'domain' => '',
11086 
              'group' => 1,
11087 
              'isClr' => 1,
11088 
              'is_floating_block' => 1,
11089 
              'period' => 1,
11090 
              'type' => 'logic',
11091 
              'valid_bit_used' => 0,
11092 
            },
11093 
            'direction' => 'in',
11094 
            'hdlType' => 'std_logic',
11095 
            'width' => 1,
11096 
          },
11097 
          'data_in' => {
11098 
            'attributes' => {
11099 
              'bin_pt' => 0,
11100 
              'is_floating_block' => 1,
11101 
              'must_be_hdl_vector' => 1,
11102 
              'period' => 1.0,
11103 
              'port_id' => '0',
11104 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11105 
              'type' => 'UFix_32_0',
11106 
            },
11107 
            'direction' => 'in',
11108 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11109 
            'width' => 32,
11110 
          },
11111 
          'dout' => {
11112 
            'attributes' => {
11113 
              'bin_pt' => 0,
11114 
              'is_floating_block' => 1,
11115 
              'must_be_hdl_vector' => 1,
11116 
              'period' => 1.0,
11117 
              'port_id' => '0',
11118 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11119 
              'type' => 'UFix_32_0',
11120 
            },
11121 
            'direction' => 'out',
11122 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11123 
            'width' => 32,
11124 
          },
11125 
          'en' => {
11126 
            'attributes' => {
11127 
              'bin_pt' => 0,
11128 
              'is_floating_block' => 1,
11129 
              'must_be_hdl_vector' => 1,
11130 
              'period' => 1.0,
11131 
              'port_id' => '1',
11132 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11133 
              'type' => 'Bool',
11134 
            },
11135 
            'direction' => 'in',
11136 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11137 
            'width' => 1,
11138 
          },
11139 
        },
11140 
      },
11141 
      'entityName' => 'x_x28',
11142 
    },
11143 
    'to_register6' => {
11144 
      'connections' => {
11145 
        'ce' => 'ce_1_sg',
11146 
        'clk' => 'clk_1_sg',
11147 
        'clr' => [
11148 
          'constant',
11149 
          '\'0\'',
11150 
        ],
11151 
        'data_in' => 'debug_in_1i_net_x0',
11152 
        'dout' => 'to_register6_dout_net',
11153 
        'en' => 'constant5_op_net_x16',
11154 
      },
11155 
      'entity' => {
11156 
        'attributes' => {
11157 
          'generics' => [],
11158 
          'is_floating_block' => 1,
11159 
          'mask' => {
11160 
            'Block_Handle' => 2148.00048828125,
11161 
            'Block_handle' => 2148.00048828125,
11162 
            'MDL_Handle' => 2083.00048828125,
11163 
            'MDL_handle' => 2083.00048828125,
11164 
            'arith_type' => 1,
11165 
            'bin_pt' => 14,
11166 
            'block_config' => 'sysgen_blockset:toreg_config',
11167 
            'block_handle' => 2148.00048828125,
11168 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
11169 
            'block_type' => 'toreg',
11170 
            'dbl_ovrd' => 0,
11171 
            'explicit_data_type' => 0,
11172 
            'gui_display_data_type' => 1,
11173 
            'init' => 0.0,
11174 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
11175 
            'mdl_handle' => 2083.00048828125,
11176 
            'model_handle' => 2083.00048828125,
11177 
            'n_bits' => 16,
11178 
            'ownership' => 1,
11179 
            'preci_type' => 1,
11180 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
11181 
            'shared_memory_name' => 'debug1i',
11182 
          },
11183 
          'needs_vhdl_wrapper' => 0,
11184 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
11185 
        },
11186 
        'entityName' => 'x_x29',
11187 
        'ports' => {
11188 
          'ce' => {
11189 
            'attributes' => {
11190 
              'domain' => '',
11191 
              'group' => 1,
11192 
              'isCe' => 1,
11193 
              'is_floating_block' => 1,
11194 
              'period' => 1.0,
11195 
              'type' => 'logic',
11196 
            },
11197 
            'direction' => 'in',
11198 
            'hdlType' => 'std_logic',
11199 
            'width' => 1,
11200 
          },
11201 
          'clk' => {
11202 
            'attributes' => {
11203 
              'domain' => '',
11204 
              'group' => 1,
11205 
              'isClk' => 1,
11206 
              'is_floating_block' => 1,
11207 
              'period' => 1.0,
11208 
              'type' => 'logic',
11209 
            },
11210 
            'direction' => 'in',
11211 
            'hdlType' => 'std_logic',
11212 
            'width' => 1,
11213 
          },
11214 
          'clr' => {
11215 
            'attributes' => {
11216 
              'domain' => '',
11217 
              'group' => 1,
11218 
              'isClr' => 1,
11219 
              'is_floating_block' => 1,
11220 
              'period' => 1,
11221 
              'type' => 'logic',
11222 
              'valid_bit_used' => 0,
11223 
            },
11224 
            'direction' => 'in',
11225 
            'hdlType' => 'std_logic',
11226 
            'width' => 1,
11227 
          },
11228 
          'data_in' => {
11229 
            'attributes' => {
11230 
              'bin_pt' => 0,
11231 
              'is_floating_block' => 1,
11232 
              'must_be_hdl_vector' => 1,
11233 
              'period' => 1.0,
11234 
              'port_id' => '0',
11235 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11236 
              'type' => 'UFix_32_0',
11237 
            },
11238 
            'direction' => 'in',
11239 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11240 
            'width' => 32,
11241 
          },
11242 
          'dout' => {
11243 
            'attributes' => {
11244 
              'bin_pt' => 0,
11245 
              'is_floating_block' => 1,
11246 
              'must_be_hdl_vector' => 1,
11247 
              'period' => 1.0,
11248 
              'port_id' => '0',
11249 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11250 
              'type' => 'UFix_32_0',
11251 
            },
11252 
            'direction' => 'out',
11253 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11254 
            'width' => 32,
11255 
          },
11256 
          'en' => {
11257 
            'attributes' => {
11258 
              'bin_pt' => 0,
11259 
              'is_floating_block' => 1,
11260 
              'must_be_hdl_vector' => 1,
11261 
              'period' => 1.0,
11262 
              'port_id' => '1',
11263 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11264 
              'type' => 'Bool',
11265 
            },
11266 
            'direction' => 'in',
11267 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11268 
            'width' => 1,
11269 
          },
11270 
        },
11271 
      },
11272 
      'entityName' => 'x_x29',
11273 
    },
11274 
    'to_register7' => {
11275 
      'connections' => {
11276 
        'ce' => 'ce_1_sg',
11277 
        'clk' => 'clk_1_sg',
11278 
        'clr' => [
11279 
          'constant',
11280 
          '\'0\'',
11281 
        ],
11282 
        'data_in' => 'reg01_td_net_x0',
11283 
        'dout' => 'to_register7_dout_net',
11284 
        'en' => 'constant5_op_net_x17',
11285 
      },
11286 
      'entity' => {
11287 
        'attributes' => {
11288 
          'generics' => [],
11289 
          'is_floating_block' => 1,
11290 
          'mask' => {
11291 
            'Block_Handle' => 2149.00048828125,
11292 
            'Block_handle' => 2149.00048828125,
11293 
            'MDL_Handle' => 2083.00048828125,
11294 
            'MDL_handle' => 2083.00048828125,
11295 
            'arith_type' => 1,
11296 
            'bin_pt' => 14,
11297 
            'block_config' => 'sysgen_blockset:toreg_config',
11298 
            'block_handle' => 2149.00048828125,
11299 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
11300 
            'block_type' => 'toreg',
11301 
            'dbl_ovrd' => 0,
11302 
            'explicit_data_type' => 0,
11303 
            'gui_display_data_type' => 1,
11304 
            'init' => 0.0,
11305 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
11306 
            'mdl_handle' => 2083.00048828125,
11307 
            'model_handle' => 2083.00048828125,
11308 
            'n_bits' => 16,
11309 
            'ownership' => 1,
11310 
            'preci_type' => 1,
11311 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
11312 
            'shared_memory_name' => 'register01td',
11313 
          },
11314 
          'needs_vhdl_wrapper' => 0,
11315 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
11316 
        },
11317 
        'entityName' => 'x_x30',
11318 
        'ports' => {
11319 
          'ce' => {
11320 
            'attributes' => {
11321 
              'domain' => '',
11322 
              'group' => 1,
11323 
              'isCe' => 1,
11324 
              'is_floating_block' => 1,
11325 
              'period' => 1.0,
11326 
              'type' => 'logic',
11327 
            },
11328 
            'direction' => 'in',
11329 
            'hdlType' => 'std_logic',
11330 
            'width' => 1,
11331 
          },
11332 
          'clk' => {
11333 
            'attributes' => {
11334 
              'domain' => '',
11335 
              'group' => 1,
11336 
              'isClk' => 1,
11337 
              'is_floating_block' => 1,
11338 
              'period' => 1.0,
11339 
              'type' => 'logic',
11340 
            },
11341 
            'direction' => 'in',
11342 
            'hdlType' => 'std_logic',
11343 
            'width' => 1,
11344 
          },
11345 
          'clr' => {
11346 
            'attributes' => {
11347 
              'domain' => '',
11348 
              'group' => 1,
11349 
              'isClr' => 1,
11350 
              'is_floating_block' => 1,
11351 
              'period' => 1,
11352 
              'type' => 'logic',
11353 
              'valid_bit_used' => 0,
11354 
            },
11355 
            'direction' => 'in',
11356 
            'hdlType' => 'std_logic',
11357 
            'width' => 1,
11358 
          },
11359 
          'data_in' => {
11360 
            'attributes' => {
11361 
              'bin_pt' => 0,
11362 
              'is_floating_block' => 1,
11363 
              'must_be_hdl_vector' => 1,
11364 
              'period' => 1.0,
11365 
              'port_id' => '0',
11366 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11367 
              'type' => 'UFix_32_0',
11368 
            },
11369 
            'direction' => 'in',
11370 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11371 
            'width' => 32,
11372 
          },
11373 
          'dout' => {
11374 
            'attributes' => {
11375 
              'bin_pt' => 0,
11376 
              'is_floating_block' => 1,
11377 
              'must_be_hdl_vector' => 1,
11378 
              'period' => 1.0,
11379 
              'port_id' => '0',
11380 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11381 
              'type' => 'UFix_32_0',
11382 
            },
11383 
            'direction' => 'out',
11384 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11385 
            'width' => 32,
11386 
          },
11387 
          'en' => {
11388 
            'attributes' => {
11389 
              'bin_pt' => 0,
11390 
              'is_floating_block' => 1,
11391 
              'must_be_hdl_vector' => 1,
11392 
              'period' => 1.0,
11393 
              'port_id' => '1',
11394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11395 
              'type' => 'Bool',
11396 
            },
11397 
            'direction' => 'in',
11398 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11399 
            'width' => 1,
11400 
          },
11401 
        },
11402 
      },
11403 
      'entityName' => 'x_x30',
11404 
    },
11405 
    'to_register8' => {
11406 
      'connections' => {
11407 
        'ce' => 'ce_1_sg',
11408 
        'clk' => 'clk_1_sg',
11409 
        'clr' => [
11410 
          'constant',
11411 
          '\'0\'',
11412 
        ],
11413 
        'data_in' => 'reg03_tv_net_x0',
11414 
        'dout' => 'to_register8_dout_net',
11415 
        'en' => 'constant5_op_net_x18',
11416 
      },
11417 
      'entity' => {
11418 
        'attributes' => {
11419 
          'generics' => [],
11420 
          'is_floating_block' => 1,
11421 
          'mask' => {
11422 
            'Block_Handle' => 2150.00048828125,
11423 
            'Block_handle' => 2150.00048828125,
11424 
            'MDL_Handle' => 2083.00048828125,
11425 
            'MDL_handle' => 2083.00048828125,
11426 
            'arith_type' => 1,
11427 
            'bin_pt' => 14,
11428 
            'block_config' => 'sysgen_blockset:toreg_config',
11429 
            'block_handle' => 2150.00048828125,
11430 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
11431 
            'block_type' => 'toreg',
11432 
            'dbl_ovrd' => 0,
11433 
            'explicit_data_type' => 0,
11434 
            'gui_display_data_type' => 1,
11435 
            'init' => 0.0,
11436 
            'init_bit_vector' => '\'b0',
11437 
            'mdl_handle' => 2083.00048828125,
11438 
            'model_handle' => 2083.00048828125,
11439 
            'n_bits' => 16,
11440 
            'ownership' => 1,
11441 
            'preci_type' => 1,
11442 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
11443 
            'shared_memory_name' => 'register03tv',
11444 
          },
11445 
          'needs_vhdl_wrapper' => 0,
11446 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
11447 
        },
11448 
        'entityName' => 'x_x31',
11449 
        'ports' => {
11450 
          'ce' => {
11451 
            'attributes' => {
11452 
              'domain' => '',
11453 
              'group' => 1,
11454 
              'isCe' => 1,
11455 
              'is_floating_block' => 1,
11456 
              'period' => 1.0,
11457 
              'type' => 'logic',
11458 
            },
11459 
            'direction' => 'in',
11460 
            'hdlType' => 'std_logic',
11461 
            'width' => 1,
11462 
          },
11463 
          'clk' => {
11464 
            'attributes' => {
11465 
              'domain' => '',
11466 
              'group' => 1,
11467 
              'isClk' => 1,
11468 
              'is_floating_block' => 1,
11469 
              'period' => 1.0,
11470 
              'type' => 'logic',
11471 
            },
11472 
            'direction' => 'in',
11473 
            'hdlType' => 'std_logic',
11474 
            'width' => 1,
11475 
          },
11476 
          'clr' => {
11477 
            'attributes' => {
11478 
              'domain' => '',
11479 
              'group' => 1,
11480 
              'isClr' => 1,
11481 
              'is_floating_block' => 1,
11482 
              'period' => 1,
11483 
              'type' => 'logic',
11484 
              'valid_bit_used' => 0,
11485 
            },
11486 
            'direction' => 'in',
11487 
            'hdlType' => 'std_logic',
11488 
            'width' => 1,
11489 
          },
11490 
          'data_in' => {
11491 
            'attributes' => {
11492 
              'bin_pt' => 0,
11493 
              'is_floating_block' => 1,
11494 
              'must_be_hdl_vector' => 1,
11495 
              'period' => 1.0,
11496 
              'port_id' => '0',
11497 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11498 
              'type' => 'Bool',
11499 
            },
11500 
            'direction' => 'in',
11501 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11502 
            'width' => 1,
11503 
          },
11504 
          'dout' => {
11505 
            'attributes' => {
11506 
              'bin_pt' => 0,
11507 
              'is_floating_block' => 1,
11508 
              'must_be_hdl_vector' => 1,
11509 
              'period' => 1.0,
11510 
              'port_id' => '0',
11511 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11512 
              'type' => 'Bool',
11513 
            },
11514 
            'direction' => 'out',
11515 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11516 
            'width' => 1,
11517 
          },
11518 
          'en' => {
11519 
            'attributes' => {
11520 
              'bin_pt' => 0,
11521 
              'is_floating_block' => 1,
11522 
              'must_be_hdl_vector' => 1,
11523 
              'period' => 1.0,
11524 
              'port_id' => '1',
11525 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11526 
              'type' => 'Bool',
11527 
            },
11528 
            'direction' => 'in',
11529 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11530 
            'width' => 1,
11531 
          },
11532 
        },
11533 
      },
11534 
      'entityName' => 'x_x31',
11535 
    },
11536 
    'to_register9' => {
11537 
      'connections' => {
11538 
        'ce' => 'ce_1_sg',
11539 
        'clk' => 'clk_1_sg',
11540 
        'clr' => [
11541 
          'constant',
11542 
          '\'0\'',
11543 
        ],
11544 
        'data_in' => 'reg03_td_net_x0',
11545 
        'dout' => 'to_register9_dout_net',
11546 
        'en' => 'constant5_op_net_x19',
11547 
      },
11548 
      'entity' => {
11549 
        'attributes' => {
11550 
          'generics' => [],
11551 
          'is_floating_block' => 1,
11552 
          'mask' => {
11553 
            'Block_Handle' => 2151.00048828125,
11554 
            'Block_handle' => 2151.00048828125,
11555 
            'MDL_Handle' => 2083.00048828125,
11556 
            'MDL_handle' => 2083.00048828125,
11557 
            'arith_type' => 1,
11558 
            'bin_pt' => 14,
11559 
            'block_config' => 'sysgen_blockset:toreg_config',
11560 
            'block_handle' => 2151.00048828125,
11561 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
11562 
            'block_type' => 'toreg',
11563 
            'dbl_ovrd' => 0,
11564 
            'explicit_data_type' => 0,
11565 
            'gui_display_data_type' => 1,
11566 
            'init' => 0.0,
11567 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
11568 
            'mdl_handle' => 2083.00048828125,
11569 
            'model_handle' => 2083.00048828125,
11570 
            'n_bits' => 16,
11571 
            'ownership' => 1,
11572 
            'preci_type' => 1,
11573 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
11574 
            'shared_memory_name' => 'register03td',
11575 
          },
11576 
          'needs_vhdl_wrapper' => 0,
11577 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
11578 
        },
11579 
        'entityName' => 'x_x32',
11580 
        'ports' => {
11581 
          'ce' => {
11582 
            'attributes' => {
11583 
              'domain' => '',
11584 
              'group' => 1,
11585 
              'isCe' => 1,
11586 
              'is_floating_block' => 1,
11587 
              'period' => 1.0,
11588 
              'type' => 'logic',
11589 
            },
11590 
            'direction' => 'in',
11591 
            'hdlType' => 'std_logic',
11592 
            'width' => 1,
11593 
          },
11594 
          'clk' => {
11595 
            'attributes' => {
11596 
              'domain' => '',
11597 
              'group' => 1,
11598 
              'isClk' => 1,
11599 
              'is_floating_block' => 1,
11600 
              'period' => 1.0,
11601 
              'type' => 'logic',
11602 
            },
11603 
            'direction' => 'in',
11604 
            'hdlType' => 'std_logic',
11605 
            'width' => 1,
11606 
          },
11607 
          'clr' => {
11608 
            'attributes' => {
11609 
              'domain' => '',
11610 
              'group' => 1,
11611 
              'isClr' => 1,
11612 
              'is_floating_block' => 1,
11613 
              'period' => 1,
11614 
              'type' => 'logic',
11615 
              'valid_bit_used' => 0,
11616 
            },
11617 
            'direction' => 'in',
11618 
            'hdlType' => 'std_logic',
11619 
            'width' => 1,
11620 
          },
11621 
          'data_in' => {
11622 
            'attributes' => {
11623 
              'bin_pt' => 0,
11624 
              'is_floating_block' => 1,
11625 
              'must_be_hdl_vector' => 1,
11626 
              'period' => 1.0,
11627 
              'port_id' => '0',
11628 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11629 
              'type' => 'UFix_32_0',
11630 
            },
11631 
            'direction' => 'in',
11632 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11633 
            'width' => 32,
11634 
          },
11635 
          'dout' => {
11636 
            'attributes' => {
11637 
              'bin_pt' => 0,
11638 
              'is_floating_block' => 1,
11639 
              'must_be_hdl_vector' => 1,
11640 
              'period' => 1.0,
11641 
              'port_id' => '0',
11642 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11643 
              'type' => 'UFix_32_0',
11644 
            },
11645 
            'direction' => 'out',
11646 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11647 
            'width' => 32,
11648 
          },
11649 
          'en' => {
11650 
            'attributes' => {
11651 
              'bin_pt' => 0,
11652 
              'is_floating_block' => 1,
11653 
              'must_be_hdl_vector' => 1,
11654 
              'period' => 1.0,
11655 
              'port_id' => '1',
11656 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11657 
              'type' => 'Bool',
11658 
            },
11659 
            'direction' => 'in',
11660 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11661 
            'width' => 1,
11662 
          },
11663 
        },
11664 
      },
11665 
      'entityName' => 'x_x32',
11666 
    },
11667 
  },
11668 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.