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barabba |
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2012 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file cntr_11_0_341fbb8cfa0e669e.vhd when simulating
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-- the core, cntr_11_0_341fbb8cfa0e669e. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY cntr_11_0_341fbb8cfa0e669e IS
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sinit : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END cntr_11_0_341fbb8cfa0e669e;
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ARCHITECTURE cntr_11_0_341fbb8cfa0e669e_a OF cntr_11_0_341fbb8cfa0e669e IS
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-- synthesis translate_off
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COMPONENT wrapped_cntr_11_0_341fbb8cfa0e669e
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sinit : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END COMPONENT;
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62 |
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-- Configuration specification
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FOR ALL : wrapped_cntr_11_0_341fbb8cfa0e669e USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
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GENERIC MAP (
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c_ainit_val => "0",
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c_ce_overrides_sync => 0,
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c_count_by => "1",
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c_count_mode => 0,
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c_count_to => "1",
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c_fb_latency => 0,
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c_has_ce => 1,
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c_has_load => 0,
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c_has_sclr => 0,
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c_has_sinit => 1,
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c_has_sset => 0,
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c_has_thresh0 => 0,
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c_implementation => 0,
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c_latency => 1,
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c_load_low => 0,
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c_restrict_count => 0,
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c_sclr_overrides_sset => 1,
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c_sinit_val => "0",
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c_thresh0_value => "1",
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c_verbosity => 0,
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c_width => 12,
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c_xdevicefamily => "virtex6"
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);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_cntr_11_0_341fbb8cfa0e669e
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PORT MAP (
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clk => clk,
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ce => ce,
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sinit => sinit,
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q => q
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);
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-- synthesis translate_on
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END cntr_11_0_341fbb8cfa0e669e_a;
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-------------------------------------------------------------------------------
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-- Copyright (c) 2012 Xilinx, Inc.
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-- All Rights Reserved
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 13.3
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-- \ \ Application: XILINX CORE Generator
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-- / / Filename : icon_1_06_a_87e2f476e984e565.vhd
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-- /___/ /\ Timestamp : Tue Feb 07 11:26:21 ora solare Europa occidentale 2012
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-- \ \ / \
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-- \___\/\___\
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--
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-- Design Name: VHDL Synthesis Wrapper
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-------------------------------------------------------------------------------
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-- This wrapper is used to integrate with Project Navigator and PlanAhead
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY icon_1_06_a_87e2f476e984e565 IS
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port (
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CONTROL0: inout std_logic_vector(35 downto 0));
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END icon_1_06_a_87e2f476e984e565;
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ARCHITECTURE icon_1_06_a_87e2f476e984e565_a OF icon_1_06_a_87e2f476e984e565 IS
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BEGIN
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END icon_1_06_a_87e2f476e984e565_a;
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-------------------------------------------------------------------------------
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-- Copyright (c) 2012 Xilinx, Inc.
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-- All Rights Reserved
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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137 |
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 13.3
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139 |
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-- \ \ Application: XILINX CORE Generator
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-- / / Filename : ila_1_05_a_b6735eb4b876dee5.vhd
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-- /___/ /\ Timestamp : Mon Mar 26 13:34:48 ora legale Europa occidentale 2012
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-- \ \ / \
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-- \___\/\___\
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--
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-- Design Name: VHDL Synthesis Wrapper
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-------------------------------------------------------------------------------
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147 |
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-- This wrapper is used to integrate with Project Navigator and PlanAhead
|
148 |
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|
149 |
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LIBRARY ieee;
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150 |
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USE ieee.std_logic_1164.ALL;
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151 |
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ENTITY ila_1_05_a_b6735eb4b876dee5 IS
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port (
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CONTROL: inout std_logic_vector(35 downto 0);
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CLK: in std_logic;
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155 |
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TRIG0: in std_logic_vector(11 downto 0);
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156 |
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TRIG1: in std_logic_vector(63 downto 0);
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157 |
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TRIG2: in std_logic_vector(0 to 0);
|
158 |
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TRIG3: in std_logic_vector(0 to 0);
|
159 |
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TRIG4: in std_logic_vector(0 to 0);
|
160 |
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TRIG5: in std_logic_vector(71 downto 0);
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161 |
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TRIG6: in std_logic_vector(0 to 0);
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162 |
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TRIG7: in std_logic_vector(14 downto 0);
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163 |
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TRIG8: in std_logic_vector(0 to 0);
|
164 |
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TRIG9: in std_logic_vector(0 to 0);
|
165 |
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TRIG10: in std_logic_vector(14 downto 0));
|
166 |
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END ila_1_05_a_b6735eb4b876dee5;
|
167 |
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|
168 |
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ARCHITECTURE ila_1_05_a_b6735eb4b876dee5_a OF ila_1_05_a_b6735eb4b876dee5 IS
|
169 |
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BEGIN
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END ila_1_05_a_b6735eb4b876dee5_a;
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-------------------------------------------------------------------
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174 |
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-- System Generator version 13.2 VHDL source file.
|
175 |
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--
|
176 |
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-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
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177 |
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-- text/file contains proprietary, confidential information of Xilinx,
|
178 |
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-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
179 |
|
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-- copied and/or disclosed only pursuant to the terms of a valid license
|
180 |
|
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-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
181 |
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-- this text/file solely for design, simulation, implementation and
|
182 |
|
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-- creation of design files limited to Xilinx devices or technologies.
|
183 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
184 |
|
|
-- and immediately terminates your license unless covered by a separate
|
185 |
|
|
-- agreement.
|
186 |
|
|
--
|
187 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
188 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
189 |
|
|
-- providing this design, code, or information as one possible
|
190 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
191 |
|
|
-- making no representation that this implementation is free from any
|
192 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
193 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
194 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
195 |
|
|
-- implementation, including but not limited to warranties of
|
196 |
|
|
-- merchantability or fitness for a particular purpose.
|
197 |
|
|
--
|
198 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
199 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
200 |
|
|
--
|
201 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
202 |
|
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-- sole risk and will be unsupported.
|
203 |
|
|
--
|
204 |
|
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-- This copyright and support notice must be retained as part of this
|
205 |
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-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
206 |
|
|
-- reserved.
|
207 |
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-------------------------------------------------------------------
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208 |
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library IEEE;
|
209 |
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use IEEE.std_logic_1164.all;
|
210 |
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use IEEE.numeric_std.all;
|
211 |
|
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package conv_pkg is
|
212 |
|
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constant simulating : boolean := false
|
213 |
|
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-- synopsys translate_off
|
214 |
|
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or true
|
215 |
|
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-- synopsys translate_on
|
216 |
|
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;
|
217 |
|
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constant xlUnsigned : integer := 1;
|
218 |
|
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constant xlSigned : integer := 2;
|
219 |
|
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constant xlFloat : integer := 3;
|
220 |
|
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constant xlWrap : integer := 1;
|
221 |
|
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constant xlSaturate : integer := 2;
|
222 |
|
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constant xlTruncate : integer := 1;
|
223 |
|
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constant xlRound : integer := 2;
|
224 |
|
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constant xlRoundBanker : integer := 3;
|
225 |
|
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constant xlAddMode : integer := 1;
|
226 |
|
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constant xlSubMode : integer := 2;
|
227 |
|
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attribute black_box : boolean;
|
228 |
|
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attribute syn_black_box : boolean;
|
229 |
|
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attribute fpga_dont_touch: string;
|
230 |
|
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attribute box_type : string;
|
231 |
|
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attribute keep : string;
|
232 |
|
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attribute syn_keep : boolean;
|
233 |
|
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function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
|
234 |
|
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function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
|
235 |
|
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function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
|
236 |
|
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function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
|
237 |
|
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function unsigned_to_signed(inp : unsigned) return signed;
|
238 |
|
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function signed_to_unsigned(inp : signed) return unsigned;
|
239 |
|
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function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
|
240 |
|
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function all_same(inp: std_logic_vector) return boolean;
|
241 |
|
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function all_zeros(inp: std_logic_vector) return boolean;
|
242 |
|
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function is_point_five(inp: std_logic_vector) return boolean;
|
243 |
|
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function all_ones(inp: std_logic_vector) return boolean;
|
244 |
|
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function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
|
245 |
|
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old_arith, new_width, new_bin_pt, new_arith,
|
246 |
|
|
quantization, overflow : INTEGER)
|
247 |
|
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return std_logic_vector;
|
248 |
|
|
function cast (inp : std_logic_vector; old_bin_pt,
|
249 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
250 |
|
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return std_logic_vector;
|
251 |
|
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function shift_division_result(quotient, fraction: std_logic_vector;
|
252 |
|
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fraction_width, shift_value, shift_dir: INTEGER)
|
253 |
|
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return std_logic_vector;
|
254 |
|
|
function shift_op (inp: std_logic_vector;
|
255 |
|
|
result_width, shift_value, shift_dir: INTEGER)
|
256 |
|
|
return std_logic_vector;
|
257 |
|
|
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
|
258 |
|
|
return std_logic_vector;
|
259 |
|
|
function s2u_slice (inp : signed; upper, lower : INTEGER)
|
260 |
|
|
return unsigned;
|
261 |
|
|
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
|
262 |
|
|
return unsigned;
|
263 |
|
|
function s2s_cast (inp : signed; old_bin_pt,
|
264 |
|
|
new_width, new_bin_pt : INTEGER)
|
265 |
|
|
return signed;
|
266 |
|
|
function u2s_cast (inp : unsigned; old_bin_pt,
|
267 |
|
|
new_width, new_bin_pt : INTEGER)
|
268 |
|
|
return signed;
|
269 |
|
|
function s2u_cast (inp : signed; old_bin_pt,
|
270 |
|
|
new_width, new_bin_pt : INTEGER)
|
271 |
|
|
return unsigned;
|
272 |
|
|
function u2u_cast (inp : unsigned; old_bin_pt,
|
273 |
|
|
new_width, new_bin_pt : INTEGER)
|
274 |
|
|
return unsigned;
|
275 |
|
|
function u2v_cast (inp : unsigned; old_bin_pt,
|
276 |
|
|
new_width, new_bin_pt : INTEGER)
|
277 |
|
|
return std_logic_vector;
|
278 |
|
|
function s2v_cast (inp : signed; old_bin_pt,
|
279 |
|
|
new_width, new_bin_pt : INTEGER)
|
280 |
|
|
return std_logic_vector;
|
281 |
|
|
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
|
282 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
283 |
|
|
return std_logic_vector;
|
284 |
|
|
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
|
285 |
|
|
old_arith, new_width, new_bin_pt,
|
286 |
|
|
new_arith : INTEGER) return std_logic_vector;
|
287 |
|
|
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
|
288 |
|
|
old_arith, new_width, new_bin_pt,
|
289 |
|
|
new_arith : INTEGER) return std_logic_vector;
|
290 |
|
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function max_signed(width : INTEGER) return std_logic_vector;
|
291 |
|
|
function min_signed(width : INTEGER) return std_logic_vector;
|
292 |
|
|
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
293 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
294 |
|
|
: INTEGER) return std_logic_vector;
|
295 |
|
|
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
296 |
|
|
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
|
297 |
|
|
return std_logic_vector;
|
298 |
|
|
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
|
299 |
|
|
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
|
300 |
|
|
return INTEGER;
|
301 |
|
|
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
|
302 |
|
|
return std_logic_vector;
|
303 |
|
|
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
|
304 |
|
|
return std_logic_vector;
|
305 |
|
|
function zero_ext(inp : std_logic; new_width : INTEGER)
|
306 |
|
|
return std_logic_vector;
|
307 |
|
|
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
|
308 |
|
|
return std_logic_vector;
|
309 |
|
|
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
|
310 |
|
|
new_width: INTEGER)
|
311 |
|
|
return std_logic_vector;
|
312 |
|
|
function pad_LSB(inp : std_logic_vector; new_width: integer)
|
313 |
|
|
return std_logic_vector;
|
314 |
|
|
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
|
315 |
|
|
return std_logic_vector;
|
316 |
|
|
function max(L, R: INTEGER) return INTEGER;
|
317 |
|
|
function min(L, R: INTEGER) return INTEGER;
|
318 |
|
|
function "="(left,right: STRING) return boolean;
|
319 |
|
|
function boolean_to_signed (inp : boolean; width: integer)
|
320 |
|
|
return signed;
|
321 |
|
|
function boolean_to_unsigned (inp : boolean; width: integer)
|
322 |
|
|
return unsigned;
|
323 |
|
|
function boolean_to_vector (inp : boolean)
|
324 |
|
|
return std_logic_vector;
|
325 |
|
|
function std_logic_to_vector (inp : std_logic)
|
326 |
|
|
return std_logic_vector;
|
327 |
|
|
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
|
328 |
|
|
return std_logic_vector;
|
329 |
|
|
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
|
330 |
|
|
return integer;
|
331 |
|
|
function std_logic_to_integer(constant inp : std_logic := '0')
|
332 |
|
|
return integer;
|
333 |
|
|
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
|
334 |
|
|
return std_logic_vector;
|
335 |
|
|
function bin_string_to_std_logic_vector (inp : string)
|
336 |
|
|
return std_logic_vector;
|
337 |
|
|
function hex_string_to_std_logic_vector (inp : string; width : integer)
|
338 |
|
|
return std_logic_vector;
|
339 |
|
|
function makeZeroBinStr (width : integer) return STRING;
|
340 |
|
|
function and_reduce(inp: std_logic_vector) return std_logic;
|
341 |
|
|
-- synopsys translate_off
|
342 |
|
|
function is_binary_string_invalid (inp : string)
|
343 |
|
|
return boolean;
|
344 |
|
|
function is_binary_string_undefined (inp : string)
|
345 |
|
|
return boolean;
|
346 |
|
|
function is_XorU(inp : std_logic_vector)
|
347 |
|
|
return boolean;
|
348 |
|
|
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
|
349 |
|
|
return real;
|
350 |
|
|
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
|
351 |
|
|
return real;
|
352 |
|
|
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
|
353 |
|
|
return std_logic_vector;
|
354 |
|
|
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
|
355 |
|
|
return std_logic_vector;
|
356 |
|
|
constant display_precision : integer := 20;
|
357 |
|
|
function real_to_string (inp : real) return string;
|
358 |
|
|
function valid_bin_string(inp : string) return boolean;
|
359 |
|
|
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
|
360 |
|
|
function std_logic_to_bin_string(inp : std_logic) return string;
|
361 |
|
|
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
|
362 |
|
|
return string;
|
363 |
|
|
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
|
364 |
|
|
return string;
|
365 |
|
|
type stdlogic_to_char_t is array(std_logic) of character;
|
366 |
|
|
constant to_char : stdlogic_to_char_t := (
|
367 |
|
|
'U' => 'U',
|
368 |
|
|
'X' => 'X',
|
369 |
|
|
'0' => '0',
|
370 |
|
|
'1' => '1',
|
371 |
|
|
'Z' => 'Z',
|
372 |
|
|
'W' => 'W',
|
373 |
|
|
'L' => 'L',
|
374 |
|
|
'H' => 'H',
|
375 |
|
|
'-' => '-');
|
376 |
|
|
-- synopsys translate_on
|
377 |
|
|
end conv_pkg;
|
378 |
|
|
package body conv_pkg is
|
379 |
|
|
function std_logic_vector_to_unsigned(inp : std_logic_vector)
|
380 |
|
|
return unsigned
|
381 |
|
|
is
|
382 |
|
|
begin
|
383 |
|
|
return unsigned (inp);
|
384 |
|
|
end;
|
385 |
|
|
function unsigned_to_std_logic_vector(inp : unsigned)
|
386 |
|
|
return std_logic_vector
|
387 |
|
|
is
|
388 |
|
|
begin
|
389 |
|
|
return std_logic_vector(inp);
|
390 |
|
|
end;
|
391 |
|
|
function std_logic_vector_to_signed(inp : std_logic_vector)
|
392 |
|
|
return signed
|
393 |
|
|
is
|
394 |
|
|
begin
|
395 |
|
|
return signed (inp);
|
396 |
|
|
end;
|
397 |
|
|
function signed_to_std_logic_vector(inp : signed)
|
398 |
|
|
return std_logic_vector
|
399 |
|
|
is
|
400 |
|
|
begin
|
401 |
|
|
return std_logic_vector(inp);
|
402 |
|
|
end;
|
403 |
|
|
function unsigned_to_signed (inp : unsigned)
|
404 |
|
|
return signed
|
405 |
|
|
is
|
406 |
|
|
begin
|
407 |
|
|
return signed(std_logic_vector(inp));
|
408 |
|
|
end;
|
409 |
|
|
function signed_to_unsigned (inp : signed)
|
410 |
|
|
return unsigned
|
411 |
|
|
is
|
412 |
|
|
begin
|
413 |
|
|
return unsigned(std_logic_vector(inp));
|
414 |
|
|
end;
|
415 |
|
|
function pos(inp : std_logic_vector; arith : INTEGER)
|
416 |
|
|
return boolean
|
417 |
|
|
is
|
418 |
|
|
constant width : integer := inp'length;
|
419 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
420 |
|
|
begin
|
421 |
|
|
vec := inp;
|
422 |
|
|
if arith = xlUnsigned then
|
423 |
|
|
return true;
|
424 |
|
|
else
|
425 |
|
|
if vec(width-1) = '0' then
|
426 |
|
|
return true;
|
427 |
|
|
else
|
428 |
|
|
return false;
|
429 |
|
|
end if;
|
430 |
|
|
end if;
|
431 |
|
|
return true;
|
432 |
|
|
end;
|
433 |
|
|
function max_signed(width : INTEGER)
|
434 |
|
|
return std_logic_vector
|
435 |
|
|
is
|
436 |
|
|
variable ones : std_logic_vector(width-2 downto 0);
|
437 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
438 |
|
|
begin
|
439 |
|
|
ones := (others => '1');
|
440 |
|
|
result(width-1) := '0';
|
441 |
|
|
result(width-2 downto 0) := ones;
|
442 |
|
|
return result;
|
443 |
|
|
end;
|
444 |
|
|
function min_signed(width : INTEGER)
|
445 |
|
|
return std_logic_vector
|
446 |
|
|
is
|
447 |
|
|
variable zeros : std_logic_vector(width-2 downto 0);
|
448 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
449 |
|
|
begin
|
450 |
|
|
zeros := (others => '0');
|
451 |
|
|
result(width-1) := '1';
|
452 |
|
|
result(width-2 downto 0) := zeros;
|
453 |
|
|
return result;
|
454 |
|
|
end;
|
455 |
|
|
function and_reduce(inp: std_logic_vector) return std_logic
|
456 |
|
|
is
|
457 |
|
|
variable result: std_logic;
|
458 |
|
|
constant width : integer := inp'length;
|
459 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
460 |
|
|
begin
|
461 |
|
|
vec := inp;
|
462 |
|
|
result := vec(0);
|
463 |
|
|
if width > 1 then
|
464 |
|
|
for i in 1 to width-1 loop
|
465 |
|
|
result := result and vec(i);
|
466 |
|
|
end loop;
|
467 |
|
|
end if;
|
468 |
|
|
return result;
|
469 |
|
|
end;
|
470 |
|
|
function all_same(inp: std_logic_vector) return boolean
|
471 |
|
|
is
|
472 |
|
|
variable result: boolean;
|
473 |
|
|
constant width : integer := inp'length;
|
474 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
475 |
|
|
begin
|
476 |
|
|
vec := inp;
|
477 |
|
|
result := true;
|
478 |
|
|
if width > 0 then
|
479 |
|
|
for i in 1 to width-1 loop
|
480 |
|
|
if vec(i) /= vec(0) then
|
481 |
|
|
result := false;
|
482 |
|
|
end if;
|
483 |
|
|
end loop;
|
484 |
|
|
end if;
|
485 |
|
|
return result;
|
486 |
|
|
end;
|
487 |
|
|
function all_zeros(inp: std_logic_vector)
|
488 |
|
|
return boolean
|
489 |
|
|
is
|
490 |
|
|
constant width : integer := inp'length;
|
491 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
492 |
|
|
variable zero : std_logic_vector(width-1 downto 0);
|
493 |
|
|
variable result : boolean;
|
494 |
|
|
begin
|
495 |
|
|
zero := (others => '0');
|
496 |
|
|
vec := inp;
|
497 |
|
|
-- synopsys translate_off
|
498 |
|
|
if (is_XorU(vec)) then
|
499 |
|
|
return false;
|
500 |
|
|
end if;
|
501 |
|
|
-- synopsys translate_on
|
502 |
|
|
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
|
503 |
|
|
result := true;
|
504 |
|
|
else
|
505 |
|
|
result := false;
|
506 |
|
|
end if;
|
507 |
|
|
return result;
|
508 |
|
|
end;
|
509 |
|
|
function is_point_five(inp: std_logic_vector)
|
510 |
|
|
return boolean
|
511 |
|
|
is
|
512 |
|
|
constant width : integer := inp'length;
|
513 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
514 |
|
|
variable result : boolean;
|
515 |
|
|
begin
|
516 |
|
|
vec := inp;
|
517 |
|
|
-- synopsys translate_off
|
518 |
|
|
if (is_XorU(vec)) then
|
519 |
|
|
return false;
|
520 |
|
|
end if;
|
521 |
|
|
-- synopsys translate_on
|
522 |
|
|
if (width > 1) then
|
523 |
|
|
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
|
524 |
|
|
result := true;
|
525 |
|
|
else
|
526 |
|
|
result := false;
|
527 |
|
|
end if;
|
528 |
|
|
else
|
529 |
|
|
if (vec(width-1) = '1') then
|
530 |
|
|
result := true;
|
531 |
|
|
else
|
532 |
|
|
result := false;
|
533 |
|
|
end if;
|
534 |
|
|
end if;
|
535 |
|
|
return result;
|
536 |
|
|
end;
|
537 |
|
|
function all_ones(inp: std_logic_vector)
|
538 |
|
|
return boolean
|
539 |
|
|
is
|
540 |
|
|
constant width : integer := inp'length;
|
541 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
542 |
|
|
variable one : std_logic_vector(width-1 downto 0);
|
543 |
|
|
variable result : boolean;
|
544 |
|
|
begin
|
545 |
|
|
one := (others => '1');
|
546 |
|
|
vec := inp;
|
547 |
|
|
-- synopsys translate_off
|
548 |
|
|
if (is_XorU(vec)) then
|
549 |
|
|
return false;
|
550 |
|
|
end if;
|
551 |
|
|
-- synopsys translate_on
|
552 |
|
|
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
|
553 |
|
|
result := true;
|
554 |
|
|
else
|
555 |
|
|
result := false;
|
556 |
|
|
end if;
|
557 |
|
|
return result;
|
558 |
|
|
end;
|
559 |
|
|
function full_precision_num_width(quantization, overflow, old_width,
|
560 |
|
|
old_bin_pt, old_arith,
|
561 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
562 |
|
|
return integer
|
563 |
|
|
is
|
564 |
|
|
variable result : integer;
|
565 |
|
|
begin
|
566 |
|
|
result := old_width + 2;
|
567 |
|
|
return result;
|
568 |
|
|
end;
|
569 |
|
|
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
|
570 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
571 |
|
|
: INTEGER)
|
572 |
|
|
return integer
|
573 |
|
|
is
|
574 |
|
|
variable right_of_dp, left_of_dp, result : integer;
|
575 |
|
|
begin
|
576 |
|
|
right_of_dp := max(new_bin_pt, old_bin_pt);
|
577 |
|
|
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
|
578 |
|
|
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
|
579 |
|
|
return result;
|
580 |
|
|
end;
|
581 |
|
|
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
|
582 |
|
|
old_arith, new_width, new_bin_pt, new_arith,
|
583 |
|
|
quantization, overflow : INTEGER)
|
584 |
|
|
return std_logic_vector
|
585 |
|
|
is
|
586 |
|
|
constant fp_width : integer :=
|
587 |
|
|
full_precision_num_width(quantization, overflow, old_width,
|
588 |
|
|
old_bin_pt, old_arith, new_width,
|
589 |
|
|
new_bin_pt, new_arith);
|
590 |
|
|
constant fp_bin_pt : integer := old_bin_pt;
|
591 |
|
|
constant fp_arith : integer := old_arith;
|
592 |
|
|
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
|
593 |
|
|
constant q_width : integer :=
|
594 |
|
|
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
|
595 |
|
|
old_arith, new_width, new_bin_pt, new_arith);
|
596 |
|
|
constant q_bin_pt : integer := new_bin_pt;
|
597 |
|
|
constant q_arith : integer := old_arith;
|
598 |
|
|
variable quantized_result : std_logic_vector(q_width-1 downto 0);
|
599 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
600 |
|
|
begin
|
601 |
|
|
result := (others => '0');
|
602 |
|
|
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
|
603 |
|
|
fp_arith);
|
604 |
|
|
if (quantization = xlRound) then
|
605 |
|
|
quantized_result := round_towards_inf(full_precision_result,
|
606 |
|
|
fp_width, fp_bin_pt,
|
607 |
|
|
fp_arith, q_width, q_bin_pt,
|
608 |
|
|
q_arith);
|
609 |
|
|
elsif (quantization = xlRoundBanker) then
|
610 |
|
|
quantized_result := round_towards_even(full_precision_result,
|
611 |
|
|
fp_width, fp_bin_pt,
|
612 |
|
|
fp_arith, q_width, q_bin_pt,
|
613 |
|
|
q_arith);
|
614 |
|
|
else
|
615 |
|
|
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
|
616 |
|
|
fp_arith, q_width, q_bin_pt, q_arith);
|
617 |
|
|
end if;
|
618 |
|
|
if (overflow = xlSaturate) then
|
619 |
|
|
result := saturation_arith(quantized_result, q_width, q_bin_pt,
|
620 |
|
|
q_arith, new_width, new_bin_pt, new_arith);
|
621 |
|
|
else
|
622 |
|
|
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
|
623 |
|
|
new_width, new_bin_pt, new_arith);
|
624 |
|
|
end if;
|
625 |
|
|
return result;
|
626 |
|
|
end;
|
627 |
|
|
function cast (inp : std_logic_vector; old_bin_pt, new_width,
|
628 |
|
|
new_bin_pt, new_arith : INTEGER)
|
629 |
|
|
return std_logic_vector
|
630 |
|
|
is
|
631 |
|
|
constant old_width : integer := inp'length;
|
632 |
|
|
constant left_of_dp : integer := (new_width - new_bin_pt)
|
633 |
|
|
- (old_width - old_bin_pt);
|
634 |
|
|
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
|
635 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
636 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
637 |
|
|
variable j : integer;
|
638 |
|
|
begin
|
639 |
|
|
vec := inp;
|
640 |
|
|
for i in new_width-1 downto 0 loop
|
641 |
|
|
j := i - right_of_dp;
|
642 |
|
|
if ( j > old_width-1) then
|
643 |
|
|
if (new_arith = xlUnsigned) then
|
644 |
|
|
result(i) := '0';
|
645 |
|
|
else
|
646 |
|
|
result(i) := vec(old_width-1);
|
647 |
|
|
end if;
|
648 |
|
|
elsif ( j >= 0) then
|
649 |
|
|
result(i) := vec(j);
|
650 |
|
|
else
|
651 |
|
|
result(i) := '0';
|
652 |
|
|
end if;
|
653 |
|
|
end loop;
|
654 |
|
|
return result;
|
655 |
|
|
end;
|
656 |
|
|
function shift_division_result(quotient, fraction: std_logic_vector;
|
657 |
|
|
fraction_width, shift_value, shift_dir: INTEGER)
|
658 |
|
|
return std_logic_vector
|
659 |
|
|
is
|
660 |
|
|
constant q_width : integer := quotient'length;
|
661 |
|
|
constant f_width : integer := fraction'length;
|
662 |
|
|
constant vec_MSB : integer := q_width+f_width-1;
|
663 |
|
|
constant result_MSB : integer := q_width+fraction_width-1;
|
664 |
|
|
constant result_LSB : integer := vec_MSB-result_MSB;
|
665 |
|
|
variable vec : std_logic_vector(vec_MSB downto 0);
|
666 |
|
|
variable result : std_logic_vector(result_MSB downto 0);
|
667 |
|
|
begin
|
668 |
|
|
vec := ( quotient & fraction );
|
669 |
|
|
if shift_dir = 1 then
|
670 |
|
|
for i in vec_MSB downto 0 loop
|
671 |
|
|
if (i < shift_value) then
|
672 |
|
|
vec(i) := '0';
|
673 |
|
|
else
|
674 |
|
|
vec(i) := vec(i-shift_value);
|
675 |
|
|
end if;
|
676 |
|
|
end loop;
|
677 |
|
|
else
|
678 |
|
|
for i in 0 to vec_MSB loop
|
679 |
|
|
if (i > vec_MSB-shift_value) then
|
680 |
|
|
vec(i) := vec(vec_MSB);
|
681 |
|
|
else
|
682 |
|
|
vec(i) := vec(i+shift_value);
|
683 |
|
|
end if;
|
684 |
|
|
end loop;
|
685 |
|
|
end if;
|
686 |
|
|
result := vec(vec_MSB downto result_LSB);
|
687 |
|
|
return result;
|
688 |
|
|
end;
|
689 |
|
|
function shift_op (inp: std_logic_vector;
|
690 |
|
|
result_width, shift_value, shift_dir: INTEGER)
|
691 |
|
|
return std_logic_vector
|
692 |
|
|
is
|
693 |
|
|
constant inp_width : integer := inp'length;
|
694 |
|
|
constant vec_MSB : integer := inp_width-1;
|
695 |
|
|
constant result_MSB : integer := result_width-1;
|
696 |
|
|
constant result_LSB : integer := vec_MSB-result_MSB;
|
697 |
|
|
variable vec : std_logic_vector(vec_MSB downto 0);
|
698 |
|
|
variable result : std_logic_vector(result_MSB downto 0);
|
699 |
|
|
begin
|
700 |
|
|
vec := inp;
|
701 |
|
|
if shift_dir = 1 then
|
702 |
|
|
for i in vec_MSB downto 0 loop
|
703 |
|
|
if (i < shift_value) then
|
704 |
|
|
vec(i) := '0';
|
705 |
|
|
else
|
706 |
|
|
vec(i) := vec(i-shift_value);
|
707 |
|
|
end if;
|
708 |
|
|
end loop;
|
709 |
|
|
else
|
710 |
|
|
for i in 0 to vec_MSB loop
|
711 |
|
|
if (i > vec_MSB-shift_value) then
|
712 |
|
|
vec(i) := vec(vec_MSB);
|
713 |
|
|
else
|
714 |
|
|
vec(i) := vec(i+shift_value);
|
715 |
|
|
end if;
|
716 |
|
|
end loop;
|
717 |
|
|
end if;
|
718 |
|
|
result := vec(vec_MSB downto result_LSB);
|
719 |
|
|
return result;
|
720 |
|
|
end;
|
721 |
|
|
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
|
722 |
|
|
return std_logic_vector
|
723 |
|
|
is
|
724 |
|
|
begin
|
725 |
|
|
return inp(upper downto lower);
|
726 |
|
|
end;
|
727 |
|
|
function s2u_slice (inp : signed; upper, lower : INTEGER)
|
728 |
|
|
return unsigned
|
729 |
|
|
is
|
730 |
|
|
begin
|
731 |
|
|
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
|
732 |
|
|
end;
|
733 |
|
|
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
|
734 |
|
|
return unsigned
|
735 |
|
|
is
|
736 |
|
|
begin
|
737 |
|
|
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
|
738 |
|
|
end;
|
739 |
|
|
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
|
740 |
|
|
return signed
|
741 |
|
|
is
|
742 |
|
|
begin
|
743 |
|
|
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
|
744 |
|
|
end;
|
745 |
|
|
function s2u_cast (inp : signed; old_bin_pt, new_width,
|
746 |
|
|
new_bin_pt : INTEGER)
|
747 |
|
|
return unsigned
|
748 |
|
|
is
|
749 |
|
|
begin
|
750 |
|
|
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
|
751 |
|
|
end;
|
752 |
|
|
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
|
753 |
|
|
new_bin_pt : INTEGER)
|
754 |
|
|
return signed
|
755 |
|
|
is
|
756 |
|
|
begin
|
757 |
|
|
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
|
758 |
|
|
end;
|
759 |
|
|
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
|
760 |
|
|
new_bin_pt : INTEGER)
|
761 |
|
|
return unsigned
|
762 |
|
|
is
|
763 |
|
|
begin
|
764 |
|
|
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
|
765 |
|
|
end;
|
766 |
|
|
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
|
767 |
|
|
new_bin_pt : INTEGER)
|
768 |
|
|
return std_logic_vector
|
769 |
|
|
is
|
770 |
|
|
begin
|
771 |
|
|
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
|
772 |
|
|
end;
|
773 |
|
|
function s2v_cast (inp : signed; old_bin_pt, new_width,
|
774 |
|
|
new_bin_pt : INTEGER)
|
775 |
|
|
return std_logic_vector
|
776 |
|
|
is
|
777 |
|
|
begin
|
778 |
|
|
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
|
779 |
|
|
end;
|
780 |
|
|
function boolean_to_signed (inp : boolean; width : integer)
|
781 |
|
|
return signed
|
782 |
|
|
is
|
783 |
|
|
variable result : signed(width - 1 downto 0);
|
784 |
|
|
begin
|
785 |
|
|
result := (others => '0');
|
786 |
|
|
if inp then
|
787 |
|
|
result(0) := '1';
|
788 |
|
|
else
|
789 |
|
|
result(0) := '0';
|
790 |
|
|
end if;
|
791 |
|
|
return result;
|
792 |
|
|
end;
|
793 |
|
|
function boolean_to_unsigned (inp : boolean; width : integer)
|
794 |
|
|
return unsigned
|
795 |
|
|
is
|
796 |
|
|
variable result : unsigned(width - 1 downto 0);
|
797 |
|
|
begin
|
798 |
|
|
result := (others => '0');
|
799 |
|
|
if inp then
|
800 |
|
|
result(0) := '1';
|
801 |
|
|
else
|
802 |
|
|
result(0) := '0';
|
803 |
|
|
end if;
|
804 |
|
|
return result;
|
805 |
|
|
end;
|
806 |
|
|
function boolean_to_vector (inp : boolean)
|
807 |
|
|
return std_logic_vector
|
808 |
|
|
is
|
809 |
|
|
variable result : std_logic_vector(1 - 1 downto 0);
|
810 |
|
|
begin
|
811 |
|
|
result := (others => '0');
|
812 |
|
|
if inp then
|
813 |
|
|
result(0) := '1';
|
814 |
|
|
else
|
815 |
|
|
result(0) := '0';
|
816 |
|
|
end if;
|
817 |
|
|
return result;
|
818 |
|
|
end;
|
819 |
|
|
function std_logic_to_vector (inp : std_logic)
|
820 |
|
|
return std_logic_vector
|
821 |
|
|
is
|
822 |
|
|
variable result : std_logic_vector(1 - 1 downto 0);
|
823 |
|
|
begin
|
824 |
|
|
result(0) := inp;
|
825 |
|
|
return result;
|
826 |
|
|
end;
|
827 |
|
|
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
|
828 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
829 |
|
|
return std_logic_vector
|
830 |
|
|
is
|
831 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
832 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
833 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
834 |
|
|
begin
|
835 |
|
|
vec := inp;
|
836 |
|
|
if right_of_dp >= 0 then
|
837 |
|
|
if new_arith = xlUnsigned then
|
838 |
|
|
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
|
839 |
|
|
else
|
840 |
|
|
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
|
841 |
|
|
end if;
|
842 |
|
|
else
|
843 |
|
|
if new_arith = xlUnsigned then
|
844 |
|
|
result := zero_ext(pad_LSB(vec, old_width +
|
845 |
|
|
abs(right_of_dp)), new_width);
|
846 |
|
|
else
|
847 |
|
|
result := sign_ext(pad_LSB(vec, old_width +
|
848 |
|
|
abs(right_of_dp)), new_width);
|
849 |
|
|
end if;
|
850 |
|
|
end if;
|
851 |
|
|
return result;
|
852 |
|
|
end;
|
853 |
|
|
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
|
854 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
855 |
|
|
: INTEGER)
|
856 |
|
|
return std_logic_vector
|
857 |
|
|
is
|
858 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
859 |
|
|
constant expected_new_width : integer := old_width - right_of_dp + 1;
|
860 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
861 |
|
|
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
|
862 |
|
|
variable truncated_val : std_logic_vector(new_width-1 downto 0);
|
863 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
864 |
|
|
begin
|
865 |
|
|
vec := inp;
|
866 |
|
|
if right_of_dp >= 0 then
|
867 |
|
|
if new_arith = xlUnsigned then
|
868 |
|
|
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
|
869 |
|
|
new_width);
|
870 |
|
|
else
|
871 |
|
|
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
|
872 |
|
|
new_width);
|
873 |
|
|
end if;
|
874 |
|
|
else
|
875 |
|
|
if new_arith = xlUnsigned then
|
876 |
|
|
truncated_val := zero_ext(pad_LSB(vec, old_width +
|
877 |
|
|
abs(right_of_dp)), new_width);
|
878 |
|
|
else
|
879 |
|
|
truncated_val := sign_ext(pad_LSB(vec, old_width +
|
880 |
|
|
abs(right_of_dp)), new_width);
|
881 |
|
|
end if;
|
882 |
|
|
end if;
|
883 |
|
|
one_or_zero := (others => '0');
|
884 |
|
|
if (new_arith = xlSigned) then
|
885 |
|
|
if (vec(old_width-1) = '0') then
|
886 |
|
|
one_or_zero(0) := '1';
|
887 |
|
|
end if;
|
888 |
|
|
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
|
889 |
|
|
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
|
890 |
|
|
one_or_zero(0) := '1';
|
891 |
|
|
end if;
|
892 |
|
|
end if;
|
893 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
894 |
|
|
if vec(right_of_dp-1) = '0' then
|
895 |
|
|
one_or_zero(0) := '0';
|
896 |
|
|
end if;
|
897 |
|
|
else
|
898 |
|
|
one_or_zero(0) := '0';
|
899 |
|
|
end if;
|
900 |
|
|
else
|
901 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
902 |
|
|
one_or_zero(0) := vec(right_of_dp-1);
|
903 |
|
|
end if;
|
904 |
|
|
end if;
|
905 |
|
|
if new_arith = xlSigned then
|
906 |
|
|
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
|
907 |
|
|
std_logic_vector_to_signed(one_or_zero));
|
908 |
|
|
else
|
909 |
|
|
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
|
910 |
|
|
std_logic_vector_to_unsigned(one_or_zero));
|
911 |
|
|
end if;
|
912 |
|
|
return result;
|
913 |
|
|
end;
|
914 |
|
|
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
|
915 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
916 |
|
|
: INTEGER)
|
917 |
|
|
return std_logic_vector
|
918 |
|
|
is
|
919 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
920 |
|
|
constant expected_new_width : integer := old_width - right_of_dp + 1;
|
921 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
922 |
|
|
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
|
923 |
|
|
variable truncated_val : std_logic_vector(new_width-1 downto 0);
|
924 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
925 |
|
|
begin
|
926 |
|
|
vec := inp;
|
927 |
|
|
if right_of_dp >= 0 then
|
928 |
|
|
if new_arith = xlUnsigned then
|
929 |
|
|
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
|
930 |
|
|
new_width);
|
931 |
|
|
else
|
932 |
|
|
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
|
933 |
|
|
new_width);
|
934 |
|
|
end if;
|
935 |
|
|
else
|
936 |
|
|
if new_arith = xlUnsigned then
|
937 |
|
|
truncated_val := zero_ext(pad_LSB(vec, old_width +
|
938 |
|
|
abs(right_of_dp)), new_width);
|
939 |
|
|
else
|
940 |
|
|
truncated_val := sign_ext(pad_LSB(vec, old_width +
|
941 |
|
|
abs(right_of_dp)), new_width);
|
942 |
|
|
end if;
|
943 |
|
|
end if;
|
944 |
|
|
one_or_zero := (others => '0');
|
945 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
946 |
|
|
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
|
947 |
|
|
one_or_zero(0) := vec(right_of_dp-1);
|
948 |
|
|
else
|
949 |
|
|
one_or_zero(0) := vec(right_of_dp);
|
950 |
|
|
end if;
|
951 |
|
|
end if;
|
952 |
|
|
if new_arith = xlSigned then
|
953 |
|
|
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
|
954 |
|
|
std_logic_vector_to_signed(one_or_zero));
|
955 |
|
|
else
|
956 |
|
|
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
|
957 |
|
|
std_logic_vector_to_unsigned(one_or_zero));
|
958 |
|
|
end if;
|
959 |
|
|
return result;
|
960 |
|
|
end;
|
961 |
|
|
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
962 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
963 |
|
|
: INTEGER)
|
964 |
|
|
return std_logic_vector
|
965 |
|
|
is
|
966 |
|
|
constant left_of_dp : integer := (old_width - old_bin_pt) -
|
967 |
|
|
(new_width - new_bin_pt);
|
968 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
969 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
970 |
|
|
variable overflow : boolean;
|
971 |
|
|
begin
|
972 |
|
|
vec := inp;
|
973 |
|
|
overflow := true;
|
974 |
|
|
result := (others => '0');
|
975 |
|
|
if (new_width >= old_width) then
|
976 |
|
|
overflow := false;
|
977 |
|
|
end if;
|
978 |
|
|
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
|
979 |
|
|
if all_same(vec(old_width-1 downto new_width-1)) then
|
980 |
|
|
overflow := false;
|
981 |
|
|
end if;
|
982 |
|
|
end if;
|
983 |
|
|
if (old_arith = xlSigned and new_arith = xlUnsigned) then
|
984 |
|
|
if (old_width > new_width) then
|
985 |
|
|
if all_zeros(vec(old_width-1 downto new_width)) then
|
986 |
|
|
overflow := false;
|
987 |
|
|
end if;
|
988 |
|
|
else
|
989 |
|
|
if (old_width = new_width) then
|
990 |
|
|
if (vec(new_width-1) = '0') then
|
991 |
|
|
overflow := false;
|
992 |
|
|
end if;
|
993 |
|
|
end if;
|
994 |
|
|
end if;
|
995 |
|
|
end if;
|
996 |
|
|
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
|
997 |
|
|
if (old_width > new_width) then
|
998 |
|
|
if all_zeros(vec(old_width-1 downto new_width)) then
|
999 |
|
|
overflow := false;
|
1000 |
|
|
end if;
|
1001 |
|
|
else
|
1002 |
|
|
if (old_width = new_width) then
|
1003 |
|
|
overflow := false;
|
1004 |
|
|
end if;
|
1005 |
|
|
end if;
|
1006 |
|
|
end if;
|
1007 |
|
|
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
|
1008 |
|
|
if all_same(vec(old_width-1 downto new_width-1)) then
|
1009 |
|
|
overflow := false;
|
1010 |
|
|
end if;
|
1011 |
|
|
end if;
|
1012 |
|
|
if overflow then
|
1013 |
|
|
if new_arith = xlSigned then
|
1014 |
|
|
if vec(old_width-1) = '0' then
|
1015 |
|
|
result := max_signed(new_width);
|
1016 |
|
|
else
|
1017 |
|
|
result := min_signed(new_width);
|
1018 |
|
|
end if;
|
1019 |
|
|
else
|
1020 |
|
|
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
|
1021 |
|
|
result := (others => '0');
|
1022 |
|
|
else
|
1023 |
|
|
result := (others => '1');
|
1024 |
|
|
end if;
|
1025 |
|
|
end if;
|
1026 |
|
|
else
|
1027 |
|
|
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
|
1028 |
|
|
if (vec(old_width-1) = '1') then
|
1029 |
|
|
vec := (others => '0');
|
1030 |
|
|
end if;
|
1031 |
|
|
end if;
|
1032 |
|
|
if new_width <= old_width then
|
1033 |
|
|
result := vec(new_width-1 downto 0);
|
1034 |
|
|
else
|
1035 |
|
|
if new_arith = xlUnsigned then
|
1036 |
|
|
result := zero_ext(vec, new_width);
|
1037 |
|
|
else
|
1038 |
|
|
result := sign_ext(vec, new_width);
|
1039 |
|
|
end if;
|
1040 |
|
|
end if;
|
1041 |
|
|
end if;
|
1042 |
|
|
return result;
|
1043 |
|
|
end;
|
1044 |
|
|
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
1045 |
|
|
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
|
1046 |
|
|
return std_logic_vector
|
1047 |
|
|
is
|
1048 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1049 |
|
|
variable result_arith : integer;
|
1050 |
|
|
begin
|
1051 |
|
|
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
|
1052 |
|
|
result_arith := xlSigned;
|
1053 |
|
|
end if;
|
1054 |
|
|
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
|
1055 |
|
|
return result;
|
1056 |
|
|
end;
|
1057 |
|
|
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
|
1058 |
|
|
begin
|
1059 |
|
|
return max(a_bin_pt, b_bin_pt);
|
1060 |
|
|
end;
|
1061 |
|
|
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
|
1062 |
|
|
return INTEGER is
|
1063 |
|
|
begin
|
1064 |
|
|
return max(a_width - a_bin_pt, b_width - b_bin_pt);
|
1065 |
|
|
end;
|
1066 |
|
|
function pad_LSB(inp : std_logic_vector; new_width: integer)
|
1067 |
|
|
return STD_LOGIC_VECTOR
|
1068 |
|
|
is
|
1069 |
|
|
constant orig_width : integer := inp'length;
|
1070 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
1071 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1072 |
|
|
variable pos : integer;
|
1073 |
|
|
constant pad_pos : integer := new_width - orig_width - 1;
|
1074 |
|
|
begin
|
1075 |
|
|
vec := inp;
|
1076 |
|
|
pos := new_width-1;
|
1077 |
|
|
if (new_width >= orig_width) then
|
1078 |
|
|
for i in orig_width-1 downto 0 loop
|
1079 |
|
|
result(pos) := vec(i);
|
1080 |
|
|
pos := pos - 1;
|
1081 |
|
|
end loop;
|
1082 |
|
|
if pad_pos >= 0 then
|
1083 |
|
|
for i in pad_pos downto 0 loop
|
1084 |
|
|
result(i) := '0';
|
1085 |
|
|
end loop;
|
1086 |
|
|
end if;
|
1087 |
|
|
end if;
|
1088 |
|
|
return result;
|
1089 |
|
|
end;
|
1090 |
|
|
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
|
1091 |
|
|
return std_logic_vector
|
1092 |
|
|
is
|
1093 |
|
|
constant old_width : integer := inp'length;
|
1094 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
1095 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1096 |
|
|
begin
|
1097 |
|
|
vec := inp;
|
1098 |
|
|
if new_width >= old_width then
|
1099 |
|
|
result(old_width-1 downto 0) := vec;
|
1100 |
|
|
if new_width-1 >= old_width then
|
1101 |
|
|
for i in new_width-1 downto old_width loop
|
1102 |
|
|
result(i) := vec(old_width-1);
|
1103 |
|
|
end loop;
|
1104 |
|
|
end if;
|
1105 |
|
|
else
|
1106 |
|
|
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
|
1107 |
|
|
end if;
|
1108 |
|
|
return result;
|
1109 |
|
|
end;
|
1110 |
|
|
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
|
1111 |
|
|
return std_logic_vector
|
1112 |
|
|
is
|
1113 |
|
|
constant old_width : integer := inp'length;
|
1114 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
1115 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1116 |
|
|
begin
|
1117 |
|
|
vec := inp;
|
1118 |
|
|
if new_width >= old_width then
|
1119 |
|
|
result(old_width-1 downto 0) := vec;
|
1120 |
|
|
if new_width-1 >= old_width then
|
1121 |
|
|
for i in new_width-1 downto old_width loop
|
1122 |
|
|
result(i) := '0';
|
1123 |
|
|
end loop;
|
1124 |
|
|
end if;
|
1125 |
|
|
else
|
1126 |
|
|
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
|
1127 |
|
|
end if;
|
1128 |
|
|
return result;
|
1129 |
|
|
end;
|
1130 |
|
|
function zero_ext(inp : std_logic; new_width : INTEGER)
|
1131 |
|
|
return std_logic_vector
|
1132 |
|
|
is
|
1133 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1134 |
|
|
begin
|
1135 |
|
|
result(0) := inp;
|
1136 |
|
|
for i in new_width-1 downto 1 loop
|
1137 |
|
|
result(i) := '0';
|
1138 |
|
|
end loop;
|
1139 |
|
|
return result;
|
1140 |
|
|
end;
|
1141 |
|
|
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
|
1142 |
|
|
return std_logic_vector
|
1143 |
|
|
is
|
1144 |
|
|
constant orig_width : integer := inp'length;
|
1145 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
1146 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1147 |
|
|
begin
|
1148 |
|
|
vec := inp;
|
1149 |
|
|
if arith = xlUnsigned then
|
1150 |
|
|
result := zero_ext(vec, new_width);
|
1151 |
|
|
else
|
1152 |
|
|
result := sign_ext(vec, new_width);
|
1153 |
|
|
end if;
|
1154 |
|
|
return result;
|
1155 |
|
|
end;
|
1156 |
|
|
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
|
1157 |
|
|
return STD_LOGIC_VECTOR
|
1158 |
|
|
is
|
1159 |
|
|
constant orig_width : integer := inp'length;
|
1160 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
1161 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1162 |
|
|
variable pos : integer;
|
1163 |
|
|
begin
|
1164 |
|
|
vec := inp;
|
1165 |
|
|
pos := new_width-1;
|
1166 |
|
|
if (arith = xlUnsigned) then
|
1167 |
|
|
result(pos) := '0';
|
1168 |
|
|
pos := pos - 1;
|
1169 |
|
|
else
|
1170 |
|
|
result(pos) := vec(orig_width-1);
|
1171 |
|
|
pos := pos - 1;
|
1172 |
|
|
end if;
|
1173 |
|
|
if (new_width >= orig_width) then
|
1174 |
|
|
for i in orig_width-1 downto 0 loop
|
1175 |
|
|
result(pos) := vec(i);
|
1176 |
|
|
pos := pos - 1;
|
1177 |
|
|
end loop;
|
1178 |
|
|
if pos >= 0 then
|
1179 |
|
|
for i in pos downto 0 loop
|
1180 |
|
|
result(i) := '0';
|
1181 |
|
|
end loop;
|
1182 |
|
|
end if;
|
1183 |
|
|
end if;
|
1184 |
|
|
return result;
|
1185 |
|
|
end;
|
1186 |
|
|
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
|
1187 |
|
|
new_width: INTEGER)
|
1188 |
|
|
return std_logic_vector
|
1189 |
|
|
is
|
1190 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
1191 |
|
|
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
|
1192 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1193 |
|
|
begin
|
1194 |
|
|
vec := inp;
|
1195 |
|
|
if delta > 0 then
|
1196 |
|
|
padded_inp := pad_LSB(vec, old_width+delta);
|
1197 |
|
|
result := extend_MSB(padded_inp, new_width, new_arith);
|
1198 |
|
|
else
|
1199 |
|
|
result := extend_MSB(vec, new_width, new_arith);
|
1200 |
|
|
end if;
|
1201 |
|
|
return result;
|
1202 |
|
|
end;
|
1203 |
|
|
function max(L, R: INTEGER) return INTEGER is
|
1204 |
|
|
begin
|
1205 |
|
|
if L > R then
|
1206 |
|
|
return L;
|
1207 |
|
|
else
|
1208 |
|
|
return R;
|
1209 |
|
|
end if;
|
1210 |
|
|
end;
|
1211 |
|
|
function min(L, R: INTEGER) return INTEGER is
|
1212 |
|
|
begin
|
1213 |
|
|
if L < R then
|
1214 |
|
|
return L;
|
1215 |
|
|
else
|
1216 |
|
|
return R;
|
1217 |
|
|
end if;
|
1218 |
|
|
end;
|
1219 |
|
|
function "="(left,right: STRING) return boolean is
|
1220 |
|
|
begin
|
1221 |
|
|
if (left'length /= right'length) then
|
1222 |
|
|
return false;
|
1223 |
|
|
else
|
1224 |
|
|
test : for i in 1 to left'length loop
|
1225 |
|
|
if left(i) /= right(i) then
|
1226 |
|
|
return false;
|
1227 |
|
|
end if;
|
1228 |
|
|
end loop test;
|
1229 |
|
|
return true;
|
1230 |
|
|
end if;
|
1231 |
|
|
end;
|
1232 |
|
|
-- synopsys translate_off
|
1233 |
|
|
function is_binary_string_invalid (inp : string)
|
1234 |
|
|
return boolean
|
1235 |
|
|
is
|
1236 |
|
|
variable vec : string(1 to inp'length);
|
1237 |
|
|
variable result : boolean;
|
1238 |
|
|
begin
|
1239 |
|
|
vec := inp;
|
1240 |
|
|
result := false;
|
1241 |
|
|
for i in 1 to vec'length loop
|
1242 |
|
|
if ( vec(i) = 'X' ) then
|
1243 |
|
|
result := true;
|
1244 |
|
|
end if;
|
1245 |
|
|
end loop;
|
1246 |
|
|
return result;
|
1247 |
|
|
end;
|
1248 |
|
|
function is_binary_string_undefined (inp : string)
|
1249 |
|
|
return boolean
|
1250 |
|
|
is
|
1251 |
|
|
variable vec : string(1 to inp'length);
|
1252 |
|
|
variable result : boolean;
|
1253 |
|
|
begin
|
1254 |
|
|
vec := inp;
|
1255 |
|
|
result := false;
|
1256 |
|
|
for i in 1 to vec'length loop
|
1257 |
|
|
if ( vec(i) = 'U' ) then
|
1258 |
|
|
result := true;
|
1259 |
|
|
end if;
|
1260 |
|
|
end loop;
|
1261 |
|
|
return result;
|
1262 |
|
|
end;
|
1263 |
|
|
function is_XorU(inp : std_logic_vector)
|
1264 |
|
|
return boolean
|
1265 |
|
|
is
|
1266 |
|
|
constant width : integer := inp'length;
|
1267 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1268 |
|
|
variable result : boolean;
|
1269 |
|
|
begin
|
1270 |
|
|
vec := inp;
|
1271 |
|
|
result := false;
|
1272 |
|
|
for i in 0 to width-1 loop
|
1273 |
|
|
if (vec(i) = 'U') or (vec(i) = 'X') then
|
1274 |
|
|
result := true;
|
1275 |
|
|
end if;
|
1276 |
|
|
end loop;
|
1277 |
|
|
return result;
|
1278 |
|
|
end;
|
1279 |
|
|
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
|
1280 |
|
|
return real
|
1281 |
|
|
is
|
1282 |
|
|
variable vec : std_logic_vector(inp'length-1 downto 0);
|
1283 |
|
|
variable result, shift_val, undefined_real : real;
|
1284 |
|
|
variable neg_num : boolean;
|
1285 |
|
|
begin
|
1286 |
|
|
vec := inp;
|
1287 |
|
|
result := 0.0;
|
1288 |
|
|
neg_num := false;
|
1289 |
|
|
if vec(inp'length-1) = '1' then
|
1290 |
|
|
neg_num := true;
|
1291 |
|
|
end if;
|
1292 |
|
|
for i in 0 to inp'length-1 loop
|
1293 |
|
|
if vec(i) = 'U' or vec(i) = 'X' then
|
1294 |
|
|
return undefined_real;
|
1295 |
|
|
end if;
|
1296 |
|
|
if arith = xlSigned then
|
1297 |
|
|
if neg_num then
|
1298 |
|
|
if vec(i) = '0' then
|
1299 |
|
|
result := result + 2.0**i;
|
1300 |
|
|
end if;
|
1301 |
|
|
else
|
1302 |
|
|
if vec(i) = '1' then
|
1303 |
|
|
result := result + 2.0**i;
|
1304 |
|
|
end if;
|
1305 |
|
|
end if;
|
1306 |
|
|
else
|
1307 |
|
|
if vec(i) = '1' then
|
1308 |
|
|
result := result + 2.0**i;
|
1309 |
|
|
end if;
|
1310 |
|
|
end if;
|
1311 |
|
|
end loop;
|
1312 |
|
|
if arith = xlSigned then
|
1313 |
|
|
if neg_num then
|
1314 |
|
|
result := result + 1.0;
|
1315 |
|
|
result := result * (-1.0);
|
1316 |
|
|
end if;
|
1317 |
|
|
end if;
|
1318 |
|
|
shift_val := 2.0**(-1*bin_pt);
|
1319 |
|
|
result := result * shift_val;
|
1320 |
|
|
return result;
|
1321 |
|
|
end;
|
1322 |
|
|
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
|
1323 |
|
|
return real
|
1324 |
|
|
is
|
1325 |
|
|
variable result : real := 0.0;
|
1326 |
|
|
begin
|
1327 |
|
|
if inp = '1' then
|
1328 |
|
|
result := 1.0;
|
1329 |
|
|
end if;
|
1330 |
|
|
if arith = xlSigned then
|
1331 |
|
|
assert false
|
1332 |
|
|
report "It doesn't make sense to convert a 1 bit number to a signed real.";
|
1333 |
|
|
end if;
|
1334 |
|
|
return result;
|
1335 |
|
|
end;
|
1336 |
|
|
-- synopsys translate_on
|
1337 |
|
|
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
|
1338 |
|
|
return std_logic_vector
|
1339 |
|
|
is
|
1340 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1341 |
|
|
variable unsigned_val : unsigned(width-1 downto 0);
|
1342 |
|
|
variable signed_val : signed(width-1 downto 0);
|
1343 |
|
|
begin
|
1344 |
|
|
if (arith = xlSigned) then
|
1345 |
|
|
signed_val := to_signed(inp, width);
|
1346 |
|
|
result := signed_to_std_logic_vector(signed_val);
|
1347 |
|
|
else
|
1348 |
|
|
unsigned_val := to_unsigned(inp, width);
|
1349 |
|
|
result := unsigned_to_std_logic_vector(unsigned_val);
|
1350 |
|
|
end if;
|
1351 |
|
|
return result;
|
1352 |
|
|
end;
|
1353 |
|
|
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
|
1354 |
|
|
return integer
|
1355 |
|
|
is
|
1356 |
|
|
constant width : integer := inp'length;
|
1357 |
|
|
variable unsigned_val : unsigned(width-1 downto 0);
|
1358 |
|
|
variable signed_val : signed(width-1 downto 0);
|
1359 |
|
|
variable result : integer;
|
1360 |
|
|
begin
|
1361 |
|
|
if (arith = xlSigned) then
|
1362 |
|
|
signed_val := std_logic_vector_to_signed(inp);
|
1363 |
|
|
result := to_integer(signed_val);
|
1364 |
|
|
else
|
1365 |
|
|
unsigned_val := std_logic_vector_to_unsigned(inp);
|
1366 |
|
|
result := to_integer(unsigned_val);
|
1367 |
|
|
end if;
|
1368 |
|
|
return result;
|
1369 |
|
|
end;
|
1370 |
|
|
function std_logic_to_integer(constant inp : std_logic := '0')
|
1371 |
|
|
return integer
|
1372 |
|
|
is
|
1373 |
|
|
begin
|
1374 |
|
|
if inp = '1' then
|
1375 |
|
|
return 1;
|
1376 |
|
|
else
|
1377 |
|
|
return 0;
|
1378 |
|
|
end if;
|
1379 |
|
|
end;
|
1380 |
|
|
function makeZeroBinStr (width : integer) return STRING is
|
1381 |
|
|
variable result : string(1 to width+3);
|
1382 |
|
|
begin
|
1383 |
|
|
result(1) := '0';
|
1384 |
|
|
result(2) := 'b';
|
1385 |
|
|
for i in 3 to width+2 loop
|
1386 |
|
|
result(i) := '0';
|
1387 |
|
|
end loop;
|
1388 |
|
|
result(width+3) := '.';
|
1389 |
|
|
return result;
|
1390 |
|
|
end;
|
1391 |
|
|
-- synopsys translate_off
|
1392 |
|
|
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
|
1393 |
|
|
return std_logic_vector
|
1394 |
|
|
is
|
1395 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1396 |
|
|
begin
|
1397 |
|
|
result := (others => '0');
|
1398 |
|
|
return result;
|
1399 |
|
|
end;
|
1400 |
|
|
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
|
1401 |
|
|
return std_logic_vector
|
1402 |
|
|
is
|
1403 |
|
|
variable real_val : real;
|
1404 |
|
|
variable int_val : integer;
|
1405 |
|
|
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
|
1406 |
|
|
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
|
1407 |
|
|
variable signed_val : signed(width-1 downto 0) := (others => '0');
|
1408 |
|
|
begin
|
1409 |
|
|
real_val := inp;
|
1410 |
|
|
int_val := integer(real_val * 2.0**(bin_pt));
|
1411 |
|
|
if (arith = xlSigned) then
|
1412 |
|
|
signed_val := to_signed(int_val, width);
|
1413 |
|
|
result := signed_to_std_logic_vector(signed_val);
|
1414 |
|
|
else
|
1415 |
|
|
unsigned_val := to_unsigned(int_val, width);
|
1416 |
|
|
result := unsigned_to_std_logic_vector(unsigned_val);
|
1417 |
|
|
end if;
|
1418 |
|
|
return result;
|
1419 |
|
|
end;
|
1420 |
|
|
-- synopsys translate_on
|
1421 |
|
|
function valid_bin_string (inp : string)
|
1422 |
|
|
return boolean
|
1423 |
|
|
is
|
1424 |
|
|
variable vec : string(1 to inp'length);
|
1425 |
|
|
begin
|
1426 |
|
|
vec := inp;
|
1427 |
|
|
if (vec(1) = '0' and vec(2) = 'b') then
|
1428 |
|
|
return true;
|
1429 |
|
|
else
|
1430 |
|
|
return false;
|
1431 |
|
|
end if;
|
1432 |
|
|
end;
|
1433 |
|
|
function hex_string_to_std_logic_vector(inp: string; width : integer)
|
1434 |
|
|
return std_logic_vector is
|
1435 |
|
|
constant strlen : integer := inp'LENGTH;
|
1436 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1437 |
|
|
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
|
1438 |
|
|
variable posn : integer;
|
1439 |
|
|
variable ch : character;
|
1440 |
|
|
variable vec : string(1 to strlen);
|
1441 |
|
|
begin
|
1442 |
|
|
vec := inp;
|
1443 |
|
|
result := (others => '0');
|
1444 |
|
|
posn := (strlen*4)-1;
|
1445 |
|
|
for i in 1 to strlen loop
|
1446 |
|
|
ch := vec(i);
|
1447 |
|
|
case ch is
|
1448 |
|
|
when '0' => bitval(posn downto posn-3) := "0000";
|
1449 |
|
|
when '1' => bitval(posn downto posn-3) := "0001";
|
1450 |
|
|
when '2' => bitval(posn downto posn-3) := "0010";
|
1451 |
|
|
when '3' => bitval(posn downto posn-3) := "0011";
|
1452 |
|
|
when '4' => bitval(posn downto posn-3) := "0100";
|
1453 |
|
|
when '5' => bitval(posn downto posn-3) := "0101";
|
1454 |
|
|
when '6' => bitval(posn downto posn-3) := "0110";
|
1455 |
|
|
when '7' => bitval(posn downto posn-3) := "0111";
|
1456 |
|
|
when '8' => bitval(posn downto posn-3) := "1000";
|
1457 |
|
|
when '9' => bitval(posn downto posn-3) := "1001";
|
1458 |
|
|
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
|
1459 |
|
|
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
|
1460 |
|
|
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
|
1461 |
|
|
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
|
1462 |
|
|
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
|
1463 |
|
|
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
|
1464 |
|
|
when others => bitval(posn downto posn-3) := "XXXX";
|
1465 |
|
|
-- synopsys translate_off
|
1466 |
|
|
ASSERT false
|
1467 |
|
|
REPORT "Invalid hex value" SEVERITY ERROR;
|
1468 |
|
|
-- synopsys translate_on
|
1469 |
|
|
end case;
|
1470 |
|
|
posn := posn - 4;
|
1471 |
|
|
end loop;
|
1472 |
|
|
if (width <= strlen*4) then
|
1473 |
|
|
result := bitval(width-1 downto 0);
|
1474 |
|
|
else
|
1475 |
|
|
result((strlen*4)-1 downto 0) := bitval;
|
1476 |
|
|
end if;
|
1477 |
|
|
return result;
|
1478 |
|
|
end;
|
1479 |
|
|
function bin_string_to_std_logic_vector (inp : string)
|
1480 |
|
|
return std_logic_vector
|
1481 |
|
|
is
|
1482 |
|
|
variable pos : integer;
|
1483 |
|
|
variable vec : string(1 to inp'length);
|
1484 |
|
|
variable result : std_logic_vector(inp'length-1 downto 0);
|
1485 |
|
|
begin
|
1486 |
|
|
vec := inp;
|
1487 |
|
|
pos := inp'length-1;
|
1488 |
|
|
result := (others => '0');
|
1489 |
|
|
for i in 1 to vec'length loop
|
1490 |
|
|
-- synopsys translate_off
|
1491 |
|
|
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
|
1492 |
|
|
assert false
|
1493 |
|
|
report "Input string is larger than output std_logic_vector. Truncating output.";
|
1494 |
|
|
return result;
|
1495 |
|
|
end if;
|
1496 |
|
|
-- synopsys translate_on
|
1497 |
|
|
if vec(i) = '0' then
|
1498 |
|
|
result(pos) := '0';
|
1499 |
|
|
pos := pos - 1;
|
1500 |
|
|
end if;
|
1501 |
|
|
if vec(i) = '1' then
|
1502 |
|
|
result(pos) := '1';
|
1503 |
|
|
pos := pos - 1;
|
1504 |
|
|
end if;
|
1505 |
|
|
-- synopsys translate_off
|
1506 |
|
|
if (vec(i) = 'X' or vec(i) = 'U') then
|
1507 |
|
|
result(pos) := 'U';
|
1508 |
|
|
pos := pos - 1;
|
1509 |
|
|
end if;
|
1510 |
|
|
-- synopsys translate_on
|
1511 |
|
|
end loop;
|
1512 |
|
|
return result;
|
1513 |
|
|
end;
|
1514 |
|
|
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
|
1515 |
|
|
return std_logic_vector
|
1516 |
|
|
is
|
1517 |
|
|
constant str_width : integer := width + 4;
|
1518 |
|
|
constant inp_len : integer := inp'length;
|
1519 |
|
|
constant num_elements : integer := (inp_len + 1)/str_width;
|
1520 |
|
|
constant reverse_index : integer := (num_elements-1) - index;
|
1521 |
|
|
variable left_pos : integer;
|
1522 |
|
|
variable right_pos : integer;
|
1523 |
|
|
variable vec : string(1 to inp'length);
|
1524 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1525 |
|
|
begin
|
1526 |
|
|
vec := inp;
|
1527 |
|
|
result := (others => '0');
|
1528 |
|
|
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
|
1529 |
|
|
left_pos := 1;
|
1530 |
|
|
right_pos := width + 3;
|
1531 |
|
|
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
|
1532 |
|
|
end if;
|
1533 |
|
|
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
|
1534 |
|
|
left_pos := (reverse_index * str_width) + 1;
|
1535 |
|
|
right_pos := left_pos + width + 2;
|
1536 |
|
|
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
|
1537 |
|
|
end if;
|
1538 |
|
|
return result;
|
1539 |
|
|
end;
|
1540 |
|
|
-- synopsys translate_off
|
1541 |
|
|
function std_logic_vector_to_bin_string(inp : std_logic_vector)
|
1542 |
|
|
return string
|
1543 |
|
|
is
|
1544 |
|
|
variable vec : std_logic_vector(1 to inp'length);
|
1545 |
|
|
variable result : string(vec'range);
|
1546 |
|
|
begin
|
1547 |
|
|
vec := inp;
|
1548 |
|
|
for i in vec'range loop
|
1549 |
|
|
result(i) := to_char(vec(i));
|
1550 |
|
|
end loop;
|
1551 |
|
|
return result;
|
1552 |
|
|
end;
|
1553 |
|
|
function std_logic_to_bin_string(inp : std_logic)
|
1554 |
|
|
return string
|
1555 |
|
|
is
|
1556 |
|
|
variable result : string(1 to 3);
|
1557 |
|
|
begin
|
1558 |
|
|
result(1) := '0';
|
1559 |
|
|
result(2) := 'b';
|
1560 |
|
|
result(3) := to_char(inp);
|
1561 |
|
|
return result;
|
1562 |
|
|
end;
|
1563 |
|
|
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
|
1564 |
|
|
return string
|
1565 |
|
|
is
|
1566 |
|
|
variable width : integer := inp'length;
|
1567 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1568 |
|
|
variable str_pos : integer;
|
1569 |
|
|
variable result : string(1 to width+3);
|
1570 |
|
|
begin
|
1571 |
|
|
vec := inp;
|
1572 |
|
|
str_pos := 1;
|
1573 |
|
|
result(str_pos) := '0';
|
1574 |
|
|
str_pos := 2;
|
1575 |
|
|
result(str_pos) := 'b';
|
1576 |
|
|
str_pos := 3;
|
1577 |
|
|
for i in width-1 downto 0 loop
|
1578 |
|
|
if (((width+3) - bin_pt) = str_pos) then
|
1579 |
|
|
result(str_pos) := '.';
|
1580 |
|
|
str_pos := str_pos + 1;
|
1581 |
|
|
end if;
|
1582 |
|
|
result(str_pos) := to_char(vec(i));
|
1583 |
|
|
str_pos := str_pos + 1;
|
1584 |
|
|
end loop;
|
1585 |
|
|
if (bin_pt = 0) then
|
1586 |
|
|
result(str_pos) := '.';
|
1587 |
|
|
end if;
|
1588 |
|
|
return result;
|
1589 |
|
|
end;
|
1590 |
|
|
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
|
1591 |
|
|
return string
|
1592 |
|
|
is
|
1593 |
|
|
variable result : string(1 to width);
|
1594 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1595 |
|
|
begin
|
1596 |
|
|
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
|
1597 |
|
|
result := std_logic_vector_to_bin_string(vec);
|
1598 |
|
|
return result;
|
1599 |
|
|
end;
|
1600 |
|
|
function real_to_string (inp : real) return string
|
1601 |
|
|
is
|
1602 |
|
|
variable result : string(1 to display_precision) := (others => ' ');
|
1603 |
|
|
begin
|
1604 |
|
|
result(real'image(inp)'range) := real'image(inp);
|
1605 |
|
|
return result;
|
1606 |
|
|
end;
|
1607 |
|
|
-- synopsys translate_on
|
1608 |
|
|
end conv_pkg;
|
1609 |
|
|
|
1610 |
|
|
-------------------------------------------------------------------
|
1611 |
|
|
-- System Generator version 13.2 VHDL source file.
|
1612 |
|
|
--
|
1613 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
1614 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
1615 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
1616 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
1617 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
1618 |
|
|
-- this text/file solely for design, simulation, implementation and
|
1619 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
1620 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
1621 |
|
|
-- and immediately terminates your license unless covered by a separate
|
1622 |
|
|
-- agreement.
|
1623 |
|
|
--
|
1624 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
1625 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
1626 |
|
|
-- providing this design, code, or information as one possible
|
1627 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
1628 |
|
|
-- making no representation that this implementation is free from any
|
1629 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
1630 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
1631 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
1632 |
|
|
-- implementation, including but not limited to warranties of
|
1633 |
|
|
-- merchantability or fitness for a particular purpose.
|
1634 |
|
|
--
|
1635 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
1636 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
1637 |
|
|
--
|
1638 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
1639 |
|
|
-- sole risk and will be unsupported.
|
1640 |
|
|
--
|
1641 |
|
|
-- This copyright and support notice must be retained as part of this
|
1642 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
1643 |
|
|
-- reserved.
|
1644 |
|
|
-------------------------------------------------------------------
|
1645 |
|
|
-- synopsys translate_off
|
1646 |
|
|
library unisim;
|
1647 |
|
|
use unisim.vcomponents.all;
|
1648 |
|
|
-- synopsys translate_on
|
1649 |
|
|
library IEEE;
|
1650 |
|
|
use IEEE.std_logic_1164.all;
|
1651 |
|
|
use work.conv_pkg.all;
|
1652 |
|
|
entity srl17e is
|
1653 |
|
|
generic (width : integer:=16;
|
1654 |
|
|
latency : integer :=8);
|
1655 |
|
|
port (clk : in std_logic;
|
1656 |
|
|
ce : in std_logic;
|
1657 |
|
|
d : in std_logic_vector(width-1 downto 0);
|
1658 |
|
|
q : out std_logic_vector(width-1 downto 0));
|
1659 |
|
|
end srl17e;
|
1660 |
|
|
architecture structural of srl17e is
|
1661 |
|
|
component SRL16E
|
1662 |
|
|
port (D : in STD_ULOGIC;
|
1663 |
|
|
CE : in STD_ULOGIC;
|
1664 |
|
|
CLK : in STD_ULOGIC;
|
1665 |
|
|
A0 : in STD_ULOGIC;
|
1666 |
|
|
A1 : in STD_ULOGIC;
|
1667 |
|
|
A2 : in STD_ULOGIC;
|
1668 |
|
|
A3 : in STD_ULOGIC;
|
1669 |
|
|
Q : out STD_ULOGIC);
|
1670 |
|
|
end component;
|
1671 |
|
|
attribute syn_black_box of SRL16E : component is true;
|
1672 |
|
|
attribute fpga_dont_touch of SRL16E : component is "true";
|
1673 |
|
|
component FDE
|
1674 |
|
|
port(
|
1675 |
|
|
Q : out STD_ULOGIC;
|
1676 |
|
|
D : in STD_ULOGIC;
|
1677 |
|
|
C : in STD_ULOGIC;
|
1678 |
|
|
CE : in STD_ULOGIC);
|
1679 |
|
|
end component;
|
1680 |
|
|
attribute syn_black_box of FDE : component is true;
|
1681 |
|
|
attribute fpga_dont_touch of FDE : component is "true";
|
1682 |
|
|
constant a : std_logic_vector(4 downto 0) :=
|
1683 |
|
|
integer_to_std_logic_vector(latency-2,5,xlSigned);
|
1684 |
|
|
signal d_delayed : std_logic_vector(width-1 downto 0);
|
1685 |
|
|
signal srl16_out : std_logic_vector(width-1 downto 0);
|
1686 |
|
|
begin
|
1687 |
|
|
d_delayed <= d after 200 ps;
|
1688 |
|
|
reg_array : for i in 0 to width-1 generate
|
1689 |
|
|
srl16_used: if latency > 1 generate
|
1690 |
|
|
u1 : srl16e port map(clk => clk,
|
1691 |
|
|
d => d_delayed(i),
|
1692 |
|
|
q => srl16_out(i),
|
1693 |
|
|
ce => ce,
|
1694 |
|
|
a0 => a(0),
|
1695 |
|
|
a1 => a(1),
|
1696 |
|
|
a2 => a(2),
|
1697 |
|
|
a3 => a(3));
|
1698 |
|
|
end generate;
|
1699 |
|
|
srl16_not_used: if latency <= 1 generate
|
1700 |
|
|
srl16_out(i) <= d_delayed(i);
|
1701 |
|
|
end generate;
|
1702 |
|
|
fde_used: if latency /= 0 generate
|
1703 |
|
|
u2 : fde port map(c => clk,
|
1704 |
|
|
d => srl16_out(i),
|
1705 |
|
|
q => q(i),
|
1706 |
|
|
ce => ce);
|
1707 |
|
|
end generate;
|
1708 |
|
|
fde_not_used: if latency = 0 generate
|
1709 |
|
|
q(i) <= srl16_out(i);
|
1710 |
|
|
end generate;
|
1711 |
|
|
end generate;
|
1712 |
|
|
end structural;
|
1713 |
|
|
library IEEE;
|
1714 |
|
|
use IEEE.std_logic_1164.all;
|
1715 |
|
|
use work.conv_pkg.all;
|
1716 |
|
|
entity synth_reg is
|
1717 |
|
|
generic (width : integer := 8;
|
1718 |
|
|
latency : integer := 1);
|
1719 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
1720 |
|
|
ce : in std_logic;
|
1721 |
|
|
clr : in std_logic;
|
1722 |
|
|
clk : in std_logic;
|
1723 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
1724 |
|
|
end synth_reg;
|
1725 |
|
|
architecture structural of synth_reg is
|
1726 |
|
|
component srl17e
|
1727 |
|
|
generic (width : integer:=16;
|
1728 |
|
|
latency : integer :=8);
|
1729 |
|
|
port (clk : in std_logic;
|
1730 |
|
|
ce : in std_logic;
|
1731 |
|
|
d : in std_logic_vector(width-1 downto 0);
|
1732 |
|
|
q : out std_logic_vector(width-1 downto 0));
|
1733 |
|
|
end component;
|
1734 |
|
|
function calc_num_srl17es (latency : integer)
|
1735 |
|
|
return integer
|
1736 |
|
|
is
|
1737 |
|
|
variable remaining_latency : integer;
|
1738 |
|
|
variable result : integer;
|
1739 |
|
|
begin
|
1740 |
|
|
result := latency / 17;
|
1741 |
|
|
remaining_latency := latency - (result * 17);
|
1742 |
|
|
if (remaining_latency /= 0) then
|
1743 |
|
|
result := result + 1;
|
1744 |
|
|
end if;
|
1745 |
|
|
return result;
|
1746 |
|
|
end;
|
1747 |
|
|
constant complete_num_srl17es : integer := latency / 17;
|
1748 |
|
|
constant num_srl17es : integer := calc_num_srl17es(latency);
|
1749 |
|
|
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
|
1750 |
|
|
type register_array is array (num_srl17es downto 0) of
|
1751 |
|
|
std_logic_vector(width-1 downto 0);
|
1752 |
|
|
signal z : register_array;
|
1753 |
|
|
begin
|
1754 |
|
|
z(0) <= i;
|
1755 |
|
|
complete_ones : if complete_num_srl17es > 0 generate
|
1756 |
|
|
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
|
1757 |
|
|
delay_comp : srl17e
|
1758 |
|
|
generic map (width => width,
|
1759 |
|
|
latency => 17)
|
1760 |
|
|
port map (clk => clk,
|
1761 |
|
|
ce => ce,
|
1762 |
|
|
d => z(i),
|
1763 |
|
|
q => z(i+1));
|
1764 |
|
|
end generate;
|
1765 |
|
|
end generate;
|
1766 |
|
|
partial_one : if remaining_latency > 0 generate
|
1767 |
|
|
last_srl17e : srl17e
|
1768 |
|
|
generic map (width => width,
|
1769 |
|
|
latency => remaining_latency)
|
1770 |
|
|
port map (clk => clk,
|
1771 |
|
|
ce => ce,
|
1772 |
|
|
d => z(num_srl17es-1),
|
1773 |
|
|
q => z(num_srl17es));
|
1774 |
|
|
end generate;
|
1775 |
|
|
o <= z(num_srl17es);
|
1776 |
|
|
end structural;
|
1777 |
|
|
library IEEE;
|
1778 |
|
|
use IEEE.std_logic_1164.all;
|
1779 |
|
|
use work.conv_pkg.all;
|
1780 |
|
|
entity synth_reg_reg is
|
1781 |
|
|
generic (width : integer := 8;
|
1782 |
|
|
latency : integer := 1);
|
1783 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
1784 |
|
|
ce : in std_logic;
|
1785 |
|
|
clr : in std_logic;
|
1786 |
|
|
clk : in std_logic;
|
1787 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
1788 |
|
|
end synth_reg_reg;
|
1789 |
|
|
architecture behav of synth_reg_reg is
|
1790 |
|
|
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
|
1791 |
|
|
signal reg_bank : reg_array_type := (others => (others => '0'));
|
1792 |
|
|
signal reg_bank_in : reg_array_type := (others => (others => '0'));
|
1793 |
|
|
attribute syn_allow_retiming : boolean;
|
1794 |
|
|
attribute syn_srlstyle : string;
|
1795 |
|
|
attribute syn_allow_retiming of reg_bank : signal is true;
|
1796 |
|
|
attribute syn_allow_retiming of reg_bank_in : signal is true;
|
1797 |
|
|
attribute syn_srlstyle of reg_bank : signal is "registers";
|
1798 |
|
|
attribute syn_srlstyle of reg_bank_in : signal is "registers";
|
1799 |
|
|
begin
|
1800 |
|
|
latency_eq_0: if latency = 0 generate
|
1801 |
|
|
o <= i;
|
1802 |
|
|
end generate latency_eq_0;
|
1803 |
|
|
latency_gt_0: if latency >= 1 generate
|
1804 |
|
|
o <= reg_bank(latency-1);
|
1805 |
|
|
reg_bank_in(0) <= i;
|
1806 |
|
|
loop_gen: for idx in latency-2 downto 0 generate
|
1807 |
|
|
reg_bank_in(idx+1) <= reg_bank(idx);
|
1808 |
|
|
end generate loop_gen;
|
1809 |
|
|
sync_loop: for sync_idx in latency-1 downto 0 generate
|
1810 |
|
|
sync_proc: process (clk)
|
1811 |
|
|
begin
|
1812 |
|
|
if clk'event and clk = '1' then
|
1813 |
|
|
if clr = '1' then
|
1814 |
|
|
reg_bank_in <= (others => (others => '0'));
|
1815 |
|
|
elsif ce = '1' then
|
1816 |
|
|
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
|
1817 |
|
|
end if;
|
1818 |
|
|
end if;
|
1819 |
|
|
end process sync_proc;
|
1820 |
|
|
end generate sync_loop;
|
1821 |
|
|
end generate latency_gt_0;
|
1822 |
|
|
end behav;
|
1823 |
|
|
|
1824 |
|
|
-------------------------------------------------------------------
|
1825 |
|
|
-- System Generator version 13.2 VHDL source file.
|
1826 |
|
|
--
|
1827 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
1828 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
1829 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
1830 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
1831 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
1832 |
|
|
-- this text/file solely for design, simulation, implementation and
|
1833 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
1834 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
1835 |
|
|
-- and immediately terminates your license unless covered by a separate
|
1836 |
|
|
-- agreement.
|
1837 |
|
|
--
|
1838 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
1839 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
1840 |
|
|
-- providing this design, code, or information as one possible
|
1841 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
1842 |
|
|
-- making no representation that this implementation is free from any
|
1843 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
1844 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
1845 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
1846 |
|
|
-- implementation, including but not limited to warranties of
|
1847 |
|
|
-- merchantability or fitness for a particular purpose.
|
1848 |
|
|
--
|
1849 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
1850 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
1851 |
|
|
--
|
1852 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
1853 |
|
|
-- sole risk and will be unsupported.
|
1854 |
|
|
--
|
1855 |
|
|
-- This copyright and support notice must be retained as part of this
|
1856 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
1857 |
|
|
-- reserved.
|
1858 |
|
|
-------------------------------------------------------------------
|
1859 |
|
|
-- synopsys translate_off
|
1860 |
|
|
library unisim;
|
1861 |
|
|
use unisim.vcomponents.all;
|
1862 |
|
|
-- synopsys translate_on
|
1863 |
|
|
library IEEE;
|
1864 |
|
|
use IEEE.std_logic_1164.all;
|
1865 |
|
|
use work.conv_pkg.all;
|
1866 |
|
|
entity single_reg_w_init is
|
1867 |
|
|
generic (
|
1868 |
|
|
width: integer := 8;
|
1869 |
|
|
init_index: integer := 0;
|
1870 |
|
|
init_value: bit_vector := b"0000"
|
1871 |
|
|
);
|
1872 |
|
|
port (
|
1873 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1874 |
|
|
ce: in std_logic;
|
1875 |
|
|
clr: in std_logic;
|
1876 |
|
|
clk: in std_logic;
|
1877 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1878 |
|
|
);
|
1879 |
|
|
end single_reg_w_init;
|
1880 |
|
|
architecture structural of single_reg_w_init is
|
1881 |
|
|
function build_init_const(width: integer;
|
1882 |
|
|
init_index: integer;
|
1883 |
|
|
init_value: bit_vector)
|
1884 |
|
|
return std_logic_vector
|
1885 |
|
|
is
|
1886 |
|
|
variable result: std_logic_vector(width - 1 downto 0);
|
1887 |
|
|
begin
|
1888 |
|
|
if init_index = 0 then
|
1889 |
|
|
result := (others => '0');
|
1890 |
|
|
elsif init_index = 1 then
|
1891 |
|
|
result := (others => '0');
|
1892 |
|
|
result(0) := '1';
|
1893 |
|
|
else
|
1894 |
|
|
result := to_stdlogicvector(init_value);
|
1895 |
|
|
end if;
|
1896 |
|
|
return result;
|
1897 |
|
|
end;
|
1898 |
|
|
component fdre
|
1899 |
|
|
port (
|
1900 |
|
|
q: out std_ulogic;
|
1901 |
|
|
d: in std_ulogic;
|
1902 |
|
|
c: in std_ulogic;
|
1903 |
|
|
ce: in std_ulogic;
|
1904 |
|
|
r: in std_ulogic
|
1905 |
|
|
);
|
1906 |
|
|
end component;
|
1907 |
|
|
attribute syn_black_box of fdre: component is true;
|
1908 |
|
|
attribute fpga_dont_touch of fdre: component is "true";
|
1909 |
|
|
component fdse
|
1910 |
|
|
port (
|
1911 |
|
|
q: out std_ulogic;
|
1912 |
|
|
d: in std_ulogic;
|
1913 |
|
|
c: in std_ulogic;
|
1914 |
|
|
ce: in std_ulogic;
|
1915 |
|
|
s: in std_ulogic
|
1916 |
|
|
);
|
1917 |
|
|
end component;
|
1918 |
|
|
attribute syn_black_box of fdse: component is true;
|
1919 |
|
|
attribute fpga_dont_touch of fdse: component is "true";
|
1920 |
|
|
constant init_const: std_logic_vector(width - 1 downto 0)
|
1921 |
|
|
:= build_init_const(width, init_index, init_value);
|
1922 |
|
|
begin
|
1923 |
|
|
fd_prim_array: for index in 0 to width - 1 generate
|
1924 |
|
|
bit_is_0: if (init_const(index) = '0') generate
|
1925 |
|
|
fdre_comp: fdre
|
1926 |
|
|
port map (
|
1927 |
|
|
c => clk,
|
1928 |
|
|
d => i(index),
|
1929 |
|
|
q => o(index),
|
1930 |
|
|
ce => ce,
|
1931 |
|
|
r => clr
|
1932 |
|
|
);
|
1933 |
|
|
end generate;
|
1934 |
|
|
bit_is_1: if (init_const(index) = '1') generate
|
1935 |
|
|
fdse_comp: fdse
|
1936 |
|
|
port map (
|
1937 |
|
|
c => clk,
|
1938 |
|
|
d => i(index),
|
1939 |
|
|
q => o(index),
|
1940 |
|
|
ce => ce,
|
1941 |
|
|
s => clr
|
1942 |
|
|
);
|
1943 |
|
|
end generate;
|
1944 |
|
|
end generate;
|
1945 |
|
|
end architecture structural;
|
1946 |
|
|
-- synopsys translate_off
|
1947 |
|
|
library unisim;
|
1948 |
|
|
use unisim.vcomponents.all;
|
1949 |
|
|
-- synopsys translate_on
|
1950 |
|
|
library IEEE;
|
1951 |
|
|
use IEEE.std_logic_1164.all;
|
1952 |
|
|
use work.conv_pkg.all;
|
1953 |
|
|
entity synth_reg_w_init is
|
1954 |
|
|
generic (
|
1955 |
|
|
width: integer := 8;
|
1956 |
|
|
init_index: integer := 0;
|
1957 |
|
|
init_value: bit_vector := b"0000";
|
1958 |
|
|
latency: integer := 1
|
1959 |
|
|
);
|
1960 |
|
|
port (
|
1961 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1962 |
|
|
ce: in std_logic;
|
1963 |
|
|
clr: in std_logic;
|
1964 |
|
|
clk: in std_logic;
|
1965 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1966 |
|
|
);
|
1967 |
|
|
end synth_reg_w_init;
|
1968 |
|
|
architecture structural of synth_reg_w_init is
|
1969 |
|
|
component single_reg_w_init
|
1970 |
|
|
generic (
|
1971 |
|
|
width: integer := 8;
|
1972 |
|
|
init_index: integer := 0;
|
1973 |
|
|
init_value: bit_vector := b"0000"
|
1974 |
|
|
);
|
1975 |
|
|
port (
|
1976 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1977 |
|
|
ce: in std_logic;
|
1978 |
|
|
clr: in std_logic;
|
1979 |
|
|
clk: in std_logic;
|
1980 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1981 |
|
|
);
|
1982 |
|
|
end component;
|
1983 |
|
|
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
|
1984 |
|
|
signal dly_clr: std_logic;
|
1985 |
|
|
begin
|
1986 |
|
|
latency_eq_0: if (latency = 0) generate
|
1987 |
|
|
o <= i;
|
1988 |
|
|
end generate;
|
1989 |
|
|
latency_gt_0: if (latency >= 1) generate
|
1990 |
|
|
dly_i((latency + 1) * width - 1 downto latency * width) <= i
|
1991 |
|
|
after 200 ps;
|
1992 |
|
|
dly_clr <= clr after 200 ps;
|
1993 |
|
|
fd_array: for index in latency downto 1 generate
|
1994 |
|
|
reg_comp: single_reg_w_init
|
1995 |
|
|
generic map (
|
1996 |
|
|
width => width,
|
1997 |
|
|
init_index => init_index,
|
1998 |
|
|
init_value => init_value
|
1999 |
|
|
)
|
2000 |
|
|
port map (
|
2001 |
|
|
clk => clk,
|
2002 |
|
|
i => dly_i((index + 1) * width - 1 downto index * width),
|
2003 |
|
|
o => dly_i(index * width - 1 downto (index - 1) * width),
|
2004 |
|
|
ce => ce,
|
2005 |
|
|
clr => dly_clr
|
2006 |
|
|
);
|
2007 |
|
|
end generate;
|
2008 |
|
|
o <= dly_i(width - 1 downto 0);
|
2009 |
|
|
end generate;
|
2010 |
|
|
end structural;
|
2011 |
|
|
library IEEE;
|
2012 |
|
|
use IEEE.std_logic_1164.all;
|
2013 |
|
|
use IEEE.numeric_std.all;
|
2014 |
|
|
use work.conv_pkg.all;
|
2015 |
|
|
|
2016 |
|
|
entity constant_963ed6358a is
|
2017 |
|
|
port (
|
2018 |
|
|
op : out std_logic_vector((1 - 1) downto 0);
|
2019 |
|
|
clk : in std_logic;
|
2020 |
|
|
ce : in std_logic;
|
2021 |
|
|
clr : in std_logic);
|
2022 |
|
|
end constant_963ed6358a;
|
2023 |
|
|
|
2024 |
|
|
|
2025 |
|
|
architecture behavior of constant_963ed6358a is
|
2026 |
|
|
begin
|
2027 |
|
|
op <= "0";
|
2028 |
|
|
end behavior;
|
2029 |
|
|
|
2030 |
|
|
library IEEE;
|
2031 |
|
|
use IEEE.std_logic_1164.all;
|
2032 |
|
|
use IEEE.numeric_std.all;
|
2033 |
|
|
use work.conv_pkg.all;
|
2034 |
|
|
|
2035 |
|
|
entity constant_6293007044 is
|
2036 |
|
|
port (
|
2037 |
|
|
op : out std_logic_vector((1 - 1) downto 0);
|
2038 |
|
|
clk : in std_logic;
|
2039 |
|
|
ce : in std_logic;
|
2040 |
|
|
clr : in std_logic);
|
2041 |
|
|
end constant_6293007044;
|
2042 |
|
|
|
2043 |
|
|
|
2044 |
|
|
architecture behavior of constant_6293007044 is
|
2045 |
|
|
begin
|
2046 |
|
|
op <= "1";
|
2047 |
|
|
end behavior;
|
2048 |
|
|
|
2049 |
|
|
library IEEE;
|
2050 |
|
|
use IEEE.std_logic_1164.all;
|
2051 |
|
|
use IEEE.numeric_std.all;
|
2052 |
|
|
use work.conv_pkg.all;
|
2053 |
|
|
|
2054 |
|
|
entity constant_19562ab42f is
|
2055 |
|
|
port (
|
2056 |
|
|
op : out std_logic_vector((8 - 1) downto 0);
|
2057 |
|
|
clk : in std_logic;
|
2058 |
|
|
ce : in std_logic;
|
2059 |
|
|
clr : in std_logic);
|
2060 |
|
|
end constant_19562ab42f;
|
2061 |
|
|
|
2062 |
|
|
|
2063 |
|
|
architecture behavior of constant_19562ab42f is
|
2064 |
|
|
begin
|
2065 |
|
|
op <= "11111111";
|
2066 |
|
|
end behavior;
|
2067 |
|
|
|
2068 |
|
|
|
2069 |
|
|
-------------------------------------------------------------------
|
2070 |
|
|
-- System Generator version 13.2 VHDL source file.
|
2071 |
|
|
--
|
2072 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
2073 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
2074 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
2075 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
2076 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
2077 |
|
|
-- this text/file solely for design, simulation, implementation and
|
2078 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
2079 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
2080 |
|
|
-- and immediately terminates your license unless covered by a separate
|
2081 |
|
|
-- agreement.
|
2082 |
|
|
--
|
2083 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
2084 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
2085 |
|
|
-- providing this design, code, or information as one possible
|
2086 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
2087 |
|
|
-- making no representation that this implementation is free from any
|
2088 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
2089 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
2090 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
2091 |
|
|
-- implementation, including but not limited to warranties of
|
2092 |
|
|
-- merchantability or fitness for a particular purpose.
|
2093 |
|
|
--
|
2094 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
2095 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
2096 |
|
|
--
|
2097 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
2098 |
|
|
-- sole risk and will be unsupported.
|
2099 |
|
|
--
|
2100 |
|
|
-- This copyright and support notice must be retained as part of this
|
2101 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
2102 |
|
|
-- reserved.
|
2103 |
|
|
-------------------------------------------------------------------
|
2104 |
|
|
library IEEE;
|
2105 |
|
|
use IEEE.std_logic_1164.all;
|
2106 |
|
|
use work.conv_pkg.all;
|
2107 |
|
|
entity convert_func_call is
|
2108 |
|
|
generic (
|
2109 |
|
|
din_width : integer := 16;
|
2110 |
|
|
din_bin_pt : integer := 4;
|
2111 |
|
|
din_arith : integer := xlUnsigned;
|
2112 |
|
|
dout_width : integer := 8;
|
2113 |
|
|
dout_bin_pt : integer := 2;
|
2114 |
|
|
dout_arith : integer := xlUnsigned;
|
2115 |
|
|
quantization : integer := xlTruncate;
|
2116 |
|
|
overflow : integer := xlWrap);
|
2117 |
|
|
port (
|
2118 |
|
|
din : in std_logic_vector (din_width-1 downto 0);
|
2119 |
|
|
result : out std_logic_vector (dout_width-1 downto 0));
|
2120 |
|
|
end convert_func_call;
|
2121 |
|
|
architecture behavior of convert_func_call is
|
2122 |
|
|
begin
|
2123 |
|
|
result <= convert_type(din, din_width, din_bin_pt, din_arith,
|
2124 |
|
|
dout_width, dout_bin_pt, dout_arith,
|
2125 |
|
|
quantization, overflow);
|
2126 |
|
|
end behavior;
|
2127 |
|
|
library IEEE;
|
2128 |
|
|
use IEEE.std_logic_1164.all;
|
2129 |
|
|
use work.conv_pkg.all;
|
2130 |
|
|
entity xlconvert is
|
2131 |
|
|
generic (
|
2132 |
|
|
din_width : integer := 16;
|
2133 |
|
|
din_bin_pt : integer := 4;
|
2134 |
|
|
din_arith : integer := xlUnsigned;
|
2135 |
|
|
dout_width : integer := 8;
|
2136 |
|
|
dout_bin_pt : integer := 2;
|
2137 |
|
|
dout_arith : integer := xlUnsigned;
|
2138 |
|
|
en_width : integer := 1;
|
2139 |
|
|
en_bin_pt : integer := 0;
|
2140 |
|
|
en_arith : integer := xlUnsigned;
|
2141 |
|
|
bool_conversion : integer :=0;
|
2142 |
|
|
latency : integer := 0;
|
2143 |
|
|
quantization : integer := xlTruncate;
|
2144 |
|
|
overflow : integer := xlWrap);
|
2145 |
|
|
port (
|
2146 |
|
|
din : in std_logic_vector (din_width-1 downto 0);
|
2147 |
|
|
en : in std_logic_vector (en_width-1 downto 0);
|
2148 |
|
|
ce : in std_logic;
|
2149 |
|
|
clr : in std_logic;
|
2150 |
|
|
clk : in std_logic;
|
2151 |
|
|
dout : out std_logic_vector (dout_width-1 downto 0));
|
2152 |
|
|
end xlconvert;
|
2153 |
|
|
architecture behavior of xlconvert is
|
2154 |
|
|
component synth_reg
|
2155 |
|
|
generic (width : integer;
|
2156 |
|
|
latency : integer);
|
2157 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
2158 |
|
|
ce : in std_logic;
|
2159 |
|
|
clr : in std_logic;
|
2160 |
|
|
clk : in std_logic;
|
2161 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
2162 |
|
|
end component;
|
2163 |
|
|
component convert_func_call
|
2164 |
|
|
generic (
|
2165 |
|
|
din_width : integer := 16;
|
2166 |
|
|
din_bin_pt : integer := 4;
|
2167 |
|
|
din_arith : integer := xlUnsigned;
|
2168 |
|
|
dout_width : integer := 8;
|
2169 |
|
|
dout_bin_pt : integer := 2;
|
2170 |
|
|
dout_arith : integer := xlUnsigned;
|
2171 |
|
|
quantization : integer := xlTruncate;
|
2172 |
|
|
overflow : integer := xlWrap);
|
2173 |
|
|
port (
|
2174 |
|
|
din : in std_logic_vector (din_width-1 downto 0);
|
2175 |
|
|
result : out std_logic_vector (dout_width-1 downto 0));
|
2176 |
|
|
end component;
|
2177 |
|
|
-- synopsys translate_off
|
2178 |
|
|
-- synopsys translate_on
|
2179 |
|
|
signal result : std_logic_vector(dout_width-1 downto 0);
|
2180 |
|
|
signal internal_ce : std_logic;
|
2181 |
|
|
begin
|
2182 |
|
|
-- synopsys translate_off
|
2183 |
|
|
-- synopsys translate_on
|
2184 |
|
|
internal_ce <= ce and en(0);
|
2185 |
|
|
|
2186 |
|
|
bool_conversion_generate : if (bool_conversion = 1)
|
2187 |
|
|
generate
|
2188 |
|
|
result <= din;
|
2189 |
|
|
end generate;
|
2190 |
|
|
std_conversion_generate : if (bool_conversion = 0)
|
2191 |
|
|
generate
|
2192 |
|
|
convert : convert_func_call
|
2193 |
|
|
generic map (
|
2194 |
|
|
din_width => din_width,
|
2195 |
|
|
din_bin_pt => din_bin_pt,
|
2196 |
|
|
din_arith => din_arith,
|
2197 |
|
|
dout_width => dout_width,
|
2198 |
|
|
dout_bin_pt => dout_bin_pt,
|
2199 |
|
|
dout_arith => dout_arith,
|
2200 |
|
|
quantization => quantization,
|
2201 |
|
|
overflow => overflow)
|
2202 |
|
|
port map (
|
2203 |
|
|
din => din,
|
2204 |
|
|
result => result);
|
2205 |
|
|
end generate;
|
2206 |
|
|
latency_test : if (latency > 0) generate
|
2207 |
|
|
reg : synth_reg
|
2208 |
|
|
generic map (
|
2209 |
|
|
width => dout_width,
|
2210 |
|
|
latency => latency
|
2211 |
|
|
)
|
2212 |
|
|
port map (
|
2213 |
|
|
i => result,
|
2214 |
|
|
ce => internal_ce,
|
2215 |
|
|
clr => clr,
|
2216 |
|
|
clk => clk,
|
2217 |
|
|
o => dout
|
2218 |
|
|
);
|
2219 |
|
|
end generate;
|
2220 |
|
|
latency0 : if (latency = 0)
|
2221 |
|
|
generate
|
2222 |
|
|
dout <= result;
|
2223 |
|
|
end generate latency0;
|
2224 |
|
|
end behavior;
|
2225 |
|
|
|
2226 |
|
|
-------------------------------------------------------------------
|
2227 |
|
|
-- System Generator version 13.2 VHDL source file.
|
2228 |
|
|
--
|
2229 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
2230 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
2231 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
2232 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
2233 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
2234 |
|
|
-- this text/file solely for design, simulation, implementation and
|
2235 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
2236 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
2237 |
|
|
-- and immediately terminates your license unless covered by a separate
|
2238 |
|
|
-- agreement.
|
2239 |
|
|
--
|
2240 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
2241 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
2242 |
|
|
-- providing this design, code, or information as one possible
|
2243 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
2244 |
|
|
-- making no representation that this implementation is free from any
|
2245 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
2246 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
2247 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
2248 |
|
|
-- implementation, including but not limited to warranties of
|
2249 |
|
|
-- merchantability or fitness for a particular purpose.
|
2250 |
|
|
--
|
2251 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
2252 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
2253 |
|
|
--
|
2254 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
2255 |
|
|
-- sole risk and will be unsupported.
|
2256 |
|
|
--
|
2257 |
|
|
-- This copyright and support notice must be retained as part of this
|
2258 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
2259 |
|
|
-- reserved.
|
2260 |
|
|
-------------------------------------------------------------------
|
2261 |
|
|
-- synopsys translate_off
|
2262 |
|
|
library XilinxCoreLib;
|
2263 |
|
|
-- synopsys translate_on
|
2264 |
|
|
library IEEE;
|
2265 |
|
|
use IEEE.std_logic_1164.all;
|
2266 |
|
|
use work.conv_pkg.all;
|
2267 |
|
|
entity xlcounter_free is
|
2268 |
|
|
generic (
|
2269 |
|
|
core_name0: string := "";
|
2270 |
|
|
op_width: integer := 5;
|
2271 |
|
|
op_arith: integer := xlSigned
|
2272 |
|
|
);
|
2273 |
|
|
port (
|
2274 |
|
|
ce: in std_logic;
|
2275 |
|
|
clr: in std_logic;
|
2276 |
|
|
clk: in std_logic;
|
2277 |
|
|
op: out std_logic_vector(op_width - 1 downto 0);
|
2278 |
|
|
up: in std_logic_vector(0 downto 0) := (others => '0');
|
2279 |
|
|
load: in std_logic_vector(0 downto 0) := (others => '0');
|
2280 |
|
|
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
|
2281 |
|
|
en: in std_logic_vector(0 downto 0);
|
2282 |
|
|
rst: in std_logic_vector(0 downto 0)
|
2283 |
|
|
);
|
2284 |
|
|
end xlcounter_free ;
|
2285 |
|
|
architecture behavior of xlcounter_free is
|
2286 |
|
|
component cntr_11_0_341fbb8cfa0e669e
|
2287 |
|
|
port (
|
2288 |
|
|
clk: in std_logic;
|
2289 |
|
|
ce: in std_logic;
|
2290 |
|
|
SINIT: in std_logic;
|
2291 |
|
|
q: out std_logic_vector(op_width - 1 downto 0)
|
2292 |
|
|
);
|
2293 |
|
|
end component;
|
2294 |
|
|
attribute syn_black_box of cntr_11_0_341fbb8cfa0e669e:
|
2295 |
|
|
component is true;
|
2296 |
|
|
attribute fpga_dont_touch of cntr_11_0_341fbb8cfa0e669e:
|
2297 |
|
|
component is "true";
|
2298 |
|
|
attribute box_type of cntr_11_0_341fbb8cfa0e669e:
|
2299 |
|
|
component is "black_box";
|
2300 |
|
|
-- synopsys translate_off
|
2301 |
|
|
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
|
2302 |
|
|
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
|
2303 |
|
|
constant zeroStr: string(1 to op_width) :=
|
2304 |
|
|
std_logic_vector_to_bin_string(zeroVec);
|
2305 |
|
|
constant oneStr: string(1 to op_width) :=
|
2306 |
|
|
std_logic_vector_to_bin_string(oneVec);
|
2307 |
|
|
-- synopsys translate_on
|
2308 |
|
|
signal core_sinit: std_logic;
|
2309 |
|
|
signal core_ce: std_logic;
|
2310 |
|
|
signal op_net: std_logic_vector(op_width - 1 downto 0);
|
2311 |
|
|
begin
|
2312 |
|
|
core_ce <= ce and en(0);
|
2313 |
|
|
core_sinit <= (clr or rst(0)) and ce;
|
2314 |
|
|
op <= op_net;
|
2315 |
|
|
comp0: if ((core_name0 = "cntr_11_0_341fbb8cfa0e669e")) generate
|
2316 |
|
|
core_instance0: cntr_11_0_341fbb8cfa0e669e
|
2317 |
|
|
port map (
|
2318 |
|
|
clk => clk,
|
2319 |
|
|
ce => core_ce,
|
2320 |
|
|
SINIT => core_sinit,
|
2321 |
|
|
q => op_net
|
2322 |
|
|
);
|
2323 |
|
|
end generate;
|
2324 |
|
|
end behavior;
|
2325 |
|
|
library IEEE;
|
2326 |
|
|
use IEEE.std_logic_1164.all;
|
2327 |
|
|
use IEEE.numeric_std.all;
|
2328 |
|
|
use work.conv_pkg.all;
|
2329 |
|
|
|
2330 |
|
|
entity inverter_e5b38cca3b is
|
2331 |
|
|
port (
|
2332 |
|
|
ip : in std_logic_vector((1 - 1) downto 0);
|
2333 |
|
|
op : out std_logic_vector((1 - 1) downto 0);
|
2334 |
|
|
clk : in std_logic;
|
2335 |
|
|
ce : in std_logic;
|
2336 |
|
|
clr : in std_logic);
|
2337 |
|
|
end inverter_e5b38cca3b;
|
2338 |
|
|
|
2339 |
|
|
|
2340 |
|
|
architecture behavior of inverter_e5b38cca3b is
|
2341 |
|
|
signal ip_1_26: boolean;
|
2342 |
|
|
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
|
2343 |
|
|
signal op_mem_22_20: array_type_op_mem_22_20 := (
|
2344 |
|
|
|
2345 |
|
|
signal op_mem_22_20_front_din: boolean;
|
2346 |
|
|
signal op_mem_22_20_back: boolean;
|
2347 |
|
|
signal op_mem_22_20_push_front_pop_back_en: std_logic;
|
2348 |
|
|
signal internal_ip_12_1_bitnot: boolean;
|
2349 |
|
|
begin
|
2350 |
|
|
ip_1_26 <= ((ip) = "1");
|
2351 |
|
|
op_mem_22_20_back <= op_mem_22_20(0);
|
2352 |
|
|
proc_op_mem_22_20: process (clk)
|
2353 |
|
|
is
|
2354 |
|
|
variable i: integer;
|
2355 |
|
|
begin
|
2356 |
|
|
if (clk'event and (clk = '1')) then
|
2357 |
|
|
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
|
2358 |
|
|
op_mem_22_20(0) <= op_mem_22_20_front_din;
|
2359 |
|
|
end if;
|
2360 |
|
|
end if;
|
2361 |
|
|
end process proc_op_mem_22_20;
|
2362 |
|
|
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
|
2363 |
|
|
op_mem_22_20_push_front_pop_back_en <= '0';
|
2364 |
|
|
op <= boolean_to_vector(internal_ip_12_1_bitnot);
|
2365 |
|
|
end behavior;
|
2366 |
|
|
|
2367 |
|
|
library IEEE;
|
2368 |
|
|
use IEEE.std_logic_1164.all;
|
2369 |
|
|
use IEEE.numeric_std.all;
|
2370 |
|
|
use work.conv_pkg.all;
|
2371 |
|
|
|
2372 |
|
|
entity logical_80f90b97d0 is
|
2373 |
|
|
port (
|
2374 |
|
|
d0 : in std_logic_vector((1 - 1) downto 0);
|
2375 |
|
|
d1 : in std_logic_vector((1 - 1) downto 0);
|
2376 |
|
|
y : out std_logic_vector((1 - 1) downto 0);
|
2377 |
|
|
clk : in std_logic;
|
2378 |
|
|
ce : in std_logic;
|
2379 |
|
|
clr : in std_logic);
|
2380 |
|
|
end logical_80f90b97d0;
|
2381 |
|
|
|
2382 |
|
|
|
2383 |
|
|
architecture behavior of logical_80f90b97d0 is
|
2384 |
|
|
signal d0_1_24: std_logic;
|
2385 |
|
|
signal d1_1_27: std_logic;
|
2386 |
|
|
signal fully_2_1_bit: std_logic;
|
2387 |
|
|
begin
|
2388 |
|
|
d0_1_24 <= d0(0);
|
2389 |
|
|
d1_1_27 <= d1(0);
|
2390 |
|
|
fully_2_1_bit <= d0_1_24 and d1_1_27;
|
2391 |
|
|
y <= std_logic_to_vector(fully_2_1_bit);
|
2392 |
|
|
end behavior;
|
2393 |
|
|
|
2394 |
|
|
|
2395 |
|
|
-------------------------------------------------------------------
|
2396 |
|
|
-- System Generator version 13.2 VHDL source file.
|
2397 |
|
|
--
|
2398 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
2399 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
2400 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
2401 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
2402 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
2403 |
|
|
-- this text/file solely for design, simulation, implementation and
|
2404 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
2405 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
2406 |
|
|
-- and immediately terminates your license unless covered by a separate
|
2407 |
|
|
-- agreement.
|
2408 |
|
|
--
|
2409 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
2410 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
2411 |
|
|
-- providing this design, code, or information as one possible
|
2412 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
2413 |
|
|
-- making no representation that this implementation is free from any
|
2414 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
2415 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
2416 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
2417 |
|
|
-- implementation, including but not limited to warranties of
|
2418 |
|
|
-- merchantability or fitness for a particular purpose.
|
2419 |
|
|
--
|
2420 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
2421 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
2422 |
|
|
--
|
2423 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
2424 |
|
|
-- sole risk and will be unsupported.
|
2425 |
|
|
--
|
2426 |
|
|
-- This copyright and support notice must be retained as part of this
|
2427 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
2428 |
|
|
-- reserved.
|
2429 |
|
|
-------------------------------------------------------------------
|
2430 |
|
|
library IEEE;
|
2431 |
|
|
use IEEE.std_logic_1164.all;
|
2432 |
|
|
use work.conv_pkg.all;
|
2433 |
|
|
entity xlregister is
|
2434 |
|
|
generic (d_width : integer := 5;
|
2435 |
|
|
init_value : bit_vector := b"00");
|
2436 |
|
|
port (d : in std_logic_vector (d_width-1 downto 0);
|
2437 |
|
|
rst : in std_logic_vector(0 downto 0) := "0";
|
2438 |
|
|
en : in std_logic_vector(0 downto 0) := "1";
|
2439 |
|
|
ce : in std_logic;
|
2440 |
|
|
clk : in std_logic;
|
2441 |
|
|
q : out std_logic_vector (d_width-1 downto 0));
|
2442 |
|
|
end xlregister;
|
2443 |
|
|
architecture behavior of xlregister is
|
2444 |
|
|
component synth_reg_w_init
|
2445 |
|
|
generic (width : integer;
|
2446 |
|
|
init_index : integer;
|
2447 |
|
|
init_value : bit_vector;
|
2448 |
|
|
latency : integer);
|
2449 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
2450 |
|
|
ce : in std_logic;
|
2451 |
|
|
clr : in std_logic;
|
2452 |
|
|
clk : in std_logic;
|
2453 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
2454 |
|
|
end component;
|
2455 |
|
|
-- synopsys translate_off
|
2456 |
|
|
signal real_d, real_q : real;
|
2457 |
|
|
-- synopsys translate_on
|
2458 |
|
|
signal internal_clr : std_logic;
|
2459 |
|
|
signal internal_ce : std_logic;
|
2460 |
|
|
begin
|
2461 |
|
|
internal_clr <= rst(0) and ce;
|
2462 |
|
|
internal_ce <= en(0) and ce;
|
2463 |
|
|
synth_reg_inst : synth_reg_w_init
|
2464 |
|
|
generic map (width => d_width,
|
2465 |
|
|
init_index => 2,
|
2466 |
|
|
init_value => init_value,
|
2467 |
|
|
latency => 1)
|
2468 |
|
|
port map (i => d,
|
2469 |
|
|
ce => internal_ce,
|
2470 |
|
|
clr => internal_clr,
|
2471 |
|
|
clk => clk,
|
2472 |
|
|
o => q);
|
2473 |
|
|
end architecture behavior;
|
2474 |
|
|
|
2475 |
|
|
-------------------------------------------------------------------
|
2476 |
|
|
-- System Generator version 13.2 VHDL source file.
|
2477 |
|
|
--
|
2478 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
2479 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
2480 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
2481 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
2482 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
2483 |
|
|
-- this text/file solely for design, simulation, implementation and
|
2484 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
2485 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
2486 |
|
|
-- and immediately terminates your license unless covered by a separate
|
2487 |
|
|
-- agreement.
|
2488 |
|
|
--
|
2489 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
2490 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
2491 |
|
|
-- providing this design, code, or information as one possible
|
2492 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
2493 |
|
|
-- making no representation that this implementation is free from any
|
2494 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
2495 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
2496 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
2497 |
|
|
-- implementation, including but not limited to warranties of
|
2498 |
|
|
-- merchantability or fitness for a particular purpose.
|
2499 |
|
|
--
|
2500 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
2501 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
2502 |
|
|
--
|
2503 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
2504 |
|
|
-- sole risk and will be unsupported.
|
2505 |
|
|
--
|
2506 |
|
|
-- This copyright and support notice must be retained as part of this
|
2507 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
2508 |
|
|
-- reserved.
|
2509 |
|
|
-------------------------------------------------------------------
|
2510 |
|
|
library IEEE;
|
2511 |
|
|
use IEEE.std_logic_1164.all;
|
2512 |
|
|
entity xlchipscope is
|
2513 |
|
|
port (
|
2514 |
|
|
trig0 : in std_logic_vector(12-1 downto 0);
|
2515 |
|
|
trig1 : in std_logic_vector(64-1 downto 0);
|
2516 |
|
|
trig2 : in std_logic_vector(1-1 downto 0);
|
2517 |
|
|
trig3 : in std_logic_vector(1-1 downto 0);
|
2518 |
|
|
trig4 : in std_logic_vector(1-1 downto 0);
|
2519 |
|
|
trig5 : in std_logic_vector(72-1 downto 0);
|
2520 |
|
|
trig6 : in std_logic_vector(1-1 downto 0);
|
2521 |
|
|
trig7 : in std_logic_vector(15-1 downto 0);
|
2522 |
|
|
trig8 : in std_logic_vector(1-1 downto 0);
|
2523 |
|
|
trig9 : in std_logic_vector(1-1 downto 0);
|
2524 |
|
|
trig10 : in std_logic_vector(15-1 downto 0);
|
2525 |
|
|
|
2526 |
|
|
|
2527 |
|
|
ce : in std_logic;
|
2528 |
|
|
clr : in std_logic;
|
2529 |
|
|
clk : in std_logic);
|
2530 |
|
|
end xlchipscope;
|
2531 |
|
|
architecture behavior of xlchipscope is
|
2532 |
|
|
attribute syn_noprune : boolean;
|
2533 |
|
|
attribute syn_black_box : boolean;
|
2534 |
|
|
attribute box_type : string;
|
2535 |
|
|
attribute syn_noprune of behavior : architecture is true;
|
2536 |
|
|
signal data : std_logic_vector (184-1 downto 0);
|
2537 |
|
|
signal control : std_logic_vector (35 downto 0);
|
2538 |
|
|
component ila_1_05_a_b6735eb4b876dee5
|
2539 |
|
|
port (control : inout std_logic_vector(35 downto 0);
|
2540 |
|
|
trig0 : in std_logic_vector(12-1 downto 0);
|
2541 |
|
|
trig1 : in std_logic_vector(64-1 downto 0);
|
2542 |
|
|
trig2 : in std_logic_vector(1-1 downto 0);
|
2543 |
|
|
trig3 : in std_logic_vector(1-1 downto 0);
|
2544 |
|
|
trig4 : in std_logic_vector(1-1 downto 0);
|
2545 |
|
|
trig5 : in std_logic_vector(72-1 downto 0);
|
2546 |
|
|
trig6 : in std_logic_vector(1-1 downto 0);
|
2547 |
|
|
trig7 : in std_logic_vector(15-1 downto 0);
|
2548 |
|
|
trig8 : in std_logic_vector(1-1 downto 0);
|
2549 |
|
|
trig9 : in std_logic_vector(1-1 downto 0);
|
2550 |
|
|
trig10 : in std_logic_vector(15-1 downto 0);
|
2551 |
|
|
|
2552 |
|
|
clk : in std_logic
|
2553 |
|
|
);
|
2554 |
|
|
end component;
|
2555 |
|
|
attribute syn_black_box of ila_1_05_a_b6735eb4b876dee5 : component is TRUE;
|
2556 |
|
|
attribute box_type of ila_1_05_a_b6735eb4b876dee5 : component is "black_box";
|
2557 |
|
|
attribute syn_noprune of ila_1_05_a_b6735eb4b876dee5 : component is TRUE;
|
2558 |
|
|
component icon_1_06_a_87e2f476e984e565
|
2559 |
|
|
port (control0 : inout std_logic_vector(35 downto 0)
|
2560 |
|
|
);
|
2561 |
|
|
end component;
|
2562 |
|
|
attribute syn_black_box of icon_1_06_a_87e2f476e984e565 : component is TRUE;
|
2563 |
|
|
attribute box_type of icon_1_06_a_87e2f476e984e565 : component is "black_box";
|
2564 |
|
|
attribute syn_noprune of icon_1_06_a_87e2f476e984e565 : component is TRUE;
|
2565 |
|
|
|
2566 |
|
|
begin
|
2567 |
|
|
|
2568 |
|
|
i_ila : ila_1_05_a_b6735eb4b876dee5
|
2569 |
|
|
port map
|
2570 |
|
|
( control => control,
|
2571 |
|
|
trig0 => trig0,
|
2572 |
|
|
trig1 => trig1,
|
2573 |
|
|
trig2 => trig2,
|
2574 |
|
|
trig3 => trig3,
|
2575 |
|
|
trig4 => trig4,
|
2576 |
|
|
trig5 => trig5,
|
2577 |
|
|
trig6 => trig6,
|
2578 |
|
|
trig7 => trig7,
|
2579 |
|
|
trig8 => trig8,
|
2580 |
|
|
trig9 => trig9,
|
2581 |
|
|
trig10 => trig10,
|
2582 |
|
|
clk => clk
|
2583 |
|
|
);
|
2584 |
|
|
i_icon_for_syn : icon_1_06_a_87e2f476e984e565
|
2585 |
|
|
port map
|
2586 |
|
|
(
|
2587 |
|
|
control0 => control
|
2588 |
|
|
);
|
2589 |
|
|
end architecture behavior;
|
2590 |
|
|
library IEEE;
|
2591 |
|
|
use IEEE.std_logic_1164.all;
|
2592 |
|
|
use work.conv_pkg.all;
|
2593 |
|
|
|
2594 |
|
|
-- Generated from Simulink block "USER_LOGIC"
|
2595 |
|
|
|
2596 |
|
|
entity user_logic is
|
2597 |
|
|
port (
|
2598 |
|
|
bram_rd_dout: in std_logic_vector(63 downto 0);
|
2599 |
|
|
ce_1: in std_logic;
|
2600 |
|
|
clk_1: in std_logic;
|
2601 |
|
|
data_out_x1: in std_logic;
|
2602 |
|
|
data_out_x12: in std_logic_vector(31 downto 0);
|
2603 |
|
|
data_out_x13: in std_logic;
|
2604 |
|
|
data_out_x14: in std_logic_vector(31 downto 0);
|
2605 |
|
|
data_out_x15: in std_logic;
|
2606 |
|
|
data_out_x16: in std_logic_vector(31 downto 0);
|
2607 |
|
|
data_out_x17: in std_logic;
|
2608 |
|
|
data_out_x18: in std_logic_vector(31 downto 0);
|
2609 |
|
|
data_out_x19: in std_logic;
|
2610 |
|
|
data_out_x2: in std_logic_vector(31 downto 0);
|
2611 |
|
|
data_out_x20: in std_logic_vector(31 downto 0);
|
2612 |
|
|
data_out_x21: in std_logic;
|
2613 |
|
|
data_out_x22: in std_logic_vector(31 downto 0);
|
2614 |
|
|
data_out_x23: in std_logic_vector(31 downto 0);
|
2615 |
|
|
data_out_x24: in std_logic;
|
2616 |
|
|
data_out_x25: in std_logic_vector(31 downto 0);
|
2617 |
|
|
data_out_x26: in std_logic;
|
2618 |
|
|
data_out_x27: in std_logic;
|
2619 |
|
|
data_out_x28: in std_logic_vector(31 downto 0);
|
2620 |
|
|
data_out_x29: in std_logic;
|
2621 |
|
|
data_out_x3: in std_logic;
|
2622 |
|
|
data_out_x30: in std_logic_vector(31 downto 0);
|
2623 |
|
|
data_out_x31: in std_logic;
|
2624 |
|
|
data_out_x32: in std_logic_vector(31 downto 0);
|
2625 |
|
|
data_out_x4: in std_logic_vector(31 downto 0);
|
2626 |
|
|
data_out_x5: in std_logic;
|
2627 |
|
|
data_out_x8: in std_logic_vector(31 downto 0);
|
2628 |
|
|
data_out_x9: in std_logic;
|
2629 |
|
|
fifo_rd_count_x0: in std_logic_vector(14 downto 0);
|
2630 |
|
|
fifo_rd_dout: in std_logic_vector(71 downto 0);
|
2631 |
|
|
fifo_rd_empty: in std_logic;
|
2632 |
|
|
fifo_rd_pempty_x0: in std_logic;
|
2633 |
|
|
fifo_rd_valid: in std_logic;
|
2634 |
|
|
fifo_wr_count_x0: in std_logic_vector(14 downto 0);
|
2635 |
|
|
fifo_wr_full_x0: in std_logic;
|
2636 |
|
|
fifo_wr_pfull_x0: in std_logic;
|
2637 |
|
|
rst_i: in std_logic;
|
2638 |
|
|
bram_rd_addr: out std_logic_vector(11 downto 0);
|
2639 |
|
|
bram_wr_addr: out std_logic_vector(11 downto 0);
|
2640 |
|
|
bram_wr_din: out std_logic_vector(63 downto 0);
|
2641 |
|
|
bram_wr_en: out std_logic_vector(7 downto 0);
|
2642 |
|
|
data_in: out std_logic_vector(31 downto 0);
|
2643 |
|
|
data_in_x0: out std_logic;
|
2644 |
|
|
data_in_x1: out std_logic;
|
2645 |
|
|
data_in_x10: out std_logic_vector(31 downto 0);
|
2646 |
|
|
data_in_x11: out std_logic_vector(31 downto 0);
|
2647 |
|
|
data_in_x12: out std_logic;
|
2648 |
|
|
data_in_x13: out std_logic_vector(31 downto 0);
|
2649 |
|
|
data_in_x14: out std_logic;
|
2650 |
|
|
data_in_x15: out std_logic_vector(31 downto 0);
|
2651 |
|
|
data_in_x16: out std_logic;
|
2652 |
|
|
data_in_x17: out std_logic_vector(31 downto 0);
|
2653 |
|
|
data_in_x18: out std_logic;
|
2654 |
|
|
data_in_x19: out std_logic_vector(31 downto 0);
|
2655 |
|
|
data_in_x2: out std_logic;
|
2656 |
|
|
data_in_x20: out std_logic_vector(31 downto 0);
|
2657 |
|
|
data_in_x21: out std_logic;
|
2658 |
|
|
data_in_x22: out std_logic;
|
2659 |
|
|
data_in_x23: out std_logic_vector(31 downto 0);
|
2660 |
|
|
data_in_x24: out std_logic;
|
2661 |
|
|
data_in_x25: out std_logic_vector(31 downto 0);
|
2662 |
|
|
data_in_x26: out std_logic_vector(31 downto 0);
|
2663 |
|
|
data_in_x3: out std_logic;
|
2664 |
|
|
data_in_x4: out std_logic_vector(31 downto 0);
|
2665 |
|
|
data_in_x5: out std_logic;
|
2666 |
|
|
data_in_x6: out std_logic_vector(31 downto 0);
|
2667 |
|
|
data_in_x7: out std_logic;
|
2668 |
|
|
data_in_x8: out std_logic_vector(31 downto 0);
|
2669 |
|
|
data_in_x9: out std_logic;
|
2670 |
|
|
en: out std_logic;
|
2671 |
|
|
en_x0: out std_logic;
|
2672 |
|
|
en_x1: out std_logic;
|
2673 |
|
|
en_x10: out std_logic;
|
2674 |
|
|
en_x11: out std_logic;
|
2675 |
|
|
en_x12: out std_logic;
|
2676 |
|
|
en_x13: out std_logic;
|
2677 |
|
|
en_x14: out std_logic;
|
2678 |
|
|
en_x15: out std_logic;
|
2679 |
|
|
en_x16: out std_logic;
|
2680 |
|
|
en_x17: out std_logic;
|
2681 |
|
|
en_x18: out std_logic;
|
2682 |
|
|
en_x19: out std_logic;
|
2683 |
|
|
en_x2: out std_logic;
|
2684 |
|
|
en_x20: out std_logic;
|
2685 |
|
|
en_x21: out std_logic;
|
2686 |
|
|
en_x22: out std_logic;
|
2687 |
|
|
en_x23: out std_logic;
|
2688 |
|
|
en_x24: out std_logic;
|
2689 |
|
|
en_x25: out std_logic;
|
2690 |
|
|
en_x26: out std_logic;
|
2691 |
|
|
en_x3: out std_logic;
|
2692 |
|
|
en_x4: out std_logic;
|
2693 |
|
|
en_x5: out std_logic;
|
2694 |
|
|
en_x6: out std_logic;
|
2695 |
|
|
en_x7: out std_logic;
|
2696 |
|
|
en_x8: out std_logic;
|
2697 |
|
|
en_x9: out std_logic;
|
2698 |
|
|
fifo_rd_en_x1: out std_logic;
|
2699 |
|
|
fifo_wr_din: out std_logic_vector(71 downto 0);
|
2700 |
|
|
fifo_wr_en_x0: out std_logic;
|
2701 |
|
|
rst_o: out std_logic;
|
2702 |
|
|
user_int_1o: out std_logic;
|
2703 |
|
|
user_int_2o: out std_logic;
|
2704 |
|
|
user_int_3o: out std_logic
|
2705 |
|
|
);
|
2706 |
|
|
end user_logic;
|
2707 |
|
|
|
2708 |
|
|
architecture structural of user_logic is
|
2709 |
|
|
attribute core_generation_info: string;
|
2710 |
|
|
attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=351,xilinx_chipscope_block=1,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=89,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}";
|
2711 |
|
|
|
2712 |
|
|
signal bram_addr: std_logic_vector(11 downto 0);
|
2713 |
|
|
signal bram_addr_x0: std_logic_vector(11 downto 0);
|
2714 |
|
|
signal bram_data: std_logic_vector(63 downto 0);
|
2715 |
|
|
signal bram_rd_addr_net: std_logic_vector(11 downto 0);
|
2716 |
|
|
signal bram_rd_dout_net: std_logic_vector(63 downto 0);
|
2717 |
|
|
signal bram_wr_addr_net: std_logic_vector(11 downto 0);
|
2718 |
|
|
signal bram_wr_din_net: std_logic_vector(63 downto 0);
|
2719 |
|
|
signal bram_wr_en_net: std_logic_vector(7 downto 0);
|
2720 |
|
|
signal ce_1_sg_x0: std_logic;
|
2721 |
|
|
signal clk_1_sg_x0: std_logic;
|
2722 |
|
|
signal constant10_op_net: std_logic;
|
2723 |
|
|
signal constant11_op_net: std_logic;
|
2724 |
|
|
signal constant12_op_net: std_logic;
|
2725 |
|
|
signal constant14_op_net: std_logic;
|
2726 |
|
|
signal constant15_op_net: std_logic;
|
2727 |
|
|
signal constant19_op_net: std_logic;
|
2728 |
|
|
signal constant1_op_net: std_logic;
|
2729 |
|
|
signal constant20_op_net: std_logic;
|
2730 |
|
|
signal constant21_op_net: std_logic;
|
2731 |
|
|
signal constant22_op_net: std_logic;
|
2732 |
|
|
signal constant23_op_net: std_logic;
|
2733 |
|
|
signal constant24_op_net: std_logic;
|
2734 |
|
|
signal constant25_op_net: std_logic;
|
2735 |
|
|
signal constant26_op_net: std_logic;
|
2736 |
|
|
signal constant2_op_net: std_logic_vector(7 downto 0);
|
2737 |
|
|
signal constant3_op_net: std_logic;
|
2738 |
|
|
signal constant4_op_net: std_logic;
|
2739 |
|
|
signal constant6_op_net_x0: std_logic;
|
2740 |
|
|
signal constant7_op_net: std_logic;
|
2741 |
|
|
signal constant8_op_net: std_logic;
|
2742 |
|
|
signal constant9_op_net: std_logic;
|
2743 |
|
|
signal convert11_dout_net: std_logic;
|
2744 |
|
|
signal convert12_dout_net: std_logic;
|
2745 |
|
|
signal convert14_dout_net: std_logic;
|
2746 |
|
|
signal convert15_dout_net: std_logic;
|
2747 |
|
|
signal convert16_dout_net: std_logic;
|
2748 |
|
|
signal convert17_dout_net: std_logic;
|
2749 |
|
|
signal convert1_dout_net: std_logic;
|
2750 |
|
|
signal convert4_dout_net: std_logic;
|
2751 |
|
|
signal convert5_dout_net: std_logic;
|
2752 |
|
|
signal convert6_dout_net: std_logic;
|
2753 |
|
|
signal convert7_dout_net: std_logic;
|
2754 |
|
|
signal convert8_dout_net: std_logic;
|
2755 |
|
|
signal counter4_op_net: std_logic_vector(11 downto 0);
|
2756 |
|
|
signal data_in_net: std_logic_vector(31 downto 0);
|
2757 |
|
|
signal data_in_x0_net: std_logic;
|
2758 |
|
|
signal data_in_x10_net: std_logic_vector(31 downto 0);
|
2759 |
|
|
signal data_in_x11_net: std_logic_vector(31 downto 0);
|
2760 |
|
|
signal data_in_x12_net: std_logic;
|
2761 |
|
|
signal data_in_x13_net: std_logic_vector(31 downto 0);
|
2762 |
|
|
signal data_in_x14_net: std_logic;
|
2763 |
|
|
signal data_in_x15_net: std_logic_vector(31 downto 0);
|
2764 |
|
|
signal data_in_x16_net: std_logic;
|
2765 |
|
|
signal data_in_x17_net: std_logic_vector(31 downto 0);
|
2766 |
|
|
signal data_in_x18_net: std_logic;
|
2767 |
|
|
signal data_in_x19_net: std_logic_vector(31 downto 0);
|
2768 |
|
|
signal data_in_x1_net: std_logic;
|
2769 |
|
|
signal data_in_x20_net: std_logic_vector(31 downto 0);
|
2770 |
|
|
signal data_in_x21_net: std_logic;
|
2771 |
|
|
signal data_in_x22_net: std_logic;
|
2772 |
|
|
signal data_in_x23_net: std_logic_vector(31 downto 0);
|
2773 |
|
|
signal data_in_x24_net: std_logic;
|
2774 |
|
|
signal data_in_x25_net: std_logic_vector(31 downto 0);
|
2775 |
|
|
signal data_in_x26_net: std_logic_vector(31 downto 0);
|
2776 |
|
|
signal data_in_x2_net: std_logic;
|
2777 |
|
|
signal data_in_x3_net: std_logic;
|
2778 |
|
|
signal data_in_x4_net: std_logic_vector(31 downto 0);
|
2779 |
|
|
signal data_in_x5_net: std_logic;
|
2780 |
|
|
signal data_in_x6_net: std_logic_vector(31 downto 0);
|
2781 |
|
|
signal data_in_x7_net: std_logic;
|
2782 |
|
|
signal data_in_x8_net: std_logic_vector(31 downto 0);
|
2783 |
|
|
signal data_in_x9_net: std_logic;
|
2784 |
|
|
signal data_out_x12_net: std_logic_vector(31 downto 0);
|
2785 |
|
|
signal data_out_x13_net: std_logic;
|
2786 |
|
|
signal data_out_x14_net: std_logic_vector(31 downto 0);
|
2787 |
|
|
signal data_out_x15_net: std_logic;
|
2788 |
|
|
signal data_out_x16_net: std_logic_vector(31 downto 0);
|
2789 |
|
|
signal data_out_x17_net: std_logic;
|
2790 |
|
|
signal data_out_x18_net: std_logic_vector(31 downto 0);
|
2791 |
|
|
signal data_out_x19_net: std_logic;
|
2792 |
|
|
signal data_out_x1_net: std_logic;
|
2793 |
|
|
signal data_out_x20_net: std_logic_vector(31 downto 0);
|
2794 |
|
|
signal data_out_x21_net: std_logic;
|
2795 |
|
|
signal data_out_x22_net: std_logic_vector(31 downto 0);
|
2796 |
|
|
signal data_out_x23_net: std_logic_vector(31 downto 0);
|
2797 |
|
|
signal data_out_x24_net: std_logic;
|
2798 |
|
|
signal data_out_x25_net: std_logic_vector(31 downto 0);
|
2799 |
|
|
signal data_out_x26_net: std_logic;
|
2800 |
|
|
signal data_out_x27_net: std_logic;
|
2801 |
|
|
signal data_out_x28_net: std_logic_vector(31 downto 0);
|
2802 |
|
|
signal data_out_x29_net: std_logic;
|
2803 |
|
|
signal data_out_x2_net: std_logic_vector(31 downto 0);
|
2804 |
|
|
signal data_out_x30_net: std_logic_vector(31 downto 0);
|
2805 |
|
|
signal data_out_x31_net: std_logic;
|
2806 |
|
|
signal data_out_x32_net: std_logic_vector(31 downto 0);
|
2807 |
|
|
signal data_out_x3_net: std_logic;
|
2808 |
|
|
signal data_out_x4_net: std_logic_vector(31 downto 0);
|
2809 |
|
|
signal data_out_x5_net: std_logic;
|
2810 |
|
|
signal data_out_x8_net: std_logic_vector(31 downto 0);
|
2811 |
|
|
signal data_out_x9_net: std_logic;
|
2812 |
|
|
signal dinb: std_logic_vector(31 downto 0);
|
2813 |
|
|
signal dinb_x0: std_logic_vector(31 downto 0);
|
2814 |
|
|
signal fifo_data_in_out: std_logic_vector(71 downto 0);
|
2815 |
|
|
signal fifo_empty: std_logic;
|
2816 |
|
|
signal fifo_empty_x0: std_logic;
|
2817 |
|
|
signal fifo_rd_count: std_logic_vector(14 downto 0);
|
2818 |
|
|
signal fifo_rd_count_net: std_logic_vector(14 downto 0);
|
2819 |
|
|
signal fifo_rd_dout_net: std_logic_vector(71 downto 0);
|
2820 |
|
|
signal fifo_rd_empty_net: std_logic;
|
2821 |
|
|
signal fifo_rd_en: std_logic;
|
2822 |
|
|
signal fifo_rd_en_net: std_logic;
|
2823 |
|
|
signal fifo_rd_en_x0: std_logic;
|
2824 |
|
|
signal fifo_rd_pempty: std_logic;
|
2825 |
|
|
signal fifo_rd_pempty_net: std_logic;
|
2826 |
|
|
signal fifo_rd_valid_net: std_logic;
|
2827 |
|
|
signal fifo_wr_count: std_logic_vector(14 downto 0);
|
2828 |
|
|
signal fifo_wr_count_net: std_logic_vector(14 downto 0);
|
2829 |
|
|
signal fifo_wr_din_net: std_logic_vector(71 downto 0);
|
2830 |
|
|
signal fifo_wr_en: std_logic;
|
2831 |
|
|
signal fifo_wr_en_net: std_logic;
|
2832 |
|
|
signal fifo_wr_full: std_logic;
|
2833 |
|
|
signal fifo_wr_full_net: std_logic;
|
2834 |
|
|
signal fifo_wr_pfull: std_logic;
|
2835 |
|
|
signal fifo_wr_pfull_net: std_logic;
|
2836 |
|
|
signal inverter3_op_net: std_logic;
|
2837 |
|
|
signal inverter5_op_net: std_logic;
|
2838 |
|
|
signal rst_i_net: std_logic;
|
2839 |
|
|
signal rst_o_net: std_logic;
|
2840 |
|
|
signal timecountreset: std_logic;
|
2841 |
|
|
signal timecounttrigger: std_logic;
|
2842 |
|
|
signal tx_en_in107_q_net: std_logic;
|
2843 |
|
|
signal tx_en_in116_q_net: std_logic;
|
2844 |
|
|
signal tx_en_in117_q_net: std_logic_vector(31 downto 0);
|
2845 |
|
|
signal tx_en_in119_q_net: std_logic;
|
2846 |
|
|
signal tx_en_in120_q_net: std_logic_vector(31 downto 0);
|
2847 |
|
|
signal tx_en_in123_q_net: std_logic;
|
2848 |
|
|
signal tx_en_in124_q_net: std_logic_vector(31 downto 0);
|
2849 |
|
|
signal tx_en_in127_q_net: std_logic;
|
2850 |
|
|
signal tx_en_in128_q_net: std_logic_vector(31 downto 0);
|
2851 |
|
|
signal tx_en_in12_q_net: std_logic_vector(31 downto 0);
|
2852 |
|
|
signal tx_en_in17_q_net: std_logic_vector(11 downto 0);
|
2853 |
|
|
signal tx_en_in18_q_net: std_logic_vector(7 downto 0);
|
2854 |
|
|
signal tx_en_in30_q_net: std_logic_vector(11 downto 0);
|
2855 |
|
|
signal tx_en_in4_q_net: std_logic;
|
2856 |
|
|
signal tx_en_in52_q_net: std_logic_vector(31 downto 0);
|
2857 |
|
|
signal tx_en_in58_q_net: std_logic;
|
2858 |
|
|
signal tx_en_in59_q_net: std_logic;
|
2859 |
|
|
signal tx_en_in5_q_net: std_logic;
|
2860 |
|
|
signal tx_en_in60_q_net: std_logic_vector(31 downto 0);
|
2861 |
|
|
signal tx_en_in61_q_net: std_logic;
|
2862 |
|
|
signal tx_en_in65_q_net: std_logic_vector(31 downto 0);
|
2863 |
|
|
signal tx_en_in67_q_net: std_logic;
|
2864 |
|
|
signal tx_en_in6_q_net: std_logic_vector(31 downto 0);
|
2865 |
|
|
signal tx_en_in86_q_net: std_logic;
|
2866 |
|
|
signal tx_en_in87_q_net: std_logic_vector(31 downto 0);
|
2867 |
|
|
signal tx_en_in89_q_net: std_logic;
|
2868 |
|
|
signal tx_en_in8_q_net: std_logic;
|
2869 |
|
|
signal tx_en_in90_q_net: std_logic_vector(31 downto 0);
|
2870 |
|
|
signal tx_en_in92_q_net: std_logic;
|
2871 |
|
|
signal tx_en_in93_q_net: std_logic_vector(31 downto 0);
|
2872 |
|
|
signal user_int_1o_net: std_logic;
|
2873 |
|
|
signal user_int_2o_net: std_logic;
|
2874 |
|
|
signal user_int_3o_net: std_logic;
|
2875 |
|
|
|
2876 |
|
|
begin
|
2877 |
|
|
bram_rd_dout_net <= bram_rd_dout;
|
2878 |
|
|
ce_1_sg_x0 <= ce_1;
|
2879 |
|
|
clk_1_sg_x0 <= clk_1;
|
2880 |
|
|
data_out_x1_net <= data_out_x1;
|
2881 |
|
|
data_out_x12_net <= data_out_x12;
|
2882 |
|
|
data_out_x13_net <= data_out_x13;
|
2883 |
|
|
data_out_x14_net <= data_out_x14;
|
2884 |
|
|
data_out_x15_net <= data_out_x15;
|
2885 |
|
|
data_out_x16_net <= data_out_x16;
|
2886 |
|
|
data_out_x17_net <= data_out_x17;
|
2887 |
|
|
data_out_x18_net <= data_out_x18;
|
2888 |
|
|
data_out_x19_net <= data_out_x19;
|
2889 |
|
|
data_out_x2_net <= data_out_x2;
|
2890 |
|
|
data_out_x20_net <= data_out_x20;
|
2891 |
|
|
data_out_x21_net <= data_out_x21;
|
2892 |
|
|
data_out_x22_net <= data_out_x22;
|
2893 |
|
|
data_out_x23_net <= data_out_x23;
|
2894 |
|
|
data_out_x24_net <= data_out_x24;
|
2895 |
|
|
data_out_x25_net <= data_out_x25;
|
2896 |
|
|
data_out_x26_net <= data_out_x26;
|
2897 |
|
|
data_out_x27_net <= data_out_x27;
|
2898 |
|
|
data_out_x28_net <= data_out_x28;
|
2899 |
|
|
data_out_x29_net <= data_out_x29;
|
2900 |
|
|
data_out_x3_net <= data_out_x3;
|
2901 |
|
|
data_out_x30_net <= data_out_x30;
|
2902 |
|
|
data_out_x31_net <= data_out_x31;
|
2903 |
|
|
data_out_x32_net <= data_out_x32;
|
2904 |
|
|
data_out_x4_net <= data_out_x4;
|
2905 |
|
|
data_out_x5_net <= data_out_x5;
|
2906 |
|
|
data_out_x8_net <= data_out_x8;
|
2907 |
|
|
data_out_x9_net <= data_out_x9;
|
2908 |
|
|
fifo_rd_count_net <= fifo_rd_count_x0;
|
2909 |
|
|
fifo_rd_dout_net <= fifo_rd_dout;
|
2910 |
|
|
fifo_rd_empty_net <= fifo_rd_empty;
|
2911 |
|
|
fifo_rd_pempty_net <= fifo_rd_pempty_x0;
|
2912 |
|
|
fifo_rd_valid_net <= fifo_rd_valid;
|
2913 |
|
|
fifo_wr_count_net <= fifo_wr_count_x0;
|
2914 |
|
|
fifo_wr_full_net <= fifo_wr_full_x0;
|
2915 |
|
|
fifo_wr_pfull_net <= fifo_wr_pfull_x0;
|
2916 |
|
|
rst_i_net <= rst_i;
|
2917 |
|
|
bram_rd_addr <= bram_rd_addr_net;
|
2918 |
|
|
bram_wr_addr <= bram_wr_addr_net;
|
2919 |
|
|
bram_wr_din <= bram_wr_din_net;
|
2920 |
|
|
bram_wr_en <= bram_wr_en_net;
|
2921 |
|
|
data_in <= data_in_net;
|
2922 |
|
|
data_in_x0 <= data_in_x0_net;
|
2923 |
|
|
data_in_x1 <= data_in_x1_net;
|
2924 |
|
|
data_in_x10 <= data_in_x10_net;
|
2925 |
|
|
data_in_x11 <= data_in_x11_net;
|
2926 |
|
|
data_in_x12 <= data_in_x12_net;
|
2927 |
|
|
data_in_x13 <= data_in_x13_net;
|
2928 |
|
|
data_in_x14 <= data_in_x14_net;
|
2929 |
|
|
data_in_x15 <= data_in_x15_net;
|
2930 |
|
|
data_in_x16 <= data_in_x16_net;
|
2931 |
|
|
data_in_x17 <= data_in_x17_net;
|
2932 |
|
|
data_in_x18 <= data_in_x18_net;
|
2933 |
|
|
data_in_x19 <= data_in_x19_net;
|
2934 |
|
|
data_in_x2 <= data_in_x2_net;
|
2935 |
|
|
data_in_x20 <= data_in_x20_net;
|
2936 |
|
|
data_in_x21 <= data_in_x21_net;
|
2937 |
|
|
data_in_x22 <= data_in_x22_net;
|
2938 |
|
|
data_in_x23 <= data_in_x23_net;
|
2939 |
|
|
data_in_x24 <= data_in_x24_net;
|
2940 |
|
|
data_in_x25 <= data_in_x25_net;
|
2941 |
|
|
data_in_x26 <= data_in_x26_net;
|
2942 |
|
|
data_in_x3 <= data_in_x3_net;
|
2943 |
|
|
data_in_x4 <= data_in_x4_net;
|
2944 |
|
|
data_in_x5 <= data_in_x5_net;
|
2945 |
|
|
data_in_x6 <= data_in_x6_net;
|
2946 |
|
|
data_in_x7 <= data_in_x7_net;
|
2947 |
|
|
data_in_x8 <= data_in_x8_net;
|
2948 |
|
|
data_in_x9 <= data_in_x9_net;
|
2949 |
|
|
en <= constant6_op_net_x0;
|
2950 |
|
|
en_x0 <= constant6_op_net_x0;
|
2951 |
|
|
en_x1 <= constant6_op_net_x0;
|
2952 |
|
|
en_x10 <= constant6_op_net_x0;
|
2953 |
|
|
en_x11 <= constant6_op_net_x0;
|
2954 |
|
|
en_x12 <= constant6_op_net_x0;
|
2955 |
|
|
en_x13 <= constant6_op_net_x0;
|
2956 |
|
|
en_x14 <= constant6_op_net_x0;
|
2957 |
|
|
en_x15 <= constant6_op_net_x0;
|
2958 |
|
|
en_x16 <= constant6_op_net_x0;
|
2959 |
|
|
en_x17 <= constant6_op_net_x0;
|
2960 |
|
|
en_x18 <= constant6_op_net_x0;
|
2961 |
|
|
en_x19 <= constant6_op_net_x0;
|
2962 |
|
|
en_x2 <= constant6_op_net_x0;
|
2963 |
|
|
en_x20 <= constant6_op_net_x0;
|
2964 |
|
|
en_x21 <= constant6_op_net_x0;
|
2965 |
|
|
en_x22 <= constant6_op_net_x0;
|
2966 |
|
|
en_x23 <= constant6_op_net_x0;
|
2967 |
|
|
en_x24 <= constant6_op_net_x0;
|
2968 |
|
|
en_x25 <= constant6_op_net_x0;
|
2969 |
|
|
en_x26 <= constant6_op_net_x0;
|
2970 |
|
|
en_x3 <= constant6_op_net_x0;
|
2971 |
|
|
en_x4 <= constant6_op_net_x0;
|
2972 |
|
|
en_x5 <= constant6_op_net_x0;
|
2973 |
|
|
en_x6 <= constant6_op_net_x0;
|
2974 |
|
|
en_x7 <= constant6_op_net_x0;
|
2975 |
|
|
en_x8 <= constant6_op_net_x0;
|
2976 |
|
|
en_x9 <= constant6_op_net_x0;
|
2977 |
|
|
fifo_rd_en_x1 <= fifo_rd_en_net;
|
2978 |
|
|
fifo_wr_din <= fifo_wr_din_net;
|
2979 |
|
|
fifo_wr_en_x0 <= fifo_wr_en_net;
|
2980 |
|
|
rst_o <= rst_o_net;
|
2981 |
|
|
user_int_1o <= user_int_1o_net;
|
2982 |
|
|
user_int_2o <= user_int_2o_net;
|
2983 |
|
|
user_int_3o <= user_int_3o_net;
|
2984 |
|
|
|
2985 |
|
|
chipscope: entity work.xlchipscope
|
2986 |
|
|
port map (
|
2987 |
|
|
ce => ce_1_sg_x0,
|
2988 |
|
|
clk => clk_1_sg_x0,
|
2989 |
|
|
clr => '0',
|
2990 |
|
|
trig0 => bram_addr,
|
2991 |
|
|
trig1 => bram_data,
|
2992 |
|
|
trig10 => fifo_wr_count,
|
2993 |
|
|
trig2(0) => fifo_empty_x0,
|
2994 |
|
|
trig3(0) => fifo_rd_en_x0,
|
2995 |
|
|
trig4(0) => fifo_wr_en,
|
2996 |
|
|
trig5 => fifo_data_in_out,
|
2997 |
|
|
trig6(0) => fifo_rd_pempty,
|
2998 |
|
|
trig7 => fifo_rd_count,
|
2999 |
|
|
trig8(0) => fifo_wr_full,
|
3000 |
|
|
trig9(0) => fifo_wr_pfull
|
3001 |
|
|
);
|
3002 |
|
|
|
3003 |
|
|
constant1: entity work.constant_963ed6358a
|
3004 |
|
|
port map (
|
3005 |
|
|
ce => '0',
|
3006 |
|
|
clk => '0',
|
3007 |
|
|
clr => '0',
|
3008 |
|
|
op(0) => constant1_op_net
|
3009 |
|
|
);
|
3010 |
|
|
|
3011 |
|
|
constant10: entity work.constant_963ed6358a
|
3012 |
|
|
port map (
|
3013 |
|
|
ce => '0',
|
3014 |
|
|
clk => '0',
|
3015 |
|
|
clr => '0',
|
3016 |
|
|
op(0) => constant10_op_net
|
3017 |
|
|
);
|
3018 |
|
|
|
3019 |
|
|
constant11: entity work.constant_963ed6358a
|
3020 |
|
|
port map (
|
3021 |
|
|
ce => '0',
|
3022 |
|
|
clk => '0',
|
3023 |
|
|
clr => '0',
|
3024 |
|
|
op(0) => constant11_op_net
|
3025 |
|
|
);
|
3026 |
|
|
|
3027 |
|
|
constant12: entity work.constant_963ed6358a
|
3028 |
|
|
port map (
|
3029 |
|
|
ce => '0',
|
3030 |
|
|
clk => '0',
|
3031 |
|
|
clr => '0',
|
3032 |
|
|
op(0) => constant12_op_net
|
3033 |
|
|
);
|
3034 |
|
|
|
3035 |
|
|
constant14: entity work.constant_6293007044
|
3036 |
|
|
port map (
|
3037 |
|
|
ce => '0',
|
3038 |
|
|
clk => '0',
|
3039 |
|
|
clr => '0',
|
3040 |
|
|
op(0) => constant14_op_net
|
3041 |
|
|
);
|
3042 |
|
|
|
3043 |
|
|
constant15: entity work.constant_6293007044
|
3044 |
|
|
port map (
|
3045 |
|
|
ce => '0',
|
3046 |
|
|
clk => '0',
|
3047 |
|
|
clr => '0',
|
3048 |
|
|
op(0) => constant15_op_net
|
3049 |
|
|
);
|
3050 |
|
|
|
3051 |
|
|
constant19: entity work.constant_963ed6358a
|
3052 |
|
|
port map (
|
3053 |
|
|
ce => '0',
|
3054 |
|
|
clk => '0',
|
3055 |
|
|
clr => '0',
|
3056 |
|
|
op(0) => constant19_op_net
|
3057 |
|
|
);
|
3058 |
|
|
|
3059 |
|
|
constant2: entity work.constant_19562ab42f
|
3060 |
|
|
port map (
|
3061 |
|
|
ce => '0',
|
3062 |
|
|
clk => '0',
|
3063 |
|
|
clr => '0',
|
3064 |
|
|
op => constant2_op_net
|
3065 |
|
|
);
|
3066 |
|
|
|
3067 |
|
|
constant20: entity work.constant_963ed6358a
|
3068 |
|
|
port map (
|
3069 |
|
|
ce => '0',
|
3070 |
|
|
clk => '0',
|
3071 |
|
|
clr => '0',
|
3072 |
|
|
op(0) => constant20_op_net
|
3073 |
|
|
);
|
3074 |
|
|
|
3075 |
|
|
constant21: entity work.constant_963ed6358a
|
3076 |
|
|
port map (
|
3077 |
|
|
ce => '0',
|
3078 |
|
|
clk => '0',
|
3079 |
|
|
clr => '0',
|
3080 |
|
|
op(0) => constant21_op_net
|
3081 |
|
|
);
|
3082 |
|
|
|
3083 |
|
|
constant22: entity work.constant_963ed6358a
|
3084 |
|
|
port map (
|
3085 |
|
|
ce => '0',
|
3086 |
|
|
clk => '0',
|
3087 |
|
|
clr => '0',
|
3088 |
|
|
op(0) => constant22_op_net
|
3089 |
|
|
);
|
3090 |
|
|
|
3091 |
|
|
constant23: entity work.constant_963ed6358a
|
3092 |
|
|
port map (
|
3093 |
|
|
ce => '0',
|
3094 |
|
|
clk => '0',
|
3095 |
|
|
clr => '0',
|
3096 |
|
|
op(0) => constant23_op_net
|
3097 |
|
|
);
|
3098 |
|
|
|
3099 |
|
|
constant24: entity work.constant_963ed6358a
|
3100 |
|
|
port map (
|
3101 |
|
|
ce => '0',
|
3102 |
|
|
clk => '0',
|
3103 |
|
|
clr => '0',
|
3104 |
|
|
op(0) => constant24_op_net
|
3105 |
|
|
);
|
3106 |
|
|
|
3107 |
|
|
constant25: entity work.constant_963ed6358a
|
3108 |
|
|
port map (
|
3109 |
|
|
ce => '0',
|
3110 |
|
|
clk => '0',
|
3111 |
|
|
clr => '0',
|
3112 |
|
|
op(0) => constant25_op_net
|
3113 |
|
|
);
|
3114 |
|
|
|
3115 |
|
|
constant26: entity work.constant_963ed6358a
|
3116 |
|
|
port map (
|
3117 |
|
|
ce => '0',
|
3118 |
|
|
clk => '0',
|
3119 |
|
|
clr => '0',
|
3120 |
|
|
op(0) => constant26_op_net
|
3121 |
|
|
);
|
3122 |
|
|
|
3123 |
|
|
constant3: entity work.constant_963ed6358a
|
3124 |
|
|
port map (
|
3125 |
|
|
ce => '0',
|
3126 |
|
|
clk => '0',
|
3127 |
|
|
clr => '0',
|
3128 |
|
|
op(0) => constant3_op_net
|
3129 |
|
|
);
|
3130 |
|
|
|
3131 |
|
|
constant4: entity work.constant_963ed6358a
|
3132 |
|
|
port map (
|
3133 |
|
|
ce => '0',
|
3134 |
|
|
clk => '0',
|
3135 |
|
|
clr => '0',
|
3136 |
|
|
op(0) => constant4_op_net
|
3137 |
|
|
);
|
3138 |
|
|
|
3139 |
|
|
constant6: entity work.constant_6293007044
|
3140 |
|
|
port map (
|
3141 |
|
|
ce => '0',
|
3142 |
|
|
clk => '0',
|
3143 |
|
|
clr => '0',
|
3144 |
|
|
op(0) => constant6_op_net_x0
|
3145 |
|
|
);
|
3146 |
|
|
|
3147 |
|
|
constant7: entity work.constant_963ed6358a
|
3148 |
|
|
port map (
|
3149 |
|
|
ce => '0',
|
3150 |
|
|
clk => '0',
|
3151 |
|
|
clr => '0',
|
3152 |
|
|
op(0) => constant7_op_net
|
3153 |
|
|
);
|
3154 |
|
|
|
3155 |
|
|
constant8: entity work.constant_963ed6358a
|
3156 |
|
|
port map (
|
3157 |
|
|
ce => '0',
|
3158 |
|
|
clk => '0',
|
3159 |
|
|
clr => '0',
|
3160 |
|
|
op(0) => constant8_op_net
|
3161 |
|
|
);
|
3162 |
|
|
|
3163 |
|
|
constant9: entity work.constant_963ed6358a
|
3164 |
|
|
port map (
|
3165 |
|
|
ce => '0',
|
3166 |
|
|
clk => '0',
|
3167 |
|
|
clr => '0',
|
3168 |
|
|
op(0) => constant9_op_net
|
3169 |
|
|
);
|
3170 |
|
|
|
3171 |
|
|
convert1: entity work.xlconvert
|
3172 |
|
|
generic map (
|
3173 |
|
|
bool_conversion => 1,
|
3174 |
|
|
din_arith => 1,
|
3175 |
|
|
din_bin_pt => 0,
|
3176 |
|
|
din_width => 1,
|
3177 |
|
|
dout_arith => 1,
|
3178 |
|
|
dout_bin_pt => 0,
|
3179 |
|
|
dout_width => 1,
|
3180 |
|
|
latency => 0,
|
3181 |
|
|
overflow => xlWrap,
|
3182 |
|
|
quantization => xlTruncate
|
3183 |
|
|
)
|
3184 |
|
|
port map (
|
3185 |
|
|
ce => ce_1_sg_x0,
|
3186 |
|
|
clk => clk_1_sg_x0,
|
3187 |
|
|
clr => '0',
|
3188 |
|
|
din(0) => tx_en_in5_q_net,
|
3189 |
|
|
en => "1",
|
3190 |
|
|
dout(0) => convert1_dout_net
|
3191 |
|
|
);
|
3192 |
|
|
|
3193 |
|
|
convert11: entity work.xlconvert
|
3194 |
|
|
generic map (
|
3195 |
|
|
bool_conversion => 1,
|
3196 |
|
|
din_arith => 1,
|
3197 |
|
|
din_bin_pt => 0,
|
3198 |
|
|
din_width => 1,
|
3199 |
|
|
dout_arith => 1,
|
3200 |
|
|
dout_bin_pt => 0,
|
3201 |
|
|
dout_width => 1,
|
3202 |
|
|
latency => 0,
|
3203 |
|
|
overflow => xlWrap,
|
3204 |
|
|
quantization => xlTruncate
|
3205 |
|
|
)
|
3206 |
|
|
port map (
|
3207 |
|
|
ce => ce_1_sg_x0,
|
3208 |
|
|
clk => clk_1_sg_x0,
|
3209 |
|
|
clr => '0',
|
3210 |
|
|
din(0) => tx_en_in89_q_net,
|
3211 |
|
|
en => "1",
|
3212 |
|
|
dout(0) => convert11_dout_net
|
3213 |
|
|
);
|
3214 |
|
|
|
3215 |
|
|
convert12: entity work.xlconvert
|
3216 |
|
|
generic map (
|
3217 |
|
|
bool_conversion => 1,
|
3218 |
|
|
din_arith => 1,
|
3219 |
|
|
din_bin_pt => 0,
|
3220 |
|
|
din_width => 1,
|
3221 |
|
|
dout_arith => 1,
|
3222 |
|
|
dout_bin_pt => 0,
|
3223 |
|
|
dout_width => 1,
|
3224 |
|
|
latency => 0,
|
3225 |
|
|
overflow => xlWrap,
|
3226 |
|
|
quantization => xlTruncate
|
3227 |
|
|
)
|
3228 |
|
|
port map (
|
3229 |
|
|
ce => ce_1_sg_x0,
|
3230 |
|
|
clk => clk_1_sg_x0,
|
3231 |
|
|
clr => '0',
|
3232 |
|
|
din(0) => tx_en_in92_q_net,
|
3233 |
|
|
en => "1",
|
3234 |
|
|
dout(0) => convert12_dout_net
|
3235 |
|
|
);
|
3236 |
|
|
|
3237 |
|
|
convert14: entity work.xlconvert
|
3238 |
|
|
generic map (
|
3239 |
|
|
bool_conversion => 1,
|
3240 |
|
|
din_arith => 1,
|
3241 |
|
|
din_bin_pt => 0,
|
3242 |
|
|
din_width => 1,
|
3243 |
|
|
dout_arith => 1,
|
3244 |
|
|
dout_bin_pt => 0,
|
3245 |
|
|
dout_width => 1,
|
3246 |
|
|
latency => 0,
|
3247 |
|
|
overflow => xlWrap,
|
3248 |
|
|
quantization => xlTruncate
|
3249 |
|
|
)
|
3250 |
|
|
port map (
|
3251 |
|
|
ce => ce_1_sg_x0,
|
3252 |
|
|
clk => clk_1_sg_x0,
|
3253 |
|
|
clr => '0',
|
3254 |
|
|
din(0) => tx_en_in116_q_net,
|
3255 |
|
|
en => "1",
|
3256 |
|
|
dout(0) => convert14_dout_net
|
3257 |
|
|
);
|
3258 |
|
|
|
3259 |
|
|
convert15: entity work.xlconvert
|
3260 |
|
|
generic map (
|
3261 |
|
|
bool_conversion => 1,
|
3262 |
|
|
din_arith => 1,
|
3263 |
|
|
din_bin_pt => 0,
|
3264 |
|
|
din_width => 1,
|
3265 |
|
|
dout_arith => 1,
|
3266 |
|
|
dout_bin_pt => 0,
|
3267 |
|
|
dout_width => 1,
|
3268 |
|
|
latency => 0,
|
3269 |
|
|
overflow => xlWrap,
|
3270 |
|
|
quantization => xlTruncate
|
3271 |
|
|
)
|
3272 |
|
|
port map (
|
3273 |
|
|
ce => ce_1_sg_x0,
|
3274 |
|
|
clk => clk_1_sg_x0,
|
3275 |
|
|
clr => '0',
|
3276 |
|
|
din(0) => tx_en_in119_q_net,
|
3277 |
|
|
en => "1",
|
3278 |
|
|
dout(0) => convert15_dout_net
|
3279 |
|
|
);
|
3280 |
|
|
|
3281 |
|
|
convert16: entity work.xlconvert
|
3282 |
|
|
generic map (
|
3283 |
|
|
bool_conversion => 1,
|
3284 |
|
|
din_arith => 1,
|
3285 |
|
|
din_bin_pt => 0,
|
3286 |
|
|
din_width => 1,
|
3287 |
|
|
dout_arith => 1,
|
3288 |
|
|
dout_bin_pt => 0,
|
3289 |
|
|
dout_width => 1,
|
3290 |
|
|
latency => 0,
|
3291 |
|
|
overflow => xlWrap,
|
3292 |
|
|
quantization => xlTruncate
|
3293 |
|
|
)
|
3294 |
|
|
port map (
|
3295 |
|
|
ce => ce_1_sg_x0,
|
3296 |
|
|
clk => clk_1_sg_x0,
|
3297 |
|
|
clr => '0',
|
3298 |
|
|
din(0) => tx_en_in123_q_net,
|
3299 |
|
|
en => "1",
|
3300 |
|
|
dout(0) => convert16_dout_net
|
3301 |
|
|
);
|
3302 |
|
|
|
3303 |
|
|
convert17: entity work.xlconvert
|
3304 |
|
|
generic map (
|
3305 |
|
|
bool_conversion => 1,
|
3306 |
|
|
din_arith => 1,
|
3307 |
|
|
din_bin_pt => 0,
|
3308 |
|
|
din_width => 1,
|
3309 |
|
|
dout_arith => 1,
|
3310 |
|
|
dout_bin_pt => 0,
|
3311 |
|
|
dout_width => 1,
|
3312 |
|
|
latency => 0,
|
3313 |
|
|
overflow => xlWrap,
|
3314 |
|
|
quantization => xlTruncate
|
3315 |
|
|
)
|
3316 |
|
|
port map (
|
3317 |
|
|
ce => ce_1_sg_x0,
|
3318 |
|
|
clk => clk_1_sg_x0,
|
3319 |
|
|
clr => '0',
|
3320 |
|
|
din(0) => tx_en_in127_q_net,
|
3321 |
|
|
en => "1",
|
3322 |
|
|
dout(0) => convert17_dout_net
|
3323 |
|
|
);
|
3324 |
|
|
|
3325 |
|
|
convert3: entity work.xlconvert
|
3326 |
|
|
generic map (
|
3327 |
|
|
bool_conversion => 1,
|
3328 |
|
|
din_arith => 1,
|
3329 |
|
|
din_bin_pt => 0,
|
3330 |
|
|
din_width => 1,
|
3331 |
|
|
dout_arith => 1,
|
3332 |
|
|
dout_bin_pt => 0,
|
3333 |
|
|
dout_width => 1,
|
3334 |
|
|
latency => 0,
|
3335 |
|
|
overflow => xlWrap,
|
3336 |
|
|
quantization => xlTruncate
|
3337 |
|
|
)
|
3338 |
|
|
port map (
|
3339 |
|
|
ce => ce_1_sg_x0,
|
3340 |
|
|
clk => clk_1_sg_x0,
|
3341 |
|
|
clr => '0',
|
3342 |
|
|
din(0) => tx_en_in4_q_net,
|
3343 |
|
|
en => "1",
|
3344 |
|
|
dout(0) => timecountreset
|
3345 |
|
|
);
|
3346 |
|
|
|
3347 |
|
|
convert4: entity work.xlconvert
|
3348 |
|
|
generic map (
|
3349 |
|
|
bool_conversion => 1,
|
3350 |
|
|
din_arith => 1,
|
3351 |
|
|
din_bin_pt => 0,
|
3352 |
|
|
din_width => 1,
|
3353 |
|
|
dout_arith => 1,
|
3354 |
|
|
dout_bin_pt => 0,
|
3355 |
|
|
dout_width => 1,
|
3356 |
|
|
latency => 0,
|
3357 |
|
|
overflow => xlWrap,
|
3358 |
|
|
quantization => xlTruncate
|
3359 |
|
|
)
|
3360 |
|
|
port map (
|
3361 |
|
|
ce => ce_1_sg_x0,
|
3362 |
|
|
clk => clk_1_sg_x0,
|
3363 |
|
|
clr => '0',
|
3364 |
|
|
din(0) => tx_en_in86_q_net,
|
3365 |
|
|
en => "1",
|
3366 |
|
|
dout(0) => convert4_dout_net
|
3367 |
|
|
);
|
3368 |
|
|
|
3369 |
|
|
convert5: entity work.xlconvert
|
3370 |
|
|
generic map (
|
3371 |
|
|
bool_conversion => 1,
|
3372 |
|
|
din_arith => 1,
|
3373 |
|
|
din_bin_pt => 0,
|
3374 |
|
|
din_width => 1,
|
3375 |
|
|
dout_arith => 1,
|
3376 |
|
|
dout_bin_pt => 0,
|
3377 |
|
|
dout_width => 1,
|
3378 |
|
|
latency => 0,
|
3379 |
|
|
overflow => xlWrap,
|
3380 |
|
|
quantization => xlTruncate
|
3381 |
|
|
)
|
3382 |
|
|
port map (
|
3383 |
|
|
ce => ce_1_sg_x0,
|
3384 |
|
|
clk => clk_1_sg_x0,
|
3385 |
|
|
clr => '0',
|
3386 |
|
|
din(0) => tx_en_in58_q_net,
|
3387 |
|
|
en => "1",
|
3388 |
|
|
dout(0) => convert5_dout_net
|
3389 |
|
|
);
|
3390 |
|
|
|
3391 |
|
|
convert6: entity work.xlconvert
|
3392 |
|
|
generic map (
|
3393 |
|
|
bool_conversion => 1,
|
3394 |
|
|
din_arith => 1,
|
3395 |
|
|
din_bin_pt => 0,
|
3396 |
|
|
din_width => 1,
|
3397 |
|
|
dout_arith => 1,
|
3398 |
|
|
dout_bin_pt => 0,
|
3399 |
|
|
dout_width => 1,
|
3400 |
|
|
latency => 0,
|
3401 |
|
|
overflow => xlWrap,
|
3402 |
|
|
quantization => xlTruncate
|
3403 |
|
|
)
|
3404 |
|
|
port map (
|
3405 |
|
|
ce => ce_1_sg_x0,
|
3406 |
|
|
clk => clk_1_sg_x0,
|
3407 |
|
|
clr => '0',
|
3408 |
|
|
din(0) => tx_en_in59_q_net,
|
3409 |
|
|
en => "1",
|
3410 |
|
|
dout(0) => convert6_dout_net
|
3411 |
|
|
);
|
3412 |
|
|
|
3413 |
|
|
convert7: entity work.xlconvert
|
3414 |
|
|
generic map (
|
3415 |
|
|
bool_conversion => 1,
|
3416 |
|
|
din_arith => 1,
|
3417 |
|
|
din_bin_pt => 0,
|
3418 |
|
|
din_width => 1,
|
3419 |
|
|
dout_arith => 1,
|
3420 |
|
|
dout_bin_pt => 0,
|
3421 |
|
|
dout_width => 1,
|
3422 |
|
|
latency => 0,
|
3423 |
|
|
overflow => xlWrap,
|
3424 |
|
|
quantization => xlTruncate
|
3425 |
|
|
)
|
3426 |
|
|
port map (
|
3427 |
|
|
ce => ce_1_sg_x0,
|
3428 |
|
|
clk => clk_1_sg_x0,
|
3429 |
|
|
clr => '0',
|
3430 |
|
|
din(0) => tx_en_in61_q_net,
|
3431 |
|
|
en => "1",
|
3432 |
|
|
dout(0) => convert7_dout_net
|
3433 |
|
|
);
|
3434 |
|
|
|
3435 |
|
|
convert8: entity work.xlconvert
|
3436 |
|
|
generic map (
|
3437 |
|
|
bool_conversion => 1,
|
3438 |
|
|
din_arith => 1,
|
3439 |
|
|
din_bin_pt => 0,
|
3440 |
|
|
din_width => 1,
|
3441 |
|
|
dout_arith => 1,
|
3442 |
|
|
dout_bin_pt => 0,
|
3443 |
|
|
dout_width => 1,
|
3444 |
|
|
latency => 0,
|
3445 |
|
|
overflow => xlWrap,
|
3446 |
|
|
quantization => xlTruncate
|
3447 |
|
|
)
|
3448 |
|
|
port map (
|
3449 |
|
|
ce => ce_1_sg_x0,
|
3450 |
|
|
clk => clk_1_sg_x0,
|
3451 |
|
|
clr => '0',
|
3452 |
|
|
din(0) => tx_en_in67_q_net,
|
3453 |
|
|
en => "1",
|
3454 |
|
|
dout(0) => convert8_dout_net
|
3455 |
|
|
);
|
3456 |
|
|
|
3457 |
|
|
convert9: entity work.xlconvert
|
3458 |
|
|
generic map (
|
3459 |
|
|
bool_conversion => 1,
|
3460 |
|
|
din_arith => 1,
|
3461 |
|
|
din_bin_pt => 0,
|
3462 |
|
|
din_width => 1,
|
3463 |
|
|
dout_arith => 1,
|
3464 |
|
|
dout_bin_pt => 0,
|
3465 |
|
|
dout_width => 1,
|
3466 |
|
|
latency => 0,
|
3467 |
|
|
overflow => xlWrap,
|
3468 |
|
|
quantization => xlTruncate
|
3469 |
|
|
)
|
3470 |
|
|
port map (
|
3471 |
|
|
ce => ce_1_sg_x0,
|
3472 |
|
|
clk => clk_1_sg_x0,
|
3473 |
|
|
clr => '0',
|
3474 |
|
|
din(0) => tx_en_in8_q_net,
|
3475 |
|
|
en => "1",
|
3476 |
|
|
dout(0) => timecounttrigger
|
3477 |
|
|
);
|
3478 |
|
|
|
3479 |
|
|
counter4: entity work.xlcounter_free
|
3480 |
|
|
generic map (
|
3481 |
|
|
core_name0 => "cntr_11_0_341fbb8cfa0e669e",
|
3482 |
|
|
op_arith => xlUnsigned,
|
3483 |
|
|
op_width => 12
|
3484 |
|
|
)
|
3485 |
|
|
port map (
|
3486 |
|
|
ce => ce_1_sg_x0,
|
3487 |
|
|
clk => clk_1_sg_x0,
|
3488 |
|
|
clr => '0',
|
3489 |
|
|
en => "1",
|
3490 |
|
|
rst => "0",
|
3491 |
|
|
op => counter4_op_net
|
3492 |
|
|
);
|
3493 |
|
|
|
3494 |
|
|
inverter3: entity work.inverter_e5b38cca3b
|
3495 |
|
|
port map (
|
3496 |
|
|
ce => ce_1_sg_x0,
|
3497 |
|
|
clk => clk_1_sg_x0,
|
3498 |
|
|
clr => '0',
|
3499 |
|
|
ip(0) => rst_i_net,
|
3500 |
|
|
op(0) => inverter3_op_net
|
3501 |
|
|
);
|
3502 |
|
|
|
3503 |
|
|
inverter5: entity work.inverter_e5b38cca3b
|
3504 |
|
|
port map (
|
3505 |
|
|
ce => ce_1_sg_x0,
|
3506 |
|
|
clk => clk_1_sg_x0,
|
3507 |
|
|
clr => '0',
|
3508 |
|
|
ip(0) => tx_en_in107_q_net,
|
3509 |
|
|
op(0) => inverter5_op_net
|
3510 |
|
|
);
|
3511 |
|
|
|
3512 |
|
|
logical4: entity work.logical_80f90b97d0
|
3513 |
|
|
port map (
|
3514 |
|
|
ce => '0',
|
3515 |
|
|
clk => '0',
|
3516 |
|
|
clr => '0',
|
3517 |
|
|
d0(0) => constant15_op_net,
|
3518 |
|
|
d1(0) => inverter5_op_net,
|
3519 |
|
|
y(0) => fifo_rd_en
|
3520 |
|
|
);
|
3521 |
|
|
|
3522 |
|
|
tx_en_in1: entity work.xlregister
|
3523 |
|
|
generic map (
|
3524 |
|
|
d_width => 1,
|
3525 |
|
|
init_value => b"0"
|
3526 |
|
|
)
|
3527 |
|
|
port map (
|
3528 |
|
|
ce => ce_1_sg_x0,
|
3529 |
|
|
clk => clk_1_sg_x0,
|
3530 |
|
|
d(0) => timecountreset,
|
3531 |
|
|
en => "1",
|
3532 |
|
|
rst => "0",
|
3533 |
|
|
q(0) => data_in_x0_net
|
3534 |
|
|
);
|
3535 |
|
|
|
3536 |
|
|
tx_en_in10: entity work.xlregister
|
3537 |
|
|
generic map (
|
3538 |
|
|
d_width => 32,
|
3539 |
|
|
init_value => b"00000000000000000000000000000000"
|
3540 |
|
|
)
|
3541 |
|
|
port map (
|
3542 |
|
|
ce => ce_1_sg_x0,
|
3543 |
|
|
clk => clk_1_sg_x0,
|
3544 |
|
|
d => tx_en_in12_q_net,
|
3545 |
|
|
en(0) => timecounttrigger,
|
3546 |
|
|
rst(0) => constant3_op_net,
|
3547 |
|
|
q => data_in_x20_net
|
3548 |
|
|
);
|
3549 |
|
|
|
3550 |
|
|
tx_en_in100: entity work.xlregister
|
3551 |
|
|
generic map (
|
3552 |
|
|
d_width => 1,
|
3553 |
|
|
init_value => b"0"
|
3554 |
|
|
)
|
3555 |
|
|
port map (
|
3556 |
|
|
ce => ce_1_sg_x0,
|
3557 |
|
|
clk => clk_1_sg_x0,
|
3558 |
|
|
d(0) => convert12_dout_net,
|
3559 |
|
|
en => "1",
|
3560 |
|
|
rst => "0",
|
3561 |
|
|
q(0) => data_in_x9_net
|
3562 |
|
|
);
|
3563 |
|
|
|
3564 |
|
|
tx_en_in105: entity work.xlregister
|
3565 |
|
|
generic map (
|
3566 |
|
|
d_width => 1,
|
3567 |
|
|
init_value => b"0"
|
3568 |
|
|
)
|
3569 |
|
|
port map (
|
3570 |
|
|
ce => ce_1_sg_x0,
|
3571 |
|
|
clk => clk_1_sg_x0,
|
3572 |
|
|
d(0) => fifo_rd_empty_net,
|
3573 |
|
|
en => "1",
|
3574 |
|
|
rst => "0",
|
3575 |
|
|
q(0) => fifo_empty
|
3576 |
|
|
);
|
3577 |
|
|
|
3578 |
|
|
tx_en_in107: entity work.xlregister
|
3579 |
|
|
generic map (
|
3580 |
|
|
d_width => 1,
|
3581 |
|
|
init_value => b"0"
|
3582 |
|
|
)
|
3583 |
|
|
port map (
|
3584 |
|
|
ce => ce_1_sg_x0,
|
3585 |
|
|
clk => clk_1_sg_x0,
|
3586 |
|
|
d(0) => fifo_empty,
|
3587 |
|
|
en => "1",
|
3588 |
|
|
rst => "0",
|
3589 |
|
|
q(0) => tx_en_in107_q_net
|
3590 |
|
|
);
|
3591 |
|
|
|
3592 |
|
|
tx_en_in108: entity work.xlregister
|
3593 |
|
|
generic map (
|
3594 |
|
|
d_width => 1,
|
3595 |
|
|
init_value => b"0"
|
3596 |
|
|
)
|
3597 |
|
|
port map (
|
3598 |
|
|
ce => ce_1_sg_x0,
|
3599 |
|
|
clk => clk_1_sg_x0,
|
3600 |
|
|
d(0) => fifo_rd_en,
|
3601 |
|
|
en(0) => constant14_op_net,
|
3602 |
|
|
rst => "0",
|
3603 |
|
|
q(0) => fifo_rd_en_net
|
3604 |
|
|
);
|
3605 |
|
|
|
3606 |
|
|
tx_en_in109: entity work.xlregister
|
3607 |
|
|
generic map (
|
3608 |
|
|
d_width => 1,
|
3609 |
|
|
init_value => b"0"
|
3610 |
|
|
)
|
3611 |
|
|
port map (
|
3612 |
|
|
ce => ce_1_sg_x0,
|
3613 |
|
|
clk => clk_1_sg_x0,
|
3614 |
|
|
d(0) => fifo_rd_valid_net,
|
3615 |
|
|
en => "1",
|
3616 |
|
|
rst => "0",
|
3617 |
|
|
q(0) => fifo_wr_en_net
|
3618 |
|
|
);
|
3619 |
|
|
|
3620 |
|
|
tx_en_in11: entity work.xlregister
|
3621 |
|
|
generic map (
|
3622 |
|
|
d_width => 12,
|
3623 |
|
|
init_value => b"000000000000"
|
3624 |
|
|
)
|
3625 |
|
|
port map (
|
3626 |
|
|
ce => ce_1_sg_x0,
|
3627 |
|
|
clk => clk_1_sg_x0,
|
3628 |
|
|
d => bram_addr_x0,
|
3629 |
|
|
en => "1",
|
3630 |
|
|
rst => "0",
|
3631 |
|
|
q => bram_addr
|
3632 |
|
|
);
|
3633 |
|
|
|
3634 |
|
|
tx_en_in113: entity work.xlregister
|
3635 |
|
|
generic map (
|
3636 |
|
|
d_width => 1,
|
3637 |
|
|
init_value => b"0"
|
3638 |
|
|
)
|
3639 |
|
|
port map (
|
3640 |
|
|
ce => ce_1_sg_x0,
|
3641 |
|
|
clk => clk_1_sg_x0,
|
3642 |
|
|
d(0) => convert14_dout_net,
|
3643 |
|
|
en => "1",
|
3644 |
|
|
rst => "0",
|
3645 |
|
|
q(0) => data_in_x12_net
|
3646 |
|
|
);
|
3647 |
|
|
|
3648 |
|
|
tx_en_in114: entity work.xlregister
|
3649 |
|
|
generic map (
|
3650 |
|
|
d_width => 1,
|
3651 |
|
|
init_value => b"0"
|
3652 |
|
|
)
|
3653 |
|
|
port map (
|
3654 |
|
|
ce => ce_1_sg_x0,
|
3655 |
|
|
clk => clk_1_sg_x0,
|
3656 |
|
|
d(0) => convert15_dout_net,
|
3657 |
|
|
en => "1",
|
3658 |
|
|
rst => "0",
|
3659 |
|
|
q(0) => data_in_x14_net
|
3660 |
|
|
);
|
3661 |
|
|
|
3662 |
|
|
tx_en_in115: entity work.xlregister
|
3663 |
|
|
generic map (
|
3664 |
|
|
d_width => 32,
|
3665 |
|
|
init_value => b"00000000000000110000110100100011"
|
3666 |
|
|
)
|
3667 |
|
|
port map (
|
3668 |
|
|
ce => ce_1_sg_x0,
|
3669 |
|
|
clk => clk_1_sg_x0,
|
3670 |
|
|
d => tx_en_in117_q_net,
|
3671 |
|
|
en(0) => convert14_dout_net,
|
3672 |
|
|
rst(0) => constant19_op_net,
|
3673 |
|
|
q => data_in_x13_net
|
3674 |
|
|
);
|
3675 |
|
|
|
3676 |
|
|
tx_en_in116: entity work.xlregister
|
3677 |
|
|
generic map (
|
3678 |
|
|
d_width => 1,
|
3679 |
|
|
init_value => b"0"
|
3680 |
|
|
)
|
3681 |
|
|
port map (
|
3682 |
|
|
ce => ce_1_sg_x0,
|
3683 |
|
|
clk => clk_1_sg_x0,
|
3684 |
|
|
d(0) => data_out_x19_net,
|
3685 |
|
|
en => "1",
|
3686 |
|
|
rst => "0",
|
3687 |
|
|
q(0) => tx_en_in116_q_net
|
3688 |
|
|
);
|
3689 |
|
|
|
3690 |
|
|
tx_en_in117: entity work.xlregister
|
3691 |
|
|
generic map (
|
3692 |
|
|
d_width => 32,
|
3693 |
|
|
init_value => b"00000000000000000000000000000000"
|
3694 |
|
|
)
|
3695 |
|
|
port map (
|
3696 |
|
|
ce => ce_1_sg_x0,
|
3697 |
|
|
clk => clk_1_sg_x0,
|
3698 |
|
|
d => data_out_x18_net,
|
3699 |
|
|
en => "1",
|
3700 |
|
|
rst => "0",
|
3701 |
|
|
q => tx_en_in117_q_net
|
3702 |
|
|
);
|
3703 |
|
|
|
3704 |
|
|
tx_en_in118: entity work.xlregister
|
3705 |
|
|
generic map (
|
3706 |
|
|
d_width => 32,
|
3707 |
|
|
init_value => b"00000000000000000100101011000000"
|
3708 |
|
|
)
|
3709 |
|
|
port map (
|
3710 |
|
|
ce => ce_1_sg_x0,
|
3711 |
|
|
clk => clk_1_sg_x0,
|
3712 |
|
|
d => tx_en_in120_q_net,
|
3713 |
|
|
en(0) => convert15_dout_net,
|
3714 |
|
|
rst(0) => constant21_op_net,
|
3715 |
|
|
q => data_in_x15_net
|
3716 |
|
|
);
|
3717 |
|
|
|
3718 |
|
|
tx_en_in119: entity work.xlregister
|
3719 |
|
|
generic map (
|
3720 |
|
|
d_width => 1,
|
3721 |
|
|
init_value => b"0"
|
3722 |
|
|
)
|
3723 |
|
|
port map (
|
3724 |
|
|
ce => ce_1_sg_x0,
|
3725 |
|
|
clk => clk_1_sg_x0,
|
3726 |
|
|
d(0) => data_out_x21_net,
|
3727 |
|
|
en => "1",
|
3728 |
|
|
rst => "0",
|
3729 |
|
|
q(0) => tx_en_in119_q_net
|
3730 |
|
|
);
|
3731 |
|
|
|
3732 |
|
|
tx_en_in12: entity work.xlregister
|
3733 |
|
|
generic map (
|
3734 |
|
|
d_width => 32,
|
3735 |
|
|
init_value => b"00000000000000000000000000000000"
|
3736 |
|
|
)
|
3737 |
|
|
port map (
|
3738 |
|
|
ce => ce_1_sg_x0,
|
3739 |
|
|
clk => clk_1_sg_x0,
|
3740 |
|
|
d => data_out_x30_net,
|
3741 |
|
|
en => "1",
|
3742 |
|
|
rst => "0",
|
3743 |
|
|
q => tx_en_in12_q_net
|
3744 |
|
|
);
|
3745 |
|
|
|
3746 |
|
|
tx_en_in120: entity work.xlregister
|
3747 |
|
|
generic map (
|
3748 |
|
|
d_width => 32,
|
3749 |
|
|
init_value => b"00000000000000000000000000000000"
|
3750 |
|
|
)
|
3751 |
|
|
port map (
|
3752 |
|
|
ce => ce_1_sg_x0,
|
3753 |
|
|
clk => clk_1_sg_x0,
|
3754 |
|
|
d => data_out_x20_net,
|
3755 |
|
|
en => "1",
|
3756 |
|
|
rst => "0",
|
3757 |
|
|
q => tx_en_in120_q_net
|
3758 |
|
|
);
|
3759 |
|
|
|
3760 |
|
|
tx_en_in121: entity work.xlregister
|
3761 |
|
|
generic map (
|
3762 |
|
|
d_width => 1,
|
3763 |
|
|
init_value => b"0"
|
3764 |
|
|
)
|
3765 |
|
|
port map (
|
3766 |
|
|
ce => ce_1_sg_x0,
|
3767 |
|
|
clk => clk_1_sg_x0,
|
3768 |
|
|
d(0) => convert16_dout_net,
|
3769 |
|
|
en => "1",
|
3770 |
|
|
rst => "0",
|
3771 |
|
|
q(0) => data_in_x16_net
|
3772 |
|
|
);
|
3773 |
|
|
|
3774 |
|
|
tx_en_in122: entity work.xlregister
|
3775 |
|
|
generic map (
|
3776 |
|
|
d_width => 32,
|
3777 |
|
|
init_value => b"00000000000000000000000000000000"
|
3778 |
|
|
)
|
3779 |
|
|
port map (
|
3780 |
|
|
ce => ce_1_sg_x0,
|
3781 |
|
|
clk => clk_1_sg_x0,
|
3782 |
|
|
d => tx_en_in124_q_net,
|
3783 |
|
|
en(0) => convert16_dout_net,
|
3784 |
|
|
rst(0) => constant22_op_net,
|
3785 |
|
|
q => data_in_x17_net
|
3786 |
|
|
);
|
3787 |
|
|
|
3788 |
|
|
tx_en_in123: entity work.xlregister
|
3789 |
|
|
generic map (
|
3790 |
|
|
d_width => 1,
|
3791 |
|
|
init_value => b"0"
|
3792 |
|
|
)
|
3793 |
|
|
port map (
|
3794 |
|
|
ce => ce_1_sg_x0,
|
3795 |
|
|
clk => clk_1_sg_x0,
|
3796 |
|
|
d(0) => data_out_x24_net,
|
3797 |
|
|
en => "1",
|
3798 |
|
|
rst => "0",
|
3799 |
|
|
q(0) => tx_en_in123_q_net
|
3800 |
|
|
);
|
3801 |
|
|
|
3802 |
|
|
tx_en_in124: entity work.xlregister
|
3803 |
|
|
generic map (
|
3804 |
|
|
d_width => 32,
|
3805 |
|
|
init_value => b"00000000000000000000000000000000"
|
3806 |
|
|
)
|
3807 |
|
|
port map (
|
3808 |
|
|
ce => ce_1_sg_x0,
|
3809 |
|
|
clk => clk_1_sg_x0,
|
3810 |
|
|
d => data_out_x23_net,
|
3811 |
|
|
en => "1",
|
3812 |
|
|
rst => "0",
|
3813 |
|
|
q => tx_en_in124_q_net
|
3814 |
|
|
);
|
3815 |
|
|
|
3816 |
|
|
tx_en_in125: entity work.xlregister
|
3817 |
|
|
generic map (
|
3818 |
|
|
d_width => 1,
|
3819 |
|
|
init_value => b"0"
|
3820 |
|
|
)
|
3821 |
|
|
port map (
|
3822 |
|
|
ce => ce_1_sg_x0,
|
3823 |
|
|
clk => clk_1_sg_x0,
|
3824 |
|
|
d(0) => convert17_dout_net,
|
3825 |
|
|
en => "1",
|
3826 |
|
|
rst => "0",
|
3827 |
|
|
q(0) => data_in_x18_net
|
3828 |
|
|
);
|
3829 |
|
|
|
3830 |
|
|
tx_en_in126: entity work.xlregister
|
3831 |
|
|
generic map (
|
3832 |
|
|
d_width => 32,
|
3833 |
|
|
init_value => b"00000000000000000000000000000000"
|
3834 |
|
|
)
|
3835 |
|
|
port map (
|
3836 |
|
|
ce => ce_1_sg_x0,
|
3837 |
|
|
clk => clk_1_sg_x0,
|
3838 |
|
|
d => tx_en_in128_q_net,
|
3839 |
|
|
en(0) => convert17_dout_net,
|
3840 |
|
|
rst(0) => constant23_op_net,
|
3841 |
|
|
q => data_in_x19_net
|
3842 |
|
|
);
|
3843 |
|
|
|
3844 |
|
|
tx_en_in127: entity work.xlregister
|
3845 |
|
|
generic map (
|
3846 |
|
|
d_width => 1,
|
3847 |
|
|
init_value => b"0"
|
3848 |
|
|
)
|
3849 |
|
|
port map (
|
3850 |
|
|
ce => ce_1_sg_x0,
|
3851 |
|
|
clk => clk_1_sg_x0,
|
3852 |
|
|
d(0) => data_out_x26_net,
|
3853 |
|
|
en => "1",
|
3854 |
|
|
rst => "0",
|
3855 |
|
|
q(0) => tx_en_in127_q_net
|
3856 |
|
|
);
|
3857 |
|
|
|
3858 |
|
|
tx_en_in128: entity work.xlregister
|
3859 |
|
|
generic map (
|
3860 |
|
|
d_width => 32,
|
3861 |
|
|
init_value => b"00000000000000000000000000000000"
|
3862 |
|
|
)
|
3863 |
|
|
port map (
|
3864 |
|
|
ce => ce_1_sg_x0,
|
3865 |
|
|
clk => clk_1_sg_x0,
|
3866 |
|
|
d => data_out_x25_net,
|
3867 |
|
|
en => "1",
|
3868 |
|
|
rst => "0",
|
3869 |
|
|
q => tx_en_in128_q_net
|
3870 |
|
|
);
|
3871 |
|
|
|
3872 |
|
|
tx_en_in13: entity work.xlregister
|
3873 |
|
|
generic map (
|
3874 |
|
|
d_width => 1,
|
3875 |
|
|
init_value => b"0"
|
3876 |
|
|
)
|
3877 |
|
|
port map (
|
3878 |
|
|
ce => ce_1_sg_x0,
|
3879 |
|
|
clk => clk_1_sg_x0,
|
3880 |
|
|
d(0) => convert8_dout_net,
|
3881 |
|
|
en => "1",
|
3882 |
|
|
rst => "0",
|
3883 |
|
|
q(0) => data_in_x3_net
|
3884 |
|
|
);
|
3885 |
|
|
|
3886 |
|
|
tx_en_in14: entity work.xlregister
|
3887 |
|
|
generic map (
|
3888 |
|
|
d_width => 64,
|
3889 |
|
|
init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
|
3890 |
|
|
)
|
3891 |
|
|
port map (
|
3892 |
|
|
ce => ce_1_sg_x0,
|
3893 |
|
|
clk => clk_1_sg_x0,
|
3894 |
|
|
d => bram_rd_dout_net,
|
3895 |
|
|
en => "1",
|
3896 |
|
|
rst => "0",
|
3897 |
|
|
q => bram_data
|
3898 |
|
|
);
|
3899 |
|
|
|
3900 |
|
|
tx_en_in15: entity work.xlregister
|
3901 |
|
|
generic map (
|
3902 |
|
|
d_width => 12,
|
3903 |
|
|
init_value => b"000000000000"
|
3904 |
|
|
)
|
3905 |
|
|
port map (
|
3906 |
|
|
ce => ce_1_sg_x0,
|
3907 |
|
|
clk => clk_1_sg_x0,
|
3908 |
|
|
d => counter4_op_net,
|
3909 |
|
|
en => "1",
|
3910 |
|
|
rst => "0",
|
3911 |
|
|
q => bram_rd_addr_net
|
3912 |
|
|
);
|
3913 |
|
|
|
3914 |
|
|
tx_en_in16: entity work.xlregister
|
3915 |
|
|
generic map (
|
3916 |
|
|
d_width => 12,
|
3917 |
|
|
init_value => b"000000000000"
|
3918 |
|
|
)
|
3919 |
|
|
port map (
|
3920 |
|
|
ce => ce_1_sg_x0,
|
3921 |
|
|
clk => clk_1_sg_x0,
|
3922 |
|
|
d => tx_en_in30_q_net,
|
3923 |
|
|
en => "1",
|
3924 |
|
|
rst => "0",
|
3925 |
|
|
q => bram_addr_x0
|
3926 |
|
|
);
|
3927 |
|
|
|
3928 |
|
|
tx_en_in17: entity work.xlregister
|
3929 |
|
|
generic map (
|
3930 |
|
|
d_width => 12,
|
3931 |
|
|
init_value => b"000000000000"
|
3932 |
|
|
)
|
3933 |
|
|
port map (
|
3934 |
|
|
ce => ce_1_sg_x0,
|
3935 |
|
|
clk => clk_1_sg_x0,
|
3936 |
|
|
d => counter4_op_net,
|
3937 |
|
|
en => "1",
|
3938 |
|
|
rst => "0",
|
3939 |
|
|
q => tx_en_in17_q_net
|
3940 |
|
|
);
|
3941 |
|
|
|
3942 |
|
|
tx_en_in18: entity work.xlregister
|
3943 |
|
|
generic map (
|
3944 |
|
|
d_width => 8,
|
3945 |
|
|
init_value => b"00000000"
|
3946 |
|
|
)
|
3947 |
|
|
port map (
|
3948 |
|
|
ce => ce_1_sg_x0,
|
3949 |
|
|
clk => clk_1_sg_x0,
|
3950 |
|
|
d => constant2_op_net,
|
3951 |
|
|
en => "1",
|
3952 |
|
|
rst => "0",
|
3953 |
|
|
q => tx_en_in18_q_net
|
3954 |
|
|
);
|
3955 |
|
|
|
3956 |
|
|
tx_en_in19: entity work.xlregister
|
3957 |
|
|
generic map (
|
3958 |
|
|
d_width => 12,
|
3959 |
|
|
init_value => b"000000000000"
|
3960 |
|
|
)
|
3961 |
|
|
port map (
|
3962 |
|
|
ce => ce_1_sg_x0,
|
3963 |
|
|
clk => clk_1_sg_x0,
|
3964 |
|
|
d => bram_addr_x0,
|
3965 |
|
|
en => "1",
|
3966 |
|
|
rst => "0",
|
3967 |
|
|
q => bram_wr_addr_net
|
3968 |
|
|
);
|
3969 |
|
|
|
3970 |
|
|
tx_en_in2: entity work.xlregister
|
3971 |
|
|
generic map (
|
3972 |
|
|
d_width => 32,
|
3973 |
|
|
init_value => b"00000000000000000000000000000000"
|
3974 |
|
|
)
|
3975 |
|
|
port map (
|
3976 |
|
|
ce => ce_1_sg_x0,
|
3977 |
|
|
clk => clk_1_sg_x0,
|
3978 |
|
|
d => dinb_x0,
|
3979 |
|
|
en(0) => timecountreset,
|
3980 |
|
|
rst(0) => constant1_op_net,
|
3981 |
|
|
q => data_in_net
|
3982 |
|
|
);
|
3983 |
|
|
|
3984 |
|
|
tx_en_in20: entity work.xlregister
|
3985 |
|
|
generic map (
|
3986 |
|
|
d_width => 64,
|
3987 |
|
|
init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
|
3988 |
|
|
)
|
3989 |
|
|
port map (
|
3990 |
|
|
ce => ce_1_sg_x0,
|
3991 |
|
|
clk => clk_1_sg_x0,
|
3992 |
|
|
d => bram_rd_dout_net,
|
3993 |
|
|
en => "1",
|
3994 |
|
|
rst => "0",
|
3995 |
|
|
q => bram_wr_din_net
|
3996 |
|
|
);
|
3997 |
|
|
|
3998 |
|
|
tx_en_in21: entity work.xlregister
|
3999 |
|
|
generic map (
|
4000 |
|
|
d_width => 1,
|
4001 |
|
|
init_value => b"0"
|
4002 |
|
|
)
|
4003 |
|
|
port map (
|
4004 |
|
|
ce => ce_1_sg_x0,
|
4005 |
|
|
clk => clk_1_sg_x0,
|
4006 |
|
|
d(0) => fifo_empty,
|
4007 |
|
|
en => "1",
|
4008 |
|
|
rst => "0",
|
4009 |
|
|
q(0) => fifo_empty_x0
|
4010 |
|
|
);
|
4011 |
|
|
|
4012 |
|
|
tx_en_in22: entity work.xlregister
|
4013 |
|
|
generic map (
|
4014 |
|
|
d_width => 1,
|
4015 |
|
|
init_value => b"0"
|
4016 |
|
|
)
|
4017 |
|
|
port map (
|
4018 |
|
|
ce => ce_1_sg_x0,
|
4019 |
|
|
clk => clk_1_sg_x0,
|
4020 |
|
|
d(0) => fifo_rd_en,
|
4021 |
|
|
en => "1",
|
4022 |
|
|
rst => "0",
|
4023 |
|
|
q(0) => fifo_rd_en_x0
|
4024 |
|
|
);
|
4025 |
|
|
|
4026 |
|
|
tx_en_in23: entity work.xlregister
|
4027 |
|
|
generic map (
|
4028 |
|
|
d_width => 1,
|
4029 |
|
|
init_value => b"0"
|
4030 |
|
|
)
|
4031 |
|
|
port map (
|
4032 |
|
|
ce => ce_1_sg_x0,
|
4033 |
|
|
clk => clk_1_sg_x0,
|
4034 |
|
|
d(0) => fifo_rd_valid_net,
|
4035 |
|
|
en => "1",
|
4036 |
|
|
rst => "0",
|
4037 |
|
|
q(0) => fifo_wr_en
|
4038 |
|
|
);
|
4039 |
|
|
|
4040 |
|
|
tx_en_in24: entity work.xlregister
|
4041 |
|
|
generic map (
|
4042 |
|
|
d_width => 72,
|
4043 |
|
|
init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000"
|
4044 |
|
|
)
|
4045 |
|
|
port map (
|
4046 |
|
|
ce => ce_1_sg_x0,
|
4047 |
|
|
clk => clk_1_sg_x0,
|
4048 |
|
|
d => fifo_rd_dout_net,
|
4049 |
|
|
en => "1",
|
4050 |
|
|
rst => "0",
|
4051 |
|
|
q => fifo_data_in_out
|
4052 |
|
|
);
|
4053 |
|
|
|
4054 |
|
|
tx_en_in25: entity work.xlregister
|
4055 |
|
|
generic map (
|
4056 |
|
|
d_width => 1,
|
4057 |
|
|
init_value => b"0"
|
4058 |
|
|
)
|
4059 |
|
|
port map (
|
4060 |
|
|
ce => ce_1_sg_x0,
|
4061 |
|
|
clk => clk_1_sg_x0,
|
4062 |
|
|
d(0) => fifo_rd_pempty_net,
|
4063 |
|
|
en => "1",
|
4064 |
|
|
rst => "0",
|
4065 |
|
|
q(0) => fifo_rd_pempty
|
4066 |
|
|
);
|
4067 |
|
|
|
4068 |
|
|
tx_en_in26: entity work.xlregister
|
4069 |
|
|
generic map (
|
4070 |
|
|
d_width => 1,
|
4071 |
|
|
init_value => b"0"
|
4072 |
|
|
)
|
4073 |
|
|
port map (
|
4074 |
|
|
ce => ce_1_sg_x0,
|
4075 |
|
|
clk => clk_1_sg_x0,
|
4076 |
|
|
d(0) => inverter3_op_net,
|
4077 |
|
|
en => "1",
|
4078 |
|
|
rst => "0",
|
4079 |
|
|
q(0) => rst_o_net
|
4080 |
|
|
);
|
4081 |
|
|
|
4082 |
|
|
tx_en_in27: entity work.xlregister
|
4083 |
|
|
generic map (
|
4084 |
|
|
d_width => 15,
|
4085 |
|
|
init_value => b"000000000000000"
|
4086 |
|
|
)
|
4087 |
|
|
port map (
|
4088 |
|
|
ce => ce_1_sg_x0,
|
4089 |
|
|
clk => clk_1_sg_x0,
|
4090 |
|
|
d => fifo_rd_count_net,
|
4091 |
|
|
en => "1",
|
4092 |
|
|
rst => "0",
|
4093 |
|
|
q => fifo_rd_count
|
4094 |
|
|
);
|
4095 |
|
|
|
4096 |
|
|
tx_en_in28: entity work.xlregister
|
4097 |
|
|
generic map (
|
4098 |
|
|
d_width => 1,
|
4099 |
|
|
init_value => b"0"
|
4100 |
|
|
)
|
4101 |
|
|
port map (
|
4102 |
|
|
ce => ce_1_sg_x0,
|
4103 |
|
|
clk => clk_1_sg_x0,
|
4104 |
|
|
d(0) => fifo_wr_full_net,
|
4105 |
|
|
en => "1",
|
4106 |
|
|
rst => "0",
|
4107 |
|
|
q(0) => fifo_wr_full
|
4108 |
|
|
);
|
4109 |
|
|
|
4110 |
|
|
tx_en_in29: entity work.xlregister
|
4111 |
|
|
generic map (
|
4112 |
|
|
d_width => 1,
|
4113 |
|
|
init_value => b"0"
|
4114 |
|
|
)
|
4115 |
|
|
port map (
|
4116 |
|
|
ce => ce_1_sg_x0,
|
4117 |
|
|
clk => clk_1_sg_x0,
|
4118 |
|
|
d(0) => fifo_wr_pfull_net,
|
4119 |
|
|
en => "1",
|
4120 |
|
|
rst => "0",
|
4121 |
|
|
q(0) => fifo_wr_pfull
|
4122 |
|
|
);
|
4123 |
|
|
|
4124 |
|
|
tx_en_in3: entity work.xlregister
|
4125 |
|
|
generic map (
|
4126 |
|
|
d_width => 1,
|
4127 |
|
|
init_value => b"0"
|
4128 |
|
|
)
|
4129 |
|
|
port map (
|
4130 |
|
|
ce => ce_1_sg_x0,
|
4131 |
|
|
clk => clk_1_sg_x0,
|
4132 |
|
|
d(0) => constant8_op_net,
|
4133 |
|
|
en => "1",
|
4134 |
|
|
rst => "0",
|
4135 |
|
|
q(0) => user_int_1o_net
|
4136 |
|
|
);
|
4137 |
|
|
|
4138 |
|
|
tx_en_in30: entity work.xlregister
|
4139 |
|
|
generic map (
|
4140 |
|
|
d_width => 12,
|
4141 |
|
|
init_value => b"000000000000"
|
4142 |
|
|
)
|
4143 |
|
|
port map (
|
4144 |
|
|
ce => ce_1_sg_x0,
|
4145 |
|
|
clk => clk_1_sg_x0,
|
4146 |
|
|
d => tx_en_in17_q_net,
|
4147 |
|
|
en => "1",
|
4148 |
|
|
rst => "0",
|
4149 |
|
|
q => tx_en_in30_q_net
|
4150 |
|
|
);
|
4151 |
|
|
|
4152 |
|
|
tx_en_in31: entity work.xlregister
|
4153 |
|
|
generic map (
|
4154 |
|
|
d_width => 15,
|
4155 |
|
|
init_value => b"000000000000000"
|
4156 |
|
|
)
|
4157 |
|
|
port map (
|
4158 |
|
|
ce => ce_1_sg_x0,
|
4159 |
|
|
clk => clk_1_sg_x0,
|
4160 |
|
|
d => fifo_wr_count_net,
|
4161 |
|
|
en => "1",
|
4162 |
|
|
rst => "0",
|
4163 |
|
|
q => fifo_wr_count
|
4164 |
|
|
);
|
4165 |
|
|
|
4166 |
|
|
tx_en_in33: entity work.xlregister
|
4167 |
|
|
generic map (
|
4168 |
|
|
d_width => 32,
|
4169 |
|
|
init_value => b"00000000000000000000000000000000"
|
4170 |
|
|
)
|
4171 |
|
|
port map (
|
4172 |
|
|
ce => ce_1_sg_x0,
|
4173 |
|
|
clk => clk_1_sg_x0,
|
4174 |
|
|
d => tx_en_in6_q_net,
|
4175 |
|
|
en(0) => convert1_dout_net,
|
4176 |
|
|
rst(0) => constant26_op_net,
|
4177 |
|
|
q => data_in_x11_net
|
4178 |
|
|
);
|
4179 |
|
|
|
4180 |
|
|
tx_en_in38: entity work.xlregister
|
4181 |
|
|
generic map (
|
4182 |
|
|
d_width => 72,
|
4183 |
|
|
init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000"
|
4184 |
|
|
)
|
4185 |
|
|
port map (
|
4186 |
|
|
ce => ce_1_sg_x0,
|
4187 |
|
|
clk => clk_1_sg_x0,
|
4188 |
|
|
d => fifo_rd_dout_net,
|
4189 |
|
|
en => "1",
|
4190 |
|
|
rst => "0",
|
4191 |
|
|
q => fifo_wr_din_net
|
4192 |
|
|
);
|
4193 |
|
|
|
4194 |
|
|
tx_en_in4: entity work.xlregister
|
4195 |
|
|
generic map (
|
4196 |
|
|
d_width => 1,
|
4197 |
|
|
init_value => b"0"
|
4198 |
|
|
)
|
4199 |
|
|
port map (
|
4200 |
|
|
ce => ce_1_sg_x0,
|
4201 |
|
|
clk => clk_1_sg_x0,
|
4202 |
|
|
d(0) => data_out_x27_net,
|
4203 |
|
|
en => "1",
|
4204 |
|
|
rst => "0",
|
4205 |
|
|
q(0) => tx_en_in4_q_net
|
4206 |
|
|
);
|
4207 |
|
|
|
4208 |
|
|
tx_en_in43: entity work.xlregister
|
4209 |
|
|
generic map (
|
4210 |
|
|
d_width => 8,
|
4211 |
|
|
init_value => b"00000000"
|
4212 |
|
|
)
|
4213 |
|
|
port map (
|
4214 |
|
|
ce => ce_1_sg_x0,
|
4215 |
|
|
clk => clk_1_sg_x0,
|
4216 |
|
|
d => tx_en_in18_q_net,
|
4217 |
|
|
en => "1",
|
4218 |
|
|
rst => "0",
|
4219 |
|
|
q => bram_wr_en_net
|
4220 |
|
|
);
|
4221 |
|
|
|
4222 |
|
|
tx_en_in5: entity work.xlregister
|
4223 |
|
|
generic map (
|
4224 |
|
|
d_width => 1,
|
4225 |
|
|
init_value => b"0"
|
4226 |
|
|
)
|
4227 |
|
|
port map (
|
4228 |
|
|
ce => ce_1_sg_x0,
|
4229 |
|
|
clk => clk_1_sg_x0,
|
4230 |
|
|
d(0) => data_out_x29_net,
|
4231 |
|
|
en => "1",
|
4232 |
|
|
rst => "0",
|
4233 |
|
|
q(0) => tx_en_in5_q_net
|
4234 |
|
|
);
|
4235 |
|
|
|
4236 |
|
|
tx_en_in50: entity work.xlregister
|
4237 |
|
|
generic map (
|
4238 |
|
|
d_width => 32,
|
4239 |
|
|
init_value => b"00000000000000000000000000000000"
|
4240 |
|
|
)
|
4241 |
|
|
port map (
|
4242 |
|
|
ce => ce_1_sg_x0,
|
4243 |
|
|
clk => clk_1_sg_x0,
|
4244 |
|
|
d => dinb,
|
4245 |
|
|
en(0) => convert5_dout_net,
|
4246 |
|
|
rst(0) => constant25_op_net,
|
4247 |
|
|
q => data_in_x23_net
|
4248 |
|
|
);
|
4249 |
|
|
|
4250 |
|
|
tx_en_in51: entity work.xlregister
|
4251 |
|
|
generic map (
|
4252 |
|
|
d_width => 1,
|
4253 |
|
|
init_value => b"0"
|
4254 |
|
|
)
|
4255 |
|
|
port map (
|
4256 |
|
|
ce => ce_1_sg_x0,
|
4257 |
|
|
clk => clk_1_sg_x0,
|
4258 |
|
|
d(0) => constant11_op_net,
|
4259 |
|
|
en => "1",
|
4260 |
|
|
rst => "0",
|
4261 |
|
|
q(0) => user_int_3o_net
|
4262 |
|
|
);
|
4263 |
|
|
|
4264 |
|
|
tx_en_in52: entity work.xlregister
|
4265 |
|
|
generic map (
|
4266 |
|
|
d_width => 32,
|
4267 |
|
|
init_value => b"00000000000000000000000000000000"
|
4268 |
|
|
)
|
4269 |
|
|
port map (
|
4270 |
|
|
ce => ce_1_sg_x0,
|
4271 |
|
|
clk => clk_1_sg_x0,
|
4272 |
|
|
d => data_out_x4_net,
|
4273 |
|
|
en => "1",
|
4274 |
|
|
rst => "0",
|
4275 |
|
|
q => tx_en_in52_q_net
|
4276 |
|
|
);
|
4277 |
|
|
|
4278 |
|
|
tx_en_in53: entity work.xlregister
|
4279 |
|
|
generic map (
|
4280 |
|
|
d_width => 32,
|
4281 |
|
|
init_value => b"00000000000000000000000000000000"
|
4282 |
|
|
)
|
4283 |
|
|
port map (
|
4284 |
|
|
ce => ce_1_sg_x0,
|
4285 |
|
|
clk => clk_1_sg_x0,
|
4286 |
|
|
d => tx_en_in60_q_net,
|
4287 |
|
|
en(0) => convert6_dout_net,
|
4288 |
|
|
rst(0) => constant24_op_net,
|
4289 |
|
|
q => data_in_x25_net
|
4290 |
|
|
);
|
4291 |
|
|
|
4292 |
|
|
tx_en_in54: entity work.xlregister
|
4293 |
|
|
generic map (
|
4294 |
|
|
d_width => 32,
|
4295 |
|
|
init_value => b"00000000000000000000000000000000"
|
4296 |
|
|
)
|
4297 |
|
|
port map (
|
4298 |
|
|
ce => ce_1_sg_x0,
|
4299 |
|
|
clk => clk_1_sg_x0,
|
4300 |
|
|
d => tx_en_in52_q_net,
|
4301 |
|
|
en(0) => convert7_dout_net,
|
4302 |
|
|
rst(0) => constant20_op_net,
|
4303 |
|
|
q => data_in_x26_net
|
4304 |
|
|
);
|
4305 |
|
|
|
4306 |
|
|
tx_en_in58: entity work.xlregister
|
4307 |
|
|
generic map (
|
4308 |
|
|
d_width => 1,
|
4309 |
|
|
init_value => b"0"
|
4310 |
|
|
)
|
4311 |
|
|
port map (
|
4312 |
|
|
ce => ce_1_sg_x0,
|
4313 |
|
|
clk => clk_1_sg_x0,
|
4314 |
|
|
d(0) => data_out_x1_net,
|
4315 |
|
|
en => "1",
|
4316 |
|
|
rst => "0",
|
4317 |
|
|
q(0) => tx_en_in58_q_net
|
4318 |
|
|
);
|
4319 |
|
|
|
4320 |
|
|
tx_en_in59: entity work.xlregister
|
4321 |
|
|
generic map (
|
4322 |
|
|
d_width => 1,
|
4323 |
|
|
init_value => b"0"
|
4324 |
|
|
)
|
4325 |
|
|
port map (
|
4326 |
|
|
ce => ce_1_sg_x0,
|
4327 |
|
|
clk => clk_1_sg_x0,
|
4328 |
|
|
d(0) => data_out_x3_net,
|
4329 |
|
|
en => "1",
|
4330 |
|
|
rst => "0",
|
4331 |
|
|
q(0) => tx_en_in59_q_net
|
4332 |
|
|
);
|
4333 |
|
|
|
4334 |
|
|
tx_en_in6: entity work.xlregister
|
4335 |
|
|
generic map (
|
4336 |
|
|
d_width => 32,
|
4337 |
|
|
init_value => b"00000000000000000000000000000000"
|
4338 |
|
|
)
|
4339 |
|
|
port map (
|
4340 |
|
|
ce => ce_1_sg_x0,
|
4341 |
|
|
clk => clk_1_sg_x0,
|
4342 |
|
|
d => data_out_x28_net,
|
4343 |
|
|
en => "1",
|
4344 |
|
|
rst => "0",
|
4345 |
|
|
q => tx_en_in6_q_net
|
4346 |
|
|
);
|
4347 |
|
|
|
4348 |
|
|
tx_en_in60: entity work.xlregister
|
4349 |
|
|
generic map (
|
4350 |
|
|
d_width => 32,
|
4351 |
|
|
init_value => b"00000000000000000000000000000000"
|
4352 |
|
|
)
|
4353 |
|
|
port map (
|
4354 |
|
|
ce => ce_1_sg_x0,
|
4355 |
|
|
clk => clk_1_sg_x0,
|
4356 |
|
|
d => data_out_x2_net,
|
4357 |
|
|
en => "1",
|
4358 |
|
|
rst => "0",
|
4359 |
|
|
q => tx_en_in60_q_net
|
4360 |
|
|
);
|
4361 |
|
|
|
4362 |
|
|
tx_en_in61: entity work.xlregister
|
4363 |
|
|
generic map (
|
4364 |
|
|
d_width => 1,
|
4365 |
|
|
init_value => b"0"
|
4366 |
|
|
)
|
4367 |
|
|
port map (
|
4368 |
|
|
ce => ce_1_sg_x0,
|
4369 |
|
|
clk => clk_1_sg_x0,
|
4370 |
|
|
d(0) => data_out_x5_net,
|
4371 |
|
|
en => "1",
|
4372 |
|
|
rst => "0",
|
4373 |
|
|
q(0) => tx_en_in61_q_net
|
4374 |
|
|
);
|
4375 |
|
|
|
4376 |
|
|
tx_en_in62: entity work.xlregister
|
4377 |
|
|
generic map (
|
4378 |
|
|
d_width => 32,
|
4379 |
|
|
init_value => b"00000000000000000000000000000000"
|
4380 |
|
|
)
|
4381 |
|
|
port map (
|
4382 |
|
|
ce => ce_1_sg_x0,
|
4383 |
|
|
clk => clk_1_sg_x0,
|
4384 |
|
|
d => data_out_x32_net,
|
4385 |
|
|
en => "1",
|
4386 |
|
|
rst => "0",
|
4387 |
|
|
q => dinb
|
4388 |
|
|
);
|
4389 |
|
|
|
4390 |
|
|
tx_en_in65: entity work.xlregister
|
4391 |
|
|
generic map (
|
4392 |
|
|
d_width => 32,
|
4393 |
|
|
init_value => b"00000000000000000000000000000000"
|
4394 |
|
|
)
|
4395 |
|
|
port map (
|
4396 |
|
|
ce => ce_1_sg_x0,
|
4397 |
|
|
clk => clk_1_sg_x0,
|
4398 |
|
|
d => data_out_x8_net,
|
4399 |
|
|
en => "1",
|
4400 |
|
|
rst => "0",
|
4401 |
|
|
q => tx_en_in65_q_net
|
4402 |
|
|
);
|
4403 |
|
|
|
4404 |
|
|
tx_en_in66: entity work.xlregister
|
4405 |
|
|
generic map (
|
4406 |
|
|
d_width => 32,
|
4407 |
|
|
init_value => b"00000000000000000000000000000000"
|
4408 |
|
|
)
|
4409 |
|
|
port map (
|
4410 |
|
|
ce => ce_1_sg_x0,
|
4411 |
|
|
clk => clk_1_sg_x0,
|
4412 |
|
|
d => tx_en_in65_q_net,
|
4413 |
|
|
en(0) => convert8_dout_net,
|
4414 |
|
|
rst(0) => constant12_op_net,
|
4415 |
|
|
q => data_in_x4_net
|
4416 |
|
|
);
|
4417 |
|
|
|
4418 |
|
|
tx_en_in67: entity work.xlregister
|
4419 |
|
|
generic map (
|
4420 |
|
|
d_width => 1,
|
4421 |
|
|
init_value => b"0"
|
4422 |
|
|
)
|
4423 |
|
|
port map (
|
4424 |
|
|
ce => ce_1_sg_x0,
|
4425 |
|
|
clk => clk_1_sg_x0,
|
4426 |
|
|
d(0) => data_out_x9_net,
|
4427 |
|
|
en => "1",
|
4428 |
|
|
rst => "0",
|
4429 |
|
|
q(0) => tx_en_in67_q_net
|
4430 |
|
|
);
|
4431 |
|
|
|
4432 |
|
|
tx_en_in7: entity work.xlregister
|
4433 |
|
|
generic map (
|
4434 |
|
|
d_width => 1,
|
4435 |
|
|
init_value => b"0"
|
4436 |
|
|
)
|
4437 |
|
|
port map (
|
4438 |
|
|
ce => ce_1_sg_x0,
|
4439 |
|
|
clk => clk_1_sg_x0,
|
4440 |
|
|
d(0) => timecounttrigger,
|
4441 |
|
|
en => "1",
|
4442 |
|
|
rst => "0",
|
4443 |
|
|
q(0) => data_in_x22_net
|
4444 |
|
|
);
|
4445 |
|
|
|
4446 |
|
|
tx_en_in75: entity work.xlregister
|
4447 |
|
|
generic map (
|
4448 |
|
|
d_width => 1,
|
4449 |
|
|
init_value => b"0"
|
4450 |
|
|
)
|
4451 |
|
|
port map (
|
4452 |
|
|
ce => ce_1_sg_x0,
|
4453 |
|
|
clk => clk_1_sg_x0,
|
4454 |
|
|
d(0) => constant10_op_net,
|
4455 |
|
|
en => "1",
|
4456 |
|
|
rst => "0",
|
4457 |
|
|
q(0) => user_int_2o_net
|
4458 |
|
|
);
|
4459 |
|
|
|
4460 |
|
|
tx_en_in8: entity work.xlregister
|
4461 |
|
|
generic map (
|
4462 |
|
|
d_width => 1,
|
4463 |
|
|
init_value => b"0"
|
4464 |
|
|
)
|
4465 |
|
|
port map (
|
4466 |
|
|
ce => ce_1_sg_x0,
|
4467 |
|
|
clk => clk_1_sg_x0,
|
4468 |
|
|
d(0) => data_out_x31_net,
|
4469 |
|
|
en => "1",
|
4470 |
|
|
rst => "0",
|
4471 |
|
|
q(0) => tx_en_in8_q_net
|
4472 |
|
|
);
|
4473 |
|
|
|
4474 |
|
|
tx_en_in85: entity work.xlregister
|
4475 |
|
|
generic map (
|
4476 |
|
|
d_width => 32,
|
4477 |
|
|
init_value => b"00000000000000000000000000000001"
|
4478 |
|
|
)
|
4479 |
|
|
port map (
|
4480 |
|
|
ce => ce_1_sg_x0,
|
4481 |
|
|
clk => clk_1_sg_x0,
|
4482 |
|
|
d => tx_en_in87_q_net,
|
4483 |
|
|
en(0) => convert4_dout_net,
|
4484 |
|
|
rst(0) => constant7_op_net,
|
4485 |
|
|
q => data_in_x6_net
|
4486 |
|
|
);
|
4487 |
|
|
|
4488 |
|
|
tx_en_in86: entity work.xlregister
|
4489 |
|
|
generic map (
|
4490 |
|
|
d_width => 1,
|
4491 |
|
|
init_value => b"0"
|
4492 |
|
|
)
|
4493 |
|
|
port map (
|
4494 |
|
|
ce => ce_1_sg_x0,
|
4495 |
|
|
clk => clk_1_sg_x0,
|
4496 |
|
|
d(0) => data_out_x13_net,
|
4497 |
|
|
en => "1",
|
4498 |
|
|
rst => "0",
|
4499 |
|
|
q(0) => tx_en_in86_q_net
|
4500 |
|
|
);
|
4501 |
|
|
|
4502 |
|
|
tx_en_in87: entity work.xlregister
|
4503 |
|
|
generic map (
|
4504 |
|
|
d_width => 32,
|
4505 |
|
|
init_value => b"00000000000000000000000000000000"
|
4506 |
|
|
)
|
4507 |
|
|
port map (
|
4508 |
|
|
ce => ce_1_sg_x0,
|
4509 |
|
|
clk => clk_1_sg_x0,
|
4510 |
|
|
d => data_out_x12_net,
|
4511 |
|
|
en => "1",
|
4512 |
|
|
rst => "0",
|
4513 |
|
|
q => tx_en_in87_q_net
|
4514 |
|
|
);
|
4515 |
|
|
|
4516 |
|
|
tx_en_in88: entity work.xlregister
|
4517 |
|
|
generic map (
|
4518 |
|
|
d_width => 32,
|
4519 |
|
|
init_value => b"10000000000000000000000000000000"
|
4520 |
|
|
)
|
4521 |
|
|
port map (
|
4522 |
|
|
ce => ce_1_sg_x0,
|
4523 |
|
|
clk => clk_1_sg_x0,
|
4524 |
|
|
d => tx_en_in90_q_net,
|
4525 |
|
|
en(0) => convert11_dout_net,
|
4526 |
|
|
rst(0) => constant4_op_net,
|
4527 |
|
|
q => data_in_x8_net
|
4528 |
|
|
);
|
4529 |
|
|
|
4530 |
|
|
tx_en_in89: entity work.xlregister
|
4531 |
|
|
generic map (
|
4532 |
|
|
d_width => 1,
|
4533 |
|
|
init_value => b"0"
|
4534 |
|
|
)
|
4535 |
|
|
port map (
|
4536 |
|
|
ce => ce_1_sg_x0,
|
4537 |
|
|
clk => clk_1_sg_x0,
|
4538 |
|
|
d(0) => data_out_x15_net,
|
4539 |
|
|
en => "1",
|
4540 |
|
|
rst => "0",
|
4541 |
|
|
q(0) => tx_en_in89_q_net
|
4542 |
|
|
);
|
4543 |
|
|
|
4544 |
|
|
tx_en_in9: entity work.xlregister
|
4545 |
|
|
generic map (
|
4546 |
|
|
d_width => 32,
|
4547 |
|
|
init_value => b"00000000000000000000000000000000"
|
4548 |
|
|
)
|
4549 |
|
|
port map (
|
4550 |
|
|
ce => ce_1_sg_x0,
|
4551 |
|
|
clk => clk_1_sg_x0,
|
4552 |
|
|
d => data_out_x22_net,
|
4553 |
|
|
en => "1",
|
4554 |
|
|
rst => "0",
|
4555 |
|
|
q => dinb_x0
|
4556 |
|
|
);
|
4557 |
|
|
|
4558 |
|
|
tx_en_in90: entity work.xlregister
|
4559 |
|
|
generic map (
|
4560 |
|
|
d_width => 32,
|
4561 |
|
|
init_value => b"00000000000000000000000000000000"
|
4562 |
|
|
)
|
4563 |
|
|
port map (
|
4564 |
|
|
ce => ce_1_sg_x0,
|
4565 |
|
|
clk => clk_1_sg_x0,
|
4566 |
|
|
d => data_out_x14_net,
|
4567 |
|
|
en => "1",
|
4568 |
|
|
rst => "0",
|
4569 |
|
|
q => tx_en_in90_q_net
|
4570 |
|
|
);
|
4571 |
|
|
|
4572 |
|
|
tx_en_in91: entity work.xlregister
|
4573 |
|
|
generic map (
|
4574 |
|
|
d_width => 32,
|
4575 |
|
|
init_value => b"00000000000000000000000000000000"
|
4576 |
|
|
)
|
4577 |
|
|
port map (
|
4578 |
|
|
ce => ce_1_sg_x0,
|
4579 |
|
|
clk => clk_1_sg_x0,
|
4580 |
|
|
d => tx_en_in93_q_net,
|
4581 |
|
|
en(0) => convert12_dout_net,
|
4582 |
|
|
rst(0) => constant9_op_net,
|
4583 |
|
|
q => data_in_x10_net
|
4584 |
|
|
);
|
4585 |
|
|
|
4586 |
|
|
tx_en_in92: entity work.xlregister
|
4587 |
|
|
generic map (
|
4588 |
|
|
d_width => 1,
|
4589 |
|
|
init_value => b"0"
|
4590 |
|
|
)
|
4591 |
|
|
port map (
|
4592 |
|
|
ce => ce_1_sg_x0,
|
4593 |
|
|
clk => clk_1_sg_x0,
|
4594 |
|
|
d(0) => data_out_x17_net,
|
4595 |
|
|
en => "1",
|
4596 |
|
|
rst => "0",
|
4597 |
|
|
q(0) => tx_en_in92_q_net
|
4598 |
|
|
);
|
4599 |
|
|
|
4600 |
|
|
tx_en_in93: entity work.xlregister
|
4601 |
|
|
generic map (
|
4602 |
|
|
d_width => 32,
|
4603 |
|
|
init_value => b"00000000000000000000000000000000"
|
4604 |
|
|
)
|
4605 |
|
|
port map (
|
4606 |
|
|
ce => ce_1_sg_x0,
|
4607 |
|
|
clk => clk_1_sg_x0,
|
4608 |
|
|
d => data_out_x16_net,
|
4609 |
|
|
en => "1",
|
4610 |
|
|
rst => "0",
|
4611 |
|
|
q => tx_en_in93_q_net
|
4612 |
|
|
);
|
4613 |
|
|
|
4614 |
|
|
tx_en_in94: entity work.xlregister
|
4615 |
|
|
generic map (
|
4616 |
|
|
d_width => 1,
|
4617 |
|
|
init_value => b"0"
|
4618 |
|
|
)
|
4619 |
|
|
port map (
|
4620 |
|
|
ce => ce_1_sg_x0,
|
4621 |
|
|
clk => clk_1_sg_x0,
|
4622 |
|
|
d(0) => convert1_dout_net,
|
4623 |
|
|
en => "1",
|
4624 |
|
|
rst => "0",
|
4625 |
|
|
q(0) => data_in_x21_net
|
4626 |
|
|
);
|
4627 |
|
|
|
4628 |
|
|
tx_en_in95: entity work.xlregister
|
4629 |
|
|
generic map (
|
4630 |
|
|
d_width => 1,
|
4631 |
|
|
init_value => b"0"
|
4632 |
|
|
)
|
4633 |
|
|
port map (
|
4634 |
|
|
ce => ce_1_sg_x0,
|
4635 |
|
|
clk => clk_1_sg_x0,
|
4636 |
|
|
d(0) => convert5_dout_net,
|
4637 |
|
|
en => "1",
|
4638 |
|
|
rst => "0",
|
4639 |
|
|
q(0) => data_in_x24_net
|
4640 |
|
|
);
|
4641 |
|
|
|
4642 |
|
|
tx_en_in96: entity work.xlregister
|
4643 |
|
|
generic map (
|
4644 |
|
|
d_width => 1,
|
4645 |
|
|
init_value => b"0"
|
4646 |
|
|
)
|
4647 |
|
|
port map (
|
4648 |
|
|
ce => ce_1_sg_x0,
|
4649 |
|
|
clk => clk_1_sg_x0,
|
4650 |
|
|
d(0) => convert6_dout_net,
|
4651 |
|
|
en => "1",
|
4652 |
|
|
rst => "0",
|
4653 |
|
|
q(0) => data_in_x1_net
|
4654 |
|
|
);
|
4655 |
|
|
|
4656 |
|
|
tx_en_in97: entity work.xlregister
|
4657 |
|
|
generic map (
|
4658 |
|
|
d_width => 1,
|
4659 |
|
|
init_value => b"0"
|
4660 |
|
|
)
|
4661 |
|
|
port map (
|
4662 |
|
|
ce => ce_1_sg_x0,
|
4663 |
|
|
clk => clk_1_sg_x0,
|
4664 |
|
|
d(0) => convert7_dout_net,
|
4665 |
|
|
en => "1",
|
4666 |
|
|
rst => "0",
|
4667 |
|
|
q(0) => data_in_x2_net
|
4668 |
|
|
);
|
4669 |
|
|
|
4670 |
|
|
tx_en_in98: entity work.xlregister
|
4671 |
|
|
generic map (
|
4672 |
|
|
d_width => 1,
|
4673 |
|
|
init_value => b"0"
|
4674 |
|
|
)
|
4675 |
|
|
port map (
|
4676 |
|
|
ce => ce_1_sg_x0,
|
4677 |
|
|
clk => clk_1_sg_x0,
|
4678 |
|
|
d(0) => convert4_dout_net,
|
4679 |
|
|
en => "1",
|
4680 |
|
|
rst => "0",
|
4681 |
|
|
q(0) => data_in_x5_net
|
4682 |
|
|
);
|
4683 |
|
|
|
4684 |
|
|
tx_en_in99: entity work.xlregister
|
4685 |
|
|
generic map (
|
4686 |
|
|
d_width => 1,
|
4687 |
|
|
init_value => b"0"
|
4688 |
|
|
)
|
4689 |
|
|
port map (
|
4690 |
|
|
ce => ce_1_sg_x0,
|
4691 |
|
|
clk => clk_1_sg_x0,
|
4692 |
|
|
d(0) => convert11_dout_net,
|
4693 |
|
|
en => "1",
|
4694 |
|
|
rst => "0",
|
4695 |
|
|
q(0) => data_in_x7_net
|
4696 |
|
|
);
|
4697 |
|
|
|
4698 |
|
|
end structural;
|