Subversion Repositories pcie_sg_dma

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--    This file is owned and controlled by Xilinx and must be used solely     --

--    for design, simulation, implementation and creation of design files     --

--    limited to Xilinx devices or technologies. Use with non-Xilinx          --

--    devices or technologies is expressly prohibited and immediately         --

--    terminates your license.                                                --

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--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --

--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --

--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --

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--    (c) Copyright 1995-2012 Xilinx, Inc.                                    --

--    All rights reserved.                                                    --

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-- You must compile the wrapper file cntr_11_0_341fbb8cfa0e669e.vhd when simulating

-- the core, cntr_11_0_341fbb8cfa0e669e. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY cntr_11_0_341fbb8cfa0e669e IS

  PORT (

    clk : IN STD_LOGIC;

    ce : IN STD_LOGIC;

    sinit : IN STD_LOGIC;

    q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)

  );

END cntr_11_0_341fbb8cfa0e669e;

ARCHITECTURE cntr_11_0_341fbb8cfa0e669e_a OF cntr_11_0_341fbb8cfa0e669e IS

-- synthesis translate_off

COMPONENT wrapped_cntr_11_0_341fbb8cfa0e669e

  PORT (

    clk : IN STD_LOGIC;

    ce : IN STD_LOGIC;

    sinit : IN STD_LOGIC;

    q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_cntr_11_0_341fbb8cfa0e669e USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)

    GENERIC MAP (

      c_ainit_val => "0",

      c_ce_overrides_sync => 0,

      c_count_by => "1",

      c_count_mode => 0,

      c_count_to => "1",

      c_fb_latency => 0,

      c_has_ce => 1,

      c_has_load => 0,

      c_has_sclr => 0,

      c_has_sinit => 1,

      c_has_sset => 0,

      c_has_thresh0 => 0,

      c_implementation => 0,

      c_latency => 1,

      c_load_low => 0,

      c_restrict_count => 0,

      c_sclr_overrides_sset => 1,

      c_sinit_val => "0",

      c_thresh0_value => "1",

      c_verbosity => 0,

      c_width => 12,

      c_xdevicefamily => "virtex6"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_cntr_11_0_341fbb8cfa0e669e

  PORT MAP (

    clk => clk,

    ce => ce,

    sinit => sinit,

    q => q

  );

-- synthesis translate_on

END cntr_11_0_341fbb8cfa0e669e_a;