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--
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-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : PIO.vhd
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-- Version : 1.6
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----
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---- Description: Programmed I/O module. Design implements 8 KBytes of programmable
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---- memory space. Host processor can access this memory space using
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---- Memory Read 32 and Memory Write 32 TLPs. Design accepts
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---- 1 Double Word (DW) payload length on Memory Write 32 TLP and
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---- responds to 1 DW length Memory Read 32 TLPs with a Completion
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---- with Data TLP (1DW payload).
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----
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---- Module is designed to operate with 32 bit and 64 bit interfaces.
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity PIO is
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port (
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trn_clk : in std_logic;
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trn_reset_n : in std_logic;
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trn_lnk_up_n : in std_logic;
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trn_td : out std_logic_vector(63 downto 0);
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trn_trem_n : out std_logic_vector(7 downto 0);
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_tdst_rdy_n : in std_logic;
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trn_tdst_dsc_n : in std_logic;
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic_vector(7 downto 0);
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_rdst_rdy_n : out std_logic;
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cfg_to_turnoff_n : in std_logic;
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cfg_turnoff_ok_n : out std_logic;
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cfg_completer_id : in std_logic_vector(15 downto 0);
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cfg_bus_mstr_enable : in std_logic
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);
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end PIO;
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architecture rtl of PIO is
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-- Local wires
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signal req_compl : std_logic;
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signal compl_done : std_logic;
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signal pio_reset_n : std_logic;
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component PIO_EP
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- LocalLink Tx
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trn_td : out std_logic_vector(63 downto 0);
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trn_trem_n : out std_logic_vector(7 downto 0);
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tdst_dsc_n : in std_logic;
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trn_tdst_rdy_n : in std_logic;
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-- LocalLink Rx
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic_vector(7 downto 0);
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_rdst_rdy_n : out std_logic;
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req_compl_o : out std_logic;
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compl_done_o : out std_logic;
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cfg_completer_id : in std_logic_vector(15 downto 0);
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cfg_bus_mstr_enable : in std_logic
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);
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end component;
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component PIO_TO_CTRL
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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req_compl_i : in std_logic;
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compl_done_i : in std_logic;
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cfg_to_turnoff_n : in std_logic;
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cfg_turnoff_ok_n : out std_logic
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);
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end component;
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begin
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pio_reset_n <= not trn_lnk_up_n;
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-- PIO instance
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PIO_EP_ins : PIO_EP
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port map (
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clk => trn_clk, -- I
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rst_n => pio_reset_n, -- I
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trn_td => trn_td, -- O [127/63:0]
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trn_trem_n => trn_trem_n, -- O [1/0:0]
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trn_tsof_n => trn_tsof_n, -- O
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trn_teof_n => trn_teof_n, -- O
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trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
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trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
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trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
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trn_tdst_dsc_n => trn_tdst_dsc_n, -- I
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trn_rd => trn_rd, -- I [127/63:0]
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trn_rrem_n => trn_rrem_n, -- I [1/0:0]
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trn_rsof_n => trn_rsof_n, -- I
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trn_reof_n => trn_reof_n, -- I
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trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
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trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
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trn_rbar_hit_n => trn_rbar_hit_n, -- I
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trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
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req_compl_o => req_compl, -- O
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compl_done_o => compl_done, -- O
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cfg_completer_id => cfg_completer_id, -- I [15:0]
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cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I
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);
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--
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-- Turn-Off controller
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--
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PIO_TO : PIO_TO_CTRL port map (
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clk => trn_clk, -- I
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rst_n => trn_reset_n, -- I
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req_compl_i => req_compl, -- I
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compl_done_i => compl_done, -- I
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cfg_to_turnoff_n => cfg_to_turnoff_n, -- I
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cfg_turnoff_ok_n => cfg_turnoff_ok_n -- O
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);
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end; -- PIO
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