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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : PIO_EP_MEM_ACCESS.vhd
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-- Version : 1.6
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----
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---- Description: Endpoint Memory Access Unit. This module provides access functions
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---- to the Endpoint memory aperture.
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----
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---- Read Access: Module returns data for the specifed address and
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---- byte enables selected.
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----
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---- Write Access: Module accepts data and byte enables and updates
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---- data when write enable is asserted. Modules signals write busy
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---- write is in progress.
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity PIO_EP_MEM_ACCESS is port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- Read Port
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rd_addr_i : in std_logic_vector(10 downto 0);
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rd_be_i : in std_logic_vector(3 downto 0);
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rd_data_o : out std_logic_vector(31 downto 0);
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-- Write Port
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wr_addr_i : in std_logic_vector(10 downto 0);
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wr_be_i : in std_logic_vector(7 downto 0);
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wr_data_i : in std_logic_vector(31 downto 0);
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wr_en_i : in std_logic;
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wr_busy_o : out std_logic
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);
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end PIO_EP_MEM_ACCESS;
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architecture rtl of PIO_EP_MEM_ACCESS is
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type state_type is (PIO_MEM_ACCESS_WR_RST,
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PIO_MEM_ACCESS_WR_READ,
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PIO_MEM_ACCESS_WR_WRITE
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);
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component EP_MEM port (
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clk_i : in std_logic ;
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a_rd_a_i_0 : in std_logic_vector(8 downto 0);
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a_rd_d_o_0 : out std_logic_vector(31 downto 0);
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a_rd_en_i_0 : in std_logic ;
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b_wr_a_i_0 : in std_logic_vector(8 downto 0);
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b_wr_d_i_0 : in std_logic_vector(31 downto 0);
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b_wr_en_i_0 : in std_logic ;
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b_rd_d_o_0 : out std_logic_vector(31 downto 0);
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b_rd_en_i_0 : in std_logic ;
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a_rd_a_i_1 : in std_logic_vector(8 downto 0);
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a_rd_d_o_1 : out std_logic_vector(31 downto 0);
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a_rd_en_i_1 : in std_logic ;
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b_wr_a_i_1 : in std_logic_vector(8 downto 0);
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b_wr_d_i_1 : in std_logic_vector(31 downto 0);
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b_wr_en_i_1 : in std_logic ;
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b_rd_d_o_1 : out std_logic_vector(31 downto 0);
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b_rd_en_i_1 : in std_logic ;
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a_rd_a_i_2 : in std_logic_vector(8 downto 0);
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a_rd_d_o_2 : out std_logic_vector(31 downto 0);
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a_rd_en_i_2 : in std_logic ;
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b_wr_a_i_2 : in std_logic_vector(8 downto 0);
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b_wr_d_i_2 : in std_logic_vector(31 downto 0);
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b_wr_en_i_2 : in std_logic ;
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b_rd_d_o_2 : out std_logic_vector(31 downto 0);
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b_rd_en_i_2 : in std_logic ;
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a_rd_a_i_3 : in std_logic_vector(8 downto 0);
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a_rd_d_o_3 : out std_logic_vector(31 downto 0);
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a_rd_en_i_3 : in std_logic ;
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b_wr_a_i_3 : in std_logic_vector(8 downto 0);
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b_wr_d_i_3 : in std_logic_vector(31 downto 0);
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b_wr_en_i_3 : in std_logic ;
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b_rd_d_o_3 : out std_logic_vector(31 downto 0);
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b_rd_en_i_3 : in std_logic
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);
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end component;
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signal rd_data0_q : std_logic_vector(31 downto 0);
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signal rd_data1_q : std_logic_vector(31 downto 0);
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signal rd_data2_q : std_logic_vector(31 downto 0);
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signal rd_data3_q : std_logic_vector(31 downto 0);
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signal rd_data0_o : std_logic_vector(31 downto 0);
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signal rd_data1_o : std_logic_vector(31 downto 0);
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signal rd_data2_o : std_logic_vector(31 downto 0);
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signal rd_data3_o : std_logic_vector(31 downto 0);
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signal write_en : std_logic;
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signal post_wr_data : std_logic_vector(31 downto 0);
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signal w_pre_wr_data : std_logic_vector(31 downto 0);
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signal wr_mem_state : state_type;
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signal pre_wr_data : std_logic_vector(31 downto 0);
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signal w_pre_wr_data0 : std_logic_vector(31 downto 0);
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signal w_pre_wr_data1 : std_logic_vector(31 downto 0);
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signal w_pre_wr_data2 : std_logic_vector(31 downto 0);
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signal w_pre_wr_data3 : std_logic_vector(31 downto 0);
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signal pre_wr_data0_q, pre_wr_data1_q : std_logic_vector(31 downto 0);
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signal pre_wr_data2_q, pre_wr_data3_q : std_logic_vector(31 downto 0);
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signal rd_data_raw_o : std_logic_vector(31 downto 0);
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-- Memory Write Process
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-- Extract current data bytes. These need to be swizzled
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-- BRAM storage format :
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-- data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
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signal w_pre_wr_data_b3 : std_logic_vector(7 downto 0);
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signal w_pre_wr_data_b2 : std_logic_vector(7 downto 0);
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signal w_pre_wr_data_b1 : std_logic_vector(7 downto 0);
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signal w_pre_wr_data_b0 : std_logic_vector(7 downto 0);
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-- Extract new data bytes from payload
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-- TLP Payload format :
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-- data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
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signal w_wr_data_b3 : std_logic_vector(7 downto 0);
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signal w_wr_data_b2 : std_logic_vector(7 downto 0);
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signal w_wr_data_b1 : std_logic_vector(7 downto 0);
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signal w_wr_data_b0 : std_logic_vector(7 downto 0);
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signal w_wr_data0_int : std_logic_vector(7 downto 0);
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signal w_wr_data1_int : std_logic_vector(7 downto 0);
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signal w_wr_data2_int : std_logic_vector(7 downto 0);
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signal w_wr_data3_int : std_logic_vector(7 downto 0);
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signal rd_data0_en : std_logic;
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signal rd_data1_en : std_logic;
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signal rd_data2_en : std_logic;
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signal rd_data3_en : std_logic;
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signal interim : std_logic;
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signal rd_data_raw_int0 : std_logic_vector(7 downto 0);
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signal rd_data_raw_int1 : std_logic_vector(7 downto 0);
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signal rd_data_raw_int2 : std_logic_vector(7 downto 0);
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signal rd_data_raw_int3 : std_logic_vector(7 downto 0);
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signal b_wr_en_0, b_wr_en_0_int : std_logic;
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signal b_wr_en_1, b_wr_en_1_int : std_logic;
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signal b_wr_en_2, b_wr_en_2_int : std_logic;
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signal b_wr_en_3, b_wr_en_3_int : std_logic;
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signal wr_addr_0 : std_logic;
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signal wr_addr_1 : std_logic;
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signal wr_addr_2 : std_logic;
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signal wr_addr_3 : std_logic;
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begin
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w_wr_data_b3 <= wr_data_i(7 downto 0);
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w_wr_data_b2 <= wr_data_i(15 downto 8);
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w_wr_data_b1 <= wr_data_i(23 downto 16);
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w_wr_data_b0 <= wr_data_i(31 downto 24);
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w_pre_wr_data_b3 <= pre_wr_data(31 downto 24);
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w_pre_wr_data_b2 <= pre_wr_data(23 downto 16);
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w_pre_wr_data_b1 <= pre_wr_data(15 downto 08);
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w_pre_wr_data_b0 <= pre_wr_data(07 downto 00);
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w_wr_data3_int <= w_wr_data_b3 when (wr_be_i(3) = '1') else w_pre_wr_data_b3;
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w_wr_data2_int <= w_wr_data_b2 when (wr_be_i(2) = '1') else w_pre_wr_data_b2;
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w_wr_data1_int <= w_wr_data_b1 when (wr_be_i(1) = '1') else w_pre_wr_data_b1;
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w_wr_data0_int <= w_wr_data_b0 when (wr_be_i(0) = '1') else w_pre_wr_data_b0;
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process(clk, rst_n)
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begin
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if ( rst_n = '0' ) then
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write_en <= '0';
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pre_wr_data <= (others => '0');
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post_wr_data <= (others => '0');
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pre_wr_data <= (others => '0');
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pre_wr_data0_q <= (others => '0');
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pre_wr_data1_q <= (others => '0');
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pre_wr_data2_q <= (others => '0');
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pre_wr_data3_q <= (others => '0');
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wr_mem_state <= PIO_MEM_ACCESS_WR_RST;
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else
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if (clk'event and clk = '1') then
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case ( wr_mem_state ) is
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when PIO_MEM_ACCESS_WR_RST =>
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if (wr_en_i = '1') then -- read state
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-- Pipeline B port data before processing
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pre_wr_data0_q <= w_pre_wr_data0;
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pre_wr_data1_q <= w_pre_wr_data1;
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pre_wr_data2_q <= w_pre_wr_data2;
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pre_wr_data3_q <= w_pre_wr_data3;
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write_en <= '0';
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wr_mem_state <= PIO_MEM_ACCESS_WR_READ ;
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else
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write_en <= '0';
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wr_mem_state <= PIO_MEM_ACCESS_WR_RST;
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end if;
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when PIO_MEM_ACCESS_WR_READ =>
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-- Now save the selected BRAM B port data out
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pre_wr_data <= w_pre_wr_data;
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write_en <= '0';
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wr_mem_state <= PIO_MEM_ACCESS_WR_WRITE;
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when PIO_MEM_ACCESS_WR_WRITE =>
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-- Merge new enabled data and write target BlockRAM location
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post_wr_data <= w_wr_data3_int &
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w_wr_data2_int &
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w_wr_data1_int &
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w_wr_data0_int;
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write_en <= '1';
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wr_mem_state <= PIO_MEM_ACCESS_WR_RST;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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-- Write controller busy
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wr_busy_o <= wr_en_i or interim;
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interim <= '1' when (wr_mem_state /= PIO_MEM_ACCESS_WR_RST) else '0';
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-- Select BlockRAM output based on higher 2 address bits
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process(wr_addr_i, pre_wr_data0_q, pre_wr_data1_q, pre_wr_data2_q,
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pre_wr_data3_q)
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begin
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case (wr_addr_i(10 downto 9)) is
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when "00" => w_pre_wr_data <= pre_wr_data0_q;
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when "01" => w_pre_wr_data <= pre_wr_data1_q;
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323 |
|
|
when "10" => w_pre_wr_data <= pre_wr_data2_q;
|
324 |
|
|
when "11" => w_pre_wr_data <= pre_wr_data3_q;
|
325 |
|
|
when others => null;
|
326 |
|
|
|
327 |
|
|
end case;
|
328 |
|
|
|
329 |
|
|
end process;
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
-- Memory Read Controller
|
333 |
|
|
|
334 |
|
|
rd_data0_en <= '1' when (rd_addr_i(10 downto 9) = "00") else '0';
|
335 |
|
|
rd_data1_en <= '1' when (rd_addr_i(10 downto 9) = "01") else '0';
|
336 |
|
|
rd_data2_en <= '1' when (rd_addr_i(10 downto 9) = "10") else '0';
|
337 |
|
|
rd_data3_en <= '1' when (rd_addr_i(10 downto 9) = "11") else '0';
|
338 |
|
|
|
339 |
|
|
-- pipeline stage BRAM read data before processing --
|
340 |
|
|
|
341 |
|
|
process(rst_n, clk)
|
342 |
|
|
begin
|
343 |
|
|
|
344 |
|
|
if ( rst_n = '0' ) then
|
345 |
|
|
|
346 |
|
|
rd_data0_q <= (others => '0');
|
347 |
|
|
rd_data1_q <= (others => '0');
|
348 |
|
|
rd_data2_q <= (others => '0');
|
349 |
|
|
rd_data3_q <= (others => '0');
|
350 |
|
|
|
351 |
|
|
else
|
352 |
|
|
|
353 |
|
|
if (clk'event and clk='1') then
|
354 |
|
|
|
355 |
|
|
rd_data0_q <= rd_data0_o(31 downto 0);
|
356 |
|
|
rd_data1_q <= rd_data1_o(31 downto 0);
|
357 |
|
|
rd_data2_q <= rd_data2_o(31 downto 0);
|
358 |
|
|
rd_data3_q <= rd_data3_o(31 downto 0);
|
359 |
|
|
|
360 |
|
|
end if;
|
361 |
|
|
|
362 |
|
|
end if;
|
363 |
|
|
|
364 |
|
|
end process;
|
365 |
|
|
|
366 |
|
|
process(rd_addr_i(10 downto 0), rd_data0_q(31 downto 0), rd_data1_q(31 downto 0),
|
367 |
|
|
rd_data2_q(31 downto 0), rd_data3_q(31 downto 0))
|
368 |
|
|
begin
|
369 |
|
|
|
370 |
|
|
case (rd_addr_i(10 downto 9)) is
|
371 |
|
|
|
372 |
|
|
when "00" => rd_data_raw_o <= rd_data0_q(31 downto 0);
|
373 |
|
|
when "01" => rd_data_raw_o <= rd_data1_q(31 downto 0);
|
374 |
|
|
when "10" => rd_data_raw_o <= rd_data2_q(31 downto 0);
|
375 |
|
|
when "11" => rd_data_raw_o <= rd_data3_q(31 downto 0);
|
376 |
|
|
when others => null;
|
377 |
|
|
|
378 |
|
|
end case;
|
379 |
|
|
|
380 |
|
|
end process;
|
381 |
|
|
|
382 |
|
|
-- Handle Read byte enables --
|
383 |
|
|
|
384 |
|
|
rd_data_o <= rd_data_raw_int0 &
|
385 |
|
|
rd_data_raw_int1 &
|
386 |
|
|
rd_data_raw_int2 &
|
387 |
|
|
rd_data_raw_int3 ;
|
388 |
|
|
|
389 |
|
|
rd_data_raw_int0 <= rd_data_raw_o(7 downto 0) when (rd_be_i(0) = '1') else (others => '0');
|
390 |
|
|
rd_data_raw_int1 <= rd_data_raw_o(15 downto 8) when (rd_be_i(1) = '1') else (others => '0');
|
391 |
|
|
rd_data_raw_int2 <= rd_data_raw_o(23 downto 16) when (rd_be_i(2) = '1') else (others => '0');
|
392 |
|
|
rd_data_raw_int3 <= rd_data_raw_o (31 downto 24) when (rd_be_i(3) = '1') else (others => '0');
|
393 |
|
|
|
394 |
|
|
b_wr_en_0 <= write_en and b_wr_en_0_int;
|
395 |
|
|
b_wr_en_0_int <= '1' when (wr_addr_i(10 downto 9) = "00") else '0';
|
396 |
|
|
|
397 |
|
|
b_wr_en_1 <= write_en and b_wr_en_1_int;
|
398 |
|
|
b_wr_en_1_int <= '1' when (wr_addr_i(10 downto 9) = "01") else '0';
|
399 |
|
|
|
400 |
|
|
b_wr_en_2 <= write_en and b_wr_en_2_int;
|
401 |
|
|
b_wr_en_2_int <= '1' when (wr_addr_i(10 downto 9) = "10") else '0';
|
402 |
|
|
|
403 |
|
|
b_wr_en_3 <= write_en and b_wr_en_3_int;
|
404 |
|
|
b_wr_en_3_int <= '1' when (wr_addr_i(10 downto 9) = "11") else '0';
|
405 |
|
|
|
406 |
|
|
wr_addr_0 <= '1' when (wr_addr_i(10 downto 9) = "00") else '0';
|
407 |
|
|
wr_addr_1 <= '1' when (wr_addr_i(10 downto 9) = "01") else '0';
|
408 |
|
|
wr_addr_2 <= '1' when (wr_addr_i(10 downto 9) = "10") else '0';
|
409 |
|
|
wr_addr_3 <= '1' when (wr_addr_i(10 downto 9) = "11") else '0';
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
EP_MEM_inst : EP_MEM port map (
|
413 |
|
|
|
414 |
|
|
clk_i => clk,
|
415 |
|
|
|
416 |
|
|
a_rd_a_i_0 => rd_addr_i(8 downto 0), -- I [8:0]
|
417 |
|
|
a_rd_en_i_0 => rd_data0_en, -- I [1:0]
|
418 |
|
|
a_rd_d_o_0 => rd_data0_o, -- O [31:0]
|
419 |
|
|
|
420 |
|
|
b_wr_a_i_0 => wr_addr_i(8 downto 0), -- I [8:0]
|
421 |
|
|
b_wr_d_i_0 => post_wr_data, -- I [31:0]
|
422 |
|
|
b_wr_en_i_0 => b_wr_en_0, --{write_en & (wr_addr_i[10:9] == 2'b00)}), -- I
|
423 |
|
|
b_rd_d_o_0 => w_pre_wr_data0(31 downto 0), -- O [31:0]
|
424 |
|
|
b_rd_en_i_0 => wr_addr_0, --{wr_addr_i[10:9] == 2'b00}), -- I
|
425 |
|
|
|
426 |
|
|
a_rd_a_i_1 => rd_addr_i(8 downto 0), -- I [8:0]
|
427 |
|
|
a_rd_en_i_1 => rd_data1_en, -- I [1:0]
|
428 |
|
|
a_rd_d_o_1 => rd_data1_o, -- O [31:0]
|
429 |
|
|
|
430 |
|
|
b_wr_a_i_1 => wr_addr_i(8 downto 0), -- [8:0]
|
431 |
|
|
b_wr_d_i_1 => post_wr_data, -- [31:0]
|
432 |
|
|
b_wr_en_i_1 => b_wr_en_1, --{write_en & (wr_addr_i[10:9] == 2'b01)}), -- I
|
433 |
|
|
b_rd_d_o_1 => w_pre_wr_data1(31 downto 0), -- [31:0]
|
434 |
|
|
b_rd_en_i_1 => wr_addr_1, --{wr_addr_i[10:9] == 2'b01}), -- I
|
435 |
|
|
|
436 |
|
|
a_rd_a_i_2 => rd_addr_i(8 downto 0), -- I [8:0]
|
437 |
|
|
a_rd_en_i_2 => rd_data2_en, -- I [1:0]
|
438 |
|
|
a_rd_d_o_2 => rd_data2_o, -- O [31:0]
|
439 |
|
|
|
440 |
|
|
b_wr_a_i_2 => wr_addr_i(8 downto 0), -- I [8:0]
|
441 |
|
|
b_wr_d_i_2 => post_wr_data, -- I [31:0]
|
442 |
|
|
b_wr_en_i_2 => b_wr_en_2, --{write_en & (wr_addr_i[10:9] == 2'b10)}), -- I
|
443 |
|
|
b_rd_d_o_2 => w_pre_wr_data2(31 downto 0), -- I [31:0]
|
444 |
|
|
b_rd_en_i_2 => wr_addr_2, --{wr_addr_i[10:9] == 2'b10}), -- I
|
445 |
|
|
|
446 |
|
|
a_rd_a_i_3 => rd_addr_i(8 downto 0), -- [8:0]
|
447 |
|
|
a_rd_en_i_3 => rd_data3_en, -- [1:0]
|
448 |
|
|
a_rd_d_o_3 => rd_data3_o, -- O [31:0]
|
449 |
|
|
|
450 |
|
|
b_wr_a_i_3 => wr_addr_i(8 downto 0), -- I [8:0]
|
451 |
|
|
b_wr_d_i_3 => post_wr_data, -- I [31:0]
|
452 |
|
|
b_wr_en_i_3 => b_wr_en_3, --{write_en & (wr_addr_i(10 downto 9) == 2'b11)}), -- I
|
453 |
|
|
b_rd_d_o_3 => w_pre_wr_data3(31 downto 0), -- I [31:0]
|
454 |
|
|
b_rd_en_i_3 => wr_addr_3 --{wr_addr_i[10:9] == 2'b11} -- I
|
455 |
|
|
|
456 |
|
|
);
|
457 |
|
|
|
458 |
|
|
end; -- PIO_EP_MEM_ACCESS
|
459 |
|
|
|