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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_2_0_rport_v6.vhd
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-- Version : 1.6
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-- Description: Virtex6 solution wrapper : Root Port for PCI Express
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_2_0_rport_v6 is
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generic (
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REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
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PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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PCIE_DRP_ENABLE : boolean := FALSE;
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DS_PORT_HOT_RST : boolean := FALSE; -- FALSE - for ROOT PORT(default), TRUE - for DOWNSTREAM PORT
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LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
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LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
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AER_BASE_PTR : bit_vector := X"128";
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AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;
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AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;
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AER_CAP_ID : bit_vector := X"1111";
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AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";
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AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";
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AER_CAP_NEXTPTR : bit_vector := X"160";
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AER_CAP_ON : boolean := FALSE;
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AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;
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AER_CAP_VERSION : bit_vector := X"1";
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ALLOW_X8_GEN2 : boolean := FALSE;
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BAR0 : bit_vector := X"00000000"; -- Memory aperture disabled
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BAR1 : bit_vector := X"00000000"; -- Memory aperture disabled
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BAR2 : bit_vector := X"00FFFFFF"; -- Constant for rport
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BAR3 : bit_vector := X"FFFF0000"; -- IO Limit/Base Registers not implemented
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BAR4 : bit_vector := X"FFF0FFF0"; -- Constant for rport
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BAR5 : bit_vector := X"FFF1FFF1"; -- Prefetchable Memory Limit/Base Registers implemented
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CAPABILITIES_PTR : bit_vector := X"40";
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CARDBUS_CIS_POINTER : bit_vector := X"00000000";
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CLASS_CODE : bit_vector := X"060400";
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CMD_INTX_IMPLEMENTED : boolean := TRUE;
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CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;
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CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
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CRM_MODULE_RSTS : bit_vector := X"00";
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DEVICE_ID : bit_vector := X"0007";
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DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;
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DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
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DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
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DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;
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DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;
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DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
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DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
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DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
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DEV_CAP_RSVD_14_12 : integer := 0;
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DEV_CAP_RSVD_17_16 : integer := 0;
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DEV_CAP_RSVD_31_29 : integer := 0;
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DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;
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DISABLE_ASPM_L1_TIMER : boolean := FALSE;
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DISABLE_BAR_FILTERING : boolean := TRUE;
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DISABLE_ID_CHECK : boolean := TRUE;
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DISABLE_LANE_REVERSAL : boolean := FALSE;
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DISABLE_RX_TC_FILTER : boolean := TRUE;
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DISABLE_SCRAMBLING : boolean := FALSE;
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DNSTREAM_LINK_NUM : bit_vector := X"00";
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DSN_BASE_PTR : bit_vector := X"100";
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DSN_CAP_ID : bit_vector := X"0003";
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DSN_CAP_NEXTPTR : bit_vector := X"01C";
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DSN_CAP_ON : boolean := TRUE;
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DSN_CAP_VERSION : bit_vector := X"1";
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ENABLE_MSG_ROUTE : bit_vector := X"000";
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ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
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ENTER_RVRY_EI_L0 : boolean := TRUE;
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EXIT_LOOPBACK_ON_EI : boolean := TRUE;
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EXPANSION_ROM : bit_vector := X"00000000"; -- Memory aperture disabled
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EXT_CFG_CAP_PTR : bit_vector := X"3F";
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EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
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HEADER_TYPE : bit_vector := X"01";
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INFER_EI : bit_vector := X"0C";
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INTERRUPT_PIN : bit_vector := X"01";
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IS_SWITCH : boolean := FALSE;
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LAST_CONFIG_DWORD : bit_vector := X"042";
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;
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LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
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LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;
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LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
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LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
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LINK_CAP_RSVD_23_22 : integer := 0;
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LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;
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LINK_CONTROL_RCB : integer := 0;
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LINK_CTRL2_DEEMPHASIS : boolean := FALSE;
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LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;
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LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
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LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
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LL_ACK_TIMEOUT : bit_vector := X"0000";
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LL_ACK_TIMEOUT_EN : boolean := FALSE;
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LL_ACK_TIMEOUT_FUNC : integer := 0;
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LL_REPLAY_TIMEOUT : bit_vector := X"0000";
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LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
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LL_REPLAY_TIMEOUT_FUNC : integer := 0;
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MSIX_BASE_PTR : bit_vector := X"9C";
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MSIX_CAP_ID : bit_vector := X"11";
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MSIX_CAP_NEXTPTR : bit_vector := X"00";
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MSIX_CAP_ON : boolean := TRUE;
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MSIX_CAP_PBA_BIR : integer := 0;
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MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
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MSIX_CAP_TABLE_BIR : integer := 0;
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MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
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MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
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MSI_BASE_PTR : bit_vector := X"48";
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MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;
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MSI_CAP_ID : bit_vector := X"05";
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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MSI_CAP_NEXTPTR : bit_vector := X"60";
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MSI_CAP_ON : boolean := TRUE;
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MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;
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N_FTS_COMCLK_GEN1 : integer := 255;
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N_FTS_COMCLK_GEN2 : integer := 255;
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N_FTS_GEN1 : integer := 255;
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N_FTS_GEN2 : integer := 255;
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PCIE_BASE_PTR : bit_vector := X"60";
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PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
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PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"4";
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PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";
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PCIE_CAP_NEXTPTR : bit_vector := X"9C";
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PCIE_CAP_ON : boolean := TRUE;
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PCIE_CAP_RSVD_15_14 : integer := 0;
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PCIE_CAP_SLOT_IMPLEMENTED : boolean := TRUE;
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PCIE_REVISION : integer := 2;
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PGL0_LANE : integer := 0;
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PGL1_LANE : integer := 1;
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PGL2_LANE : integer := 2;
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PGL3_LANE : integer := 3;
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PGL4_LANE : integer := 4;
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PGL5_LANE : integer := 5;
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PGL6_LANE : integer := 6;
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PGL7_LANE : integer := 7;
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PL_AUTO_CONFIG : integer := 0;
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PL_FAST_TRAIN : boolean := FALSE;
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PM_BASE_PTR : bit_vector := X"40";
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PM_CAP_AUXCURRENT : integer := 0;
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PM_CAP_D1SUPPORT : boolean := TRUE;
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PM_CAP_D2SUPPORT : boolean := TRUE;
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PM_CAP_DSI : boolean := FALSE;
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PM_CAP_ID : bit_vector := X"11";
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PM_CAP_NEXTPTR : bit_vector := X"48";
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PM_CAP_ON : boolean := TRUE;
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PM_CAP_PMESUPPORT : bit_vector := X"0F";
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PM_CAP_PME_CLOCK : boolean := FALSE;
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PM_CAP_RSVD_04 : integer := 0;
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PM_CAP_VERSION : integer := 3;
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PM_CSR_B2B3 : boolean := FALSE;
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PM_CSR_BPCCEN : boolean := FALSE;
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PM_CSR_NOSOFTRST : boolean := TRUE;
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PM_DATA0 : bit_vector := X"01";
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PM_DATA1 : bit_vector := X"01";
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PM_DATA2 : bit_vector := X"01";
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PM_DATA3 : bit_vector := X"01";
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PM_DATA4 : bit_vector := X"01";
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PM_DATA5 : bit_vector := X"01";
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PM_DATA6 : bit_vector := X"01";
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PM_DATA7 : bit_vector := X"01";
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PM_DATA_SCALE0 : bit_vector := X"1";
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PM_DATA_SCALE1 : bit_vector := X"1";
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PM_DATA_SCALE2 : bit_vector := X"1";
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PM_DATA_SCALE3 : bit_vector := X"1";
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PM_DATA_SCALE4 : bit_vector := X"1";
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PM_DATA_SCALE5 : bit_vector := X"1";
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PM_DATA_SCALE6 : bit_vector := X"1";
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PM_DATA_SCALE7 : bit_vector := X"1";
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RECRC_CHK : integer := 0;
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RECRC_CHK_TRIM : boolean := FALSE;
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REVISION_ID : bit_vector := X"00";
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ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;
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SELECT_DLL_IF : boolean := FALSE;
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SIM_VERSION : string := "1.0";
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SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
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SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;
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SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;
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SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;
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SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;
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SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;
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SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
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249 |
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SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;
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SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
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SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
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SPARE_BIT0 : integer := 0;
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SPARE_BIT1 : integer := 0;
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SPARE_BIT2 : integer := 0;
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SPARE_BIT3 : integer := 0;
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SPARE_BIT4 : integer := 0;
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SPARE_BIT5 : integer := 0;
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SPARE_BIT6 : integer := 0;
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SPARE_BIT7 : integer := 0;
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SPARE_BIT8 : integer := 0;
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SPARE_BYTE0 : bit_vector := X"00";
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SPARE_BYTE1 : bit_vector := X"00";
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SPARE_BYTE2 : bit_vector := X"00";
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SPARE_BYTE3 : bit_vector := X"00";
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SPARE_WORD0 : bit_vector := X"00000000";
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267 |
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SPARE_WORD1 : bit_vector := X"00000000";
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268 |
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SPARE_WORD2 : bit_vector := X"00000000";
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269 |
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SPARE_WORD3 : bit_vector := X"00000000";
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270 |
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SUBSYSTEM_ID : bit_vector := X"0007";
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271 |
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SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";
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TL_RBYPASS : boolean := FALSE;
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273 |
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TL_RX_RAM_RADDR_LATENCY : integer := 0;
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TL_RX_RAM_RDATA_LATENCY : integer := 2;
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TL_RX_RAM_WRITE_LATENCY : integer := 0;
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TL_TFC_DISABLE : boolean := FALSE;
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277 |
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TL_TX_CHECKS_DISABLE : boolean := FALSE;
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278 |
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TL_TX_RAM_RADDR_LATENCY : integer := 0;
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279 |
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TL_TX_RAM_RDATA_LATENCY : integer := 2;
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280 |
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TL_TX_RAM_WRITE_LATENCY : integer := 0;
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281 |
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UPCONFIG_CAPABLE : boolean := TRUE;
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282 |
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UPSTREAM_FACING : boolean := FALSE;
|
283 |
|
|
UR_INV_REQ : boolean := TRUE;
|
284 |
|
|
USER_CLK_FREQ : integer := 3;
|
285 |
|
|
VC0_CPL_INFINITE : boolean := TRUE;
|
286 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
287 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 127;
|
288 |
|
|
VC0_TOTAL_CREDITS_CH : integer := 31;
|
289 |
|
|
VC0_TOTAL_CREDITS_NPH : integer := 12;
|
290 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 288;
|
291 |
|
|
VC0_TOTAL_CREDITS_PH : integer := 32;
|
292 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
293 |
|
|
VC_BASE_PTR : bit_vector := X"10C";
|
294 |
|
|
VC_CAP_ID : bit_vector := X"0002";
|
295 |
|
|
VC_CAP_NEXTPTR : bit_vector := X"128";
|
296 |
|
|
VC_CAP_ON : boolean := TRUE;
|
297 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;
|
298 |
|
|
VC_CAP_VERSION : bit_vector := X"1";
|
299 |
|
|
VENDOR_ID : bit_vector := X"10EE";
|
300 |
|
|
VSEC_BASE_PTR : bit_vector := X"160";
|
301 |
|
|
VSEC_CAP_HDR_ID : bit_vector := X"1234";
|
302 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
|
303 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
|
304 |
|
|
VSEC_CAP_ID : bit_vector := X"000B";
|
305 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;
|
306 |
|
|
VSEC_CAP_NEXTPTR : bit_vector := X"000";
|
307 |
|
|
VSEC_CAP_ON : boolean := TRUE;
|
308 |
|
|
VSEC_CAP_VERSION : bit_vector := X"1"
|
309 |
|
|
);
|
310 |
|
|
port (
|
311 |
|
|
---------------------------------------------------------
|
312 |
|
|
-- 1. PCI Express (pci_exp) Interface
|
313 |
|
|
---------------------------------------------------------
|
314 |
|
|
|
315 |
|
|
-- Tx
|
316 |
|
|
pci_exp_txp : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
317 |
|
|
pci_exp_txn : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
318 |
|
|
|
319 |
|
|
-- Rx
|
320 |
|
|
pci_exp_rxp : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
321 |
|
|
pci_exp_rxn : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
322 |
|
|
|
323 |
|
|
---------------------------------------------------------
|
324 |
|
|
-- 2. Transaction (TRN) Interface
|
325 |
|
|
---------------------------------------------------------
|
326 |
|
|
|
327 |
|
|
-- Common
|
328 |
|
|
|
329 |
|
|
trn_clk : out std_logic;
|
330 |
|
|
trn_reset_n : out std_logic;
|
331 |
|
|
trn_lnk_up_n : out std_logic;
|
332 |
|
|
|
333 |
|
|
-- Tx
|
334 |
|
|
trn_tbuf_av : out std_logic_vector(5 downto 0);
|
335 |
|
|
trn_tcfg_req_n : out std_logic;
|
336 |
|
|
trn_terr_drop_n : out std_logic;
|
337 |
|
|
trn_tdst_rdy_n : out std_logic;
|
338 |
|
|
trn_td : in std_logic_vector(63 downto 0);
|
339 |
|
|
trn_trem_n : in std_logic;
|
340 |
|
|
trn_tsof_n : in std_logic;
|
341 |
|
|
trn_teof_n : in std_logic;
|
342 |
|
|
trn_tsrc_rdy_n : in std_logic;
|
343 |
|
|
trn_tsrc_dsc_n : in std_logic;
|
344 |
|
|
trn_terrfwd_n : in std_logic;
|
345 |
|
|
trn_tcfg_gnt_n : in std_logic;
|
346 |
|
|
trn_tstr_n : in std_logic;
|
347 |
|
|
|
348 |
|
|
-- Rx
|
349 |
|
|
trn_rd : out std_logic_vector(63 downto 0);
|
350 |
|
|
trn_rrem_n : out std_logic;
|
351 |
|
|
trn_rsof_n : out std_logic;
|
352 |
|
|
trn_reof_n : out std_logic;
|
353 |
|
|
trn_rsrc_rdy_n : out std_logic;
|
354 |
|
|
trn_rsrc_dsc_n : out std_logic;
|
355 |
|
|
trn_rerrfwd_n : out std_logic;
|
356 |
|
|
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
|
357 |
|
|
trn_rdst_rdy_n : in std_logic;
|
358 |
|
|
trn_rnp_ok_n : in std_logic;
|
359 |
|
|
trn_recrc_err_n : out std_logic;
|
360 |
|
|
|
361 |
|
|
-- Flow Control
|
362 |
|
|
trn_fc_cpld : out std_logic_vector(11 downto 0);
|
363 |
|
|
trn_fc_cplh : out std_logic_vector(7 downto 0);
|
364 |
|
|
trn_fc_npd : out std_logic_vector(11 downto 0);
|
365 |
|
|
trn_fc_nph : out std_logic_vector(7 downto 0);
|
366 |
|
|
trn_fc_pd : out std_logic_vector(11 downto 0);
|
367 |
|
|
trn_fc_ph : out std_logic_vector(7 downto 0);
|
368 |
|
|
trn_fc_sel : in std_logic_vector(2 downto 0);
|
369 |
|
|
|
370 |
|
|
---------------------------------------------------------
|
371 |
|
|
-- 3. Configuration (CFG) Interface
|
372 |
|
|
---------------------------------------------------------
|
373 |
|
|
|
374 |
|
|
cfg_do : out std_logic_vector(31 downto 0);
|
375 |
|
|
cfg_rd_wr_done_n : out std_logic;
|
376 |
|
|
cfg_di : in std_logic_vector(31 downto 0);
|
377 |
|
|
cfg_byte_en_n : in std_logic_vector(3 downto 0);
|
378 |
|
|
cfg_dwaddr : in std_logic_vector(9 downto 0);
|
379 |
|
|
cfg_wr_en_n : in std_logic;
|
380 |
|
|
cfg_wr_rw1c_as_rw_n : in std_logic;
|
381 |
|
|
cfg_rd_en_n : in std_logic;
|
382 |
|
|
|
383 |
|
|
cfg_err_cor_n : in std_logic;
|
384 |
|
|
cfg_err_ur_n : in std_logic;
|
385 |
|
|
cfg_err_ecrc_n : in std_logic;
|
386 |
|
|
cfg_err_cpl_timeout_n : in std_logic;
|
387 |
|
|
cfg_err_cpl_abort_n : in std_logic;
|
388 |
|
|
cfg_err_cpl_unexpect_n : in std_logic;
|
389 |
|
|
cfg_err_posted_n : in std_logic;
|
390 |
|
|
cfg_err_locked_n : in std_logic;
|
391 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
392 |
|
|
cfg_err_cpl_rdy_n : out std_logic;
|
393 |
|
|
cfg_interrupt_n : in std_logic;
|
394 |
|
|
cfg_interrupt_rdy_n : out std_logic;
|
395 |
|
|
cfg_interrupt_assert_n : in std_logic;
|
396 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
397 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
398 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
399 |
|
|
cfg_interrupt_msienable : out std_logic;
|
400 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
401 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
402 |
|
|
cfg_trn_pending_n : in std_logic;
|
403 |
|
|
cfg_pm_send_pme_to_n : in std_logic;
|
404 |
|
|
cfg_status : out std_logic_vector(15 downto 0);
|
405 |
|
|
cfg_command : out std_logic_vector(15 downto 0);
|
406 |
|
|
cfg_dstatus : out std_logic_vector(15 downto 0);
|
407 |
|
|
cfg_dcommand : out std_logic_vector(15 downto 0);
|
408 |
|
|
cfg_lstatus : out std_logic_vector(15 downto 0);
|
409 |
|
|
cfg_lcommand : out std_logic_vector(15 downto 0);
|
410 |
|
|
cfg_dcommand2 : out std_logic_vector(15 downto 0);
|
411 |
|
|
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
|
412 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0);
|
413 |
|
|
cfg_pmcsr_pme_en : out std_logic;
|
414 |
|
|
cfg_pmcsr_pme_status : out std_logic;
|
415 |
|
|
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
|
416 |
|
|
|
417 |
|
|
cfg_msg_received : out std_logic;
|
418 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
419 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
420 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
421 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
422 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
423 |
|
|
cfg_msg_received_assert_inta : out std_logic;
|
424 |
|
|
cfg_msg_received_assert_intb : out std_logic;
|
425 |
|
|
cfg_msg_received_assert_intc : out std_logic;
|
426 |
|
|
cfg_msg_received_assert_intd : out std_logic;
|
427 |
|
|
cfg_msg_received_deassert_inta : out std_logic;
|
428 |
|
|
cfg_msg_received_deassert_intb : out std_logic;
|
429 |
|
|
cfg_msg_received_deassert_intc : out std_logic;
|
430 |
|
|
cfg_msg_received_deassert_intd : out std_logic;
|
431 |
|
|
|
432 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
|
433 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0);
|
434 |
|
|
|
435 |
|
|
---------------------------------------------------------
|
436 |
|
|
-- 4. Physical Layer Control and Status (PL) Interface
|
437 |
|
|
---------------------------------------------------------
|
438 |
|
|
|
439 |
|
|
pl_initial_link_width : out std_logic_vector(2 downto 0);
|
440 |
|
|
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
|
441 |
|
|
pl_link_gen2_capable : out std_logic;
|
442 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
443 |
|
|
pl_link_upcfg_capable : out std_logic;
|
444 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
445 |
|
|
pl_sel_link_rate : out std_logic;
|
446 |
|
|
pl_sel_link_width : out std_logic_vector(1 downto 0);
|
447 |
|
|
pl_directed_link_auton : in std_logic;
|
448 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
449 |
|
|
pl_directed_link_speed : in std_logic;
|
450 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0);
|
451 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
452 |
|
|
pl_transmit_hot_rst : in std_logic;
|
453 |
|
|
|
454 |
|
|
---------------------------------------------------------
|
455 |
|
|
-- 5. PCIe DRP (PCIe DRP) Interface
|
456 |
|
|
---------------------------------------------------------
|
457 |
|
|
|
458 |
|
|
pcie_drp_clk : in std_logic;
|
459 |
|
|
pcie_drp_den : in std_logic;
|
460 |
|
|
pcie_drp_dwe : in std_logic;
|
461 |
|
|
pcie_drp_daddr : in std_logic_vector(8 downto 0);
|
462 |
|
|
pcie_drp_di : in std_logic_vector(15 downto 0);
|
463 |
|
|
pcie_drp_do : out std_logic_vector(15 downto 0);
|
464 |
|
|
pcie_drp_drdy : out std_logic;
|
465 |
|
|
|
466 |
|
|
---------------------------------------------------------
|
467 |
|
|
-- 6. System (SYS) Interface
|
468 |
|
|
---------------------------------------------------------
|
469 |
|
|
|
470 |
|
|
sys_clk : in std_logic;
|
471 |
|
|
sys_reset_n : in std_logic
|
472 |
|
|
);
|
473 |
|
|
end pcie_2_0_rport_v6;
|
474 |
|
|
|
475 |
|
|
architecture v6_pcie of pcie_2_0_rport_v6 is
|
476 |
|
|
|
477 |
|
|
component pcie_reset_delay_v6
|
478 |
|
|
generic (
|
479 |
|
|
PL_FAST_TRAIN : boolean;
|
480 |
|
|
REF_CLK_FREQ : integer);
|
481 |
|
|
port (
|
482 |
|
|
ref_clk : in std_logic;
|
483 |
|
|
sys_reset_n : in std_logic;
|
484 |
|
|
delayed_sys_reset_n : out std_logic);
|
485 |
|
|
end component;
|
486 |
|
|
|
487 |
|
|
component pcie_clocking_v6
|
488 |
|
|
generic (
|
489 |
|
|
IS_ENDPOINT : boolean;
|
490 |
|
|
CAP_LINK_WIDTH : integer;
|
491 |
|
|
CAP_LINK_SPEED : integer;
|
492 |
|
|
REF_CLK_FREQ : integer;
|
493 |
|
|
USER_CLK_FREQ : integer);
|
494 |
|
|
port (
|
495 |
|
|
sys_clk : in std_logic;
|
496 |
|
|
gt_pll_lock : in std_logic;
|
497 |
|
|
sel_lnk_rate : in std_logic;
|
498 |
|
|
sel_lnk_width : in std_logic_vector(1 downto 0);
|
499 |
|
|
sys_clk_bufg : out std_logic;
|
500 |
|
|
pipe_clk : out std_logic;
|
501 |
|
|
user_clk : out std_logic;
|
502 |
|
|
block_clk : out std_logic;
|
503 |
|
|
drp_clk : out std_logic;
|
504 |
|
|
clock_locked : out std_logic);
|
505 |
|
|
end component;
|
506 |
|
|
|
507 |
|
|
component pcie_2_0_v6_rp
|
508 |
|
|
generic (
|
509 |
|
|
REF_CLK_FREQ : integer;
|
510 |
|
|
PIPE_PIPELINE_STAGES : integer;
|
511 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer;
|
512 |
|
|
AER_BASE_PTR : bit_vector;
|
513 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE : boolean;
|
514 |
|
|
AER_CAP_ECRC_GEN_CAPABLE : boolean;
|
515 |
|
|
AER_CAP_ID : bit_vector;
|
516 |
|
|
AER_CAP_INT_MSG_NUM_MSI : bit_vector;
|
517 |
|
|
AER_CAP_INT_MSG_NUM_MSIX : bit_vector;
|
518 |
|
|
AER_CAP_NEXTPTR : bit_vector;
|
519 |
|
|
AER_CAP_ON : boolean;
|
520 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean;
|
521 |
|
|
AER_CAP_VERSION : bit_vector;
|
522 |
|
|
ALLOW_X8_GEN2 : boolean;
|
523 |
|
|
BAR0 : bit_vector;
|
524 |
|
|
BAR1 : bit_vector;
|
525 |
|
|
BAR2 : bit_vector;
|
526 |
|
|
BAR3 : bit_vector;
|
527 |
|
|
BAR4 : bit_vector;
|
528 |
|
|
BAR5 : bit_vector;
|
529 |
|
|
CAPABILITIES_PTR : bit_vector;
|
530 |
|
|
CARDBUS_CIS_POINTER : bit_vector;
|
531 |
|
|
CLASS_CODE : bit_vector;
|
532 |
|
|
CMD_INTX_IMPLEMENTED : boolean;
|
533 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean;
|
534 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector;
|
535 |
|
|
CRM_MODULE_RSTS : bit_vector;
|
536 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean;
|
537 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean;
|
538 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY : integer;
|
539 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY : integer;
|
540 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED : boolean;
|
541 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean;
|
542 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
|
543 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer;
|
544 |
|
|
DEV_CAP_ROLE_BASED_ERROR : boolean;
|
545 |
|
|
DEV_CAP_RSVD_14_12 : integer;
|
546 |
|
|
DEV_CAP_RSVD_17_16 : integer;
|
547 |
|
|
DEV_CAP_RSVD_31_29 : integer;
|
548 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean;
|
549 |
|
|
DEVICE_ID : bit_vector;
|
550 |
|
|
DISABLE_ASPM_L1_TIMER : boolean;
|
551 |
|
|
DISABLE_BAR_FILTERING : boolean;
|
552 |
|
|
DISABLE_ID_CHECK : boolean;
|
553 |
|
|
DISABLE_LANE_REVERSAL : boolean;
|
554 |
|
|
DISABLE_RX_TC_FILTER : boolean;
|
555 |
|
|
DISABLE_SCRAMBLING : boolean;
|
556 |
|
|
DNSTREAM_LINK_NUM : bit_vector;
|
557 |
|
|
DSN_BASE_PTR : bit_vector;
|
558 |
|
|
DSN_CAP_ID : bit_vector;
|
559 |
|
|
DSN_CAP_NEXTPTR : bit_vector;
|
560 |
|
|
DSN_CAP_ON : boolean;
|
561 |
|
|
DSN_CAP_VERSION : bit_vector;
|
562 |
|
|
ENABLE_MSG_ROUTE : bit_vector;
|
563 |
|
|
ENABLE_RX_TD_ECRC_TRIM : boolean;
|
564 |
|
|
ENTER_RVRY_EI_L0 : boolean;
|
565 |
|
|
EXPANSION_ROM : bit_vector;
|
566 |
|
|
EXT_CFG_CAP_PTR : bit_vector;
|
567 |
|
|
EXT_CFG_XP_CAP_PTR : bit_vector;
|
568 |
|
|
HEADER_TYPE : bit_vector;
|
569 |
|
|
INFER_EI : bit_vector;
|
570 |
|
|
INTERRUPT_PIN : bit_vector;
|
571 |
|
|
IS_SWITCH : boolean;
|
572 |
|
|
LAST_CONFIG_DWORD : bit_vector;
|
573 |
|
|
LINK_CAP_ASPM_SUPPORT : integer;
|
574 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean;
|
575 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean;
|
576 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer;
|
577 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer;
|
578 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer;
|
579 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer;
|
580 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer;
|
581 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer;
|
582 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer;
|
583 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer;
|
584 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;
|
585 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector;
|
586 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector;
|
587 |
|
|
LINK_CAP_RSVD_23_22 : integer;
|
588 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean;
|
589 |
|
|
LINK_CONTROL_RCB : integer;
|
590 |
|
|
LINK_CTRL2_DEEMPHASIS : boolean;
|
591 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean;
|
592 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
|
593 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean;
|
594 |
|
|
LL_ACK_TIMEOUT : bit_vector;
|
595 |
|
|
LL_ACK_TIMEOUT_EN : boolean;
|
596 |
|
|
LL_ACK_TIMEOUT_FUNC : integer;
|
597 |
|
|
LL_REPLAY_TIMEOUT : bit_vector;
|
598 |
|
|
LL_REPLAY_TIMEOUT_EN : boolean;
|
599 |
|
|
LL_REPLAY_TIMEOUT_FUNC : integer;
|
600 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector;
|
601 |
|
|
MSI_BASE_PTR : bit_vector;
|
602 |
|
|
MSI_CAP_ID : bit_vector;
|
603 |
|
|
MSI_CAP_MULTIMSGCAP : integer;
|
604 |
|
|
MSI_CAP_MULTIMSG_EXTENSION : integer;
|
605 |
|
|
MSI_CAP_NEXTPTR : bit_vector;
|
606 |
|
|
MSI_CAP_ON : boolean;
|
607 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean;
|
608 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean;
|
609 |
|
|
MSIX_BASE_PTR : bit_vector;
|
610 |
|
|
MSIX_CAP_ID : bit_vector;
|
611 |
|
|
MSIX_CAP_NEXTPTR : bit_vector;
|
612 |
|
|
MSIX_CAP_ON : boolean;
|
613 |
|
|
MSIX_CAP_PBA_BIR : integer;
|
614 |
|
|
MSIX_CAP_PBA_OFFSET : bit_vector;
|
615 |
|
|
MSIX_CAP_TABLE_BIR : integer;
|
616 |
|
|
MSIX_CAP_TABLE_OFFSET : bit_vector;
|
617 |
|
|
MSIX_CAP_TABLE_SIZE : bit_vector;
|
618 |
|
|
N_FTS_COMCLK_GEN1 : integer;
|
619 |
|
|
N_FTS_COMCLK_GEN2 : integer;
|
620 |
|
|
N_FTS_GEN1 : integer;
|
621 |
|
|
N_FTS_GEN2 : integer;
|
622 |
|
|
PCIE_BASE_PTR : bit_vector;
|
623 |
|
|
PCIE_CAP_CAPABILITY_ID : bit_vector;
|
624 |
|
|
PCIE_CAP_CAPABILITY_VERSION : bit_vector;
|
625 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector;
|
626 |
|
|
PCIE_CAP_INT_MSG_NUM : bit_vector;
|
627 |
|
|
PCIE_CAP_NEXTPTR : bit_vector;
|
628 |
|
|
PCIE_CAP_ON : boolean;
|
629 |
|
|
PCIE_CAP_RSVD_15_14 : integer;
|
630 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED : boolean;
|
631 |
|
|
PCIE_REVISION : integer;
|
632 |
|
|
PGL0_LANE : integer;
|
633 |
|
|
PGL1_LANE : integer;
|
634 |
|
|
PGL2_LANE : integer;
|
635 |
|
|
PGL3_LANE : integer;
|
636 |
|
|
PGL4_LANE : integer;
|
637 |
|
|
PGL5_LANE : integer;
|
638 |
|
|
PGL6_LANE : integer;
|
639 |
|
|
PGL7_LANE : integer;
|
640 |
|
|
PL_AUTO_CONFIG : integer;
|
641 |
|
|
PL_FAST_TRAIN : boolean;
|
642 |
|
|
PM_BASE_PTR : bit_vector;
|
643 |
|
|
PM_CAP_AUXCURRENT : integer;
|
644 |
|
|
PM_CAP_DSI : boolean;
|
645 |
|
|
PM_CAP_D1SUPPORT : boolean;
|
646 |
|
|
PM_CAP_D2SUPPORT : boolean;
|
647 |
|
|
PM_CAP_ID : bit_vector;
|
648 |
|
|
PM_CAP_NEXTPTR : bit_vector;
|
649 |
|
|
PM_CAP_ON : boolean;
|
650 |
|
|
PM_CAP_PME_CLOCK : boolean;
|
651 |
|
|
PM_CAP_PMESUPPORT : bit_vector;
|
652 |
|
|
PM_CAP_RSVD_04 : integer;
|
653 |
|
|
PM_CAP_VERSION : integer;
|
654 |
|
|
PM_CSR_BPCCEN : boolean;
|
655 |
|
|
PM_CSR_B2B3 : boolean;
|
656 |
|
|
PM_CSR_NOSOFTRST : boolean;
|
657 |
|
|
PM_DATA0 : bit_vector;
|
658 |
|
|
PM_DATA1 : bit_vector;
|
659 |
|
|
PM_DATA2 : bit_vector;
|
660 |
|
|
PM_DATA3 : bit_vector;
|
661 |
|
|
PM_DATA4 : bit_vector;
|
662 |
|
|
PM_DATA5 : bit_vector;
|
663 |
|
|
PM_DATA6 : bit_vector;
|
664 |
|
|
PM_DATA7 : bit_vector;
|
665 |
|
|
PM_DATA_SCALE0 : bit_vector;
|
666 |
|
|
PM_DATA_SCALE1 : bit_vector;
|
667 |
|
|
PM_DATA_SCALE2 : bit_vector;
|
668 |
|
|
PM_DATA_SCALE3 : bit_vector;
|
669 |
|
|
PM_DATA_SCALE4 : bit_vector;
|
670 |
|
|
PM_DATA_SCALE5 : bit_vector;
|
671 |
|
|
PM_DATA_SCALE6 : bit_vector;
|
672 |
|
|
PM_DATA_SCALE7 : bit_vector;
|
673 |
|
|
RECRC_CHK : integer;
|
674 |
|
|
RECRC_CHK_TRIM : boolean;
|
675 |
|
|
REVISION_ID : bit_vector;
|
676 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY : boolean;
|
677 |
|
|
SELECT_DLL_IF : boolean;
|
678 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT : boolean;
|
679 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean;
|
680 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean;
|
681 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE : boolean;
|
682 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE : boolean;
|
683 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT : boolean;
|
684 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean;
|
685 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector;
|
686 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean;
|
687 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean;
|
688 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer;
|
689 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector;
|
690 |
|
|
SPARE_BIT0 : integer;
|
691 |
|
|
SPARE_BIT1 : integer;
|
692 |
|
|
SPARE_BIT2 : integer;
|
693 |
|
|
SPARE_BIT3 : integer;
|
694 |
|
|
SPARE_BIT4 : integer;
|
695 |
|
|
SPARE_BIT5 : integer;
|
696 |
|
|
SPARE_BIT6 : integer;
|
697 |
|
|
SPARE_BIT7 : integer;
|
698 |
|
|
SPARE_BIT8 : integer;
|
699 |
|
|
SPARE_BYTE0 : bit_vector;
|
700 |
|
|
SPARE_BYTE1 : bit_vector;
|
701 |
|
|
SPARE_BYTE2 : bit_vector;
|
702 |
|
|
SPARE_BYTE3 : bit_vector;
|
703 |
|
|
SPARE_WORD0 : bit_vector;
|
704 |
|
|
SPARE_WORD1 : bit_vector;
|
705 |
|
|
SPARE_WORD2 : bit_vector;
|
706 |
|
|
SPARE_WORD3 : bit_vector;
|
707 |
|
|
SUBSYSTEM_ID : bit_vector;
|
708 |
|
|
SUBSYSTEM_VENDOR_ID : bit_vector;
|
709 |
|
|
TL_RBYPASS : boolean;
|
710 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer;
|
711 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer;
|
712 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer;
|
713 |
|
|
TL_TFC_DISABLE : boolean;
|
714 |
|
|
TL_TX_CHECKS_DISABLE : boolean;
|
715 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer;
|
716 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer;
|
717 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer;
|
718 |
|
|
UPCONFIG_CAPABLE : boolean;
|
719 |
|
|
UPSTREAM_FACING : boolean;
|
720 |
|
|
UR_INV_REQ : boolean;
|
721 |
|
|
USER_CLK_FREQ : integer;
|
722 |
|
|
EXIT_LOOPBACK_ON_EI : boolean;
|
723 |
|
|
VC_BASE_PTR : bit_vector;
|
724 |
|
|
VC_CAP_ID : bit_vector;
|
725 |
|
|
VC_CAP_NEXTPTR : bit_vector;
|
726 |
|
|
VC_CAP_ON : boolean;
|
727 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean;
|
728 |
|
|
VC_CAP_VERSION : bit_vector;
|
729 |
|
|
VC0_CPL_INFINITE : boolean;
|
730 |
|
|
VC0_RX_RAM_LIMIT : bit_vector;
|
731 |
|
|
VC0_TOTAL_CREDITS_CD : integer;
|
732 |
|
|
VC0_TOTAL_CREDITS_CH : integer;
|
733 |
|
|
VC0_TOTAL_CREDITS_NPH : integer;
|
734 |
|
|
VC0_TOTAL_CREDITS_PD : integer;
|
735 |
|
|
VC0_TOTAL_CREDITS_PH : integer;
|
736 |
|
|
VC0_TX_LASTPACKET : integer;
|
737 |
|
|
VENDOR_ID : bit_vector;
|
738 |
|
|
VSEC_BASE_PTR : bit_vector;
|
739 |
|
|
VSEC_CAP_HDR_ID : bit_vector;
|
740 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector;
|
741 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector;
|
742 |
|
|
VSEC_CAP_ID : bit_vector;
|
743 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : boolean;
|
744 |
|
|
VSEC_CAP_NEXTPTR : bit_vector;
|
745 |
|
|
VSEC_CAP_ON : boolean;
|
746 |
|
|
VSEC_CAP_VERSION : bit_vector);
|
747 |
|
|
port (
|
748 |
|
|
PCIEXPRXN : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
749 |
|
|
PCIEXPRXP : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
750 |
|
|
PCIEXPTXN : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
751 |
|
|
PCIEXPTXP : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
|
752 |
|
|
SYSCLK : in std_logic;
|
753 |
|
|
FUNDRSTN : in std_logic;
|
754 |
|
|
TRNLNKUPN : out std_logic;
|
755 |
|
|
TRNCLK : out std_logic;
|
756 |
|
|
PHYRDYN : out std_logic;
|
757 |
|
|
USERRSTN : out std_logic;
|
758 |
|
|
RECEIVEDFUNCLVLRSTN : out std_logic;
|
759 |
|
|
LNKCLKEN : out std_logic;
|
760 |
|
|
SYSRSTN : in std_logic;
|
761 |
|
|
PLRSTN : in std_logic;
|
762 |
|
|
DLRSTN : in std_logic;
|
763 |
|
|
TLRSTN : in std_logic;
|
764 |
|
|
FUNCLVLRSTN : in std_logic;
|
765 |
|
|
CMRSTN : in std_logic;
|
766 |
|
|
CMSTICKYRSTN : in std_logic;
|
767 |
|
|
TRNRBARHITN : out std_logic_vector(6 downto 0);
|
768 |
|
|
TRNRD : out std_logic_vector(63 downto 0);
|
769 |
|
|
TRNRECRCERRN : out std_logic;
|
770 |
|
|
TRNREOFN : out std_logic;
|
771 |
|
|
TRNRERRFWDN : out std_logic;
|
772 |
|
|
TRNRREMN : out std_logic;
|
773 |
|
|
TRNRSOFN : out std_logic;
|
774 |
|
|
TRNRSRCDSCN : out std_logic;
|
775 |
|
|
TRNRSRCRDYN : out std_logic;
|
776 |
|
|
TRNRDSTRDYN : in std_logic;
|
777 |
|
|
TRNRNPOKN : in std_logic;
|
778 |
|
|
TRNTBUFAV : out std_logic_vector(5 downto 0);
|
779 |
|
|
TRNTCFGREQN : out std_logic;
|
780 |
|
|
TRNTDLLPDSTRDYN : out std_logic;
|
781 |
|
|
TRNTDSTRDYN : out std_logic;
|
782 |
|
|
TRNTERRDROPN : out std_logic;
|
783 |
|
|
TRNTCFGGNTN : in std_logic;
|
784 |
|
|
TRNTD : in std_logic_vector(63 downto 0);
|
785 |
|
|
TRNTDLLPDATA : in std_logic_vector(31 downto 0);
|
786 |
|
|
TRNTDLLPSRCRDYN : in std_logic;
|
787 |
|
|
TRNTECRCGENN : in std_logic;
|
788 |
|
|
TRNTEOFN : in std_logic;
|
789 |
|
|
TRNTERRFWDN : in std_logic;
|
790 |
|
|
TRNTREMN : in std_logic;
|
791 |
|
|
TRNTSOFN : in std_logic;
|
792 |
|
|
TRNTSRCDSCN : in std_logic;
|
793 |
|
|
TRNTSRCRDYN : in std_logic;
|
794 |
|
|
TRNTSTRN : in std_logic;
|
795 |
|
|
TRNFCCPLD : out std_logic_vector(11 downto 0);
|
796 |
|
|
TRNFCCPLH : out std_logic_vector(7 downto 0);
|
797 |
|
|
TRNFCNPD : out std_logic_vector(11 downto 0);
|
798 |
|
|
TRNFCNPH : out std_logic_vector(7 downto 0);
|
799 |
|
|
TRNFCPD : out std_logic_vector(11 downto 0);
|
800 |
|
|
TRNFCPH : out std_logic_vector(7 downto 0);
|
801 |
|
|
TRNFCSEL : in std_logic_vector(2 downto 0);
|
802 |
|
|
CFGAERECRCCHECKEN : out std_logic;
|
803 |
|
|
CFGAERECRCGENEN : out std_logic;
|
804 |
|
|
CFGCOMMANDBUSMASTERENABLE : out std_logic;
|
805 |
|
|
CFGCOMMANDINTERRUPTDISABLE : out std_logic;
|
806 |
|
|
CFGCOMMANDIOENABLE : out std_logic;
|
807 |
|
|
CFGCOMMANDMEMENABLE : out std_logic;
|
808 |
|
|
CFGCOMMANDSERREN : out std_logic;
|
809 |
|
|
CFGDEVCONTROLAUXPOWEREN : out std_logic;
|
810 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic;
|
811 |
|
|
CFGDEVCONTROLENABLERO : out std_logic;
|
812 |
|
|
CFGDEVCONTROLEXTTAGEN : out std_logic;
|
813 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic;
|
814 |
|
|
CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0);
|
815 |
|
|
CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0);
|
816 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic;
|
817 |
|
|
CFGDEVCONTROLNOSNOOPEN : out std_logic;
|
818 |
|
|
CFGDEVCONTROLPHANTOMEN : out std_logic;
|
819 |
|
|
CFGDEVCONTROLURERRREPORTINGEN : out std_logic;
|
820 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic;
|
821 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0);
|
822 |
|
|
CFGDEVSTATUSCORRERRDETECTED : out std_logic;
|
823 |
|
|
CFGDEVSTATUSFATALERRDETECTED : out std_logic;
|
824 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED : out std_logic;
|
825 |
|
|
CFGDEVSTATUSURDETECTED : out std_logic;
|
826 |
|
|
CFGDO : out std_logic_vector(31 downto 0);
|
827 |
|
|
CFGERRAERHEADERLOGSETN : out std_logic;
|
828 |
|
|
CFGERRCPLRDYN : out std_logic;
|
829 |
|
|
CFGINTERRUPTDO : out std_logic_vector(7 downto 0);
|
830 |
|
|
CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0);
|
831 |
|
|
CFGINTERRUPTMSIENABLE : out std_logic;
|
832 |
|
|
CFGINTERRUPTMSIXENABLE : out std_logic;
|
833 |
|
|
CFGINTERRUPTMSIXFM : out std_logic;
|
834 |
|
|
CFGINTERRUPTRDYN : out std_logic;
|
835 |
|
|
CFGLINKCONTROLRCB : out std_logic;
|
836 |
|
|
CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0);
|
837 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic;
|
838 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN : out std_logic;
|
839 |
|
|
CFGLINKCONTROLCLOCKPMEN : out std_logic;
|
840 |
|
|
CFGLINKCONTROLCOMMONCLOCK : out std_logic;
|
841 |
|
|
CFGLINKCONTROLEXTENDEDSYNC : out std_logic;
|
842 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic;
|
843 |
|
|
CFGLINKCONTROLLINKDISABLE : out std_logic;
|
844 |
|
|
CFGLINKCONTROLRETRAINLINK : out std_logic;
|
845 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic;
|
846 |
|
|
CFGLINKSTATUSBANDWITHSTATUS : out std_logic;
|
847 |
|
|
CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0);
|
848 |
|
|
CFGLINKSTATUSDLLACTIVE : out std_logic;
|
849 |
|
|
CFGLINKSTATUSLINKTRAINING : out std_logic;
|
850 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0);
|
851 |
|
|
CFGMSGDATA : out std_logic_vector(15 downto 0);
|
852 |
|
|
CFGMSGRECEIVED : out std_logic;
|
853 |
|
|
CFGMSGRECEIVEDASSERTINTA : out std_logic;
|
854 |
|
|
CFGMSGRECEIVEDASSERTINTB : out std_logic;
|
855 |
|
|
CFGMSGRECEIVEDASSERTINTC : out std_logic;
|
856 |
|
|
CFGMSGRECEIVEDASSERTINTD : out std_logic;
|
857 |
|
|
CFGMSGRECEIVEDDEASSERTINTA : out std_logic;
|
858 |
|
|
CFGMSGRECEIVEDDEASSERTINTB : out std_logic;
|
859 |
|
|
CFGMSGRECEIVEDDEASSERTINTC : out std_logic;
|
860 |
|
|
CFGMSGRECEIVEDDEASSERTINTD : out std_logic;
|
861 |
|
|
CFGMSGRECEIVEDERRCOR : out std_logic;
|
862 |
|
|
CFGMSGRECEIVEDERRFATAL : out std_logic;
|
863 |
|
|
CFGMSGRECEIVEDERRNONFATAL : out std_logic;
|
864 |
|
|
CFGMSGRECEIVEDPMASNAK : out std_logic;
|
865 |
|
|
CFGMSGRECEIVEDPMETO : out std_logic;
|
866 |
|
|
CFGMSGRECEIVEDPMETOACK : out std_logic;
|
867 |
|
|
CFGMSGRECEIVEDPMPME : out std_logic;
|
868 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic;
|
869 |
|
|
CFGMSGRECEIVEDUNLOCK : out std_logic;
|
870 |
|
|
CFGPCIELINKSTATE : out std_logic_vector(2 downto 0);
|
871 |
|
|
CFGPMCSRPMEEN : out std_logic;
|
872 |
|
|
CFGPMCSRPMESTATUS : out std_logic;
|
873 |
|
|
CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0);
|
874 |
|
|
CFGPMRCVASREQL1N : out std_logic;
|
875 |
|
|
CFGPMRCVENTERL1N : out std_logic;
|
876 |
|
|
CFGPMRCVENTERL23N : out std_logic;
|
877 |
|
|
CFGPMRCVREQACKN : out std_logic;
|
878 |
|
|
CFGRDWRDONEN : out std_logic;
|
879 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
|
880 |
|
|
CFGTRANSACTION : out std_logic;
|
881 |
|
|
CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0);
|
882 |
|
|
CFGTRANSACTIONTYPE : out std_logic;
|
883 |
|
|
CFGVCTCVCMAP : out std_logic_vector(6 downto 0);
|
884 |
|
|
CFGBYTEENN : in std_logic_vector(3 downto 0);
|
885 |
|
|
CFGDI : in std_logic_vector(31 downto 0);
|
886 |
|
|
CFGDSBUSNUMBER : in std_logic_vector(7 downto 0);
|
887 |
|
|
CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0);
|
888 |
|
|
CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0);
|
889 |
|
|
CFGDSN : in std_logic_vector(63 downto 0);
|
890 |
|
|
CFGDWADDR : in std_logic_vector(9 downto 0);
|
891 |
|
|
CFGERRACSN : in std_logic;
|
892 |
|
|
CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0);
|
893 |
|
|
CFGERRCORN : in std_logic;
|
894 |
|
|
CFGERRCPLABORTN : in std_logic;
|
895 |
|
|
CFGERRCPLTIMEOUTN : in std_logic;
|
896 |
|
|
CFGERRCPLUNEXPECTN : in std_logic;
|
897 |
|
|
CFGERRECRCN : in std_logic;
|
898 |
|
|
CFGERRLOCKEDN : in std_logic;
|
899 |
|
|
CFGERRPOSTEDN : in std_logic;
|
900 |
|
|
CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0);
|
901 |
|
|
CFGERRURN : in std_logic;
|
902 |
|
|
CFGINTERRUPTASSERTN : in std_logic;
|
903 |
|
|
CFGINTERRUPTDI : in std_logic_vector(7 downto 0);
|
904 |
|
|
CFGINTERRUPTN : in std_logic;
|
905 |
|
|
CFGPMDIRECTASPML1N : in std_logic;
|
906 |
|
|
CFGPMSENDPMACKN : in std_logic;
|
907 |
|
|
CFGPMSENDPMETON : in std_logic;
|
908 |
|
|
CFGPMSENDPMNAKN : in std_logic;
|
909 |
|
|
CFGPMTURNOFFOKN : in std_logic;
|
910 |
|
|
CFGPMWAKEN : in std_logic;
|
911 |
|
|
CFGPORTNUMBER : in std_logic_vector(7 downto 0);
|
912 |
|
|
CFGRDENN : in std_logic;
|
913 |
|
|
CFGTRNPENDINGN : in std_logic;
|
914 |
|
|
CFGWRENN : in std_logic;
|
915 |
|
|
CFGWRREADONLYN : in std_logic;
|
916 |
|
|
CFGWRRW1CASRWN : in std_logic;
|
917 |
|
|
PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0);
|
918 |
|
|
PLLANEREVERSALMODE : out std_logic_vector(1 downto 0);
|
919 |
|
|
PLLINKGEN2CAP : out std_logic;
|
920 |
|
|
PLLINKPARTNERGEN2SUPPORTED : out std_logic;
|
921 |
|
|
PLLINKUPCFGCAP : out std_logic;
|
922 |
|
|
PLLTSSMSTATE : out std_logic_vector(5 downto 0);
|
923 |
|
|
PLPHYLNKUPN : out std_logic;
|
924 |
|
|
PLRECEIVEDHOTRST : out std_logic;
|
925 |
|
|
PLRXPMSTATE : out std_logic_vector(1 downto 0);
|
926 |
|
|
PLSELLNKRATE : out std_logic;
|
927 |
|
|
PLSELLNKWIDTH : out std_logic_vector(1 downto 0);
|
928 |
|
|
PLTXPMSTATE : out std_logic_vector(2 downto 0);
|
929 |
|
|
PLDIRECTEDLINKAUTON : in std_logic;
|
930 |
|
|
PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0);
|
931 |
|
|
PLDIRECTEDLINKSPEED : in std_logic;
|
932 |
|
|
PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0);
|
933 |
|
|
PLDOWNSTREAMDEEMPHSOURCE : in std_logic;
|
934 |
|
|
PLUPSTREAMPREFERDEEMPH : in std_logic;
|
935 |
|
|
PLTRANSMITHOTRST : in std_logic;
|
936 |
|
|
DBGSCLRA : out std_logic;
|
937 |
|
|
DBGSCLRB : out std_logic;
|
938 |
|
|
DBGSCLRC : out std_logic;
|
939 |
|
|
DBGSCLRD : out std_logic;
|
940 |
|
|
DBGSCLRE : out std_logic;
|
941 |
|
|
DBGSCLRF : out std_logic;
|
942 |
|
|
DBGSCLRG : out std_logic;
|
943 |
|
|
DBGSCLRH : out std_logic;
|
944 |
|
|
DBGSCLRI : out std_logic;
|
945 |
|
|
DBGSCLRJ : out std_logic;
|
946 |
|
|
DBGSCLRK : out std_logic;
|
947 |
|
|
DBGVECA : out std_logic_vector(63 downto 0);
|
948 |
|
|
DBGVECB : out std_logic_vector(63 downto 0);
|
949 |
|
|
DBGVECC : out std_logic_vector(11 downto 0);
|
950 |
|
|
PLDBGVEC : out std_logic_vector(11 downto 0);
|
951 |
|
|
DBGMODE : in std_logic_vector(1 downto 0);
|
952 |
|
|
DBGSUBMODE : in std_logic;
|
953 |
|
|
PLDBGMODE : in std_logic_vector(2 downto 0);
|
954 |
|
|
PCIEDRPDO : out std_logic_vector(15 downto 0);
|
955 |
|
|
PCIEDRPDRDY : out std_logic;
|
956 |
|
|
PCIEDRPCLK : in std_logic;
|
957 |
|
|
PCIEDRPDADDR : in std_logic_vector(8 downto 0);
|
958 |
|
|
PCIEDRPDEN : in std_logic;
|
959 |
|
|
PCIEDRPDI : in std_logic_vector(15 downto 0);
|
960 |
|
|
PCIEDRPDWE : in std_logic;
|
961 |
|
|
GTPLLLOCK : out std_logic;
|
962 |
|
|
PIPECLK : in std_logic;
|
963 |
|
|
USERCLK : in std_logic;
|
964 |
|
|
DRPCLK : in std_logic;
|
965 |
|
|
CLOCKLOCKED : in std_logic;
|
966 |
|
|
TxOutClk : out std_logic);
|
967 |
|
|
end component;
|
968 |
|
|
|
969 |
|
|
FUNCTION to_integer (
|
970 |
|
|
val_in : bit_vector) RETURN integer IS
|
971 |
|
|
|
972 |
|
|
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
|
973 |
|
|
VARIABLE ret : integer := 0;
|
974 |
|
|
BEGIN
|
975 |
|
|
FOR index IN vctr'RANGE LOOP
|
976 |
|
|
IF (vctr(index) = '1') THEN
|
977 |
|
|
ret := ret + (2**index);
|
978 |
|
|
END IF;
|
979 |
|
|
END LOOP;
|
980 |
|
|
RETURN(ret);
|
981 |
|
|
END to_integer;
|
982 |
|
|
|
983 |
|
|
FUNCTION to_stdlogic (
|
984 |
|
|
in_val : IN boolean) RETURN std_logic IS
|
985 |
|
|
BEGIN
|
986 |
|
|
IF (in_val) THEN
|
987 |
|
|
RETURN('1');
|
988 |
|
|
ELSE
|
989 |
|
|
RETURN('0');
|
990 |
|
|
END IF;
|
991 |
|
|
END to_stdlogic;
|
992 |
|
|
|
993 |
|
|
function lp_lnk_bw_notif (
|
994 |
|
|
link_width : integer;
|
995 |
|
|
link_spd : integer)
|
996 |
|
|
return boolean is
|
997 |
|
|
begin -- lp_lnk_bw_notif
|
998 |
|
|
if ((link_width > 1) or (link_spd > 1)) then
|
999 |
|
|
return true;
|
1000 |
|
|
else
|
1001 |
|
|
return false;
|
1002 |
|
|
end if;
|
1003 |
|
|
end lp_lnk_bw_notif;
|
1004 |
|
|
|
1005 |
|
|
function pad_gen (
|
1006 |
|
|
in_vec : bit_vector;
|
1007 |
|
|
op_len : integer)
|
1008 |
|
|
return bit_vector is
|
1009 |
|
|
variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
|
1010 |
|
|
constant len : integer := in_vec'length; -- length of input vector
|
1011 |
|
|
begin -- pad_gen
|
1012 |
|
|
for i in 0 to op_len-1 loop
|
1013 |
|
|
if (i < len) then
|
1014 |
|
|
ret(i) := in_vec(len-i-1);
|
1015 |
|
|
else
|
1016 |
|
|
ret(i) := '0';
|
1017 |
|
|
end if;
|
1018 |
|
|
end loop; -- i
|
1019 |
|
|
return ret;
|
1020 |
|
|
end pad_gen;
|
1021 |
|
|
|
1022 |
|
|
constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
|
1023 |
|
|
|
1024 |
|
|
constant LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := lp_lnk_bw_notif(LINK_CAP_MAX_LINK_WIDTH_int, LINK_CAP_MAX_LINK_SPEED_int);
|
1025 |
|
|
|
1026 |
|
|
constant LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus : std_logic := to_stdlogic(LINK_STATUS_SLOT_CLOCK_CONFIG);
|
1027 |
|
|
|
1028 |
|
|
signal rx_func_level_reset_n : std_logic;
|
1029 |
|
|
|
1030 |
|
|
signal block_clk : std_logic;
|
1031 |
|
|
|
1032 |
|
|
signal cfg_cmd_bme : std_logic;
|
1033 |
|
|
signal cfg_cmd_intdis : std_logic;
|
1034 |
|
|
signal cfg_cmd_io_en : std_logic;
|
1035 |
|
|
signal cfg_cmd_mem_en : std_logic;
|
1036 |
|
|
signal cfg_cmd_serr_en : std_logic;
|
1037 |
|
|
signal cfg_dev_control_aux_power_en : std_logic;
|
1038 |
|
|
signal cfg_dev_control_corr_err_reporting_en : std_logic;
|
1039 |
|
|
signal cfg_dev_control_enable_relaxed_order : std_logic;
|
1040 |
|
|
signal cfg_dev_control_ext_tag_en : std_logic;
|
1041 |
|
|
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
|
1042 |
|
|
signal cfg_dev_control_maxpayload : std_logic_vector(2 downto 0);
|
1043 |
|
|
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
|
1044 |
|
|
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
|
1045 |
|
|
signal cfg_dev_control_nosnoop_en : std_logic;
|
1046 |
|
|
signal cfg_dev_control_phantom_en : std_logic;
|
1047 |
|
|
signal cfg_dev_control_ur_err_reporting_en : std_logic;
|
1048 |
|
|
signal cfg_dev_control2_cpltimeout_dis : std_logic;
|
1049 |
|
|
signal cfg_dev_control2_cpltimeout_val : std_logic_vector(3 downto 0);
|
1050 |
|
|
signal cfg_dev_status_corr_err_detected : std_logic;
|
1051 |
|
|
signal cfg_dev_status_fatal_err_detected : std_logic;
|
1052 |
|
|
signal cfg_dev_status_nonfatal_err_detected : std_logic;
|
1053 |
|
|
signal cfg_dev_status_ur_detected : std_logic;
|
1054 |
|
|
signal cfg_link_control_auto_bandwidth_int_en : std_logic;
|
1055 |
|
|
signal cfg_link_control_bandwidth_int_en : std_logic;
|
1056 |
|
|
signal cfg_link_control_hw_auto_width_dis : std_logic;
|
1057 |
|
|
signal cfg_link_control_clock_pm_en : std_logic;
|
1058 |
|
|
signal cfg_link_control_extended_sync : std_logic;
|
1059 |
|
|
signal cfg_link_control_common_clock : std_logic;
|
1060 |
|
|
signal cfg_link_control_retrain_link : std_logic;
|
1061 |
|
|
signal cfg_link_control_linkdisable : std_logic;
|
1062 |
|
|
signal cfg_link_control_rcb : std_logic;
|
1063 |
|
|
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
|
1064 |
|
|
signal cfg_link_status_auto_bandwidth_status : std_logic;
|
1065 |
|
|
signal cfg_link_status_bandwidth_status : std_logic;
|
1066 |
|
|
signal cfg_link_status_dll_active : std_logic;
|
1067 |
|
|
signal cfg_link_status_link_training : std_logic;
|
1068 |
|
|
signal cfg_link_status_negotiated_link_width : std_logic_vector(3 downto 0);
|
1069 |
|
|
signal cfg_link_status_current_speed : std_logic_vector(1 downto 0);
|
1070 |
|
|
|
1071 |
|
|
signal sys_reset_n_d : std_logic;
|
1072 |
|
|
signal phy_rdy_n : std_logic;
|
1073 |
|
|
|
1074 |
|
|
signal trn_lnk_up_n_int : std_logic;
|
1075 |
|
|
signal trn_lnk_up_n_int1 : std_logic;
|
1076 |
|
|
|
1077 |
|
|
signal trn_reset_n_int : std_logic;
|
1078 |
|
|
signal trn_reset_n_int1 : std_logic;
|
1079 |
|
|
|
1080 |
|
|
|
1081 |
|
|
signal TxOutClk : std_logic;
|
1082 |
|
|
signal TxOutClk_bufg : std_logic;
|
1083 |
|
|
|
1084 |
|
|
signal gt_pll_lock : std_logic;
|
1085 |
|
|
|
1086 |
|
|
signal user_clk : std_logic;
|
1087 |
|
|
signal drp_clk : std_logic;
|
1088 |
|
|
signal clock_locked : std_logic;
|
1089 |
|
|
-- X-HDL generated signals
|
1090 |
|
|
|
1091 |
|
|
signal v6pcie63 : std_logic;
|
1092 |
|
|
signal v6pcie64 : std_logic;
|
1093 |
|
|
signal v6pcie65 : std_logic;
|
1094 |
|
|
signal v6pcie66 : std_logic;
|
1095 |
|
|
signal v6pcie67 : std_logic;
|
1096 |
|
|
signal v6pcie68 : std_logic_vector(1 downto 0);
|
1097 |
|
|
signal v6pcie69 : std_logic;
|
1098 |
|
|
signal func_lvl_rstn : std_logic;
|
1099 |
|
|
signal cm_rstn : std_logic;
|
1100 |
|
|
|
1101 |
|
|
-- Declare intermediate signals for referenced outputs
|
1102 |
|
|
signal pci_exp_txp_v6pcie28 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
1103 |
|
|
signal pci_exp_txn_v6pcie27 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
1104 |
|
|
signal trn_clk_v6pcie41 : std_logic;
|
1105 |
|
|
signal trn_reset_n_v6pcie54 : std_logic;
|
1106 |
|
|
signal trn_lnk_up_n_v6pcie48 : std_logic;
|
1107 |
|
|
signal trn_tbuf_av_v6pcie59 : std_logic_vector(5 downto 0);
|
1108 |
|
|
signal trn_tcfg_req_n_v6pcie60 : std_logic;
|
1109 |
|
|
signal trn_terr_drop_n_v6pcie62 : std_logic;
|
1110 |
|
|
signal trn_tdst_rdy_n_v6pcie61 : std_logic;
|
1111 |
|
|
signal trn_rd_v6pcie50 : std_logic_vector(63 downto 0);
|
1112 |
|
|
signal trn_rrem_n_v6pcie55 : std_logic;
|
1113 |
|
|
signal trn_rsof_n_v6pcie56 : std_logic;
|
1114 |
|
|
signal trn_reof_n_v6pcie52 : std_logic;
|
1115 |
|
|
signal trn_rsrc_rdy_n_v6pcie58 : std_logic;
|
1116 |
|
|
signal trn_rsrc_dsc_n_v6pcie57 : std_logic;
|
1117 |
|
|
signal trn_rerrfwd_n_v6pcie53 : std_logic;
|
1118 |
|
|
signal trn_rbar_hit_n_v6pcie49 : std_logic_vector(6 downto 0);
|
1119 |
|
|
signal trn_recrc_err_n_v6pcie51 : std_logic;
|
1120 |
|
|
signal trn_fc_cpld_v6pcie42 : std_logic_vector(11 downto 0);
|
1121 |
|
|
signal trn_fc_cplh_v6pcie43 : std_logic_vector(7 downto 0);
|
1122 |
|
|
signal trn_fc_npd_v6pcie44 : std_logic_vector(11 downto 0);
|
1123 |
|
|
signal trn_fc_nph_v6pcie45 : std_logic_vector(7 downto 0);
|
1124 |
|
|
signal trn_fc_pd_v6pcie46 : std_logic_vector(11 downto 0);
|
1125 |
|
|
signal trn_fc_ph_v6pcie47 : std_logic_vector(7 downto 0);
|
1126 |
|
|
signal cfg_err_cpl_rdy_n_v6pcie1 : std_logic;
|
1127 |
|
|
signal cfg_interrupt_rdy_n_v6pcie7 : std_logic;
|
1128 |
|
|
signal cfg_interrupt_do_v6pcie2 : std_logic_vector(7 downto 0);
|
1129 |
|
|
signal cfg_interrupt_mmenable_v6pcie3 : std_logic_vector(2 downto 0);
|
1130 |
|
|
signal cfg_interrupt_msienable_v6pcie4 : std_logic;
|
1131 |
|
|
signal cfg_interrupt_msixenable_v6pcie5 : std_logic;
|
1132 |
|
|
signal cfg_interrupt_msixfm_v6pcie6 : std_logic;
|
1133 |
|
|
signal cfg_pcie_link_state_n_v6pcie22 : std_logic_vector(2 downto 0);
|
1134 |
|
|
signal cfg_pmcsr_pme_en_v6pcie23 : std_logic;
|
1135 |
|
|
signal cfg_pmcsr_pme_status_v6pcie24 : std_logic;
|
1136 |
|
|
signal cfg_pmcsr_powerstate_v6pcie25 : std_logic_vector(1 downto 0);
|
1137 |
|
|
signal cfg_msg_received_v6pcie9 : std_logic;
|
1138 |
|
|
signal cfg_msg_data_v6pcie8 : std_logic_vector(15 downto 0);
|
1139 |
|
|
signal cfg_msg_received_err_cor_v6pcie18 : std_logic;
|
1140 |
|
|
signal cfg_msg_received_err_non_fatal_v6pcie20 : std_logic;
|
1141 |
|
|
signal cfg_msg_received_err_fatal_v6pcie19 : std_logic;
|
1142 |
|
|
signal cfg_msg_received_pme_to_ack_v6pcie21 : std_logic;
|
1143 |
|
|
signal cfg_msg_received_assert_inta_v6pcie10 : std_logic;
|
1144 |
|
|
signal cfg_msg_received_assert_intb_v6pcie11 : std_logic;
|
1145 |
|
|
signal cfg_msg_received_assert_intc_v6pcie12 : std_logic;
|
1146 |
|
|
signal cfg_msg_received_assert_intd_v6pcie13 : std_logic;
|
1147 |
|
|
signal cfg_msg_received_deassert_inta_v6pcie14 : std_logic;
|
1148 |
|
|
signal cfg_msg_received_deassert_intb_v6pcie15 : std_logic;
|
1149 |
|
|
signal cfg_msg_received_deassert_intc_v6pcie16 : std_logic;
|
1150 |
|
|
signal cfg_msg_received_deassert_intd_v6pcie17 : std_logic;
|
1151 |
|
|
signal pipe_clk : std_logic;
|
1152 |
|
|
signal pl_phy_lnk_up_n : std_logic;
|
1153 |
|
|
signal pl_initial_link_width_v6pcie32 : std_logic_vector(2 downto 0);
|
1154 |
|
|
signal pl_lane_reversal_mode_v6pcie33 : std_logic_vector(1 downto 0);
|
1155 |
|
|
signal pl_link_gen2_capable_v6pcie34 : std_logic;
|
1156 |
|
|
signal pl_link_partner_gen2_supported_v6pcie35 : std_logic;
|
1157 |
|
|
signal pl_link_upcfg_capable_v6pcie36 : std_logic;
|
1158 |
|
|
signal pl_ltssm_state_v6pcie37 : std_logic_vector(5 downto 0);
|
1159 |
|
|
signal pl_sel_link_rate_v6pcie39 : std_logic;
|
1160 |
|
|
signal pl_sel_link_width_v6pcie40 : std_logic_vector(1 downto 0);
|
1161 |
|
|
signal pcie_drp_do_v6pcie29 : std_logic_vector(15 downto 0);
|
1162 |
|
|
signal pcie_drp_drdy_v6pcie30 : std_logic;
|
1163 |
|
|
begin
|
1164 |
|
|
-- Drive referenced outputs
|
1165 |
|
|
pci_exp_txp <= pci_exp_txp_v6pcie28;
|
1166 |
|
|
pci_exp_txn <= pci_exp_txn_v6pcie27;
|
1167 |
|
|
trn_clk <= trn_clk_v6pcie41;
|
1168 |
|
|
trn_reset_n <= trn_reset_n_v6pcie54;
|
1169 |
|
|
trn_lnk_up_n <= trn_lnk_up_n_v6pcie48;
|
1170 |
|
|
trn_tbuf_av <= trn_tbuf_av_v6pcie59;
|
1171 |
|
|
trn_tcfg_req_n <= trn_tcfg_req_n_v6pcie60;
|
1172 |
|
|
trn_terr_drop_n <= trn_terr_drop_n_v6pcie62;
|
1173 |
|
|
trn_tdst_rdy_n <= trn_tdst_rdy_n_v6pcie61;
|
1174 |
|
|
trn_rd <= trn_rd_v6pcie50;
|
1175 |
|
|
trn_rrem_n <= trn_rrem_n_v6pcie55;
|
1176 |
|
|
trn_rsof_n <= trn_rsof_n_v6pcie56;
|
1177 |
|
|
trn_reof_n <= trn_reof_n_v6pcie52;
|
1178 |
|
|
trn_rsrc_rdy_n <= trn_rsrc_rdy_n_v6pcie58;
|
1179 |
|
|
trn_rsrc_dsc_n <= trn_rsrc_dsc_n_v6pcie57;
|
1180 |
|
|
trn_rerrfwd_n <= trn_rerrfwd_n_v6pcie53;
|
1181 |
|
|
trn_rbar_hit_n <= trn_rbar_hit_n_v6pcie49;
|
1182 |
|
|
trn_recrc_err_n <= trn_recrc_err_n_v6pcie51;
|
1183 |
|
|
trn_fc_cpld <= trn_fc_cpld_v6pcie42;
|
1184 |
|
|
trn_fc_cplh <= trn_fc_cplh_v6pcie43;
|
1185 |
|
|
trn_fc_npd <= trn_fc_npd_v6pcie44;
|
1186 |
|
|
trn_fc_nph <= trn_fc_nph_v6pcie45;
|
1187 |
|
|
trn_fc_pd <= trn_fc_pd_v6pcie46;
|
1188 |
|
|
trn_fc_ph <= trn_fc_ph_v6pcie47;
|
1189 |
|
|
cfg_err_cpl_rdy_n <= cfg_err_cpl_rdy_n_v6pcie1;
|
1190 |
|
|
cfg_interrupt_rdy_n <= cfg_interrupt_rdy_n_v6pcie7;
|
1191 |
|
|
cfg_interrupt_do <= cfg_interrupt_do_v6pcie2;
|
1192 |
|
|
cfg_interrupt_mmenable <= cfg_interrupt_mmenable_v6pcie3;
|
1193 |
|
|
cfg_interrupt_msienable <= cfg_interrupt_msienable_v6pcie4;
|
1194 |
|
|
cfg_interrupt_msixenable <= cfg_interrupt_msixenable_v6pcie5;
|
1195 |
|
|
cfg_interrupt_msixfm <= cfg_interrupt_msixfm_v6pcie6;
|
1196 |
|
|
cfg_pcie_link_state_n <= cfg_pcie_link_state_n_v6pcie22;
|
1197 |
|
|
cfg_pmcsr_pme_en <= cfg_pmcsr_pme_en_v6pcie23;
|
1198 |
|
|
cfg_pmcsr_pme_status <= cfg_pmcsr_pme_status_v6pcie24;
|
1199 |
|
|
cfg_pmcsr_powerstate <= cfg_pmcsr_powerstate_v6pcie25;
|
1200 |
|
|
cfg_msg_received <= cfg_msg_received_v6pcie9;
|
1201 |
|
|
cfg_msg_data <= cfg_msg_data_v6pcie8;
|
1202 |
|
|
cfg_msg_received_err_cor <= cfg_msg_received_err_cor_v6pcie18;
|
1203 |
|
|
cfg_msg_received_err_non_fatal <= cfg_msg_received_err_non_fatal_v6pcie20;
|
1204 |
|
|
cfg_msg_received_err_fatal <= cfg_msg_received_err_fatal_v6pcie19;
|
1205 |
|
|
cfg_msg_received_pme_to_ack <= cfg_msg_received_pme_to_ack_v6pcie21;
|
1206 |
|
|
cfg_msg_received_assert_inta <= cfg_msg_received_assert_inta_v6pcie10;
|
1207 |
|
|
cfg_msg_received_assert_intb <= cfg_msg_received_assert_intb_v6pcie11;
|
1208 |
|
|
cfg_msg_received_assert_intc <= cfg_msg_received_assert_intc_v6pcie12;
|
1209 |
|
|
cfg_msg_received_assert_intd <= cfg_msg_received_assert_intd_v6pcie13;
|
1210 |
|
|
cfg_msg_received_deassert_inta <= cfg_msg_received_deassert_inta_v6pcie14;
|
1211 |
|
|
cfg_msg_received_deassert_intb <= cfg_msg_received_deassert_intb_v6pcie15;
|
1212 |
|
|
cfg_msg_received_deassert_intc <= cfg_msg_received_deassert_intc_v6pcie16;
|
1213 |
|
|
cfg_msg_received_deassert_intd <= cfg_msg_received_deassert_intd_v6pcie17;
|
1214 |
|
|
pl_initial_link_width <= pl_initial_link_width_v6pcie32;
|
1215 |
|
|
pl_lane_reversal_mode <= pl_lane_reversal_mode_v6pcie33;
|
1216 |
|
|
pl_link_gen2_capable <= pl_link_gen2_capable_v6pcie34;
|
1217 |
|
|
pl_link_partner_gen2_supported <= pl_link_partner_gen2_supported_v6pcie35;
|
1218 |
|
|
pl_link_upcfg_capable <= pl_link_upcfg_capable_v6pcie36;
|
1219 |
|
|
pl_ltssm_state <= pl_ltssm_state_v6pcie37;
|
1220 |
|
|
pl_sel_link_rate <= pl_sel_link_rate_v6pcie39;
|
1221 |
|
|
pl_sel_link_width <= pl_sel_link_width_v6pcie40;
|
1222 |
|
|
pcie_drp_do <= pcie_drp_do_v6pcie29;
|
1223 |
|
|
pcie_drp_drdy <= pcie_drp_drdy_v6pcie30;
|
1224 |
|
|
|
1225 |
|
|
-- assigns to outputs
|
1226 |
|
|
|
1227 |
|
|
cfg_status <= "0000000000000000";
|
1228 |
|
|
|
1229 |
|
|
cfg_command <= ("00000" &
|
1230 |
|
|
cfg_cmd_intdis &
|
1231 |
|
|
'0' &
|
1232 |
|
|
cfg_cmd_serr_en &
|
1233 |
|
|
"00000" &
|
1234 |
|
|
cfg_cmd_bme &
|
1235 |
|
|
cfg_cmd_mem_en &
|
1236 |
|
|
cfg_cmd_io_en);
|
1237 |
|
|
|
1238 |
|
|
cfg_dstatus <= ("0000000000" &
|
1239 |
|
|
cfg_trn_pending_n &
|
1240 |
|
|
'0' &
|
1241 |
|
|
cfg_dev_status_ur_detected &
|
1242 |
|
|
cfg_dev_status_fatal_err_detected &
|
1243 |
|
|
cfg_dev_status_nonfatal_err_detected &
|
1244 |
|
|
cfg_dev_status_corr_err_detected);
|
1245 |
|
|
|
1246 |
|
|
cfg_dcommand <= ('0' &
|
1247 |
|
|
cfg_dev_control_max_read_req &
|
1248 |
|
|
cfg_dev_control_nosnoop_en &
|
1249 |
|
|
cfg_dev_control_aux_power_en &
|
1250 |
|
|
cfg_dev_control_phantom_en &
|
1251 |
|
|
cfg_dev_control_ext_tag_en &
|
1252 |
|
|
cfg_dev_control_maxpayload &
|
1253 |
|
|
cfg_dev_control_enable_relaxed_order &
|
1254 |
|
|
cfg_dev_control_ur_err_reporting_en &
|
1255 |
|
|
cfg_dev_control_fatal_err_reporting_en &
|
1256 |
|
|
cfg_dev_control_non_fatal_reporting_en &
|
1257 |
|
|
cfg_dev_control_corr_err_reporting_en);
|
1258 |
|
|
|
1259 |
|
|
cfg_lstatus <= (cfg_link_status_auto_bandwidth_status &
|
1260 |
|
|
cfg_link_status_bandwidth_status &
|
1261 |
|
|
cfg_link_status_dll_active &
|
1262 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus &
|
1263 |
|
|
cfg_link_status_link_training &
|
1264 |
|
|
'0' &
|
1265 |
|
|
("00" & cfg_link_status_negotiated_link_width) &
|
1266 |
|
|
("00" & cfg_link_status_current_speed));
|
1267 |
|
|
|
1268 |
|
|
cfg_lcommand <= ("0000" &
|
1269 |
|
|
cfg_link_control_auto_bandwidth_int_en &
|
1270 |
|
|
cfg_link_control_bandwidth_int_en &
|
1271 |
|
|
cfg_link_control_hw_auto_width_dis &
|
1272 |
|
|
cfg_link_control_clock_pm_en &
|
1273 |
|
|
cfg_link_control_extended_sync &
|
1274 |
|
|
cfg_link_control_common_clock &
|
1275 |
|
|
cfg_link_control_retrain_link &
|
1276 |
|
|
cfg_link_control_linkdisable &
|
1277 |
|
|
cfg_link_control_rcb &
|
1278 |
|
|
'0' &
|
1279 |
|
|
cfg_link_control_aspm_control);
|
1280 |
|
|
|
1281 |
|
|
cfg_dcommand2 <= ("00000000000" &
|
1282 |
|
|
cfg_dev_control2_cpltimeout_dis &
|
1283 |
|
|
cfg_dev_control2_cpltimeout_val);
|
1284 |
|
|
|
1285 |
|
|
|
1286 |
|
|
-- Generate trn_lnk_up_n
|
1287 |
|
|
|
1288 |
|
|
trn_lnk_up_n_i : FDCP
|
1289 |
|
|
generic map (
|
1290 |
|
|
INIT => '1'
|
1291 |
|
|
)
|
1292 |
|
|
port map (
|
1293 |
|
|
Q => trn_lnk_up_n_v6pcie48,
|
1294 |
|
|
D => trn_lnk_up_n_int1,
|
1295 |
|
|
C => trn_clk_v6pcie41,
|
1296 |
|
|
CLR => '0',
|
1297 |
|
|
PRE => '0'
|
1298 |
|
|
);
|
1299 |
|
|
|
1300 |
|
|
|
1301 |
|
|
trn_lnk_up_n_int_i : FDCP
|
1302 |
|
|
generic map (
|
1303 |
|
|
INIT => '1'
|
1304 |
|
|
)
|
1305 |
|
|
port map (
|
1306 |
|
|
Q => trn_lnk_up_n_int1,
|
1307 |
|
|
D => trn_lnk_up_n_int,
|
1308 |
|
|
C => trn_clk_v6pcie41,
|
1309 |
|
|
CLR => '0',
|
1310 |
|
|
PRE => '0'
|
1311 |
|
|
);
|
1312 |
|
|
|
1313 |
|
|
|
1314 |
|
|
-- Generate trn_reset_n
|
1315 |
|
|
|
1316 |
|
|
v6pcie63 <= trn_reset_n_int1 and not(phy_rdy_n);
|
1317 |
|
|
v6pcie64 <= not(sys_reset_n_d);
|
1318 |
|
|
|
1319 |
|
|
-- Generate trn_reset_n
|
1320 |
|
|
|
1321 |
|
|
trn_reset_n_i : FDCP
|
1322 |
|
|
generic map (
|
1323 |
|
|
INIT => '0'
|
1324 |
|
|
)
|
1325 |
|
|
port map (
|
1326 |
|
|
Q => trn_reset_n_v6pcie54,
|
1327 |
|
|
D => v6pcie63,
|
1328 |
|
|
C => trn_clk_v6pcie41,
|
1329 |
|
|
CLR => v6pcie64,
|
1330 |
|
|
PRE => '0'
|
1331 |
|
|
);
|
1332 |
|
|
|
1333 |
|
|
v6pcie65 <= trn_reset_n_int and not(phy_rdy_n);
|
1334 |
|
|
v6pcie66 <= not(sys_reset_n_d);
|
1335 |
|
|
|
1336 |
|
|
trn_reset_n_int_i : FDCP
|
1337 |
|
|
generic map (
|
1338 |
|
|
INIT => '0'
|
1339 |
|
|
)
|
1340 |
|
|
port map (
|
1341 |
|
|
Q => trn_reset_n_int1,
|
1342 |
|
|
D => v6pcie65,
|
1343 |
|
|
C => trn_clk_v6pcie41,
|
1344 |
|
|
CLR => v6pcie66,
|
1345 |
|
|
PRE => '0'
|
1346 |
|
|
);
|
1347 |
|
|
|
1348 |
|
|
|
1349 |
|
|
---------------------------------------------------------
|
1350 |
|
|
-- PCI Express Reset Delay Module
|
1351 |
|
|
---------------------------------------------------------
|
1352 |
|
|
|
1353 |
|
|
pcie_reset_delay_i : pcie_reset_delay_v6
|
1354 |
|
|
generic map (
|
1355 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
1356 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ
|
1357 |
|
|
)
|
1358 |
|
|
port map (
|
1359 |
|
|
ref_clk => TxOutClk_bufg,
|
1360 |
|
|
sys_reset_n => sys_reset_n,
|
1361 |
|
|
delayed_sys_reset_n => sys_reset_n_d
|
1362 |
|
|
);
|
1363 |
|
|
|
1364 |
|
|
|
1365 |
|
|
---------------------------------------------------------
|
1366 |
|
|
-- PCI Express Clocking Module
|
1367 |
|
|
---------------------------------------------------------
|
1368 |
|
|
|
1369 |
|
|
pcie_clocking_i : pcie_clocking_v6
|
1370 |
|
|
generic map (
|
1371 |
|
|
IS_ENDPOINT => FALSE,
|
1372 |
|
|
CAP_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int,
|
1373 |
|
|
CAP_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int,
|
1374 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
1375 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ
|
1376 |
|
|
)
|
1377 |
|
|
port map (
|
1378 |
|
|
sys_clk => TxOutClk,
|
1379 |
|
|
gt_pll_lock => gt_pll_lock,
|
1380 |
|
|
sel_lnk_rate => pl_sel_link_rate_v6pcie39,
|
1381 |
|
|
sel_lnk_width => pl_sel_link_width_v6pcie40,
|
1382 |
|
|
sys_clk_bufg => TxOutClk_bufg,
|
1383 |
|
|
pipe_clk => pipe_clk,
|
1384 |
|
|
user_clk => user_clk,
|
1385 |
|
|
block_clk => open,
|
1386 |
|
|
drp_clk => drp_clk,
|
1387 |
|
|
clock_locked => clock_locked
|
1388 |
|
|
);
|
1389 |
|
|
|
1390 |
|
|
---------------------------------------------------------
|
1391 |
|
|
-- Virtex6 PCI Express Block Module
|
1392 |
|
|
---------------------------------------------------------
|
1393 |
|
|
|
1394 |
|
|
|
1395 |
|
|
|
1396 |
|
|
|
1397 |
|
|
v6pcie67 <= not(phy_rdy_n);
|
1398 |
|
|
|
1399 |
|
|
-- Debug
|
1400 |
|
|
-- Debug
|
1401 |
|
|
-- Debug
|
1402 |
|
|
v6pcie68 <= pl_directed_link_change;
|
1403 |
|
|
v6pcie69 <= pl_directed_link_speed;
|
1404 |
|
|
|
1405 |
|
|
func_lvl_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
|
1406 |
|
|
'1';
|
1407 |
|
|
cm_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
|
1408 |
|
|
'1';
|
1409 |
|
|
|
1410 |
|
|
pcie_2_0_i : pcie_2_0_v6_rp
|
1411 |
|
|
generic map (
|
1412 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
1413 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES,
|
1414 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
|
1415 |
|
|
AER_BASE_PTR => AER_BASE_PTR,
|
1416 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE,
|
1417 |
|
|
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE,
|
1418 |
|
|
AER_CAP_ID => AER_CAP_ID,
|
1419 |
|
|
AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI,
|
1420 |
|
|
AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX,
|
1421 |
|
|
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR,
|
1422 |
|
|
AER_CAP_ON => AER_CAP_ON,
|
1423 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE,
|
1424 |
|
|
AER_CAP_VERSION => AER_CAP_VERSION,
|
1425 |
|
|
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
|
1426 |
|
|
BAR0 => pad_gen(BAR0, 32),
|
1427 |
|
|
BAR1 => pad_gen(BAR1, 32),
|
1428 |
|
|
BAR2 => pad_gen(BAR2, 32),
|
1429 |
|
|
BAR3 => pad_gen(BAR3, 32),
|
1430 |
|
|
BAR4 => pad_gen(BAR4, 32),
|
1431 |
|
|
BAR5 => pad_gen(BAR5, 32),
|
1432 |
|
|
CAPABILITIES_PTR => CAPABILITIES_PTR,
|
1433 |
|
|
CARDBUS_CIS_POINTER => pad_gen(CARDBUS_CIS_POINTER, 32),
|
1434 |
|
|
CLASS_CODE => pad_gen(CLASS_CODE, 24),
|
1435 |
|
|
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED,
|
1436 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED,
|
1437 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4),
|
1438 |
|
|
CRM_MODULE_RSTS => CRM_MODULE_RSTS,
|
1439 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
|
1440 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
|
1441 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
|
1442 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
|
1443 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
|
1444 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
|
1445 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
1446 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
|
1447 |
|
|
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
|
1448 |
|
|
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12,
|
1449 |
|
|
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16,
|
1450 |
|
|
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29,
|
1451 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED,
|
1452 |
|
|
DEVICE_ID => pad_gen(DEVICE_ID, 16),
|
1453 |
|
|
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER,
|
1454 |
|
|
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
|
1455 |
|
|
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
|
1456 |
|
|
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL,
|
1457 |
|
|
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER,
|
1458 |
|
|
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
|
1459 |
|
|
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM,
|
1460 |
|
|
DSN_BASE_PTR => pad_gen(DSN_BASE_PTR, 12),
|
1461 |
|
|
DSN_CAP_ID => DSN_CAP_ID,
|
1462 |
|
|
DSN_CAP_NEXTPTR => pad_gen(DSN_CAP_NEXTPTR, 12),
|
1463 |
|
|
DSN_CAP_ON => DSN_CAP_ON,
|
1464 |
|
|
DSN_CAP_VERSION => DSN_CAP_VERSION,
|
1465 |
|
|
ENABLE_MSG_ROUTE => pad_gen(ENABLE_MSG_ROUTE, 11),
|
1466 |
|
|
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
|
1467 |
|
|
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0,
|
1468 |
|
|
EXPANSION_ROM => pad_gen(EXPANSION_ROM, 32),
|
1469 |
|
|
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR,
|
1470 |
|
|
EXT_CFG_XP_CAP_PTR => pad_gen(EXT_CFG_XP_CAP_PTR, 10),
|
1471 |
|
|
HEADER_TYPE => pad_gen(HEADER_TYPE, 8),
|
1472 |
|
|
INFER_EI => INFER_EI,
|
1473 |
|
|
INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8),
|
1474 |
|
|
IS_SWITCH => IS_SWITCH,
|
1475 |
|
|
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD,
|
1476 |
|
|
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
|
1477 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT,
|
1478 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
|
1479 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
|
1480 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
|
1481 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
|
1482 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
|
1483 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
|
1484 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
|
1485 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
|
1486 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1,
|
1487 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2,
|
1488 |
|
|
LINK_CAP_MAX_LINK_SPEED => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4),
|
1489 |
|
|
LINK_CAP_MAX_LINK_WIDTH => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6),
|
1490 |
|
|
LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22,
|
1491 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
|
1492 |
|
|
LINK_CONTROL_RCB => LINK_CONTROL_RCB,
|
1493 |
|
|
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS,
|
1494 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
|
1495 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4),
|
1496 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
|
1497 |
|
|
LL_ACK_TIMEOUT => pad_gen(LL_ACK_TIMEOUT, 15),
|
1498 |
|
|
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
|
1499 |
|
|
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC,
|
1500 |
|
|
LL_REPLAY_TIMEOUT => pad_gen(LL_REPLAY_TIMEOUT, 15),
|
1501 |
|
|
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
|
1502 |
|
|
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC,
|
1503 |
|
|
LTSSM_MAX_LINK_WIDTH => pad_gen(LTSSM_MAX_LINK_WIDTH, 6),
|
1504 |
|
|
MSI_BASE_PTR => MSI_BASE_PTR,
|
1505 |
|
|
MSI_CAP_ID => MSI_CAP_ID,
|
1506 |
|
|
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
|
1507 |
|
|
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
|
1508 |
|
|
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR,
|
1509 |
|
|
MSI_CAP_ON => MSI_CAP_ON,
|
1510 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
|
1511 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE,
|
1512 |
|
|
MSIX_BASE_PTR => MSIX_BASE_PTR,
|
1513 |
|
|
MSIX_CAP_ID => MSIX_CAP_ID,
|
1514 |
|
|
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR,
|
1515 |
|
|
MSIX_CAP_ON => MSIX_CAP_ON,
|
1516 |
|
|
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR,
|
1517 |
|
|
MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29),
|
1518 |
|
|
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR,
|
1519 |
|
|
MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29),
|
1520 |
|
|
MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11),
|
1521 |
|
|
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1,
|
1522 |
|
|
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2,
|
1523 |
|
|
N_FTS_GEN1 => N_FTS_GEN1,
|
1524 |
|
|
N_FTS_GEN2 => N_FTS_GEN2,
|
1525 |
|
|
PCIE_BASE_PTR => PCIE_BASE_PTR,
|
1526 |
|
|
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID,
|
1527 |
|
|
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
|
1528 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4),
|
1529 |
|
|
PCIE_CAP_INT_MSG_NUM => pad_gen(PCIE_CAP_INT_MSG_NUM, 5),
|
1530 |
|
|
PCIE_CAP_NEXTPTR => pad_gen(PCIE_CAP_NEXTPTR, 8),
|
1531 |
|
|
PCIE_CAP_ON => PCIE_CAP_ON,
|
1532 |
|
|
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14,
|
1533 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
|
1534 |
|
|
PCIE_REVISION => PCIE_REVISION,
|
1535 |
|
|
PGL0_LANE => PGL0_LANE,
|
1536 |
|
|
PGL1_LANE => PGL1_LANE,
|
1537 |
|
|
PGL2_LANE => PGL2_LANE,
|
1538 |
|
|
PGL3_LANE => PGL3_LANE,
|
1539 |
|
|
PGL4_LANE => PGL4_LANE,
|
1540 |
|
|
PGL5_LANE => PGL5_LANE,
|
1541 |
|
|
PGL6_LANE => PGL6_LANE,
|
1542 |
|
|
PGL7_LANE => PGL7_LANE,
|
1543 |
|
|
PL_AUTO_CONFIG => PL_AUTO_CONFIG,
|
1544 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
1545 |
|
|
PM_BASE_PTR => PM_BASE_PTR,
|
1546 |
|
|
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
|
1547 |
|
|
PM_CAP_DSI => PM_CAP_DSI,
|
1548 |
|
|
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
|
1549 |
|
|
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
|
1550 |
|
|
PM_CAP_ID => PM_CAP_ID,
|
1551 |
|
|
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR,
|
1552 |
|
|
PM_CAP_ON => PM_CAP_ON,
|
1553 |
|
|
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
|
1554 |
|
|
PM_CAP_PMESUPPORT => pad_gen(PM_CAP_PMESUPPORT, 5),
|
1555 |
|
|
PM_CAP_RSVD_04 => PM_CAP_RSVD_04,
|
1556 |
|
|
PM_CAP_VERSION => PM_CAP_VERSION,
|
1557 |
|
|
PM_CSR_BPCCEN => PM_CSR_BPCCEN,
|
1558 |
|
|
PM_CSR_B2B3 => PM_CSR_B2B3,
|
1559 |
|
|
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST,
|
1560 |
|
|
PM_DATA_SCALE0 => pad_gen(PM_DATA_SCALE0, 2),
|
1561 |
|
|
PM_DATA_SCALE1 => pad_gen(PM_DATA_SCALE1, 2),
|
1562 |
|
|
PM_DATA_SCALE2 => pad_gen(PM_DATA_SCALE2, 2),
|
1563 |
|
|
PM_DATA_SCALE3 => pad_gen(PM_DATA_SCALE3, 2),
|
1564 |
|
|
PM_DATA_SCALE4 => pad_gen(PM_DATA_SCALE4, 2),
|
1565 |
|
|
PM_DATA_SCALE5 => pad_gen(PM_DATA_SCALE5, 2),
|
1566 |
|
|
PM_DATA_SCALE6 => pad_gen(PM_DATA_SCALE6, 2),
|
1567 |
|
|
PM_DATA_SCALE7 => pad_gen(PM_DATA_SCALE7, 2),
|
1568 |
|
|
PM_DATA0 => pad_gen(PM_DATA0, 8),
|
1569 |
|
|
PM_DATA1 => pad_gen(PM_DATA1, 8),
|
1570 |
|
|
PM_DATA2 => pad_gen(PM_DATA2, 8),
|
1571 |
|
|
PM_DATA3 => pad_gen(PM_DATA3, 8),
|
1572 |
|
|
PM_DATA4 => pad_gen(PM_DATA4, 8),
|
1573 |
|
|
PM_DATA5 => pad_gen(PM_DATA5, 8),
|
1574 |
|
|
PM_DATA6 => pad_gen(PM_DATA6, 8),
|
1575 |
|
|
PM_DATA7 => pad_gen(PM_DATA7, 8),
|
1576 |
|
|
RECRC_CHK => RECRC_CHK,
|
1577 |
|
|
RECRC_CHK_TRIM => RECRC_CHK_TRIM,
|
1578 |
|
|
REVISION_ID => pad_gen(REVISION_ID, 8),
|
1579 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY,
|
1580 |
|
|
SELECT_DLL_IF => SELECT_DLL_IF,
|
1581 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
|
1582 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
|
1583 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
|
1584 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE,
|
1585 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE,
|
1586 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT,
|
1587 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
|
1588 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM,
|
1589 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT,
|
1590 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
|
1591 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
|
1592 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
|
1593 |
|
|
SPARE_BIT0 => SPARE_BIT0,
|
1594 |
|
|
SPARE_BIT1 => SPARE_BIT1,
|
1595 |
|
|
SPARE_BIT2 => SPARE_BIT2,
|
1596 |
|
|
SPARE_BIT3 => SPARE_BIT3,
|
1597 |
|
|
SPARE_BIT4 => SPARE_BIT4,
|
1598 |
|
|
SPARE_BIT5 => SPARE_BIT5,
|
1599 |
|
|
SPARE_BIT6 => SPARE_BIT6,
|
1600 |
|
|
SPARE_BIT7 => SPARE_BIT7,
|
1601 |
|
|
SPARE_BIT8 => SPARE_BIT8,
|
1602 |
|
|
SPARE_BYTE0 => SPARE_BYTE0,
|
1603 |
|
|
SPARE_BYTE1 => SPARE_BYTE1,
|
1604 |
|
|
SPARE_BYTE2 => SPARE_BYTE2,
|
1605 |
|
|
SPARE_BYTE3 => SPARE_BYTE3,
|
1606 |
|
|
SPARE_WORD0 => SPARE_WORD0,
|
1607 |
|
|
SPARE_WORD1 => SPARE_WORD1,
|
1608 |
|
|
SPARE_WORD2 => SPARE_WORD2,
|
1609 |
|
|
SPARE_WORD3 => SPARE_WORD3,
|
1610 |
|
|
SUBSYSTEM_ID => pad_gen(SUBSYSTEM_ID, 16),
|
1611 |
|
|
SUBSYSTEM_VENDOR_ID => pad_gen(SUBSYSTEM_VENDOR_ID, 16),
|
1612 |
|
|
TL_RBYPASS => TL_RBYPASS,
|
1613 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
1614 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
1615 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
|
1616 |
|
|
TL_TFC_DISABLE => TL_TFC_DISABLE,
|
1617 |
|
|
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
|
1618 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
1619 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
1620 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
|
1621 |
|
|
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE,
|
1622 |
|
|
UPSTREAM_FACING => UPSTREAM_FACING,
|
1623 |
|
|
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI,
|
1624 |
|
|
UR_INV_REQ => UR_INV_REQ,
|
1625 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ,
|
1626 |
|
|
VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12),
|
1627 |
|
|
VC_CAP_ID => VC_CAP_ID,
|
1628 |
|
|
VC_CAP_NEXTPTR => pad_gen(VC_CAP_NEXTPTR, 12),
|
1629 |
|
|
VC_CAP_ON => VC_CAP_ON,
|
1630 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
|
1631 |
|
|
VC_CAP_VERSION => VC_CAP_VERSION,
|
1632 |
|
|
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
|
1633 |
|
|
VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13),
|
1634 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
|
1635 |
|
|
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
|
1636 |
|
|
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
|
1637 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
|
1638 |
|
|
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
|
1639 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
1640 |
|
|
VENDOR_ID => pad_gen(VENDOR_ID, 16),
|
1641 |
|
|
VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12),
|
1642 |
|
|
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID,
|
1643 |
|
|
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH,
|
1644 |
|
|
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION,
|
1645 |
|
|
VSEC_CAP_ID => VSEC_CAP_ID,
|
1646 |
|
|
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE,
|
1647 |
|
|
VSEC_CAP_NEXTPTR => pad_gen(VSEC_CAP_NEXTPTR, 12),
|
1648 |
|
|
VSEC_CAP_ON => VSEC_CAP_ON,
|
1649 |
|
|
VSEC_CAP_VERSION => VSEC_CAP_VERSION
|
1650 |
|
|
)
|
1651 |
|
|
port map (
|
1652 |
|
|
PCIEXPRXN => pci_exp_rxn,
|
1653 |
|
|
PCIEXPRXP => pci_exp_rxp,
|
1654 |
|
|
PCIEXPTXN => pci_exp_txn_v6pcie27,
|
1655 |
|
|
PCIEXPTXP => pci_exp_txp_v6pcie28,
|
1656 |
|
|
SYSCLK => sys_clk,
|
1657 |
|
|
TRNLNKUPN => trn_lnk_up_n_int,
|
1658 |
|
|
TRNCLK => trn_clk_v6pcie41,
|
1659 |
|
|
FUNDRSTN => sys_reset_n_d,
|
1660 |
|
|
PHYRDYN => phy_rdy_n,
|
1661 |
|
|
LNKCLKEN => open,
|
1662 |
|
|
USERRSTN => trn_reset_n_int,
|
1663 |
|
|
RECEIVEDFUNCLVLRSTN => rx_func_level_reset_n,
|
1664 |
|
|
SYSRSTN => v6pcie67,
|
1665 |
|
|
PLRSTN => '1',
|
1666 |
|
|
DLRSTN => '1',
|
1667 |
|
|
TLRSTN => '1',
|
1668 |
|
|
FUNCLVLRSTN => func_lvl_rstn,
|
1669 |
|
|
CMRSTN => cm_rstn,
|
1670 |
|
|
CMSTICKYRSTN => '1',
|
1671 |
|
|
|
1672 |
|
|
TRNRBARHITN => trn_rbar_hit_n_v6pcie49,
|
1673 |
|
|
TRNRD => trn_rd_v6pcie50,
|
1674 |
|
|
TRNRECRCERRN => trn_recrc_err_n_v6pcie51,
|
1675 |
|
|
TRNREOFN => trn_reof_n_v6pcie52,
|
1676 |
|
|
TRNRERRFWDN => trn_rerrfwd_n_v6pcie53,
|
1677 |
|
|
TRNRREMN => trn_rrem_n_v6pcie55,
|
1678 |
|
|
TRNRSOFN => trn_rsof_n_v6pcie56,
|
1679 |
|
|
TRNRSRCDSCN => trn_rsrc_dsc_n_v6pcie57,
|
1680 |
|
|
TRNRSRCRDYN => trn_rsrc_rdy_n_v6pcie58,
|
1681 |
|
|
TRNRDSTRDYN => trn_rdst_rdy_n,
|
1682 |
|
|
TRNRNPOKN => trn_rnp_ok_n,
|
1683 |
|
|
|
1684 |
|
|
TRNTBUFAV => trn_tbuf_av_v6pcie59,
|
1685 |
|
|
TRNTCFGREQN => trn_tcfg_req_n_v6pcie60,
|
1686 |
|
|
TRNTDLLPDSTRDYN => open,
|
1687 |
|
|
TRNTDSTRDYN => trn_tdst_rdy_n_v6pcie61,
|
1688 |
|
|
TRNTERRDROPN => trn_terr_drop_n_v6pcie62,
|
1689 |
|
|
TRNTCFGGNTN => trn_tcfg_gnt_n,
|
1690 |
|
|
TRNTD => trn_td,
|
1691 |
|
|
TRNTDLLPDATA => "00000000000000000000000000000000",
|
1692 |
|
|
TRNTDLLPSRCRDYN => '1',
|
1693 |
|
|
TRNTECRCGENN => '1',
|
1694 |
|
|
TRNTEOFN => trn_teof_n,
|
1695 |
|
|
TRNTERRFWDN => trn_terrfwd_n,
|
1696 |
|
|
TRNTREMN => trn_trem_n,
|
1697 |
|
|
TRNTSOFN => trn_tsof_n,
|
1698 |
|
|
TRNTSRCDSCN => trn_tsrc_dsc_n,
|
1699 |
|
|
TRNTSRCRDYN => trn_tsrc_rdy_n,
|
1700 |
|
|
TRNTSTRN => trn_tstr_n,
|
1701 |
|
|
TRNFCCPLD => trn_fc_cpld_v6pcie42,
|
1702 |
|
|
TRNFCCPLH => trn_fc_cplh_v6pcie43,
|
1703 |
|
|
TRNFCNPD => trn_fc_npd_v6pcie44,
|
1704 |
|
|
TRNFCNPH => trn_fc_nph_v6pcie45,
|
1705 |
|
|
TRNFCPD => trn_fc_pd_v6pcie46,
|
1706 |
|
|
TRNFCPH => trn_fc_ph_v6pcie47,
|
1707 |
|
|
TRNFCSEL => trn_fc_sel,
|
1708 |
|
|
CFGAERECRCCHECKEN => open,
|
1709 |
|
|
CFGAERECRCGENEN => open,
|
1710 |
|
|
CFGCOMMANDBUSMASTERENABLE => cfg_cmd_bme,
|
1711 |
|
|
CFGCOMMANDINTERRUPTDISABLE => cfg_cmd_intdis,
|
1712 |
|
|
CFGCOMMANDIOENABLE => cfg_cmd_io_en,
|
1713 |
|
|
CFGCOMMANDMEMENABLE => cfg_cmd_mem_en,
|
1714 |
|
|
CFGCOMMANDSERREN => cfg_cmd_serr_en,
|
1715 |
|
|
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
|
1716 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
|
1717 |
|
|
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_relaxed_order,
|
1718 |
|
|
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
|
1719 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
|
1720 |
|
|
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_maxpayload,
|
1721 |
|
|
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
|
1722 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
|
1723 |
|
|
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_nosnoop_en,
|
1724 |
|
|
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
|
1725 |
|
|
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
|
1726 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpltimeout_dis,
|
1727 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpltimeout_val,
|
1728 |
|
|
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
|
1729 |
|
|
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
|
1730 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
|
1731 |
|
|
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
|
1732 |
|
|
CFGDO => cfg_do,
|
1733 |
|
|
CFGERRAERHEADERLOGSETN => open,
|
1734 |
|
|
CFGERRCPLRDYN => cfg_err_cpl_rdy_n_v6pcie1,
|
1735 |
|
|
CFGINTERRUPTDO => cfg_interrupt_do_v6pcie2,
|
1736 |
|
|
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable_v6pcie3,
|
1737 |
|
|
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable_v6pcie4,
|
1738 |
|
|
CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable_v6pcie5,
|
1739 |
|
|
CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm_v6pcie6,
|
1740 |
|
|
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n_v6pcie7,
|
1741 |
|
|
CFGLINKCONTROLRCB => cfg_link_control_rcb,
|
1742 |
|
|
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
|
1743 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en,
|
1744 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en,
|
1745 |
|
|
CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en,
|
1746 |
|
|
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
|
1747 |
|
|
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
|
1748 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis,
|
1749 |
|
|
CFGLINKCONTROLLINKDISABLE => cfg_link_control_linkdisable,
|
1750 |
|
|
CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link,
|
1751 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_auto_bandwidth_status,
|
1752 |
|
|
CFGLINKSTATUSBANDWITHSTATUS => cfg_link_status_bandwidth_status,
|
1753 |
|
|
CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed,
|
1754 |
|
|
CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active,
|
1755 |
|
|
CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training,
|
1756 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_link_width,
|
1757 |
|
|
CFGMSGDATA => cfg_msg_data_v6pcie8,
|
1758 |
|
|
CFGMSGRECEIVED => cfg_msg_received_v6pcie9,
|
1759 |
|
|
CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_inta_v6pcie10,
|
1760 |
|
|
CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_intb_v6pcie11,
|
1761 |
|
|
CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_intc_v6pcie12,
|
1762 |
|
|
CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_intd_v6pcie13,
|
1763 |
|
|
CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_inta_v6pcie14,
|
1764 |
|
|
CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_intb_v6pcie15,
|
1765 |
|
|
CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_intc_v6pcie16,
|
1766 |
|
|
CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_intd_v6pcie17,
|
1767 |
|
|
CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor_v6pcie18,
|
1768 |
|
|
CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal_v6pcie19,
|
1769 |
|
|
CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal_v6pcie20,
|
1770 |
|
|
CFGMSGRECEIVEDPMASNAK => open,
|
1771 |
|
|
CFGMSGRECEIVEDPMETO => open,
|
1772 |
|
|
CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack_v6pcie21,
|
1773 |
|
|
CFGMSGRECEIVEDPMPME => open,
|
1774 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => open,
|
1775 |
|
|
CFGMSGRECEIVEDUNLOCK => open,
|
1776 |
|
|
CFGPCIELINKSTATE => cfg_pcie_link_state_n_v6pcie22,
|
1777 |
|
|
CFGPMRCVASREQL1N => open,
|
1778 |
|
|
CFGPMRCVENTERL1N => open,
|
1779 |
|
|
CFGPMRCVENTERL23N => open,
|
1780 |
|
|
CFGPMRCVREQACKN => open,
|
1781 |
|
|
CFGPMCSRPMEEN => cfg_pmcsr_pme_en_v6pcie23,
|
1782 |
|
|
CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status_v6pcie24,
|
1783 |
|
|
CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate_v6pcie25,
|
1784 |
|
|
CFGRDWRDONEN => cfg_rd_wr_done_n,
|
1785 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE => open,
|
1786 |
|
|
CFGTRANSACTION => open,
|
1787 |
|
|
CFGTRANSACTIONADDR => open,
|
1788 |
|
|
CFGTRANSACTIONTYPE => open,
|
1789 |
|
|
CFGVCTCVCMAP => open,
|
1790 |
|
|
CFGBYTEENN => cfg_byte_en_n,
|
1791 |
|
|
CFGDI => cfg_di,
|
1792 |
|
|
CFGDSBUSNUMBER => cfg_ds_bus_number,
|
1793 |
|
|
CFGDSDEVICENUMBER => cfg_ds_device_number,
|
1794 |
|
|
CFGDSFUNCTIONNUMBER => "000",
|
1795 |
|
|
CFGDSN => cfg_dsn,
|
1796 |
|
|
CFGDWADDR => cfg_dwaddr,
|
1797 |
|
|
CFGERRACSN => '1',
|
1798 |
|
|
CFGERRAERHEADERLOG => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
1799 |
|
|
CFGERRCORN => cfg_err_cor_n,
|
1800 |
|
|
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
|
1801 |
|
|
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
|
1802 |
|
|
CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
|
1803 |
|
|
CFGERRECRCN => cfg_err_ecrc_n,
|
1804 |
|
|
CFGERRLOCKEDN => cfg_err_locked_n,
|
1805 |
|
|
CFGERRPOSTEDN => cfg_err_posted_n,
|
1806 |
|
|
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
|
1807 |
|
|
CFGERRURN => cfg_err_ur_n,
|
1808 |
|
|
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
|
1809 |
|
|
CFGINTERRUPTDI => cfg_interrupt_di,
|
1810 |
|
|
CFGINTERRUPTN => cfg_interrupt_n,
|
1811 |
|
|
CFGPMDIRECTASPML1N => '1',
|
1812 |
|
|
CFGPMSENDPMACKN => '1',
|
1813 |
|
|
CFGPMSENDPMETON => cfg_pm_send_pme_to_n,
|
1814 |
|
|
CFGPMSENDPMNAKN => '1',
|
1815 |
|
|
CFGPMTURNOFFOKN => '1',
|
1816 |
|
|
CFGPMWAKEN => '1',
|
1817 |
|
|
CFGPORTNUMBER => "00000000",
|
1818 |
|
|
CFGRDENN => cfg_rd_en_n,
|
1819 |
|
|
CFGTRNPENDINGN => cfg_trn_pending_n,
|
1820 |
|
|
CFGWRENN => cfg_wr_en_n,
|
1821 |
|
|
CFGWRREADONLYN => '1',
|
1822 |
|
|
CFGWRRW1CASRWN => '1',
|
1823 |
|
|
PLINITIALLINKWIDTH => pl_initial_link_width_v6pcie32,
|
1824 |
|
|
PLLANEREVERSALMODE => pl_lane_reversal_mode_v6pcie33,
|
1825 |
|
|
PLLINKGEN2CAP => pl_link_gen2_capable_v6pcie34,
|
1826 |
|
|
PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported_v6pcie35,
|
1827 |
|
|
PLLINKUPCFGCAP => pl_link_upcfg_capable_v6pcie36,
|
1828 |
|
|
PLLTSSMSTATE => pl_ltssm_state_v6pcie37,
|
1829 |
|
|
PLPHYLNKUPN => pl_phy_lnk_up_n,
|
1830 |
|
|
PLRECEIVEDHOTRST => open,
|
1831 |
|
|
PLRXPMSTATE => open,
|
1832 |
|
|
PLSELLNKRATE => pl_sel_link_rate_v6pcie39,
|
1833 |
|
|
PLSELLNKWIDTH => pl_sel_link_width_v6pcie40,
|
1834 |
|
|
PLTXPMSTATE => open,
|
1835 |
|
|
PLDIRECTEDLINKAUTON => pl_directed_link_auton,
|
1836 |
|
|
PLDIRECTEDLINKCHANGE => v6pcie68,
|
1837 |
|
|
PLDIRECTEDLINKSPEED => v6pcie69,
|
1838 |
|
|
PLDIRECTEDLINKWIDTH => pl_directed_link_width,
|
1839 |
|
|
PLDOWNSTREAMDEEMPHSOURCE => '1',
|
1840 |
|
|
PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
|
1841 |
|
|
PLTRANSMITHOTRST => pl_transmit_hot_rst,
|
1842 |
|
|
DBGSCLRA => open,
|
1843 |
|
|
DBGSCLRB => open,
|
1844 |
|
|
DBGSCLRC => open,
|
1845 |
|
|
DBGSCLRD => open,
|
1846 |
|
|
DBGSCLRE => open,
|
1847 |
|
|
DBGSCLRF => open,
|
1848 |
|
|
DBGSCLRG => open,
|
1849 |
|
|
DBGSCLRH => open,
|
1850 |
|
|
DBGSCLRI => open,
|
1851 |
|
|
DBGSCLRJ => open,
|
1852 |
|
|
DBGSCLRK => open,
|
1853 |
|
|
DBGVECA => open,
|
1854 |
|
|
DBGVECB => open,
|
1855 |
|
|
DBGVECC => open,
|
1856 |
|
|
PLDBGVEC => open,
|
1857 |
|
|
DBGMODE => "00",
|
1858 |
|
|
DBGSUBMODE => '0',
|
1859 |
|
|
PLDBGMODE => "000",
|
1860 |
|
|
|
1861 |
|
|
PCIEDRPDO => pcie_drp_do_v6pcie29,
|
1862 |
|
|
PCIEDRPDRDY => pcie_drp_drdy_v6pcie30,
|
1863 |
|
|
PCIEDRPCLK => pcie_drp_clk,
|
1864 |
|
|
PCIEDRPDADDR => pcie_drp_daddr,
|
1865 |
|
|
PCIEDRPDEN => pcie_drp_den,
|
1866 |
|
|
PCIEDRPDI => pcie_drp_di,
|
1867 |
|
|
PCIEDRPDWE => pcie_drp_dwe,
|
1868 |
|
|
|
1869 |
|
|
GTPLLLOCK => gt_pll_lock,
|
1870 |
|
|
PIPECLK => pipe_clk,
|
1871 |
|
|
USERCLK => user_clk,
|
1872 |
|
|
DRPCLK => drp_clk,
|
1873 |
|
|
CLOCKLOCKED => clock_locked,
|
1874 |
|
|
TxOutClk => TxOutClk );
|
1875 |
|
|
|
1876 |
|
|
|
1877 |
|
|
end v6_pcie;
|