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-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: O.76xd
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-- \ \ Application: netgen
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-- / / Filename: v6_afifo_8x8.vhd
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-- /___/ /\ Timestamp: Mon Mar 26 15:32:20 2012
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-- \ \ / \
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-- \___\/\___\
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--
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-- Command : -w -sim -ofmt vhdl "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_afifo_8x8.ngc" "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_afifo_8x8.vhd"
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-- Device : 6vlx240tff1156-1
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-- Input file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_afifo_8x8.ngc
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-- Output file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_afifo_8x8.vhd
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-- # of Entities : 1
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-- Design Name : v6_afifo_8x8
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-- Xilinx : C:\Programmi\Xilinx\13.3\ISE_DS\ISE\
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--
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-- Purpose:
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-- This VHDL netlist is a verification model and uses simulation
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-- primitives which may not represent the true implementation of the
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-- device, however the netlist is functionally correct and should not
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-- be modified. This file cannot be synthesized and should only be used
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-- with supported simulation tools.
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--
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-- Reference:
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-- Command Line Tools User Guide, Chapter 23
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-- Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity v6_afifo_8x8 is
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port (
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rst : in STD_LOGIC := 'X';
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wr_clk : in STD_LOGIC := 'X';
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rd_clk : in STD_LOGIC := 'X';
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wr_en : in STD_LOGIC := 'X';
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rd_en : in STD_LOGIC := 'X';
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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din : in STD_LOGIC_VECTOR ( 7 downto 0 );
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dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
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);
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end v6_afifo_8x8;
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architecture STRUCTURE of v6_afifo_8x8 is
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signal N1 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_11 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_15 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_16 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_28 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_29 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_60 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_31_o_MUX_16_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_65 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_67 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_68 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_69 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_70 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_71 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_1_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_2_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_3_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_1_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_2_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_3_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_5_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_4_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_12_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_11_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_12_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_11_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_10_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_3_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_2_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_1_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_6_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_13_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o1_124 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o2_125 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o3_126 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o1 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o11_128 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o12_129 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_130 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1_cepot : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0_dpot_132 : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM22_SPO_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM21_SPO_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2 : STD_LOGIC_VECTOR ( 3 downto 1 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 1 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 7 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count : STD_LOGIC_VECTOR ( 3 downto 1 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016 : STD_LOGIC_VECTOR ( 7 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last : STD_LOGIC_VECTOR ( 3 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg : STD_LOGIC_VECTOR ( 3 downto 0 );
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begin
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dout(7) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7);
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dout(6) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6);
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dout(5) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5);
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dout(4) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4);
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dout(3) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3);
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dout(2) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2);
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dout(1) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1);
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dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
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full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_11;
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empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_16;
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XST_GND : GND
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port map (
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G => N1
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);
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U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i : FDP
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generic map(
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INIT => '1'
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)
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port map (
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C => rd_clk,
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D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o,
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PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
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Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_16
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);
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U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i : FDP
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|
|
generic map(
|
156 |
|
|
INIT => '1'
|
157 |
|
|
)
|
158 |
|
|
port map (
|
159 |
|
|
C => rd_clk,
|
160 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o,
|
161 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
162 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_15
|
163 |
|
|
);
|
164 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i : FDP
|
165 |
|
|
generic map(
|
166 |
|
|
INIT => '1'
|
167 |
|
|
)
|
168 |
|
|
port map (
|
169 |
|
|
C => wr_clk,
|
170 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_31_o_MUX_16_o,
|
171 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_28,
|
172 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_11
|
173 |
|
|
);
|
174 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i : FDP
|
175 |
|
|
generic map(
|
176 |
|
|
INIT => '1'
|
177 |
|
|
)
|
178 |
|
|
port map (
|
179 |
|
|
C => wr_clk,
|
180 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_31_o_MUX_16_o,
|
181 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_28,
|
182 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_60
|
183 |
|
|
);
|
184 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
|
185 |
|
|
generic map(
|
186 |
|
|
INIT => '0'
|
187 |
|
|
)
|
188 |
|
|
port map (
|
189 |
|
|
C => wr_clk,
|
190 |
|
|
CLR => rst,
|
191 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_70,
|
192 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_29
|
193 |
|
|
);
|
194 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
|
195 |
|
|
generic map(
|
196 |
|
|
INIT => '0'
|
197 |
|
|
)
|
198 |
|
|
port map (
|
199 |
|
|
C => rd_clk,
|
200 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66,
|
201 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_65
|
202 |
|
|
);
|
203 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
|
204 |
|
|
generic map(
|
205 |
|
|
INIT => '0'
|
206 |
|
|
)
|
207 |
|
|
port map (
|
208 |
|
|
C => wr_clk,
|
209 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_69,
|
210 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_68
|
211 |
|
|
);
|
212 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3 : FDP
|
213 |
|
|
generic map(
|
214 |
|
|
INIT => '1'
|
215 |
|
|
)
|
216 |
|
|
port map (
|
217 |
|
|
C => wr_clk,
|
218 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_28,
|
219 |
|
|
PRE => rst,
|
220 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_70
|
221 |
|
|
);
|
222 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
|
223 |
|
|
generic map(
|
224 |
|
|
INIT => '0'
|
225 |
|
|
)
|
226 |
|
|
port map (
|
227 |
|
|
C => rd_clk,
|
228 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
|
229 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66
|
230 |
|
|
);
|
231 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
|
232 |
|
|
generic map(
|
233 |
|
|
INIT => '0'
|
234 |
|
|
)
|
235 |
|
|
port map (
|
236 |
|
|
C => wr_clk,
|
237 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_67,
|
238 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_69
|
239 |
|
|
);
|
240 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2 : FDP
|
241 |
|
|
generic map(
|
242 |
|
|
INIT => '1'
|
243 |
|
|
)
|
244 |
|
|
port map (
|
245 |
|
|
C => wr_clk,
|
246 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_71,
|
247 |
|
|
PRE => rst,
|
248 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_28
|
249 |
|
|
);
|
250 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP
|
251 |
|
|
generic map(
|
252 |
|
|
INIT => '1'
|
253 |
|
|
)
|
254 |
|
|
port map (
|
255 |
|
|
C => rd_clk,
|
256 |
|
|
D => N1,
|
257 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
258 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2)
|
259 |
|
|
);
|
260 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_1 : FDP
|
261 |
|
|
generic map(
|
262 |
|
|
INIT => '1'
|
263 |
|
|
)
|
264 |
|
|
port map (
|
265 |
|
|
C => rd_clk,
|
266 |
|
|
D => N1,
|
267 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
268 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1)
|
269 |
|
|
);
|
270 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP
|
271 |
|
|
generic map(
|
272 |
|
|
INIT => '1'
|
273 |
|
|
)
|
274 |
|
|
port map (
|
275 |
|
|
C => rd_clk,
|
276 |
|
|
D => N1,
|
277 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
278 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0)
|
279 |
|
|
);
|
280 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
|
281 |
|
|
port map (
|
282 |
|
|
C => rd_clk,
|
283 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66,
|
284 |
|
|
D => N1,
|
285 |
|
|
PRE => rst,
|
286 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64
|
287 |
|
|
);
|
288 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP
|
289 |
|
|
generic map(
|
290 |
|
|
INIT => '1'
|
291 |
|
|
)
|
292 |
|
|
port map (
|
293 |
|
|
C => wr_clk,
|
294 |
|
|
D => N1,
|
295 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
|
296 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1)
|
297 |
|
|
);
|
298 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_0 : FDP
|
299 |
|
|
generic map(
|
300 |
|
|
INIT => '1'
|
301 |
|
|
)
|
302 |
|
|
port map (
|
303 |
|
|
C => wr_clk,
|
304 |
|
|
D => N1,
|
305 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
|
306 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0)
|
307 |
|
|
);
|
308 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1 : FDP
|
309 |
|
|
generic map(
|
310 |
|
|
INIT => '1'
|
311 |
|
|
)
|
312 |
|
|
port map (
|
313 |
|
|
C => wr_clk,
|
314 |
|
|
D => N1,
|
315 |
|
|
PRE => rst,
|
316 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_71
|
317 |
|
|
);
|
318 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM22 : RAM32X1D
|
319 |
|
|
generic map(
|
320 |
|
|
INIT => X"00000000"
|
321 |
|
|
)
|
322 |
|
|
port map (
|
323 |
|
|
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
324 |
|
|
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1),
|
325 |
|
|
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
326 |
|
|
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
327 |
|
|
A4 => N1,
|
328 |
|
|
D => din(7),
|
329 |
|
|
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
330 |
|
|
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
331 |
|
|
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
332 |
|
|
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
333 |
|
|
DPRA4 => N1,
|
334 |
|
|
WCLK => wr_clk,
|
335 |
|
|
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
336 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM22_SPO_UNCONNECTED,
|
337 |
|
|
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(7)
|
338 |
|
|
);
|
339 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM21 : RAM32X1D
|
340 |
|
|
generic map(
|
341 |
|
|
INIT => X"00000000"
|
342 |
|
|
)
|
343 |
|
|
port map (
|
344 |
|
|
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
345 |
|
|
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1),
|
346 |
|
|
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
347 |
|
|
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
348 |
|
|
A4 => N1,
|
349 |
|
|
D => din(6),
|
350 |
|
|
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
351 |
|
|
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
352 |
|
|
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
353 |
|
|
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
354 |
|
|
DPRA4 => N1,
|
355 |
|
|
WCLK => wr_clk,
|
356 |
|
|
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
357 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM21_SPO_UNCONNECTED,
|
358 |
|
|
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(6)
|
359 |
|
|
);
|
360 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM32M
|
361 |
|
|
generic map(
|
362 |
|
|
INIT_A => X"0000000000000000",
|
363 |
|
|
INIT_B => X"0000000000000000",
|
364 |
|
|
INIT_C => X"0000000000000000",
|
365 |
|
|
INIT_D => X"0000000000000000"
|
366 |
|
|
)
|
367 |
|
|
port map (
|
368 |
|
|
WCLK => wr_clk,
|
369 |
|
|
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
370 |
|
|
DIA(1) => din(1),
|
371 |
|
|
DIA(0) => din(0),
|
372 |
|
|
DIB(1) => din(3),
|
373 |
|
|
DIB(0) => din(2),
|
374 |
|
|
DIC(1) => din(5),
|
375 |
|
|
DIC(0) => din(4),
|
376 |
|
|
DID(1) => N1,
|
377 |
|
|
DID(0) => N1,
|
378 |
|
|
ADDRA(4) => N1,
|
379 |
|
|
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
380 |
|
|
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
381 |
|
|
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
382 |
|
|
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
383 |
|
|
ADDRB(4) => N1,
|
384 |
|
|
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
385 |
|
|
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
386 |
|
|
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
387 |
|
|
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
388 |
|
|
ADDRC(4) => N1,
|
389 |
|
|
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
390 |
|
|
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
391 |
|
|
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
392 |
|
|
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
393 |
|
|
ADDRD(4) => N1,
|
394 |
|
|
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
395 |
|
|
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
396 |
|
|
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1),
|
397 |
|
|
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
398 |
|
|
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(1),
|
399 |
|
|
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(0),
|
400 |
|
|
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(3),
|
401 |
|
|
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(2),
|
402 |
|
|
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(5),
|
403 |
|
|
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(4),
|
404 |
|
|
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED,
|
405 |
|
|
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED
|
406 |
|
|
);
|
407 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_7 : FDCE
|
408 |
|
|
generic map(
|
409 |
|
|
INIT => '0'
|
410 |
|
|
)
|
411 |
|
|
port map (
|
412 |
|
|
C => rd_clk,
|
413 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
414 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
415 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(7),
|
416 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7)
|
417 |
|
|
);
|
418 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_6 : FDCE
|
419 |
|
|
generic map(
|
420 |
|
|
INIT => '0'
|
421 |
|
|
)
|
422 |
|
|
port map (
|
423 |
|
|
C => rd_clk,
|
424 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
425 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
426 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(6),
|
427 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6)
|
428 |
|
|
);
|
429 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_5 : FDCE
|
430 |
|
|
generic map(
|
431 |
|
|
INIT => '0'
|
432 |
|
|
)
|
433 |
|
|
port map (
|
434 |
|
|
C => rd_clk,
|
435 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
436 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
437 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(5),
|
438 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5)
|
439 |
|
|
);
|
440 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_4 : FDCE
|
441 |
|
|
generic map(
|
442 |
|
|
INIT => '0'
|
443 |
|
|
)
|
444 |
|
|
port map (
|
445 |
|
|
C => rd_clk,
|
446 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
447 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
448 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(4),
|
449 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4)
|
450 |
|
|
);
|
451 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_3 : FDCE
|
452 |
|
|
generic map(
|
453 |
|
|
INIT => '0'
|
454 |
|
|
)
|
455 |
|
|
port map (
|
456 |
|
|
C => rd_clk,
|
457 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
458 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
459 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(3),
|
460 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3)
|
461 |
|
|
);
|
462 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_2 : FDCE
|
463 |
|
|
generic map(
|
464 |
|
|
INIT => '0'
|
465 |
|
|
)
|
466 |
|
|
port map (
|
467 |
|
|
C => rd_clk,
|
468 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
469 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
470 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(2),
|
471 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2)
|
472 |
|
|
);
|
473 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_1 : FDCE
|
474 |
|
|
generic map(
|
475 |
|
|
INIT => '0'
|
476 |
|
|
)
|
477 |
|
|
port map (
|
478 |
|
|
C => rd_clk,
|
479 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
480 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
481 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(1),
|
482 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1)
|
483 |
|
|
);
|
484 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
|
485 |
|
|
generic map(
|
486 |
|
|
INIT => '0'
|
487 |
|
|
)
|
488 |
|
|
port map (
|
489 |
|
|
C => rd_clk,
|
490 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
491 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
492 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0016(0),
|
493 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
|
494 |
|
|
);
|
495 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE
|
496 |
|
|
generic map(
|
497 |
|
|
INIT => '0'
|
498 |
|
|
)
|
499 |
|
|
port map (
|
500 |
|
|
C => rd_clk,
|
501 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
502 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
503 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
504 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3)
|
505 |
|
|
);
|
506 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE
|
507 |
|
|
generic map(
|
508 |
|
|
INIT => '0'
|
509 |
|
|
)
|
510 |
|
|
port map (
|
511 |
|
|
C => rd_clk,
|
512 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
513 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
514 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
515 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2)
|
516 |
|
|
);
|
517 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE
|
518 |
|
|
generic map(
|
519 |
|
|
INIT => '0'
|
520 |
|
|
)
|
521 |
|
|
port map (
|
522 |
|
|
C => rd_clk,
|
523 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
524 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
525 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
526 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1)
|
527 |
|
|
);
|
528 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE
|
529 |
|
|
generic map(
|
530 |
|
|
INIT => '0'
|
531 |
|
|
)
|
532 |
|
|
port map (
|
533 |
|
|
C => rd_clk,
|
534 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
535 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
536 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_3_Q,
|
537 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3)
|
538 |
|
|
);
|
539 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE
|
540 |
|
|
generic map(
|
541 |
|
|
INIT => '0'
|
542 |
|
|
)
|
543 |
|
|
port map (
|
544 |
|
|
C => rd_clk,
|
545 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
546 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
547 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_2_Q,
|
548 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2)
|
549 |
|
|
);
|
550 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE
|
551 |
|
|
generic map(
|
552 |
|
|
INIT => '0'
|
553 |
|
|
)
|
554 |
|
|
port map (
|
555 |
|
|
C => rd_clk,
|
556 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
557 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
558 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_1_Q,
|
559 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1)
|
560 |
|
|
);
|
561 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_0 : FDPE
|
562 |
|
|
generic map(
|
563 |
|
|
INIT => '1'
|
564 |
|
|
)
|
565 |
|
|
port map (
|
566 |
|
|
C => rd_clk,
|
567 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
568 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
569 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
570 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0)
|
571 |
|
|
);
|
572 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_3 : FDCE
|
573 |
|
|
generic map(
|
574 |
|
|
INIT => '0'
|
575 |
|
|
)
|
576 |
|
|
port map (
|
577 |
|
|
C => wr_clk,
|
578 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
579 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
580 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
581 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3)
|
582 |
|
|
);
|
583 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_2 : FDCE
|
584 |
|
|
generic map(
|
585 |
|
|
INIT => '0'
|
586 |
|
|
)
|
587 |
|
|
port map (
|
588 |
|
|
C => wr_clk,
|
589 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
590 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
591 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
592 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2)
|
593 |
|
|
);
|
594 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_1 : FDCE
|
595 |
|
|
generic map(
|
596 |
|
|
INIT => '0'
|
597 |
|
|
)
|
598 |
|
|
port map (
|
599 |
|
|
C => wr_clk,
|
600 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
601 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
602 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1),
|
603 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1)
|
604 |
|
|
);
|
605 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_3 : FDCE
|
606 |
|
|
generic map(
|
607 |
|
|
INIT => '0'
|
608 |
|
|
)
|
609 |
|
|
port map (
|
610 |
|
|
C => wr_clk,
|
611 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
612 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
613 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
614 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3)
|
615 |
|
|
);
|
616 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_2 : FDCE
|
617 |
|
|
generic map(
|
618 |
|
|
INIT => '0'
|
619 |
|
|
)
|
620 |
|
|
port map (
|
621 |
|
|
C => wr_clk,
|
622 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
623 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
624 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
625 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2)
|
626 |
|
|
);
|
627 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_1 : FDCE
|
628 |
|
|
generic map(
|
629 |
|
|
INIT => '0'
|
630 |
|
|
)
|
631 |
|
|
port map (
|
632 |
|
|
C => wr_clk,
|
633 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
634 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
635 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
636 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1)
|
637 |
|
|
);
|
638 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0 : FDPE
|
639 |
|
|
generic map(
|
640 |
|
|
INIT => '1'
|
641 |
|
|
)
|
642 |
|
|
port map (
|
643 |
|
|
C => wr_clk,
|
644 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1_cepot,
|
645 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0_dpot_132,
|
646 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
647 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0)
|
648 |
|
|
);
|
649 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3 : FDCE
|
650 |
|
|
generic map(
|
651 |
|
|
INIT => '0'
|
652 |
|
|
)
|
653 |
|
|
port map (
|
654 |
|
|
C => wr_clk,
|
655 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
656 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
657 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_3_Q,
|
658 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3)
|
659 |
|
|
);
|
660 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_2 : FDCE
|
661 |
|
|
generic map(
|
662 |
|
|
INIT => '0'
|
663 |
|
|
)
|
664 |
|
|
port map (
|
665 |
|
|
C => wr_clk,
|
666 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
667 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
668 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_2_Q,
|
669 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2)
|
670 |
|
|
);
|
671 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_1 : FDPE
|
672 |
|
|
generic map(
|
673 |
|
|
INIT => '1'
|
674 |
|
|
)
|
675 |
|
|
port map (
|
676 |
|
|
C => wr_clk,
|
677 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
678 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_1_Q,
|
679 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
680 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1)
|
681 |
|
|
);
|
682 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_3 : FDC
|
683 |
|
|
generic map(
|
684 |
|
|
INIT => '0'
|
685 |
|
|
)
|
686 |
|
|
port map (
|
687 |
|
|
C => rd_clk,
|
688 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
689 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
690 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3)
|
691 |
|
|
);
|
692 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_2 : FDC
|
693 |
|
|
generic map(
|
694 |
|
|
INIT => '0'
|
695 |
|
|
)
|
696 |
|
|
port map (
|
697 |
|
|
C => rd_clk,
|
698 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
699 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_4_o,
|
700 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2)
|
701 |
|
|
);
|
702 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_1 : FDC
|
703 |
|
|
generic map(
|
704 |
|
|
INIT => '0'
|
705 |
|
|
)
|
706 |
|
|
port map (
|
707 |
|
|
C => rd_clk,
|
708 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
709 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_5_o,
|
710 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1)
|
711 |
|
|
);
|
712 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_0 : FDC
|
713 |
|
|
generic map(
|
714 |
|
|
INIT => '0'
|
715 |
|
|
)
|
716 |
|
|
port map (
|
717 |
|
|
C => rd_clk,
|
718 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
719 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_6_o,
|
720 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0)
|
721 |
|
|
);
|
722 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_3 : FDC
|
723 |
|
|
generic map(
|
724 |
|
|
INIT => '0'
|
725 |
|
|
)
|
726 |
|
|
port map (
|
727 |
|
|
C => wr_clk,
|
728 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
729 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
730 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3)
|
731 |
|
|
);
|
732 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_2 : FDC
|
733 |
|
|
generic map(
|
734 |
|
|
INIT => '0'
|
735 |
|
|
)
|
736 |
|
|
port map (
|
737 |
|
|
C => wr_clk,
|
738 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
739 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_11_o,
|
740 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2)
|
741 |
|
|
);
|
742 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_1 : FDC
|
743 |
|
|
generic map(
|
744 |
|
|
INIT => '0'
|
745 |
|
|
)
|
746 |
|
|
port map (
|
747 |
|
|
C => wr_clk,
|
748 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
749 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_12_o,
|
750 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1)
|
751 |
|
|
);
|
752 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_0 : FDC
|
753 |
|
|
generic map(
|
754 |
|
|
INIT => '0'
|
755 |
|
|
)
|
756 |
|
|
port map (
|
757 |
|
|
C => wr_clk,
|
758 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
759 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_13_o,
|
760 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0)
|
761 |
|
|
);
|
762 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3 : FDC
|
763 |
|
|
generic map(
|
764 |
|
|
INIT => '0'
|
765 |
|
|
)
|
766 |
|
|
port map (
|
767 |
|
|
C => rd_clk,
|
768 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
769 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(3),
|
770 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3)
|
771 |
|
|
);
|
772 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_2 : FDC
|
773 |
|
|
generic map(
|
774 |
|
|
INIT => '0'
|
775 |
|
|
)
|
776 |
|
|
port map (
|
777 |
|
|
C => rd_clk,
|
778 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
779 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(2),
|
780 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2)
|
781 |
|
|
);
|
782 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_1 : FDC
|
783 |
|
|
generic map(
|
784 |
|
|
INIT => '0'
|
785 |
|
|
)
|
786 |
|
|
port map (
|
787 |
|
|
C => rd_clk,
|
788 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
789 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(1),
|
790 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1)
|
791 |
|
|
);
|
792 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_0 : FDC
|
793 |
|
|
generic map(
|
794 |
|
|
INIT => '0'
|
795 |
|
|
)
|
796 |
|
|
port map (
|
797 |
|
|
C => rd_clk,
|
798 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
799 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(0),
|
800 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(0)
|
801 |
|
|
);
|
802 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3 : FDC
|
803 |
|
|
generic map(
|
804 |
|
|
INIT => '0'
|
805 |
|
|
)
|
806 |
|
|
port map (
|
807 |
|
|
C => wr_clk,
|
808 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
809 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(3),
|
810 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3)
|
811 |
|
|
);
|
812 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_2 : FDC
|
813 |
|
|
generic map(
|
814 |
|
|
INIT => '0'
|
815 |
|
|
)
|
816 |
|
|
port map (
|
817 |
|
|
C => wr_clk,
|
818 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
819 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(2),
|
820 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2)
|
821 |
|
|
);
|
822 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_1 : FDC
|
823 |
|
|
generic map(
|
824 |
|
|
INIT => '0'
|
825 |
|
|
)
|
826 |
|
|
port map (
|
827 |
|
|
C => wr_clk,
|
828 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
829 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(1),
|
830 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1)
|
831 |
|
|
);
|
832 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_0 : FDC
|
833 |
|
|
generic map(
|
834 |
|
|
INIT => '0'
|
835 |
|
|
)
|
836 |
|
|
port map (
|
837 |
|
|
C => wr_clk,
|
838 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
839 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(0),
|
840 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(0)
|
841 |
|
|
);
|
842 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_3 : FDC
|
843 |
|
|
generic map(
|
844 |
|
|
INIT => '0'
|
845 |
|
|
)
|
846 |
|
|
port map (
|
847 |
|
|
C => rd_clk,
|
848 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
849 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(3),
|
850 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(3)
|
851 |
|
|
);
|
852 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_2 : FDC
|
853 |
|
|
generic map(
|
854 |
|
|
INIT => '0'
|
855 |
|
|
)
|
856 |
|
|
port map (
|
857 |
|
|
C => rd_clk,
|
858 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
859 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(2),
|
860 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(2)
|
861 |
|
|
);
|
862 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_1 : FDC
|
863 |
|
|
generic map(
|
864 |
|
|
INIT => '0'
|
865 |
|
|
)
|
866 |
|
|
port map (
|
867 |
|
|
C => rd_clk,
|
868 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
869 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(1),
|
870 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(1)
|
871 |
|
|
);
|
872 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_0 : FDC
|
873 |
|
|
generic map(
|
874 |
|
|
INIT => '0'
|
875 |
|
|
)
|
876 |
|
|
port map (
|
877 |
|
|
C => rd_clk,
|
878 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
879 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(0),
|
880 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(0)
|
881 |
|
|
);
|
882 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_3 : FDC
|
883 |
|
|
generic map(
|
884 |
|
|
INIT => '0'
|
885 |
|
|
)
|
886 |
|
|
port map (
|
887 |
|
|
C => wr_clk,
|
888 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
889 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(3),
|
890 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(3)
|
891 |
|
|
);
|
892 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_2 : FDC
|
893 |
|
|
generic map(
|
894 |
|
|
INIT => '0'
|
895 |
|
|
)
|
896 |
|
|
port map (
|
897 |
|
|
C => wr_clk,
|
898 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
899 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(2),
|
900 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(2)
|
901 |
|
|
);
|
902 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_1 : FDC
|
903 |
|
|
generic map(
|
904 |
|
|
INIT => '0'
|
905 |
|
|
)
|
906 |
|
|
port map (
|
907 |
|
|
C => wr_clk,
|
908 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
909 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(1),
|
910 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(1)
|
911 |
|
|
);
|
912 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_0 : FDC
|
913 |
|
|
generic map(
|
914 |
|
|
INIT => '0'
|
915 |
|
|
)
|
916 |
|
|
port map (
|
917 |
|
|
C => wr_clk,
|
918 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
919 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(0),
|
920 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(0)
|
921 |
|
|
);
|
922 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_3 : FDC
|
923 |
|
|
generic map(
|
924 |
|
|
INIT => '0'
|
925 |
|
|
)
|
926 |
|
|
port map (
|
927 |
|
|
C => rd_clk,
|
928 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
929 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
930 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(3)
|
931 |
|
|
);
|
932 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_2 : FDC
|
933 |
|
|
generic map(
|
934 |
|
|
INIT => '0'
|
935 |
|
|
)
|
936 |
|
|
port map (
|
937 |
|
|
C => rd_clk,
|
938 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
939 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_10_o,
|
940 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(2)
|
941 |
|
|
);
|
942 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_1 : FDC
|
943 |
|
|
generic map(
|
944 |
|
|
INIT => '0'
|
945 |
|
|
)
|
946 |
|
|
port map (
|
947 |
|
|
C => rd_clk,
|
948 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
949 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_11_o,
|
950 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(1)
|
951 |
|
|
);
|
952 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_0 : FDC
|
953 |
|
|
generic map(
|
954 |
|
|
INIT => '0'
|
955 |
|
|
)
|
956 |
|
|
port map (
|
957 |
|
|
C => rd_clk,
|
958 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
959 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_12_o,
|
960 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(0)
|
961 |
|
|
);
|
962 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_3 : FDC
|
963 |
|
|
generic map(
|
964 |
|
|
INIT => '0'
|
965 |
|
|
)
|
966 |
|
|
port map (
|
967 |
|
|
C => wr_clk,
|
968 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
969 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
970 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(3)
|
971 |
|
|
);
|
972 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_2 : FDC
|
973 |
|
|
generic map(
|
974 |
|
|
INIT => '0'
|
975 |
|
|
)
|
976 |
|
|
port map (
|
977 |
|
|
C => wr_clk,
|
978 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
979 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_1_o,
|
980 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(2)
|
981 |
|
|
);
|
982 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_1 : FDC
|
983 |
|
|
generic map(
|
984 |
|
|
INIT => '0'
|
985 |
|
|
)
|
986 |
|
|
port map (
|
987 |
|
|
C => wr_clk,
|
988 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
989 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_2_o,
|
990 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(1)
|
991 |
|
|
);
|
992 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_0 : FDC
|
993 |
|
|
generic map(
|
994 |
|
|
INIT => '0'
|
995 |
|
|
)
|
996 |
|
|
port map (
|
997 |
|
|
C => wr_clk,
|
998 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
999 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_3_o,
|
1000 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(0)
|
1001 |
|
|
);
|
1002 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
|
1003 |
|
|
generic map(
|
1004 |
|
|
INIT => X"2"
|
1005 |
|
|
)
|
1006 |
|
|
port map (
|
1007 |
|
|
I0 => rd_en,
|
1008 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_15,
|
1009 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
|
1010 |
|
|
);
|
1011 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
|
1012 |
|
|
generic map(
|
1013 |
|
|
INIT => X"2"
|
1014 |
|
|
)
|
1015 |
|
|
port map (
|
1016 |
|
|
I0 => wr_en,
|
1017 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_60,
|
1018 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
|
1019 |
|
|
);
|
1020 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
|
1021 |
|
|
generic map(
|
1022 |
|
|
INIT => X"2"
|
1023 |
|
|
)
|
1024 |
|
|
port map (
|
1025 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
|
1026 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_65,
|
1027 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
|
1028 |
|
|
);
|
1029 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
|
1030 |
|
|
generic map(
|
1031 |
|
|
INIT => X"2"
|
1032 |
|
|
)
|
1033 |
|
|
port map (
|
1034 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_67,
|
1035 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_68,
|
1036 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
|
1037 |
|
|
);
|
1038 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_3_GND_22_o_mux_2_OUT41 : LUT4
|
1039 |
|
|
generic map(
|
1040 |
|
|
INIT => X"6AAA"
|
1041 |
|
|
)
|
1042 |
|
|
port map (
|
1043 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
1044 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1045 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
1046 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
1047 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_3_Q
|
1048 |
|
|
);
|
1049 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_3_GND_22_o_mux_2_OUT21 : LUT2
|
1050 |
|
|
generic map(
|
1051 |
|
|
INIT => X"6"
|
1052 |
|
|
)
|
1053 |
|
|
port map (
|
1054 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1055 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
1056 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_1_Q
|
1057 |
|
|
);
|
1058 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_3_GND_22_o_mux_2_OUT31 : LUT3
|
1059 |
|
|
generic map(
|
1060 |
|
|
INIT => X"6A"
|
1061 |
|
|
)
|
1062 |
|
|
port map (
|
1063 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
1064 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1065 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
1066 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_22_o_mux_2_OUT_2_Q
|
1067 |
|
|
);
|
1068 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_11_o1 : LUT2
|
1069 |
|
|
generic map(
|
1070 |
|
|
INIT => X"6"
|
1071 |
|
|
)
|
1072 |
|
|
port map (
|
1073 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
1074 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
1075 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_11_o
|
1076 |
|
|
);
|
1077 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_12_o1 : LUT3
|
1078 |
|
|
generic map(
|
1079 |
|
|
INIT => X"96"
|
1080 |
|
|
)
|
1081 |
|
|
port map (
|
1082 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
1083 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
1084 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1),
|
1085 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_12_o
|
1086 |
|
|
);
|
1087 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_4_o1 : LUT2
|
1088 |
|
|
generic map(
|
1089 |
|
|
INIT => X"6"
|
1090 |
|
|
)
|
1091 |
|
|
port map (
|
1092 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
1093 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
1094 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_4_o
|
1095 |
|
|
);
|
1096 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_5_o1 : LUT3
|
1097 |
|
|
generic map(
|
1098 |
|
|
INIT => X"96"
|
1099 |
|
|
)
|
1100 |
|
|
port map (
|
1101 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1),
|
1102 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
1103 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
1104 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_5_o
|
1105 |
|
|
);
|
1106 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_2_WR_PNTR_3_XOR_1_o_xo_0_1 : LUT2
|
1107 |
|
|
generic map(
|
1108 |
|
|
INIT => X"6"
|
1109 |
|
|
)
|
1110 |
|
|
port map (
|
1111 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
1112 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
1113 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_1_o
|
1114 |
|
|
);
|
1115 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_2_RD_PNTR_3_XOR_10_o_xo_0_1 : LUT2
|
1116 |
|
|
generic map(
|
1117 |
|
|
INIT => X"6"
|
1118 |
|
|
)
|
1119 |
|
|
port map (
|
1120 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
1121 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
1122 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_10_o
|
1123 |
|
|
);
|
1124 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_1_WR_PNTR_2_XOR_2_o_xo_0_1 : LUT2
|
1125 |
|
|
generic map(
|
1126 |
|
|
INIT => X"6"
|
1127 |
|
|
)
|
1128 |
|
|
port map (
|
1129 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1),
|
1130 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
1131 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_2_o
|
1132 |
|
|
);
|
1133 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_1_RD_PNTR_2_XOR_11_o_xo_0_1 : LUT2
|
1134 |
|
|
generic map(
|
1135 |
|
|
INIT => X"6"
|
1136 |
|
|
)
|
1137 |
|
|
port map (
|
1138 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
1139 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
1140 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_11_o
|
1141 |
|
|
);
|
1142 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_131_xo_0_1 : LUT4
|
1143 |
|
|
generic map(
|
1144 |
|
|
INIT => X"6996"
|
1145 |
|
|
)
|
1146 |
|
|
port map (
|
1147 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(0),
|
1148 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1),
|
1149 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
1150 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
1151 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3_reduce_xor_13_o
|
1152 |
|
|
);
|
1153 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_61_xo_0_1 : LUT4
|
1154 |
|
|
generic map(
|
1155 |
|
|
INIT => X"6996"
|
1156 |
|
|
)
|
1157 |
|
|
port map (
|
1158 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(0),
|
1159 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1),
|
1160 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
1161 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
1162 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3_reduce_xor_6_o
|
1163 |
|
|
);
|
1164 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o1 : LUT6
|
1165 |
|
|
generic map(
|
1166 |
|
|
INIT => X"8040201008040201"
|
1167 |
|
|
)
|
1168 |
|
|
port map (
|
1169 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
1170 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
1171 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
1172 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
1173 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
1174 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
1175 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o1_124
|
1176 |
|
|
);
|
1177 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o2 : LUT3
|
1178 |
|
|
generic map(
|
1179 |
|
|
INIT => X"41"
|
1180 |
|
|
)
|
1181 |
|
|
port map (
|
1182 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_15,
|
1183 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
1184 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
1185 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o2_125
|
1186 |
|
|
);
|
1187 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o3 : LUT5
|
1188 |
|
|
generic map(
|
1189 |
|
|
INIT => X"80082002"
|
1190 |
|
|
)
|
1191 |
|
|
port map (
|
1192 |
|
|
I0 => rd_en,
|
1193 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
1194 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
1195 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
1196 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
1197 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o3_126
|
1198 |
|
|
);
|
1199 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o11 : LUT6
|
1200 |
|
|
generic map(
|
1201 |
|
|
INIT => X"9009000000009009"
|
1202 |
|
|
)
|
1203 |
|
|
port map (
|
1204 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2),
|
1205 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
1206 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3),
|
1207 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
1208 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0),
|
1209 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1210 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o1
|
1211 |
|
|
);
|
1212 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o13 : LUT6
|
1213 |
|
|
generic map(
|
1214 |
|
|
INIT => X"0000000090000090"
|
1215 |
|
|
)
|
1216 |
|
|
port map (
|
1217 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
1218 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3),
|
1219 |
|
|
I2 => wr_en,
|
1220 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
1221 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2),
|
1222 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_60,
|
1223 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o12_129
|
1224 |
|
|
);
|
1225 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o14 : LUT6
|
1226 |
|
|
generic map(
|
1227 |
|
|
INIT => X"5541414155000000"
|
1228 |
|
|
)
|
1229 |
|
|
port map (
|
1230 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_29,
|
1231 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1),
|
1232 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1),
|
1233 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o11_128,
|
1234 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o12_129,
|
1235 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o1,
|
1236 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_31_o_MUX_16_o
|
1237 |
|
|
);
|
1238 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot : LUT3
|
1239 |
|
|
generic map(
|
1240 |
|
|
INIT => X"E4"
|
1241 |
|
|
)
|
1242 |
|
|
port map (
|
1243 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_69,
|
1244 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_67,
|
1245 |
|
|
I2 => N1,
|
1246 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_130
|
1247 |
|
|
);
|
1248 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDP
|
1249 |
|
|
port map (
|
1250 |
|
|
C => wr_clk,
|
1251 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_130,
|
1252 |
|
|
PRE => rst,
|
1253 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_67
|
1254 |
|
|
);
|
1255 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o12 : LUT4
|
1256 |
|
|
generic map(
|
1257 |
|
|
INIT => X"2184"
|
1258 |
|
|
)
|
1259 |
|
|
port map (
|
1260 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1),
|
1261 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0),
|
1262 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
1263 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1264 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_31_o_MUX_16_o11_128
|
1265 |
|
|
);
|
1266 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gic0_gc0_count_3_GND_29_o_mux_2_OUT41 : LUT4
|
1267 |
|
|
generic map(
|
1268 |
|
|
INIT => X"AA6A"
|
1269 |
|
|
)
|
1270 |
|
|
port map (
|
1271 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
1272 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
1273 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
1274 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1275 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_3_Q
|
1276 |
|
|
);
|
1277 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gic0_gc0_count_3_GND_29_o_mux_2_OUT31 : LUT3
|
1278 |
|
|
generic map(
|
1279 |
|
|
INIT => X"A6"
|
1280 |
|
|
)
|
1281 |
|
|
port map (
|
1282 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
1283 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
1284 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1285 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_2_Q
|
1286 |
|
|
);
|
1287 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gic0_gc0_count_3_GND_29_o_mux_2_OUT21 : LUT2
|
1288 |
|
|
generic map(
|
1289 |
|
|
INIT => X"9"
|
1290 |
|
|
)
|
1291 |
|
|
port map (
|
1292 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
1293 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1294 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3_GND_29_o_mux_2_OUT_1_Q
|
1295 |
|
|
);
|
1296 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_0_WR_PNTR_1_XOR_3_o_xo_0_1 : LUT2
|
1297 |
|
|
generic map(
|
1298 |
|
|
INIT => X"9"
|
1299 |
|
|
)
|
1300 |
|
|
port map (
|
1301 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1302 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(1),
|
1303 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_3_o
|
1304 |
|
|
);
|
1305 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_0_RD_PNTR_1_XOR_12_o_xo_0_1 : LUT2
|
1306 |
|
|
generic map(
|
1307 |
|
|
INIT => X"9"
|
1308 |
|
|
)
|
1309 |
|
|
port map (
|
1310 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1311 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
1312 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_12_o
|
1313 |
|
|
);
|
1314 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o4 : LUT5
|
1315 |
|
|
generic map(
|
1316 |
|
|
INIT => X"F6669000"
|
1317 |
|
|
)
|
1318 |
|
|
port map (
|
1319 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0),
|
1320 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1321 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o2_125,
|
1322 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o3_126,
|
1323 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o1_124,
|
1324 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o
|
1325 |
|
|
);
|
1326 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0_dpot : LUT2
|
1327 |
|
|
generic map(
|
1328 |
|
|
INIT => X"6"
|
1329 |
|
|
)
|
1330 |
|
|
port map (
|
1331 |
|
|
I0 => wr_en,
|
1332 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1333 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0_dpot_132
|
1334 |
|
|
);
|
1335 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_3_GND_22_o_mux_2_OUT11_INV_0 : INV
|
1336 |
|
|
port map (
|
1337 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
1338 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv
|
1339 |
|
|
);
|
1340 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv1_INV_0 : INV
|
1341 |
|
|
port map (
|
1342 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1343 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv
|
1344 |
|
|
);
|
1345 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1_cepot_INV_0 : INV
|
1346 |
|
|
port map (
|
1347 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_60,
|
1348 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1_cepot
|
1349 |
|
|
);
|
1350 |
|
|
|
1351 |
|
|
end STRUCTURE;
|
1352 |
|
|
|
1353 |
|
|
-- synthesis translate_on
|