1 |
13 |
barabba |
--------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- FIFO Generator v8.2 Core - Top-level core wrapper
|
4 |
|
|
--
|
5 |
|
|
--------------------------------------------------------------------------------
|
6 |
|
|
--
|
7 |
|
|
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
8 |
|
|
--
|
9 |
|
|
-- This file contains confidential and proprietary information
|
10 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
11 |
|
|
-- international copyright and other intellectual property
|
12 |
|
|
-- laws.
|
13 |
|
|
--
|
14 |
|
|
-- DISCLAIMER
|
15 |
|
|
-- This disclaimer is not a license and does not grant any
|
16 |
|
|
-- rights to the materials distributed herewith. Except as
|
17 |
|
|
-- otherwise provided in a valid license issued to you by
|
18 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
19 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
20 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
21 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
22 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
23 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
24 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
25 |
|
|
-- including negligence, or under any other theory of
|
26 |
|
|
-- liability) for any loss or damage of any kind or nature
|
27 |
|
|
-- related to, arising under or in connection with these
|
28 |
|
|
-- materials, including for any direct, or any indirect,
|
29 |
|
|
-- special, incidental, or consequential loss or damage
|
30 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
31 |
|
|
-- loss or damage suffered as a result of any action brought
|
32 |
|
|
-- by a third party) even if such damage or loss was
|
33 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
34 |
|
|
-- possibility of the same.
|
35 |
|
|
--
|
36 |
|
|
-- CRITICAL APPLICATIONS
|
37 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
38 |
|
|
-- safe, or for use in any application requiring fail-safe
|
39 |
|
|
-- performance, such as life-support or safety devices or
|
40 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
41 |
|
|
-- applications related to the deployment of airbags, or any
|
42 |
|
|
-- other applications that could lead to death, personal
|
43 |
|
|
-- injury, or severe property or environmental damage
|
44 |
|
|
-- (individually and collectively, "Critical
|
45 |
|
|
-- Applications"). Customer assumes the sole risk and
|
46 |
|
|
-- liability of any use of Xilinx products in Critical
|
47 |
|
|
-- Applications, subject only to applicable laws and
|
48 |
|
|
-- regulations governing limitations on product liability.
|
49 |
|
|
--
|
50 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
51 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
52 |
|
|
--------------------------------------------------------------------------------
|
53 |
|
|
--
|
54 |
|
|
-- Filename: <componenet name>_top.vhd
|
55 |
|
|
--
|
56 |
|
|
-- Description:
|
57 |
|
|
-- This is the actual FIFO core wrapper.
|
58 |
|
|
--
|
59 |
|
|
--------------------------------------------------------------------------------
|
60 |
|
|
-- Library Declarations
|
61 |
|
|
--------------------------------------------------------------------------------
|
62 |
|
|
|
63 |
|
|
library ieee;
|
64 |
|
|
use ieee.std_logic_1164.all;
|
65 |
|
|
use ieee.std_logic_arith.all;
|
66 |
|
|
use ieee.std_logic_unsigned.all;
|
67 |
|
|
|
68 |
|
|
library unisim;
|
69 |
|
|
use unisim.vcomponents.all;
|
70 |
|
|
|
71 |
|
|
--------------------------------------------------------------------------------
|
72 |
|
|
-- Entity Declaration
|
73 |
|
|
--------------------------------------------------------------------------------
|
74 |
|
|
entity v6_eb_fifo_counted_resized_top is
|
75 |
|
|
PORT (
|
76 |
|
|
CLK : IN STD_LOGIC;
|
77 |
|
|
BACKUP : IN STD_LOGIC;
|
78 |
|
|
BACKUP_MARKER : IN STD_LOGIC;
|
79 |
|
|
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
|
80 |
|
|
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
81 |
|
|
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
82 |
|
|
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
83 |
|
|
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
84 |
|
|
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
85 |
|
|
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(15-1 downto 0);
|
86 |
|
|
RD_CLK : IN STD_LOGIC;
|
87 |
|
|
RD_EN : IN STD_LOGIC;
|
88 |
|
|
RD_RST : IN STD_LOGIC;
|
89 |
|
|
RST : IN STD_LOGIC;
|
90 |
|
|
SRST : IN STD_LOGIC;
|
91 |
|
|
WR_CLK : IN STD_LOGIC;
|
92 |
|
|
WR_EN : IN STD_LOGIC;
|
93 |
|
|
WR_RST : IN STD_LOGIC;
|
94 |
|
|
INJECTDBITERR : IN STD_LOGIC;
|
95 |
|
|
INJECTSBITERR : IN STD_LOGIC;
|
96 |
|
|
ALMOST_EMPTY : OUT STD_LOGIC;
|
97 |
|
|
ALMOST_FULL : OUT STD_LOGIC;
|
98 |
|
|
DATA_COUNT : OUT STD_LOGIC_VECTOR(15-1 downto 0);
|
99 |
|
|
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
|
100 |
|
|
EMPTY : OUT STD_LOGIC;
|
101 |
|
|
FULL : OUT STD_LOGIC;
|
102 |
|
|
OVERFLOW : OUT STD_LOGIC;
|
103 |
|
|
PROG_EMPTY : OUT STD_LOGIC;
|
104 |
|
|
PROG_FULL : OUT STD_LOGIC;
|
105 |
|
|
VALID : OUT STD_LOGIC;
|
106 |
|
|
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(15-1 downto 0);
|
107 |
|
|
UNDERFLOW : OUT STD_LOGIC;
|
108 |
|
|
WR_ACK : OUT STD_LOGIC;
|
109 |
|
|
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(15-1 downto 0);
|
110 |
|
|
SBITERR : OUT STD_LOGIC;
|
111 |
|
|
DBITERR : OUT STD_LOGIC;
|
112 |
|
|
-- AXI Global Signal
|
113 |
|
|
M_ACLK : IN std_logic;
|
114 |
|
|
S_ACLK : IN std_logic;
|
115 |
|
|
S_ARESETN : IN std_logic;
|
116 |
|
|
M_ACLK_EN : IN std_logic;
|
117 |
|
|
S_ACLK_EN : IN std_logic;
|
118 |
|
|
-- AXI Full/Lite Slave Write Channel (write side)
|
119 |
|
|
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
|
120 |
|
|
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
|
121 |
|
|
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
|
122 |
|
|
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
|
123 |
|
|
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
|
124 |
|
|
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
|
125 |
|
|
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
|
126 |
|
|
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
|
127 |
|
|
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
|
128 |
|
|
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
|
129 |
|
|
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
|
130 |
|
|
S_AXI_AWVALID : IN std_logic;
|
131 |
|
|
S_AXI_AWREADY : OUT std_logic;
|
132 |
|
|
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
|
133 |
|
|
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
134 |
|
|
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
|
135 |
|
|
S_AXI_WLAST : IN std_logic;
|
136 |
|
|
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
|
137 |
|
|
S_AXI_WVALID : IN std_logic;
|
138 |
|
|
S_AXI_WREADY : OUT std_logic;
|
139 |
|
|
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
|
140 |
|
|
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
|
141 |
|
|
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
|
142 |
|
|
S_AXI_BVALID : OUT std_logic;
|
143 |
|
|
S_AXI_BREADY : IN std_logic;
|
144 |
|
|
-- AXI Full/Lite Master Write Channel (Read side)
|
145 |
|
|
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
|
146 |
|
|
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
|
147 |
|
|
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
|
148 |
|
|
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
|
149 |
|
|
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
|
150 |
|
|
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
|
151 |
|
|
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
|
152 |
|
|
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
|
153 |
|
|
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
|
154 |
|
|
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
|
155 |
|
|
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
|
156 |
|
|
M_AXI_AWVALID : OUT std_logic;
|
157 |
|
|
M_AXI_AWREADY : IN std_logic;
|
158 |
|
|
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
|
159 |
|
|
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
160 |
|
|
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
|
161 |
|
|
M_AXI_WLAST : OUT std_logic;
|
162 |
|
|
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
|
163 |
|
|
M_AXI_WVALID : OUT std_logic;
|
164 |
|
|
M_AXI_WREADY : IN std_logic;
|
165 |
|
|
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
|
166 |
|
|
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
|
167 |
|
|
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
|
168 |
|
|
M_AXI_BVALID : IN std_logic;
|
169 |
|
|
M_AXI_BREADY : OUT std_logic;
|
170 |
|
|
-- AXI Full/Lite Slave Read Channel (Write side)
|
171 |
|
|
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
|
172 |
|
|
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
|
173 |
|
|
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
|
174 |
|
|
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
|
175 |
|
|
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
|
176 |
|
|
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
|
177 |
|
|
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
|
178 |
|
|
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
|
179 |
|
|
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
|
180 |
|
|
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
|
181 |
|
|
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
|
182 |
|
|
S_AXI_ARVALID : IN std_logic;
|
183 |
|
|
S_AXI_ARREADY : OUT std_logic;
|
184 |
|
|
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
|
185 |
|
|
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
186 |
|
|
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
|
187 |
|
|
S_AXI_RLAST : OUT std_logic;
|
188 |
|
|
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
|
189 |
|
|
S_AXI_RVALID : OUT std_logic;
|
190 |
|
|
S_AXI_RREADY : IN std_logic;
|
191 |
|
|
-- AXI Full/Lite Master Read Channel (Read side)
|
192 |
|
|
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
|
193 |
|
|
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
|
194 |
|
|
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
|
195 |
|
|
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
|
196 |
|
|
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
|
197 |
|
|
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
|
198 |
|
|
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
|
199 |
|
|
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
|
200 |
|
|
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
|
201 |
|
|
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
|
202 |
|
|
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
|
203 |
|
|
M_AXI_ARVALID : OUT std_logic;
|
204 |
|
|
M_AXI_ARREADY : IN std_logic;
|
205 |
|
|
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
|
206 |
|
|
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
207 |
|
|
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
|
208 |
|
|
M_AXI_RLAST : IN std_logic;
|
209 |
|
|
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
|
210 |
|
|
M_AXI_RVALID : IN std_logic;
|
211 |
|
|
M_AXI_RREADY : OUT std_logic;
|
212 |
|
|
-- AXI Streaming Slave Signals (Write side)
|
213 |
|
|
S_AXIS_TVALID : IN std_logic;
|
214 |
|
|
S_AXIS_TREADY : OUT std_logic;
|
215 |
|
|
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
216 |
|
|
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
|
217 |
|
|
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
|
218 |
|
|
S_AXIS_TLAST : IN std_logic;
|
219 |
|
|
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
|
220 |
|
|
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
|
221 |
|
|
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
|
222 |
|
|
-- AXI Streaming Master Signals (Read side)
|
223 |
|
|
M_AXIS_TVALID : OUT std_logic;
|
224 |
|
|
M_AXIS_TREADY : IN std_logic;
|
225 |
|
|
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
226 |
|
|
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
|
227 |
|
|
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
|
228 |
|
|
M_AXIS_TLAST : OUT std_logic;
|
229 |
|
|
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
|
230 |
|
|
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
|
231 |
|
|
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
|
232 |
|
|
-- AXI Full/Lite Write Address Channel Signals
|
233 |
|
|
AXI_AW_INJECTSBITERR : IN std_logic;
|
234 |
|
|
AXI_AW_INJECTDBITERR : IN std_logic;
|
235 |
|
|
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
236 |
|
|
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
237 |
|
|
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
238 |
|
|
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
239 |
|
|
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
240 |
|
|
AXI_AW_SBITERR : OUT std_logic;
|
241 |
|
|
AXI_AW_DBITERR : OUT std_logic;
|
242 |
|
|
AXI_AW_OVERFLOW : OUT std_logic;
|
243 |
|
|
AXI_AW_UNDERFLOW : OUT std_logic;
|
244 |
|
|
-- AXI Full/Lite Write Data Channel Signals
|
245 |
|
|
AXI_W_INJECTSBITERR : IN std_logic;
|
246 |
|
|
AXI_W_INJECTDBITERR : IN std_logic;
|
247 |
|
|
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
248 |
|
|
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
249 |
|
|
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
250 |
|
|
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
251 |
|
|
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
252 |
|
|
AXI_W_SBITERR : OUT std_logic;
|
253 |
|
|
AXI_W_DBITERR : OUT std_logic;
|
254 |
|
|
AXI_W_OVERFLOW : OUT std_logic;
|
255 |
|
|
AXI_W_UNDERFLOW : OUT std_logic;
|
256 |
|
|
-- AXI Full/Lite Write Response Channel Signals
|
257 |
|
|
AXI_B_INJECTSBITERR : IN std_logic;
|
258 |
|
|
AXI_B_INJECTDBITERR : IN std_logic;
|
259 |
|
|
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
260 |
|
|
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
261 |
|
|
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
262 |
|
|
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
263 |
|
|
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
264 |
|
|
AXI_B_SBITERR : OUT std_logic;
|
265 |
|
|
AXI_B_DBITERR : OUT std_logic;
|
266 |
|
|
AXI_B_OVERFLOW : OUT std_logic;
|
267 |
|
|
AXI_B_UNDERFLOW : OUT std_logic;
|
268 |
|
|
-- AXI Full/Lite Read Address Channel Signals
|
269 |
|
|
AXI_AR_INJECTSBITERR : IN std_logic;
|
270 |
|
|
AXI_AR_INJECTDBITERR : IN std_logic;
|
271 |
|
|
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
272 |
|
|
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
|
273 |
|
|
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
274 |
|
|
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
275 |
|
|
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
|
276 |
|
|
AXI_AR_SBITERR : OUT std_logic;
|
277 |
|
|
AXI_AR_DBITERR : OUT std_logic;
|
278 |
|
|
AXI_AR_OVERFLOW : OUT std_logic;
|
279 |
|
|
AXI_AR_UNDERFLOW : OUT std_logic;
|
280 |
|
|
-- AXI Full/Lite Read Data Channel Signals
|
281 |
|
|
AXI_R_INJECTSBITERR : IN std_logic;
|
282 |
|
|
AXI_R_INJECTDBITERR : IN std_logic;
|
283 |
|
|
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
284 |
|
|
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
285 |
|
|
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
286 |
|
|
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
287 |
|
|
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
288 |
|
|
AXI_R_SBITERR : OUT std_logic;
|
289 |
|
|
AXI_R_DBITERR : OUT std_logic;
|
290 |
|
|
AXI_R_OVERFLOW : OUT std_logic;
|
291 |
|
|
AXI_R_UNDERFLOW : OUT std_logic;
|
292 |
|
|
-- AXI Streaming FIFO Related Signals
|
293 |
|
|
AXIS_INJECTSBITERR : IN std_logic;
|
294 |
|
|
AXIS_INJECTDBITERR : IN std_logic;
|
295 |
|
|
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
296 |
|
|
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
|
297 |
|
|
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
298 |
|
|
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
299 |
|
|
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
|
300 |
|
|
AXIS_SBITERR : OUT std_logic;
|
301 |
|
|
AXIS_DBITERR : OUT std_logic;
|
302 |
|
|
AXIS_OVERFLOW : OUT std_logic;
|
303 |
|
|
AXIS_UNDERFLOW : OUT std_logic);
|
304 |
|
|
|
305 |
|
|
end v6_eb_fifo_counted_resized_top;
|
306 |
|
|
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
architecture xilinx of v6_eb_fifo_counted_resized_top is
|
310 |
|
|
|
311 |
|
|
SIGNAL WR_CLK_i : std_logic;
|
312 |
|
|
SIGNAL RD_CLK_i : std_logic;
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
component v6_eb_fifo_counted_resized is
|
317 |
|
|
PORT (
|
318 |
|
|
WR_CLK : IN std_logic;
|
319 |
|
|
RD_CLK : IN std_logic;
|
320 |
|
|
WR_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
|
321 |
|
|
RD_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
|
322 |
|
|
VALID : OUT std_logic;
|
323 |
|
|
RST : IN std_logic;
|
324 |
|
|
PROG_FULL : OUT std_logic;
|
325 |
|
|
PROG_EMPTY : OUT std_logic;
|
326 |
|
|
WR_EN : IN std_logic;
|
327 |
|
|
RD_EN : IN std_logic;
|
328 |
|
|
DIN : IN std_logic_vector(64-1 DOWNTO 0);
|
329 |
|
|
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
|
330 |
|
|
FULL : OUT std_logic;
|
331 |
|
|
EMPTY : OUT std_logic);
|
332 |
|
|
end component;
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
begin
|
336 |
|
|
|
337 |
|
|
fg0 : v6_eb_fifo_counted_resized
|
338 |
|
|
port map (
|
339 |
|
|
WR_CLK => WR_CLK_i,
|
340 |
|
|
RD_CLK => RD_CLK_i,
|
341 |
|
|
WR_DATA_COUNT => WR_DATA_COUNT,
|
342 |
|
|
RD_DATA_COUNT => RD_DATA_COUNT,
|
343 |
|
|
VALID => VALID,
|
344 |
|
|
RST => RST,
|
345 |
|
|
PROG_FULL => PROG_FULL,
|
346 |
|
|
PROG_EMPTY => PROG_EMPTY,
|
347 |
|
|
WR_EN => WR_EN,
|
348 |
|
|
RD_EN => RD_EN,
|
349 |
|
|
DIN => DIN,
|
350 |
|
|
DOUT => DOUT,
|
351 |
|
|
FULL => FULL,
|
352 |
|
|
EMPTY => EMPTY);
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
wr_clk_buf: bufg
|
356 |
|
|
PORT map(
|
357 |
|
|
i => WR_CLK,
|
358 |
|
|
o => WR_CLK_i
|
359 |
|
|
);
|
360 |
|
|
|
361 |
|
|
rd_clk_buf: bufg
|
362 |
|
|
PORT map(
|
363 |
|
|
i => RD_CLK,
|
364 |
|
|
o => RD_CLK_i
|
365 |
|
|
);
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
end xilinx;
|