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barabba |
--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: O.76xd
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-- \ \ Application: netgen
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-- / / Filename: v6_mBuf_128x72.vhd
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-- /___/ /\ Timestamp: Mon Mar 26 15:48:24 2012
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-- \ \ / \
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-- \___\/\___\
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--
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-- Command : -w -sim -ofmt vhdl "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_mBuf_128x72.ngc" "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_mBuf_128x72.vhd"
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-- Device : 6vlx240tff1156-1
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-- Input file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_mBuf_128x72.ngc
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-- Output file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_mBuf_128x72.vhd
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-- # of Entities : 1
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-- Design Name : v6_mBuf_128x72
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-- Xilinx : C:\Programmi\Xilinx\13.3\ISE_DS\ISE\
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--
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-- Purpose:
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-- This VHDL netlist is a verification model and uses simulation
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-- primitives which may not represent the true implementation of the
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-- device, however the netlist is functionally correct and should not
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-- be modified. This file cannot be synthesized and should only be used
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-- with supported simulation tools.
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--
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-- Reference:
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-- Command Line Tools User Guide, Chapter 23
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-- Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity v6_mBuf_128x72 is
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port (
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clk : in STD_LOGIC := 'X';
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rst : in STD_LOGIC := 'X';
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wr_en : in STD_LOGIC := 'X';
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rd_en : in STD_LOGIC := 'X';
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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prog_full : out STD_LOGIC;
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din : in STD_LOGIC_VECTOR ( 71 downto 0 );
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dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
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);
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end v6_mBuf_128x72;
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architecture STRUCTURE of v6_mBuf_128x72 is
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signal N1 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_2 : STD_LOGIC;
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signal NlwRenamedSig_OI_empty : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_153 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
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signal N2 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163 : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
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112 |
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
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114 |
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
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116 |
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
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142 |
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
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143 |
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144 |
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signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rd_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst : STD_LOGIC_VECTOR ( 0 downto 0 );
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signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
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begin
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149 |
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empty <= NlwRenamedSig_OI_empty;
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prog_full <= U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_2;
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XST_GND : GND
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port map (
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G => N1
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);
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U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_4 : FD
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generic map(
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INIT => '0'
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)
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port map (
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C => clk,
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D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_153,
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Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(4)
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);
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U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_3 : FD
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generic map(
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INIT => '0'
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167 |
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)
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168 |
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port map (
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169 |
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C => clk,
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170 |
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D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(4),
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Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(3)
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172 |
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);
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U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_2 : FD
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generic map(
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175 |
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INIT => '0'
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176 |
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)
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177 |
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port map (
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178 |
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C => clk,
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179 |
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D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(3),
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180 |
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Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(2)
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181 |
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);
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182 |
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U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_1 : FD
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183 |
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generic map(
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184 |
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INIT => '0'
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185 |
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)
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186 |
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port map (
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187 |
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C => clk,
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188 |
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D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(2),
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189 |
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Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(1)
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190 |
|
|
);
|
191 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_0 : FD
|
192 |
|
|
generic map(
|
193 |
|
|
INIT => '0'
|
194 |
|
|
)
|
195 |
|
|
port map (
|
196 |
|
|
C => clk,
|
197 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(1),
|
198 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(0)
|
199 |
|
|
);
|
200 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg : FDPE
|
201 |
|
|
generic map(
|
202 |
|
|
INIT => '0'
|
203 |
|
|
)
|
204 |
|
|
port map (
|
205 |
|
|
C => clk,
|
206 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(0),
|
207 |
|
|
D => N1,
|
208 |
|
|
PRE => rst,
|
209 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_153
|
210 |
|
|
);
|
211 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
|
212 |
|
|
generic map(
|
213 |
|
|
ALMOST_EMPTY_OFFSET => X"0002",
|
214 |
|
|
ALMOST_FULL_OFFSET => X"0180",
|
215 |
|
|
DATA_WIDTH => 72,
|
216 |
|
|
DO_REG => 0,
|
217 |
|
|
EN_ECC_READ => FALSE,
|
218 |
|
|
EN_ECC_WRITE => FALSE,
|
219 |
|
|
EN_SYN => TRUE,
|
220 |
|
|
FIFO_MODE => "FIFO36_72",
|
221 |
|
|
FIRST_WORD_FALL_THROUGH => FALSE,
|
222 |
|
|
INIT => X"000000000000000000",
|
223 |
|
|
SIM_DEVICE => "VIRTEX6",
|
224 |
|
|
SRVAL => X"000000000000000000"
|
225 |
|
|
)
|
226 |
|
|
port map (
|
227 |
|
|
ALMOSTEMPTY =>
|
228 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
|
229 |
|
|
,
|
230 |
|
|
ALMOSTFULL => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
|
231 |
|
|
DBITERR =>
|
232 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
|
233 |
|
|
EMPTY => NlwRenamedSig_OI_empty,
|
234 |
|
|
FULL => full,
|
235 |
|
|
INJECTDBITERR => N1,
|
236 |
|
|
INJECTSBITERR => N1,
|
237 |
|
|
RDCLK => clk,
|
238 |
|
|
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
|
239 |
|
|
RDERR =>
|
240 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
|
241 |
|
|
REGCE => N1,
|
242 |
|
|
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rd_rst_i(0),
|
243 |
|
|
RSTREG => N1,
|
244 |
|
|
SBITERR =>
|
245 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
|
246 |
|
|
WRCLK => clk,
|
247 |
|
|
WREN => wr_en,
|
248 |
|
|
WRERR =>
|
249 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
|
250 |
|
|
DI(63) => din(67),
|
251 |
|
|
DI(62) => din(66),
|
252 |
|
|
DI(61) => din(65),
|
253 |
|
|
DI(60) => din(64),
|
254 |
|
|
DI(59) => din(63),
|
255 |
|
|
DI(58) => din(62),
|
256 |
|
|
DI(57) => din(61),
|
257 |
|
|
DI(56) => din(60),
|
258 |
|
|
DI(55) => din(59),
|
259 |
|
|
DI(54) => din(58),
|
260 |
|
|
DI(53) => din(57),
|
261 |
|
|
DI(52) => din(56),
|
262 |
|
|
DI(51) => din(55),
|
263 |
|
|
DI(50) => din(54),
|
264 |
|
|
DI(49) => din(53),
|
265 |
|
|
DI(48) => din(52),
|
266 |
|
|
DI(47) => din(51),
|
267 |
|
|
DI(46) => din(50),
|
268 |
|
|
DI(45) => din(49),
|
269 |
|
|
DI(44) => din(48),
|
270 |
|
|
DI(43) => din(47),
|
271 |
|
|
DI(42) => din(46),
|
272 |
|
|
DI(41) => din(45),
|
273 |
|
|
DI(40) => din(44),
|
274 |
|
|
DI(39) => din(43),
|
275 |
|
|
DI(38) => din(42),
|
276 |
|
|
DI(37) => din(41),
|
277 |
|
|
DI(36) => din(40),
|
278 |
|
|
DI(35) => din(39),
|
279 |
|
|
DI(34) => din(38),
|
280 |
|
|
DI(33) => din(37),
|
281 |
|
|
DI(32) => din(36),
|
282 |
|
|
DI(31) => din(31),
|
283 |
|
|
DI(30) => din(30),
|
284 |
|
|
DI(29) => din(29),
|
285 |
|
|
DI(28) => din(28),
|
286 |
|
|
DI(27) => din(27),
|
287 |
|
|
DI(26) => din(26),
|
288 |
|
|
DI(25) => din(25),
|
289 |
|
|
DI(24) => din(24),
|
290 |
|
|
DI(23) => din(23),
|
291 |
|
|
DI(22) => din(22),
|
292 |
|
|
DI(21) => din(21),
|
293 |
|
|
DI(20) => din(20),
|
294 |
|
|
DI(19) => din(19),
|
295 |
|
|
DI(18) => din(18),
|
296 |
|
|
DI(17) => din(17),
|
297 |
|
|
DI(16) => din(16),
|
298 |
|
|
DI(15) => din(15),
|
299 |
|
|
DI(14) => din(14),
|
300 |
|
|
DI(13) => din(13),
|
301 |
|
|
DI(12) => din(12),
|
302 |
|
|
DI(11) => din(11),
|
303 |
|
|
DI(10) => din(10),
|
304 |
|
|
DI(9) => din(9),
|
305 |
|
|
DI(8) => din(8),
|
306 |
|
|
DI(7) => din(7),
|
307 |
|
|
DI(6) => din(6),
|
308 |
|
|
DI(5) => din(5),
|
309 |
|
|
DI(4) => din(4),
|
310 |
|
|
DI(3) => din(3),
|
311 |
|
|
DI(2) => din(2),
|
312 |
|
|
DI(1) => din(1),
|
313 |
|
|
DI(0) => din(0),
|
314 |
|
|
DIP(7) => din(71),
|
315 |
|
|
DIP(6) => din(70),
|
316 |
|
|
DIP(5) => din(69),
|
317 |
|
|
DIP(4) => din(68),
|
318 |
|
|
DIP(3) => din(35),
|
319 |
|
|
DIP(2) => din(34),
|
320 |
|
|
DIP(1) => din(33),
|
321 |
|
|
DIP(0) => din(32),
|
322 |
|
|
DO(63) => dout(67),
|
323 |
|
|
DO(62) => dout(66),
|
324 |
|
|
DO(61) => dout(65),
|
325 |
|
|
DO(60) => dout(64),
|
326 |
|
|
DO(59) => dout(63),
|
327 |
|
|
DO(58) => dout(62),
|
328 |
|
|
DO(57) => dout(61),
|
329 |
|
|
DO(56) => dout(60),
|
330 |
|
|
DO(55) => dout(59),
|
331 |
|
|
DO(54) => dout(58),
|
332 |
|
|
DO(53) => dout(57),
|
333 |
|
|
DO(52) => dout(56),
|
334 |
|
|
DO(51) => dout(55),
|
335 |
|
|
DO(50) => dout(54),
|
336 |
|
|
DO(49) => dout(53),
|
337 |
|
|
DO(48) => dout(52),
|
338 |
|
|
DO(47) => dout(51),
|
339 |
|
|
DO(46) => dout(50),
|
340 |
|
|
DO(45) => dout(49),
|
341 |
|
|
DO(44) => dout(48),
|
342 |
|
|
DO(43) => dout(47),
|
343 |
|
|
DO(42) => dout(46),
|
344 |
|
|
DO(41) => dout(45),
|
345 |
|
|
DO(40) => dout(44),
|
346 |
|
|
DO(39) => dout(43),
|
347 |
|
|
DO(38) => dout(42),
|
348 |
|
|
DO(37) => dout(41),
|
349 |
|
|
DO(36) => dout(40),
|
350 |
|
|
DO(35) => dout(39),
|
351 |
|
|
DO(34) => dout(38),
|
352 |
|
|
DO(33) => dout(37),
|
353 |
|
|
DO(32) => dout(36),
|
354 |
|
|
DO(31) => dout(31),
|
355 |
|
|
DO(30) => dout(30),
|
356 |
|
|
DO(29) => dout(29),
|
357 |
|
|
DO(28) => dout(28),
|
358 |
|
|
DO(27) => dout(27),
|
359 |
|
|
DO(26) => dout(26),
|
360 |
|
|
DO(25) => dout(25),
|
361 |
|
|
DO(24) => dout(24),
|
362 |
|
|
DO(23) => dout(23),
|
363 |
|
|
DO(22) => dout(22),
|
364 |
|
|
DO(21) => dout(21),
|
365 |
|
|
DO(20) => dout(20),
|
366 |
|
|
DO(19) => dout(19),
|
367 |
|
|
DO(18) => dout(18),
|
368 |
|
|
DO(17) => dout(17),
|
369 |
|
|
DO(16) => dout(16),
|
370 |
|
|
DO(15) => dout(15),
|
371 |
|
|
DO(14) => dout(14),
|
372 |
|
|
DO(13) => dout(13),
|
373 |
|
|
DO(12) => dout(12),
|
374 |
|
|
DO(11) => dout(11),
|
375 |
|
|
DO(10) => dout(10),
|
376 |
|
|
DO(9) => dout(9),
|
377 |
|
|
DO(8) => dout(8),
|
378 |
|
|
DO(7) => dout(7),
|
379 |
|
|
DO(6) => dout(6),
|
380 |
|
|
DO(5) => dout(5),
|
381 |
|
|
DO(4) => dout(4),
|
382 |
|
|
DO(3) => dout(3),
|
383 |
|
|
DO(2) => dout(2),
|
384 |
|
|
DO(1) => dout(1),
|
385 |
|
|
DO(0) => dout(0),
|
386 |
|
|
DOP(7) => dout(71),
|
387 |
|
|
DOP(6) => dout(70),
|
388 |
|
|
DOP(5) => dout(69),
|
389 |
|
|
DOP(4) => dout(68),
|
390 |
|
|
DOP(3) => dout(35),
|
391 |
|
|
DOP(2) => dout(34),
|
392 |
|
|
DOP(1) => dout(33),
|
393 |
|
|
DOP(0) => dout(32),
|
394 |
|
|
ECCPARITY(7) =>
|
395 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
|
396 |
|
|
,
|
397 |
|
|
ECCPARITY(6) =>
|
398 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
|
399 |
|
|
,
|
400 |
|
|
ECCPARITY(5) =>
|
401 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
|
402 |
|
|
,
|
403 |
|
|
ECCPARITY(4) =>
|
404 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
|
405 |
|
|
,
|
406 |
|
|
ECCPARITY(3) =>
|
407 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
|
408 |
|
|
,
|
409 |
|
|
ECCPARITY(2) =>
|
410 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
|
411 |
|
|
,
|
412 |
|
|
ECCPARITY(1) =>
|
413 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
|
414 |
|
|
,
|
415 |
|
|
ECCPARITY(0) =>
|
416 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
|
417 |
|
|
,
|
418 |
|
|
RDCOUNT(12) =>
|
419 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
|
420 |
|
|
,
|
421 |
|
|
RDCOUNT(11) =>
|
422 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
|
423 |
|
|
,
|
424 |
|
|
RDCOUNT(10) =>
|
425 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
|
426 |
|
|
,
|
427 |
|
|
RDCOUNT(9) =>
|
428 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
|
429 |
|
|
,
|
430 |
|
|
RDCOUNT(8) =>
|
431 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
|
432 |
|
|
,
|
433 |
|
|
RDCOUNT(7) =>
|
434 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
|
435 |
|
|
,
|
436 |
|
|
RDCOUNT(6) =>
|
437 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
|
438 |
|
|
,
|
439 |
|
|
RDCOUNT(5) =>
|
440 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
|
441 |
|
|
,
|
442 |
|
|
RDCOUNT(4) =>
|
443 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
|
444 |
|
|
,
|
445 |
|
|
RDCOUNT(3) =>
|
446 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
|
447 |
|
|
,
|
448 |
|
|
RDCOUNT(2) =>
|
449 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
|
450 |
|
|
,
|
451 |
|
|
RDCOUNT(1) =>
|
452 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
|
453 |
|
|
,
|
454 |
|
|
RDCOUNT(0) =>
|
455 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
|
456 |
|
|
,
|
457 |
|
|
WRCOUNT(12) =>
|
458 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
|
459 |
|
|
,
|
460 |
|
|
WRCOUNT(11) =>
|
461 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
|
462 |
|
|
,
|
463 |
|
|
WRCOUNT(10) =>
|
464 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
|
465 |
|
|
,
|
466 |
|
|
WRCOUNT(9) =>
|
467 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
|
468 |
|
|
,
|
469 |
|
|
WRCOUNT(8) =>
|
470 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
|
471 |
|
|
,
|
472 |
|
|
WRCOUNT(7) =>
|
473 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
|
474 |
|
|
,
|
475 |
|
|
WRCOUNT(6) =>
|
476 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
|
477 |
|
|
,
|
478 |
|
|
WRCOUNT(5) =>
|
479 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
|
480 |
|
|
,
|
481 |
|
|
WRCOUNT(4) =>
|
482 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
|
483 |
|
|
,
|
484 |
|
|
WRCOUNT(3) =>
|
485 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
|
486 |
|
|
,
|
487 |
|
|
WRCOUNT(2) =>
|
488 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
|
489 |
|
|
,
|
490 |
|
|
WRCOUNT(1) =>
|
491 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
|
492 |
|
|
,
|
493 |
|
|
WRCOUNT(0) =>
|
494 |
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
|
495 |
|
|
);
|
496 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q : FDC
|
497 |
|
|
generic map(
|
498 |
|
|
INIT => '0'
|
499 |
|
|
)
|
500 |
|
|
port map (
|
501 |
|
|
C => clk,
|
502 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rd_rst_i(0),
|
503 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
|
504 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_2
|
505 |
|
|
);
|
506 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_0_1 : LUT2
|
507 |
|
|
generic map(
|
508 |
|
|
INIT => X"E"
|
509 |
|
|
)
|
510 |
|
|
port map (
|
511 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_153,
|
512 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst(0),
|
513 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rd_rst_i(0)
|
514 |
|
|
);
|
515 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
|
516 |
|
|
generic map(
|
517 |
|
|
INIT => X"2"
|
518 |
|
|
)
|
519 |
|
|
port map (
|
520 |
|
|
I0 => rd_en,
|
521 |
|
|
I1 => NlwRenamedSig_OI_empty,
|
522 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
|
523 |
|
|
);
|
524 |
|
|
XST_VCC : VCC
|
525 |
|
|
port map (
|
526 |
|
|
P => N2
|
527 |
|
|
);
|
528 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0 : SRLC16E
|
529 |
|
|
generic map(
|
530 |
|
|
INIT => X"001F"
|
531 |
|
|
)
|
532 |
|
|
port map (
|
533 |
|
|
A0 => N1,
|
534 |
|
|
A1 => N1,
|
535 |
|
|
A2 => N2,
|
536 |
|
|
A3 => N1,
|
537 |
|
|
CE => N2,
|
538 |
|
|
CLK => clk,
|
539 |
|
|
D => N1,
|
540 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163,
|
541 |
|
|
Q15 => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED
|
542 |
|
|
);
|
543 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst_0 : FDE
|
544 |
|
|
generic map(
|
545 |
|
|
INIT => '1'
|
546 |
|
|
)
|
547 |
|
|
port map (
|
548 |
|
|
C => clk,
|
549 |
|
|
CE => N2,
|
550 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163,
|
551 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst(0)
|
552 |
|
|
);
|
553 |
|
|
|
554 |
|
|
end STRUCTURE;
|
555 |
|
|
|
556 |
|
|
-- synthesis translate_on
|